Manufacturing method for semiconductor devices

Abstract

The present invention provides a method for manufacturing a semiconductor device that can suitably form a film containing multiple elements. [Solution] According to one embodiment, a method for manufacturing a semiconductor device includes preparing a first liquid containing a first element which is a metallic element or silicon, and a predetermined element which is a metallic element or silicon and is different from the first element. The method further includes generating a first gas from the first liquid which contains the first element and the predetermined element. The method further includes forming a first film containing the first element and the predetermined element on a substrate using the first gas.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device.

Background Art

[0002] When forming a film containing a plurality of elements (for example, two or more metal elements), there is a problem of how to form this film. For example, there is a problem of what raw materials to use to form this film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided is a method for manufacturing a semiconductor device capable of preferably forming a film containing a plurality of elements.

Means for Solving the Problems

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes preparing a first liquid containing a first element that is a metal element or silicon, and a predetermined element that is a metal element or silicon and is different from the first element. The method further includes generating a first gas containing the first element and the predetermined element from the first liquid. The method further includes forming a first film containing the first element and the predetermined element on a substrate using the first gas.

Brief Description of the Drawings

[0006] [Figure 1] It is a schematic diagram showing the configuration of a semiconductor manufacturing apparatus according to the first embodiment. [Figure 2] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] This is a schematic diagram showing the configuration of a semiconductor manufacturing apparatus in a comparative example of the first embodiment. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 5] This is a schematic diagram showing the configuration of a semiconductor manufacturing apparatus as a modified example of the first embodiment. [Figure 6] This is a circuit diagram showing the configuration of a semiconductor device according to the second embodiment. [Figure 7] This is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 8] This is a cross-sectional view (1 / 3) showing the manufacturing method of the semiconductor device according to the second embodiment. [Figure 9] This is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 10] This is a cross-sectional view (3 / 3) showing a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will now be described with reference to the drawings. In Figures 1 to 10, identical components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) Figure 1 is a schematic diagram showing the configuration of a semiconductor manufacturing apparatus according to the first embodiment. The semiconductor manufacturing apparatus in this embodiment is, for example, a CVD (Chemical Vapor Deposition) apparatus, and more specifically, an ALD (Atomic Layer Deposition) apparatus.

[0009] The semiconductor manufacturing apparatus of this embodiment comprises a chamber 11, a stage 12, a shaft 13, a heater 14, a gas supply unit 15, a plurality of gas flow paths 16, a shower head 17, and a control unit 18. The gas supply unit 15 comprises tanks 21-23, a gas source 24, heaters 31-33, and MFCs (Mass Flow Controllers) 41-44.

[0010] Figure 1 shows the X, Y, and Z directions perpendicular to each other. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity. In this embodiment, the X, Y, and Z directions are used, for example, to represent directions within the chamber 11.

[0011] Further details of the semiconductor manufacturing apparatus of this embodiment will be described below with reference to Figure 1. Figure 2 will also be referenced as appropriate in this description. Figure 2 is a cross-sectional view showing a semiconductor device manufacturing method of the first embodiment.

[0012] [Chamber 11] Chamber 11 houses the substrate 1 to be processed. Figure 1 shows the process of forming a film 2 on the substrate 1 in chamber 11. Substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. Film 2 is, for example, a CVD film formed by CVD. In this embodiment, substrate 1 is a semiconductor wafer and film 2 is an ALD film. Film 2 is an example of a first film.

[0013] Film 2 may contain, for example, one or more elements from among indium (In), gallium (Ga), zinc (Zn), tin (Sn), antimony (Sb), aluminum (Al), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), and tungsten (W). These elements are examples of the first, second, third, and other specified elements in the first film. Film 2 may further contain oxygen (O).

[0014] The film 2 of this embodiment is an oxide semiconductor film, for example, an IGZO film containing indium, gallium, zinc, and oxygen. The film 2 of this embodiment may further contain aluminum. The film 2 is, for example, an IGZO film containing aluminum as an impurity element. In these cases, each of indium, gallium, and zinc is an example of the first, second, and third elements in the first film, and is also an example of the metal elements in the first film. Further, aluminum is an example of a predetermined element in the first film, and is also an example of the metal elements in the first film.

[0015] Note that the film 2 may be a film other than the IGZO film. For example, the film 2 may contain one or more elements of indium, gallium, zinc, tin, aluminum, and silicon as component elements. Further, the film 2 may contain one or more elements of tin, antimony, aluminum, silicon, and niobium as impurity elements different from the component elements.

[0016] In this embodiment, the substrate 1 is carried into the chamber 11, the film 2 is formed on the substrate 1 in the chamber 11, and then the substrate 1 is carried out of the chamber 11. The substrate 1 and the film 2 may be annealed outside the chamber 11 thereafter. For example, the film 2 may be formed in the chamber 11 as a laminated film including a plurality of layers (see FIG. 2(a)), and may be changed from the laminated film to an IGZO film by annealing outside the chamber 11 (see FIG. 2(b)). Further details of such processing will be described later.

[0017] [Stage 12] The stage 12 supports the substrate 1 in the chamber 11. In FIG. 1, the substrate 1 is placed on the upper surface of the stage 12 such that the front surface of the substrate 1 faces the +Z direction and the back surface of the substrate 1 faces the -Z direction.

[0018] [Shaft 13] The shaft 13 is attached to the lower surface of the stage 12 and supports the stage 12. The shaft 13 may be configured to rotate the substrate 1 placed on the stage 12 by rotating the stage 12.

[0019] [Heater 14] The heater 14 heats the substrate 1 placed on the stage 12. This makes it possible to form the film 2 on the substrate 1 while raising the temperature of the substrate 1 and the film 2 with the heater 14.

[0020] [Gas supply unit 15] The gas supply unit 15 supplies one or more types of gas into the chamber 11. In this embodiment, these gases can be used to form a film 2 on the substrate 1. These gases may consist only of the source gas for the film 2, or they may also include other gases (e.g., a transport gas).

[0021] Tank 21 stores an indium-containing liquid (In-containing liquid). In this embodiment, Tank 21 stores an In-containing liquid that is liquid at room temperature. The In-containing liquid is, for example, TEIn (triethylindium) liquid. Heater 31 generates an indium-containing gas (In-containing gas) from the In-containing liquid by heating the In-containing liquid in Tank 21. The In-containing gas is, for example, TEIn gas. The In-containing gas is introduced into Chamber 11 via MFC 41. MFC 41 regulates the flow and flow rate of the In-containing gas. Each In-containing layer 2a shown in Figure 2(a) is formed using In-containing gas. The In-containing liquid is an example of the first liquid, the In-containing gas is an example of the first gas, and each In-containing layer 2a is an example of the first layer. Note that the substance contained in the In-containing liquid may be an In compound other than TEIn.

[0022] The In-containing solution in this embodiment contains aluminum along with indium. The In-containing solution in this embodiment is, for example, a TEIn solution containing TMAl (trimethylaluminum) as an impurity compound, and is produced by adding TMAl as a dopant to the TEIn solution. In this embodiment, the In-containing gas is a gas containing indium and aluminum, and each In-containing layer 2a is a layer containing indium and aluminum. Note that the Al compound contained in the In-containing solution may be something other than TMAl.

[0023] The In-containing solution of this embodiment contains indium and aluminum. Aluminum has a higher bond energy with oxygen and a lower free energy in the Ellingham diagram compared to indium. Therefore, the surface adsorption rate of aluminum is expected to be higher than that of indium, and Al compound molecules in the In-containing gas are expected to adsorb to the surface of the substrate 1 faster than In compound molecules in the In-containing gas. This makes it possible to increase the concentration of aluminum in the film 2 even if the concentration of aluminum in the In-containing solution is low.

[0024] For example, in a TEIn(In(C2H5)3) solution containing TMAl(Al(CH3)3), the In concentration is higher than the Al concentration. When the gas generated from such a TEIn solution and the O3 gas described later are supplied to the surface of substrate 1, In(OH)3 is formed on the surface of substrate 1. In this case, Al(CH3)3 is adsorbed faster than In(C2H5)3 on the surface of substrate 1 where In(OH)3 has been formed. The reason is that the activation energy (0.58 eV) of the following chemical formula (1) is lower than the activation energy (0.84 eV) of the following chemical formula (2).

[0025] In(OH)3+ Al(CH3)3 → InO3H2-Al(CH3)2+ CH4···(1) In(OH)3 + In(C2H5)3 → InO3H2-In(C2H5)2+ C2H6...(2) In this embodiment, the concentration of aluminum (g / L) in the In-containing solution is lower than the concentration of indium (g / L) in the In-containing solution. Investigations revealed that increasing the aluminum concentration in the In-containing solution to 50 ppb or higher significantly increased the aluminum concentration in film 2. Furthermore, it was found that a concentration of aluminum in the In-containing solution of 100 ppb or higher is even more desirable.

[0026] Tank 22 stores a gallium-containing liquid (Ga-containing liquid). In this embodiment, Tank 22 stores a Ga-containing liquid that is liquid at room temperature. The Ga-containing liquid is, for example, TEGa (triethylgallium) liquid. Heater 32 generates a gallium-containing gas (Ga-containing gas) from the Ga-containing liquid by heating the Ga-containing liquid in Tank 22. The Ga-containing gas is, for example, TEGa gas. The Ga-containing gas is introduced into Chamber 11 via MFC 42. MFC 42 regulates the flow and flow rate of the Ga-containing gas. Each Ga-containing layer 2b shown in Figure 2(a) is formed using the Ga-containing gas. The Ga-containing liquid is an example of a second liquid, the Ga-containing gas is an example of a second gas, and each Ga-containing layer 2b is an example of a second layer. Note that the substance contained in the Ga-containing liquid may be a Ga compound other than TEGa.

[0027] Tank 23 stores a zinc-containing liquid (Zn-containing liquid). In this embodiment, Tank 23 stores a Zn-containing liquid that is liquid at room temperature. The Zn-containing liquid is, for example, DEGa (diethylzinc) liquid. Heater 33 generates a zinc-containing gas (Zn-containing gas) from the Zn-containing liquid by heating the Zn-containing liquid in Tank 23. The Zn-containing gas is, for example, DEZn gas. The Zn-containing gas is introduced into Chamber 11 via MFC 43. MFC 43 regulates the flow and flow rate of the Zn-containing gas. Each Zn-containing layer 2c shown in Figure 2(a) is formed using the Zn-containing gas. The Zn-containing liquid is an example of a third liquid, the Zn-containing gas is an example of a third gas, and each Zn-containing layer 2c is an example of a third layer. Note that the substance contained in the Zn-containing liquid may be a Zn compound other than DEZn.

[0028] The gas source 24 supplies an oxygen-containing gas (O-containing gas). The gas source 24 may be located inside or outside the gas supply unit 15. The O-containing gas is, for example, O3 (ozone) gas. The O-containing gas is introduced into the chamber 11 via the MFC 44. The MFC 44 regulates the flow and flow rate of the O-containing gas. Each In-containing layer 2a, each Ga-containing layer 2b, and each Zn-containing layer 2c shown in Figure 2(a) are formed using the O-containing gas. In this embodiment, each In-containing layer 2a is an In-Al-O layer containing indium, aluminum, and oxygen; each Ga-containing layer 2b is a Ga-O layer containing gallium and oxygen; and each Zn-containing layer 2c is a Zn-O layer containing zinc and oxygen.

[0029] Hereinafter, the process of introducing an In-containing gas into the chamber 11 will be referred to as the "In introduction process," the process of introducing a Ga-containing gas into the chamber 11 will be referred to as the "Ga introduction process," the process of introducing a Zn-containing gas into the chamber 11 will be referred to as the "Zn introduction process," and the process of introducing an O-containing gas into the chamber 11 will be referred to as the "O introduction process."

[0030] The film 2 of this embodiment is formed by alternately repeating In introduction, Ga introduction, and Zn introduction processes. For example, each cycle of the process for forming film 2 is carried out by sequentially performing In introduction, O introduction, Ga introduction, O introduction, Zn introduction, and O introduction processes, and the process for forming film 2 is carried out by repeating multiple cycles. In each cycle, a purging process is performed after the completion of the In introduction process, after the completion of the first O introduction process, after the completion of the Ga introduction process, after the completion of the second O introduction process, after the completion of the Zn introduction process, and after the completion of the third O introduction process. The In introduction process, Ga introduction process, and Zn introduction process are examples of the first process, second process, and third process, respectively. Note that in each cycle, the In introduction process, Ga introduction process, and Zn introduction process may be performed in a different order than described above, or two or more In introduction processes, two or more Ga introduction processes, and / or two or more Zn introduction processes may be performed.

[0031] In this embodiment, the film 2 shown in Figure 2(a) is formed by alternately repeating the In introduction treatment, Ga introduction treatment, and Zn introduction treatment. Film 2 is formed to include multiple laminated films through multiple cycles of processing. Figure 2(a) shows examples of these laminated films, laminated film 2-1 and laminated film 2-2. Laminated film 2-1 is formed on the substrate 1 in the first cycle. Laminated film 2-2 is formed on laminated film 2-1 in the second cycle.

[0032] Each of the laminated films 2-1 and 2-2 includes an In-containing layer 2a, a Ga-containing layer 2b, and a Zn-containing layer 2c, which are stacked sequentially in the Z direction. For example, the In-containing layer 2a is formed by an In introduction treatment and a first O introduction treatment in each cycle, the Ga-containing layer 2b is formed by a Ga introduction treatment and a second O introduction treatment in each cycle, and the Zn-containing layer 2c is formed by a Zn introduction treatment and a third O introduction treatment in each cycle.

[0033] In this embodiment, the film 2 shown in Figure 2(a) is formed inside the chamber 11, and then the film 2 is annealed outside the chamber 11. As a result, the film 2 is transformed into the IGZO film shown in Figure 2(b). In this embodiment, multiple films, such as film 2, are formed on the substrate 1, and then the substrate 1 is divided into multiple chips (dicing) to manufacture the semiconductor device of this embodiment from the substrate 1.

[0034] In this embodiment, indium, gallium, zinc, and aluminum are examples of the first element, second element, third element, and predetermined element, respectively. However, the first element may be an element other than indium, the second element may be an element other than gallium, the third element may be an element other than zinc, and the predetermined element may be an element other than aluminum. In this case, it is desirable that the predetermined element has a larger bond energy with oxygen and / or a smaller free energy in the Ellingham diagram compared to the first element. This makes it possible to make the surface adsorption rate of the predetermined element greater than that of the first element. On the other hand, film 2 may not contain the second and third elements. Also, film 2 may not contain the third element, or it may contain the second and third elements, or it may contain the fourth to Nth elements (N is an integer of 4 or more) together with the first to third elements.

[0035] [Gas flow path 26] Each gas flow path 16 connects the gas supply unit 15 and the shower head 17. The semiconductor manufacturing apparatus of this embodiment includes a gas flow path 16 (In-containing gas flow path) between the tank 21 and the shower head 17, a gas flow path 16 (Ga-containing gas flow path) between the tank 22 and the shower head 17, a gas flow path 16 (Zn-containing gas flow path) between the tank 23 and the shower head 17, and a gas flow path 16 (O-containing gas flow path) between the gas source 24 and the shower head 17.

[0036] In-containing gas, Ga-containing gas, Zn-containing gas, and O-containing gas are supplied to the showerhead 17 via the In-containing gas channel, Ga-containing gas channel, Zn-containing gas channel, and O-containing gas channel, respectively. MFCs 41, 42, 43, and 44 are located on the In-containing gas channel, Ga-containing gas channel, Zn-containing gas channel, and O-containing gas channel, respectively.

[0037] [Shower head 17] The showerhead 17 supplies gas from each gas channel 16 into the chamber 11. As shown in Figure 1, the showerhead 17 is positioned above the stage 12 in the chamber 11. Therefore, the gas sprayed from the showerhead 17 reaches the surface of the substrate 1 on the stage 12. As a result, a film 2 is formed on the surface of the substrate 1.

[0038] [Control Unit 18] The control unit 18 controls various operations of the semiconductor manufacturing apparatus in this embodiment. For example, the control unit 18 controls the raising and lowering of the stage 12, the operation of the heater 14, the operation of the gas supply unit 15, and so on.

[0039] The control unit 18 operates the heater 31 to raise the temperature of the In-containing liquid in the tank 21 to a predetermined temperature. This makes it possible to vaporize the In-containing liquid into an In-containing gas. It is desirable to set the temperature of the In-containing liquid to a temperature suitable for vaporizing the In-containing liquid into an In-containing gas. Such a suitable temperature can be determined, for example, from the vapor pressure curve of the In-containing liquid. For example, the control unit 18 adjusts the temperature of the In-containing liquid in the tank 21 to 30-50°C.

[0040] Similarly, the control unit 18 operates the heater 32 to raise the temperature of the Ga-containing liquid in the tank 22 to a predetermined temperature. This makes it possible to vaporize the Ga-containing liquid into a Ga-containing gas. It is desirable to set the temperature of the Ga-containing liquid to a temperature suitable for vaporizing the Ga-containing liquid into a Ga-containing gas. Such a suitable temperature can be determined, for example, from the vapor pressure curve of the Ga-containing liquid. For example, the control unit 18 adjusts the temperature of the Ga-containing liquid in the tank 22 to 30-50°C.

[0041] Similarly, the control unit 18 operates the heater 33 to raise the temperature of the Zn-containing liquid in the tank 23 to a predetermined temperature. This makes it possible to vaporize the Zn-containing liquid into a Zn-containing gas. It is desirable to set the temperature of the Zn-containing liquid to a temperature suitable for vaporizing the Zn-containing liquid into a Zn-containing gas. Such a suitable temperature can be determined, for example, from the vapor pressure curve of the Zn-containing liquid. For example, the control unit 18 adjusts the temperature of the Zn-containing liquid in the tank 23 to 30-50°C.

[0042] Meanwhile, the control unit 18 operates the heater 14 to raise the temperature of the substrate 1 and film 2 on the stage 12 to a predetermined temperature. This makes it possible to form the film 2 at a suitable temperature. For example, the control unit 18 adjusts the temperature of the substrate 1 and film 2 on the stage 12 to 200-300°C.

[0043] As described above, the semiconductor manufacturing apparatus of this embodiment forms an aluminum-containing film 2 (IGZO film) using an aluminum-containing in-containing solution. This makes it possible to form film 2 without preparing an Al-containing solution in addition to the in-containing solution, thus simplifying the raw materials, processes, and equipment used to form film 2. Furthermore, since it is possible to form film 2 without introducing an Al-containing gas into the chamber 11 in addition to the in-containing gas, the process of forming film 2 can be performed in a short time and with fewer cycles. Moreover, as mentioned above, even if the concentration of aluminum in the in-containing solution is low, it is possible to increase the concentration of aluminum in film 2, making it possible to achieve in-situ and high-concentration aluminum doping. Thus, according to this embodiment, it is possible to suitably form film 2 containing multiple elements.

[0044] Figure 3 is a schematic diagram showing the configuration of a semiconductor manufacturing apparatus in a comparative example of the first embodiment. Figure 4 is a cross-sectional view showing a method for manufacturing a semiconductor device in a comparative example of the first embodiment.

[0045] The semiconductor manufacturing apparatus of this comparative example (Figure 3) has the same configuration as the semiconductor manufacturing apparatus of the first embodiment (Figure 1). However, the gas supply unit 15 of this comparative example includes a tank 25, a heater 35, and an MFC 45 in addition to the components shown in Figure 1. In this comparative example, film 2' is formed on the substrate 1 instead of film 2.

[0046] Tank 25 stores an aluminum-containing liquid (Al-containing liquid). In this comparative example, Tank 25 stores an Al-containing liquid that is liquid at room temperature. Heater 35 generates an aluminum-containing gas (Al-containing gas) from the Al-containing liquid by heating the Al-containing liquid in Tank 25. The Al-containing gas is introduced into Chamber 11 via MFC 45. MFC 45 regulates the flow and flow rate of the Al-containing gas. Each Al-containing layer 2d shown in Figure 4(a) is formed using Al-containing gas. Note that in this comparative example, the In-containing liquid in Tank 21 does not contain aluminum.

[0047] As shown in Figure 3, the semiconductor manufacturing apparatus of this comparative example includes a gas flow path 16 (Al-containing gas flow path) between the tank 25 and the shower head 17. The Al-containing gas is supplied to the shower head 17 via the Al-containing gas flow path. The MFC 45 is located on the Al-containing gas flow path.

[0048] Hereinafter, the process of introducing Al-containing gas into chamber 11 will be referred to as the "Al introduction process".

[0049] In this comparative example, film 2' shown in Figure 4(a) is formed by alternately repeating In introduction treatment, Al introduction treatment, Ga introduction treatment, and Zn introduction treatment. Film 2' is formed to include multiple laminated films through multiple cycles of processing. Figure 4(a) shows laminated film 2-1 and laminated film 2-2 as examples of these laminated films.

[0050] Each of the laminated films 2-1 and 2-2 contains an In-containing layer 2a', an Al-containing layer 2d, a Ga-containing layer 2b, and a Zn-containing layer 2c, which are stacked sequentially in the Z direction. In this comparative example, the In-containing layer 2a' is an In-O layer containing indium and oxygen, and the Al-containing layer 2d is an Al-O layer containing aluminum and oxygen.

[0051] In this comparative example, the film 2' shown in Figure 4(a) is formed inside the chamber 11, and then the film 2' is annealed outside the chamber 11. As a result, the film 2' is transformed into the IGZO film shown in Figure 4(b). In this embodiment, multiple films, such as film 2', are formed on the substrate 1, and then the substrate 1 is divided into multiple chips (dicing) to manufacture the semiconductor device of this comparative example from the substrate 1.

[0052] In this comparative example, since an Al-containing solution is prepared in addition to the In-containing solution to form film 2', the raw materials, processing, and equipment for forming film 2' become complex. Furthermore, since an Al-containing gas is introduced into the chamber 11 in addition to the In-containing gas to form film 2', the process of forming film 2' becomes long and involves many cycles. On the other hand, according to this embodiment, it is possible to form film 2 while suppressing these problems.

[0053] Figure 5 is a schematic diagram showing the configuration of a semiconductor manufacturing apparatus as a modified example of the first embodiment.

[0054] The semiconductor manufacturing apparatus of this modified example (Figure 5) has the same configuration as the semiconductor manufacturing apparatus of the first embodiment (Figure 1). However, the gas supply unit 15 of this modified example includes gas sources 51-53 and MFCs 61-63 instead of MFCs 41-43. In this modified example, similar to the first embodiment, the film 2 is formed on the substrate 1 in the flow shown in Figures 2(a) and 2(b).

[0055] The gas source 51 supplies a transport gas (e.g., argon gas) for transporting the in-containing gas into the tank 21. The gas source 51 may be located inside or outside the gas supply unit 15. The transport gas is supplied into the tank 21 via the MFC 61 and introduced into the chamber 11 from the tank 21 together with the in-containing gas. The MFC 61 can adjust the flow and flow rate of the in-containing gas by adjusting the flow and flow rate of the transport gas.

[0056] The gas source 52 supplies a transport gas (e.g., argon gas) for transporting the Ga-containing gas into the tank 22. The gas source 52 may be located inside or outside the gas supply unit 15. The transport gas is supplied into the tank 22 via the MFC 62 and introduced into the chamber 11 from the tank 22 together with the Ga-containing gas. The MFC 62 can adjust the flow and flow rate of the Ga-containing gas by adjusting the flow and flow rate of the transport gas.

[0057] The gas source 53 supplies a transport gas (e.g., argon gas) for transporting the Zn-containing gas into the tank 23. The gas source 53 may be located inside or outside the gas supply unit 15. The transport gas is supplied into the tank 23 via the MFC 63 and introduced into the chamber 11 from the tank 23 together with the Zn-containing gas. The MFC 63 can adjust the flow and flow rate of the Zn-containing gas by adjusting the flow and flow rate of the transport gas.

[0058] As described above, the semiconductor manufacturing apparatus of this embodiment forms an aluminum-containing film 2 (IGZO film) using an aluminum-containing in-containing liquid. Therefore, according to this embodiment, it is possible to simplify the raw materials, processes, and equipment for forming the film 2, and to perform the process of forming the film 2 in a short time and with fewer cycles, thereby enabling the suitability of forming a film 2 containing multiple elements.

[0059] (Second Embodiment) Figure 6 is a circuit diagram showing the configuration of a semiconductor device according to the second embodiment. The semiconductor device in this embodiment is, for example, a DRAM (Dynamic Random Access Memory). The semiconductor device in this embodiment corresponds to an example of the semiconductor device in the first embodiment.

[0060] The semiconductor device of this embodiment comprises a plurality of word lines WL extending in the row direction, a plurality of bit lines BL extending in the column direction, and a plurality of memory cells MC arranged in a two-dimensional array. Figure 6 shows three word lines WL as an example of a plurality of word lines WL. n WL n+1 WL n+2 (where n is an integer greater than or equal to 2). Figure 6 further shows three bit lines BL as an example of multiple bit lines BL. m BL m+1 BL m+2 This indicates that (m is an integer greater than or equal to 2).

[0061] Each memory cell MC includes a transistor Tr and a capacitor Cp, and is located near the intersection of a word line WL and a bit line BL. The gate of transistor Tr is electrically connected to the word line WL, one of the source and drain of transistor Tr is electrically connected to the bit line BL, and the other of the source and drain of transistor Tr is electrically connected to capacitor Cp. One electrode of capacitor Cp is electrically connected to transistor Tr, and the other electrode of capacitor Cp is electrically connected to the ground line.

[0062] Figure 7 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. As an example, Figure 7 shows cross-sections of four transistors Tr and four capacitors Cp that constitute four memory cells MC.

[0063] The semiconductor device of this embodiment comprises a substrate 101, a transistor 102, an interlayer insulating film 103, a plurality of contact plugs 104, a wiring layer 105, an interlayer insulating film 106, and an interlayer insulating film 107. The transistor 102 comprises a gate insulating film 102a, a gate electrode 102b, a sidewall insulating film 102c, and a source / drain region 102d.

[0064] The substrate 101 is, for example, a semiconductor substrate such as a Si substrate. In Figure 7, the surface of the substrate 101 is parallel to the X and Y directions and perpendicular to the Z direction. The substrate 101 in this embodiment corresponds to an example of the substrate 1 in the first embodiment.

[0065] The transistor 102 is formed on a substrate 101. The gate insulating film 102a and the gate electrode 102b are formed sequentially on the substrate 101, the sidewall insulating film 102c is formed on the side of the gate electrode 102b, and the source / drain region 102d is formed within the substrate 101. The semiconductor device of this embodiment comprises a plurality of transistors 102, and Figure 7 shows one of these transistors 102. These transistors Tr constitute, for example, the peripheral circuit of a DRAM.

[0066] The interlayer insulating film 103 is formed on the substrate 101 so as to cover these transistors 102. Each contact plug 104 is formed within the interlayer insulating film 103 on the gate electrode 102b or the source / drain region 102d. The wiring layer 105 is formed within the interlayer insulating film 103 on each contact plug 104. Figure 7 shows the three wirings included in the wiring layer 105. The interlayer insulating film 106 is formed on the interlayer insulating film 103 and the wiring layer 105. The interlayer insulating film 107 is formed on the interlayer insulating film 106.

[0067] Each capacitor Cp in this embodiment comprises a conductive layer 111, a dielectric layer 112, a conductive layer 113, and a conductive layer 114.

[0068] The conductive layer 111, dielectric layer 112, conductive layer 113, and conductive layer 114 are formed sequentially on the side and bottom surfaces of recesses formed within the interlayer insulating films 106 and 107. The conductive layer 111 is formed within the recess on the side surfaces of the interlayer insulating films 106 and 107 and on the upper surface of the wiring layer 105. The conductive layer 111 forms one electrode of each capacitor Cp, and the conductive layers 113 and 114 form the other electrode of each capacitor Cp. Each of the conductive layers 111, 113, and 114 is, for example, a semiconductor layer or a metal layer. The dielectric layer 112 is, for example, an SiO2 film.

[0069] The semiconductor device of this embodiment further comprises a conductive layer 121, an interlayer insulating film 122, and a via plug 123.

[0070] The conductive layer 121 includes multiple conductive layer portions arranged on multiple capacitors Cp. In Figure 7, the conductive layer 121 includes four conductive layer portions, each conductive layer portion arranged on the conductive layers 113, 114 of a corresponding capacitor Cp. Each conductive layer portion is arranged within a recess for a corresponding capacitor Cp.

[0071] The interlayer insulating film 122 is formed on the interlayer insulating film 107 so as to cover each capacitor Cp. The via plugs 123 are formed on the wiring layer 105 within the interlayer insulating films 106, 107, and 122.

[0072] Each transistor Tr in this embodiment comprises a semiconductor layer 131, an insulating film 132, and an electrode layer 133.

[0073] The semiconductor layer 131 is formed within a recess formed in the interlayer insulating film 122, via the insulating film 132. In Figure 7, the semiconductor layer 131 is formed on one conductive layer portion of the conductive layer 121. As a result, the semiconductor layer 131 of each transistor Tr is electrically connected to the conductive layers 113 and 114 of the corresponding capacitor Cp. The semiconductor layer 131 forms the channel semiconductor layer of each transistor Tr. The semiconductor layer 131 is, for example, an oxide semiconductor film such as an IGZO film. The semiconductor layer 131 in this embodiment corresponds to an example of film 2 in the first embodiment.

[0074] The insulating film 132 is formed on the side surface of a recess formed within the interlayer insulating film 122, and is formed on the side surface of the semiconductor layer 131 within the recess. The insulating film 132 forms the gate insulating film of each transistor Tr. The insulating film 132 is, for example, an SiO2 film.

[0075] The electrode layer 133 is formed on the via plug 123 within the interlayer insulating film 122. In Figure 7, the semiconductor layer 131 and insulating film 132 of each transistor Tr are formed sequentially on the side surface of the electrode layer 133, and the electrode layer 133 forms the gate electrode of each transistor Tr. Furthermore, the electrode layer 133 shown in Figure 7 forms a single word line WL for the four transistors Tr shown in Figure 7, extending in the X direction. The electrode layer 133 is, for example, a metal layer.

[0076] The semiconductor device of this embodiment further comprises a wiring layer 141 and an interlayer insulating film 142. The wiring layer 141 comprises a barrier metal layer 141a and a wiring material layer 141b.

[0077] The wiring layer 141 includes multiple wires arranged on multiple transistors Tr. The wiring layer 141 shown in Figure 7 includes four wires arranged on four transistors Tr and one additional wire. In Figure 7, each of the four wires is arranged on the semiconductor layer 131 of the corresponding transistor Tr. These four wires each form four bit lines BL for the four transistors Tr and extend in the Y direction. Each wire within the wiring layer 141 includes a barrier metal layer 141a and a wiring material layer 141b that are stacked sequentially in the Z direction.

[0078] The interlayer insulating film 142 is formed on the interlayer insulating film 122 so as to cover the wiring layer 141. The interlayer insulating film 142 is, for example, an SiO2 film.

[0079] Figures 8 to 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment.

[0080] First, a substrate 101 is prepared, and a transistor 102, an interlayer insulating film 103, multiple contact plugs 104, a wiring layer 105, an interlayer insulating film 106, and an interlayer insulating film 107 are formed on the substrate 101 (Figure 7).

[0081] Next, multiple recesses are formed within the interlayer insulating films 106 and 107, and multiple capacitors Cp are formed within these recesses (Figure 7). Each capacitor Cp is formed by sequentially forming a conductive layer 111, a dielectric layer 112, a conductive layer 113, and a conductive layer 114 within a single recess. The conductive layer 111 is formed on the wiring layer 105 within the recess. Subsequently, multiple conductive layer portions of the conductive layer 121 are also formed within the above-mentioned multiple recesses. Each conductive layer portion is formed on the conductive layers 113 and 114 within a single recess.

[0082] Next, an interlayer insulating film 122 is formed on the interlayer insulating film 107 and the conductive layer 121, via plugs 123 are formed within the interlayer insulating films 106, 107, and 122, and multiple transistors Tr are formed within the interlayer insulating film 122 (Figure 9). Each transistor Tr is formed to include a semiconductor layer 131, an insulating film 132, and an electrode layer 133 within the interlayer insulating film 122.

[0083] In Figure 9, the via plug 123 is formed by forming a via hole that penetrates the interlayer insulating film 106, the interlayer insulating film 107, and the interlayer insulating film 122 to reach the wiring layer 105, and then forming the via plug 123 within the via hole. The electrode layer 133 is formed by forming the electrode layer 133 on the lower part of the interlayer insulating film 122 and on the via plug 123, and forming the upper part of the interlayer insulating film 122 on the lower part of the interlayer insulating film 122 and on the electrode layer 133. The semiconductor layer 131 and insulating film 132 of each transistor Tr are formed by forming a recess within the interlayer insulating film 122 and electrode layer 133, and then sequentially forming the insulating film 132 and semiconductor layer 131 within the recess. The semiconductor layer 131 of each transistor Tr is formed on one conductive layer portion of the conductive layer 121. As a result, the semiconductor layer 131 of each transistor Tr is electrically connected to the conductive layers 113 and 114 of the corresponding capacitor Cp. The semiconductor layer 131 in this embodiment is formed, for example, by the same method as the film 2 in the first embodiment.

[0084] Next, a wiring layer 141 is formed on the interlayer insulating film 122 and the plurality of transistors Tr, and an interlayer insulating film 142 is formed on the interlayer insulating film 122 and the wiring layer 141 (Figure 10). As shown in Figure 10, the wiring layer 141 is formed to include a plurality of wirings arranged on the plurality of transistors Tr. In this way, the semiconductor device of this embodiment is manufactured.

[0085] According to this embodiment, it is possible to suitably form a semiconductor layer 131 corresponding to an example of the film 2 of the first embodiment.

[0086] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel methods described herein can be carried out in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0087] 1: Substrate, 2: Film, 2': Film, 2-1: Multilayer film, 2-2: Multilayer film 2a: In-containing layer, 2a': In-containing layer, 2b: Ga-containing layer, 2c: Zn-containing layer, 2d: Al-containing layer, 11: Chamber, 12: Stage, 13: Shaft, 14: Heater, 15: Gas supply unit, 16: Gas flow path, 17: Shower head, 18: Control unit, 21: Tank, 22: Tank, 23: Tank, 24: Gas source, 25: Tank, 31: Heater, 32: Heater, 33: Heater, 35: Heater, 41:MFC, 42:MFC, 43:MFC, 44:MFC, 45:MFC, 51: Gas source, 52: Gas source, 53: Gas source, 61: MFC, 62: MFC, 63: MFC, 101: circuit board, 102: transistor, 102a: Gate insulating film, 102b: Token electrode, 102c: Sidewall insulating film, 102d: Source / drain region, 103: Interlayer insulating film, 104: Contact plug, 105: Wiring layer, 106: Interlayer insulating film, 107: Interlayer insulating film, 111: conductive layer, 112: dielectric layer, 113: conductive layer, 114: conductive layer, 121: conductive layer, 122: interlayer insulating film, 123: via plug, 131: Semiconductor layer, 132: Insulating film, 133: Electrode layer, 141: Wiring layer, 141a: Barrier metal layer, 141b: Wiring material layer, 142: Interlayer insulating film

Claims

1. A first liquid is prepared containing a first element which is a metallic element or silicon, and a predetermined element which is a metallic element or silicon and is different from the first element. A first gas containing the first element and the predetermined element is generated from the first liquid. Using the first gas, a first film containing the first element and the predetermined element is formed on the substrate. A method for manufacturing a semiconductor device, including the following.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first film further contains oxygen.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the predetermined element has a larger bond energy with oxygen or a smaller free energy in the Ellingham diagram compared to the first element.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the first film is an oxide semiconductor film.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the concentration of the predetermined element in the first liquid is lower than the concentration of the first element in the first liquid.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the concentration of the predetermined element in the first liquid is 50 ppb or more.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the first liquid is produced by adding the predetermined element to a liquid containing the first element.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the first element is indium (In), gallium (Ga), zinc (Zn), tin (Sn), antimony (Sb), aluminum (Al), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), or tungsten (W).

9. The method for manufacturing a semiconductor device according to claim 1, wherein the predetermined element is indium (In), gallium (Ga), zinc (Zn), tin (Sn), antimony (Sb), aluminum (Al), silicon (Si), titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), or tungsten (W).

10. A second liquid is prepared, which is a metallic element or silicon and contains a second element different from the first element and the predetermined element. A second gas containing the second element is generated from the second liquid. This further includes, A method for manufacturing a semiconductor device according to claim 1, wherein the first film containing the first element, the second element, and the predetermined element is formed on the substrate using the first gas and the second gas.

11. A third liquid is prepared, which is a metallic element or silicon and contains a third element different from the first element, the second element, and the predetermined element. A third gas containing the third element is generated from the third liquid. This further includes, A method for manufacturing a semiconductor device according to claim 10, wherein the first film containing the first element, the second element, the third element, and the predetermined element is formed on the substrate using the first gas, the second gas, and the third gas.

12. A method for manufacturing a semiconductor device according to claim 11, wherein each of the first element, the second element, and the third element comprises indium (In), gallium (Ga), or Zn (zinc).

13. The method for manufacturing a semiconductor device according to claim 12, wherein the first film is an IGZO film.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the predetermined element is aluminum (Al).

15. The method for manufacturing a semiconductor device according to claim 14, wherein the first film is an IGZO film containing aluminum as an impurity element.

16. The method for manufacturing a semiconductor device according to claim 11, wherein the first film is formed by introducing the first gas, the second gas, and the third gas into a chamber containing the substrate.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the first film is formed by alternately repeating a first process of introducing the first gas into the chamber, a second process of introducing the second gas into the chamber, and a third process of introducing the third gas into the chamber.

18. The first film is A first layer is formed containing the first element and the predetermined element, A second layer containing the aforementioned second element is formed, A third layer containing the aforementioned third element is formed, Annealing the first layer, the second layer, and the third layer transforms the first layer, the second layer, and the third layer into the first film. A method for manufacturing a semiconductor device according to claim 11, wherein the semiconductor device is formed by the above.

19. A method for manufacturing a semiconductor device according to claim 1, further comprising forming a transistor including the first film.

20. A method for manufacturing a semiconductor device according to claim 19, further comprising forming a capacitor electrically connected to the transistor.

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