Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that control the lifetime of carriers within a semiconductor substrate. [Solution] The semiconductor device 100 comprises a first conductivity type drift region 18 provided on a semiconductor substrate 10, a second conductivity type region (including an anode region 11, a base region 14, and a contact region 15) provided above the drift region, a front electrode portion 52 provided above the semiconductor substrate, a back electrode portion 24 provided below the semiconductor substrate, and a trench-type lifetime control unit 60 extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. The trench-type lifetime control unit has a first polycrystalline silicon region 151 that is in direct contact with the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device in which polycrystalline silicon is embedded inside a semiconductor substrate has been known (see, for example, Patent Document 1 and Patent Document 2). [Prior Art Documents] [Patent Documents] [Patent Document 1] JP-A-2019-033140 [Patent Document 2] JP-A-2022-014917

Summary of the Invention

Problems to be Solved by the Invention

[0003] It is desirable to control the carrier lifetime inside the semiconductor substrate.

Means for Solving the Problems

[0004] <00000三十一日>In a first aspect of the present invention, a drift region of a first conductivity type provided in a semiconductor substrate, a second conductivity type region of a second conductivity type provided above the drift region, a front surface electrode portion provided above the semiconductor substrate, a back surface electrode portion provided below the semiconductor substrate, and a trench-type lifetime control portion provided to extend in the depth direction of the semiconductor substrate from the front surface of the semiconductor substrate are provided. The trench-type lifetime control portion may have a first polycrystalline silicon region that directly contacts the semiconductor substrate.

[0005] In the semiconductor device, the first polycrystalline silicon region may directly contact the drift region.

[0006] In any of the semiconductor devices described above, the trench-type lifetime control unit may be provided extending from the front surface of the semiconductor substrate, through the second conductivity type region, and into the interior of the drift region.

[0007] In any of the above semiconductor devices, the depth position of the lower end of the trench-type lifetime control unit in the depth direction of the semiconductor substrate may be 1 μm or more and 20 μm or less from the front surface of the semiconductor substrate.

[0008] In any of the above semiconductor devices, the trench width of the trench-type lifetime control unit may be 0.5 μm or more and 2.0 μm or less.

[0009] In any of the above semiconductor devices, the distance between the depth position of the upper end of the first polycrystalline silicon region and the depth position of the lower end of the second conductivity type region in the depth direction of the semiconductor substrate may be 0 μm or more and 1 μm or less.

[0010] In any of the above semiconductor devices, the depth position of the upper end of the first polycrystalline silicon region in the depth direction of the semiconductor substrate may be deeper than the depth position of the lower end of the second conductivity type region.

[0011] In any of the semiconductor devices described above, the depth position of the upper end of the first polycrystalline silicon region in the depth direction of the semiconductor substrate may be shallower than the depth position of the lower end of the second conductivity type region.

[0012] In any of the above semiconductor devices, the depth position of the upper end of the first polycrystalline silicon region in the depth direction of the semiconductor substrate may be 0 μm or more from the front surface of the semiconductor substrate, and may be half or less of the trench depth of the trench-type lifetime control unit.

[0013] In any of the semiconductor devices described above, the trench-type lifetime control unit may be provided above the first polycrystalline silicon region and may have a second polycrystalline silicon region having a different doping concentration from the first polycrystalline silicon region.

[0014] In any of the above-described semiconductor devices, the first polycrystalline silicon region may be undoped polycrystalline silicon. The second polycrystalline silicon region may be polycrystalline silicon of the second conductivity type.

[0015] In any of the above semiconductor devices, the first polycrystalline silicon region may be in direct contact with the drift region. The second polycrystalline silicon region may be in direct contact with the second conductivity type region.

[0016] Any of the above semiconductor devices may include a plurality of trenches, each containing at least one of a gate trench or a dummy trench. In the depth direction of the semiconductor substrate, the depth of the trench-type lifetime control unit may be the same as the depth of the plurality of trenches.

[0017] Any of the above semiconductor devices may include a plurality of trenches, each containing at least one of a gate trench or a dummy trench. In the depth direction of the semiconductor substrate, the depth of the trench-type lifetime control unit may be greater than the depth of the plurality of trenches.

[0018] Any of the above semiconductor devices may include a plurality of trenches, each containing at least one of a gate trench or a dummy trench. In the depth direction of the semiconductor substrate, the depth of the trench-type lifetime control unit may be shallower than the depth of the plurality of trenches.

[0019] Any of the above semiconductor devices may include a plurality of trenches, each containing at least one of a gate trench or a dummy trench. The trench width of the trench-type lifetime control unit may be the same as the trench width of the plurality of trenches.

[0020] In any of the semiconductor devices described above, a plurality of trench portions including at least one of the gate trench portion and the dummy trench portion may be provided. The trench width of the trench-type lifetime control portion may be larger than the trench widths of the plurality of trench portions.

[0021] In any of the semiconductor devices described above, a plurality of trench portions including at least one of the gate trench portion and the dummy trench portion may be provided. The trench width of the trench-type lifetime control portion may be smaller than the trench widths of the plurality of trench portions.

[0022] In any of the semiconductor devices described above, a plurality of trench portions including at least one of the gate trench portion and the dummy trench portion, a first mesa portion provided between the plurality of trench portions, and a second mesa portion adjacent to at least one of the trench-type lifetime control portions may be provided. The mesa width of the second mesa portion may be narrower than the mesa width of the first mesa portion.

[0023] In any of the semiconductor devices described above, the trench width of the trench-type lifetime control portion may be narrower than the mesa width of the second mesa portion.

[0024] In any of the semiconductor devices described above, the trench width of the trench-type lifetime control portion may be wider than the mesa width of the second mesa portion.

[0025] In any of the semiconductor devices described above, a diode portion which is a region where a cathode region of a first conductivity type is provided on the back surface of the semiconductor substrate, and a transistor portion which is a region where a collector region of a second conductivity type is provided on the back surface of the semiconductor substrate may be provided. The transistor portion may have a main region and a boundary region provided between the main region and the diode portion. The trench-type lifetime control portion may be provided in the boundary region.

[0026] In any of the semiconductor devices described above, the trench-type lifetime control unit may have a trench insulating film provided above the first polycrystalline silicon region.

[0027] In any of the above-described semiconductor devices, the trench insulating film may be provided on the first polycrystalline silicon region inside the trench-type lifetime control unit.

[0028] In any of the semiconductor devices described above, the trench insulating film may be provided above the first polycrystalline silicon region on the trench sidewall of the trench-type lifetime control unit.

[0029] In any of the above semiconductor devices, the trench-type lifetime control unit may have a non-contact polycrystalline silicon region provided on the trench insulating film.

[0030] In any of the above semiconductor devices, a diode portion may be provided on the back surface of the semiconductor substrate, which is a region in which a first conductive cathode region is provided. In the diode portion, the front electrode portion may be in direct contact with a first conductive region provided on the front surface of the semiconductor substrate.

[0031] In any of the semiconductor devices described above, the front electrode portion of the diode portion may be connected to the front surface of the semiconductor substrate using a Schottky connection.

[0032] In any of the above semiconductor devices, a transistor section may be provided on the back surface of the semiconductor substrate, which is a region in which a second conductive collector region is provided. On the outer periphery of the transistor section, there may be an outer peripheral lifetime control region in which a plurality of trench-type lifetime control units are arranged.

[0033] In any of the above semiconductor devices, a second conductivity type outer well region may be provided on the outer periphery of the transistor portion. The outer well region extends inward from the outer periphery of the transistor portion and may terminate in the middle of the outer lifetime control region.

[0034] In any of the semiconductor devices described above, the front electrode portion of the diode portion and the first polycrystalline silicon region may be in direct contact.

[0035] In any of the semiconductor devices described above, the front electrode portion may have a plug portion for contacting the first polycrystalline silicon region above the trench-type lifetime control unit.

[0036] Any of the above-described semiconductor devices may include a lifetime control region provided on the semiconductor substrate and formed by electron beam irradiation.

[0037] In any of the above semiconductor devices, an interlayer insulating film provided above the first polycrystalline silicon region may be included in the trench of the trench-type lifetime control unit.

[0038] A second aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a drift region of a first conductivity type on a semiconductor substrate; forming a trench-type lifetime control unit having a first polycrystalline silicon region that extends from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate and is in direct contact with the semiconductor substrate; providing a front surface electrode portion above the semiconductor substrate; and providing a back surface electrode portion below the semiconductor substrate.

[0039] The above-described method for manufacturing a semiconductor device may include a step of etching back the first polycrystalline silicon region. After the step of etching back the first polycrystalline silicon region, the method may include a step of forming a plurality of trenches extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate, a step of oxidizing the bottom and side walls of the plurality of trenches to form a trench insulating film, and a step of filling the trench insulating film with a non-contact polycrystalline silicon region.

[0040] In any of the above-described methods for manufacturing a semiconductor device, the method may include a step of forming a cap layer above the first polycrystalline silicon region after the step of etching back the first polycrystalline silicon region and before the step of forming the plurality of trenches.

[0041] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0042] [Figure 1A] This is an example of a top view of a semiconductor device 100. [Figure 1B] An example of a top view of the semiconductor device 100 is shown. [Figure 1C] This figure shows an example of a cross-section between b-b' in Figure 1B. [Figure 1D] This figure shows an example of the a-a' section in Figure 1A. [Figure 2A] This figure shows an example of a cross-section between b-b' in Figure 1B. [Figure 2B] This figure shows an example of a cross-section between b-b' in Figure 1B. [Figure 3] This figure shows a modified example of the XZ cross-section of semiconductor device 100. [Figure 4] This figure shows a modified example of the XZ cross-section of semiconductor device 100. [Figure 5] This figure shows a modified example of the XZ cross-section of semiconductor device 100. [Figure 6A]This figure shows an example of a cross-section between b-b' in Figure 1B. [Figure 6B] This figure shows an example of a cross-section between b-b' in Figure 1B. [Figure 7A] A modified example of the top view of the semiconductor device 100 is shown. [Figure 7B] This figure shows an example of a c-c' section in Figure 7A. [Figure 8A] A modified example of the top view of the semiconductor device 100 is shown. [Figure 8B] This figure shows an example of a d-d' section in Figure 8A. [Figure 9] This figure shows an example of a cross-section between b-b' in Figure 1B. [Figure 10A] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 10B] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 11A] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 11B] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 12] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 13A] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 13B] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 14A] An example of a manufacturing method for the semiconductor device 100 is shown. [Figure 14B] An example of a manufacturing method for the semiconductor device 100 is shown. [Modes for carrying out the invention]

[0043] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0044] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0045] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0046] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0047] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0048] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0049] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0050] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the bonding of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor; Si-iH defects, which are formed by the bonding of interstitial silicon (Si-i) and hydrogen; and CiOi-H defects, which are formed by the bonding of interstitial carbon (Ci), interstitial oxygen (Oi), and hydrogen, all function as electron donors. In this specification, these defects may be referred to as hydrogen donors.

[0051] In this specification, when P+ or N+ is mentioned, it means a higher doping concentration than P or N, and when P- or N- is mentioned, it means a lower doping concentration than P or N. Furthermore, when P++ or N++ is mentioned in this specification, it means a higher doping concentration than P+ or N+.

[0052] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by spheroidal resistance (SR) spectroscopy may be used as the net doping concentration. A carrier refers to an electron or hole charge carrier. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0053] Furthermore, if the concentration distribution of donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of donor, acceptor, or net doping in that region. In cases where the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping.

[0054] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state within the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, spreading resistance is measured, and the carrier concentration is converted from the measured value of spreading resistance. At this time, the carrier mobility of the crystalline state is used. On the other hand, at locations where lattice defects are introduced, the carrier concentration is calculated using the carrier mobility of the crystalline state, even though the carrier mobility is reduced. Therefore, the value will be lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0055] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that represent the donor or acceptor. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. This specification adopts the SI unit system. In this specification, units of distance and length may be expressed in cm (centimeters). In this case, calculations may be performed by converting to m (meters). Regarding the numerical representation of powers of 10, for example, the representation of 1E+16 is 1 × 10⁻⁶ 16 This indicates that the 1E-16 designation is 1 × 10 -16 This indicates.

[0056] Figure 1A is an example of a top view of a semiconductor device 100. The semiconductor device 100 comprises an active region 110, an outer peripheral region 120, and a gate pad 130. The semiconductor device 100 is a semiconductor chip comprising a transistor section 70 and a diode section 80.

[0057] The transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode section 80 includes a diode such as a freewheel diode (FWD). The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT) having the transistor section 70 and the diode section 80 on the same chip. In this example, the transistor in the transistor section 70 is an IGBT.

[0058] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an active region 110 and an outer peripheral region 120.

[0059] The transistor section 70 and the diode section 80 may be arranged alternately and periodically in the XY plane. The semiconductor device 100 in this example comprises a plurality of transistor sections 70 and a plurality of diode sections 80. The transistor section 70 and the diode section 80 in this example have trench sections extending in the Y-axis direction. However, the transistor section 70 and the diode section 80 may also have trench sections extending in the X-axis direction.

[0060] The active region 110 includes a transistor section 70 and a diode section 80. The active region 110 is the region in which the main current flows between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to the ON state. That is, it is the region in which current flows in the depth direction within the semiconductor substrate 10, from the front surface to the back surface, or from the back surface to the front surface. In this specification, the transistor section 70 and the diode section 80 are referred to as the element section or element region, respectively.

[0061] Furthermore, in a top view, the region sandwiched between the two element sections is also considered the active region 110. In this example, the region sandwiched between the element sections where the gate metal layer 50 is provided is also included in the active region 110.

[0062] The gate metal layer 50 is formed from a metal-containing material. For example, the gate metal layer 50 is formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor portion 70 and supplies a gate voltage to the transistor portion 70. In a top view, the gate metal layer 50 is provided so as to surround the outer periphery of the active region 110. The gate metal layer 50 is electrically connected to the gate pad 130 provided in the outer peripheral region 120. The gate metal layer 50 may be provided along the outer peripheral edge of the semiconductor substrate 10. The gate metal layer 50 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Also, in a top view, the gate metal layer 50 may be provided between the transistor portion 70 and the diode portion 80.

[0063] The outer peripheral region 120 is the region between the outer peripheral edge of the semiconductor substrate 10 and the active region 110, as seen from above. The outer peripheral region 120 is provided surrounding the active region 110 as seen from above. The outer peripheral region 120 may have an edge termination structure. The edge termination structure mitigates electric field concentration on the front side of the semiconductor substrate 10. For example, the edge termination structure may have a guard ring, a field plate, a resurf, or a structure combining these.

[0064] The gate pad 130 is electrically connected to the gate conductive part of the transistor section 70 via the gate metal layer 50. The gate pad 130 is set to the gate potential. In this example, the gate pad 130 is rectangular when viewed from above.

[0065] Figure 1B shows an example of a top view of the semiconductor device 100. In this example, it shows an enlarged view of region A in Figure 1A.

[0066] The transistor section 70 is a region on the back surface of the semiconductor substrate 10 in which a collector region 22 is provided. The collector region 22 has a second conductivity type. In this example, the collector region 22 is of type P+. The transistor section 70 includes a main region 75 and a boundary region 90 provided between the main region 75 and the diode section 80.

[0067] The diode section 80 is a region on the back surface of the semiconductor substrate 10 in which a first-conductivity cathode region is provided. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is of type N+.

[0068] The semiconductor device 100 in this example comprises, on the front surface of the semiconductor substrate 10, a trench-type lifetime control unit 60, a gate trench portion 40, a dummy trench portion 30, an anode region 11, an emitter region 12, a base region 14, a contact region 15, and an outer peripheral well region 17. The semiconductor device 100 in this example also comprises a front surface electrode portion 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.

[0069] The front electrode portion 52 is provided above the semiconductor substrate 10. The front electrode portion 52 is provided above the gate trench portion 40, the dummy trench portion 30, the anode region 11, the emitter region 12, the base region 14, the contact region 15, and the outer peripheral well region 17. The gate metal layer 50 is also provided above the outer peripheral well region 17. In this example, the front electrode portion 52 is set to the emitter potential of the transistor portion 70. The front electrode portion may be an emitter electrode.

[0070] The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor section 70 and supplies a gate voltage to the transistor section 70. The gate metal layer 50 is electrically connected to the gate pad 130. In a top view, the gate metal layer 50 is provided along the outer circumference of the active region 110. In a top view, the gate metal layer 50 may also be provided between the transistor section 70 and the diode section 80.

[0071] The front electrode portion 52 and the gate metal layer 50 are formed from a metal-containing material. For example, at least a portion of the front electrode portion 52 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The front electrode portion 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. The front electrode portion 52 and the gate metal layer 50 are provided separately from each other.

[0072] The front electrode portion 52 and the gate metal layer 50 are provided above the semiconductor substrate 10, with the interlayer insulating film 38 in between. The interlayer insulating film 38 is omitted in Figure 1B. Contact holes 54, 55, and 56 are provided through the interlayer insulating film 38.

[0073] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the gate trench 40. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0074] The contact hole 56 connects the front electrode portion 52 to the dummy conductive portion within the dummy trench portion 30. A plug made of tungsten or the like may be formed inside the contact hole 56.

[0075] The connecting portion 25 may electrically connect the front electrode portion 52 and the plug inside the contact hole 55. The connecting portion 25 may electrically connect the front electrode portion 52 and the plug inside the contact hole 56. The connecting portion 25 has a conductive material such as polysilicon doped with impurities. In this example, the connecting portion 25 is polysilicon doped with N-type impurities. When viewed from above, the connecting portion 25 covers a larger area than the contact hole 55. When viewed from above, the connecting portion 25 covers a larger area than the contact hole 56. The connecting portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0076] The gate trenches 40 are arranged at predetermined intervals along a predetermined alignment direction (in this example, the X-axis direction). The gate trenches 40 in this example may have two extended portions 41 that extend along an extension direction (in this example, the Y-axis direction) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the alignment direction, and a connecting portion 43 that connects the two extended portions 41.

[0077] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extended portions 41 of the gate trench portion 40, electric field concentration at the ends of the extended portions 41 can be mitigated. The gate metal layer 50 may be connected to the gate conductive portion at the connection portion 43 of the gate trench portion 40.

[0078] The dummy trench portion 30 is a trench portion electrically connected to the front surface electrode portion 52. The dummy trench portion 30, like the gate trench portion 40, is arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 in this example, like the gate trench portion 40, may have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extended portions 31 that extend along the stretching direction and a connecting portion 33 that connects the two extended portions 31.

[0079] The outer well region 17 is a second conductivity type region located on the front side of the semiconductor substrate 10, closer to the drift region 18, which will be described later. The outer well region 17 is an example of a well region located on the edge side of the semiconductor device 100. The outer well region 17 is, for example, of P+ type. The outer well region 17 is formed in a predetermined range from the end of the active region 110 on the side where the gate metal layer 50 is provided. The diffusion depth of the outer well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. A portion of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the outer well region 17. The bottom of the extending end of the gate trench portion 40 and the dummy trench portion 30 may be covered by the outer well region 17.

[0080] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are also provided above the anode region 11 and the base region 14 in the diode section 80. Furthermore, the contact holes 54 are provided above the contact region 15 in the boundary region 90. None of the contact holes 54 are provided above the outer peripheral well regions 17 located at both ends in the stretching direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film 38. The one or more contact holes 54 may be provided by extending in the stretching direction.

[0081] The main region 75 is the region of the transistor section 70 other than the boundary region 90. The channel region is formed in the main region 75 when the semiconductor device 100 is in operation. The main region 75 has an emitter region 12 and a contact region 15.

[0082] The boundary region 90 is provided in the transistor section 70 and is adjacent to the diode section 80. The boundary region 90 has a contact region 15. In this example, the boundary region 90 does not have an emitter region 12.

[0083] The trench-type lifetime control units 60, like the gate trench units 40 and dummy trench units 30, are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The trench-type lifetime control units 60, like the gate trench units 40 and dummy trench units 30, may have a U-shape on the front surface of the semiconductor substrate 10. That is, the trench-type lifetime control units 60 may have two extended portions 61 that extend along the stretching direction and a connecting portion 63 that connects the two extended portions 61.

[0084] The trench-type lifetime control unit 60 controls the lifetime of carriers when the semiconductor device 100 is switched off. The trench-type lifetime control unit 60 functions as a lifetime killer. The structure of the trench-type lifetime control unit 60 will be described later.

[0085] In this example, the trench-type lifetime control unit 60 is provided in the boundary region 90. This suppresses hole injection from the transistor section 70 to the diode section 80 when the semiconductor device 100 is turned off, thereby reducing the reverse recovery loss Err and the turn-off loss Eoff. The trench-type lifetime control unit 60 may be provided in the main region 75 or in the diode section 80.

[0086] The first mesa sections 71-1, 81-1, and 91-1 are mesa sections provided adjacent to the gate trench section 40 or dummy trench section 30 in a plane parallel to the front surface of the semiconductor substrate 10. The second mesa section 91-2 is a mesa section provided adjacent to the trench-type lifetime control section 60 in a plane parallel to the front surface of the semiconductor substrate 10. A mesa section is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench sections, and may be the portion from the front surface of the semiconductor substrate 10 to the depth of the deepest bottom of each trench section. The extended portion of each trench section may be considered as one trench section. That is, the region sandwiched between two extended portions may be considered as a mesa section.

[0087] The first mesa portion 71-1 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. On the front surface of the semiconductor substrate 10, the first mesa portion 71-1 has an outer well region 17, an emitter region 12, a base region 14, and a contact region 15. In the first mesa portion 71-1, the emitter region 12 and the contact region 15 are provided alternately in the stretching direction.

[0088] The first mesa portion 91-1 is provided in the boundary region 90. On the front surface of the semiconductor substrate 10, the first mesa portion 91-1 has a base region 14, a contact region 15, and an outer peripheral well region 17. In this example, both ends of the first mesa portion 91-1 in the alignment direction are in contact with the dummy trench portion 30, but at least one end may be in contact with the gate trench portion 40. In this example, one first mesa portion 91-1 is provided, but multiple first mesa portions 91-1 may be provided.

[0089] The second mesa portion 91-2 is provided in the boundary region 90. On the front surface of the semiconductor substrate 10, the second mesa portion 91-2 has a base region 14, a contact region 15, and an outer peripheral well region 17. In this example, the second mesa portion 91-2 is adjacent to at least one trench-type lifetime control unit 60. The second mesa portion 91-2 may be in contact with the trench-type lifetime control unit 60 at both ends.

[0090] The first mesa portion 81-1 is provided in the diode portion 80 in the region sandwiched between adjacent dummy trench portions 30. On the front surface of the semiconductor substrate 10, the first mesa portion 81-1 has an anode region 11, a base region 14, and an outer peripheral well region 17. The first mesa portion 81-1 has an outer peripheral well region 17 at the end of the trench extension direction of the plurality of trench portions. The base region 14 is provided inside the outer peripheral well region 17 in the first mesa portion 81-1. The anode region 11 is provided inside the base region 14 in the first mesa portion 81-1. The anode region 11 may be provided extending from one base region 14 to the other base region 14 of the first mesa portion 81-1 in the trench extension direction of the plurality of trench portions.

[0091] The anode region 11 is a second conductivity type region located on the front side of the semiconductor substrate 10 in the diode portion 80. The anode region 11 is, for example, P-type. The anode region 11 may be provided extending in the alignment direction from one of the two trench portions flanking the first mesa portion 81-1 to the other. The emitter region 12 is also provided below the contact hole 54.

[0092] The base region 14 is a second conductivity type region provided on the front side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. The base region 14 is, for example, P-type. The doping concentration of the base region 14 may be the same as, or greater than, the doping concentration of the anode region 11. The base region 14 may be provided at both ends in the stretching direction of the first mesa section 71-1, the first mesa section 81-1, the first mesa section 91-1, and the second mesa section 91-2 on the front side of the semiconductor substrate 10. Note that Figure 1B shows only one end of the base region 14 in the stretching direction.

[0093] The second conductivity region 19 is a region of the second conductivity type provided on the front side of the semiconductor substrate 10. The second conductivity region 19 is provided above the drift region 18. The second conductivity region 19 may include the anode region 11 and may include the base region 14. In this example, the second conductivity region 19 includes the anode region 11 and the base region 14. The second conductivity region 19 may also include regions of the second conductivity type other than the anode region 11 and the base region 14. For example, the second conductivity region 19 includes the contact region 15.

[0094] The emitter region 12 is a first conductivity type region with a higher doping concentration than the drift region 18. In this example, the emitter region 12 is N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface of the first mesa portion 71-1, in contact with the gate trench portion 40. The emitter region 12 may extend in the alignment direction from one of the two trench portions flanking the first mesa portion 71-1 to the other. The emitter region 12 is also provided below the contact hole 54.

[0095] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. The emitter region 12 does not need to be provided in the first mesa portion 91-1 of the boundary region 90.

[0096] The contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. In this example, the contact region 15 is of the P+ type. In this example, the contact region 15 is provided on the front surfaces of the first mesa portion 71-1, the first mesa portion 91-1, and the second mesa portion 91-2. The contact region 15 may be provided in the alignment direction from one of the two trench portions sandwiching the first mesa portion 71-1, the first mesa portion 91-1, or the second mesa portion 91-2 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. Also, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54. The contact area 15 may also be provided in the first mesa portion 81-1.

[0097] Figure 1C shows an example of the b-b' cross-section in Figure 1B. The b-b' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, a front electrode section 52, and a back electrode section 24 in the b-b' cross-section. The front electrode section 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0098] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0099] The field stop region 20 is a region of the first conductivity type located below the drift region 18. In this example, the field stop region 20 is N-type. The doping concentration of the field stop region 20 may be higher than the doping concentration of the drift region 18. The field stop region 20 prevents the depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0100] The collector region 22 is located below the field stop region 20 in the transistor section 70. The cathode region 82 is located below the field stop region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0101] The back electrode portion 24 is provided below the semiconductor substrate 10. The back electrode portion 24 is formed on the back surface 23 of the semiconductor substrate 10. The back electrode portion 24 is made of a conductive material such as metal. The back electrode portion 24 may be a collector electrode.

[0102] The base region 14 is a second conductive region located above the base region 14 in the first mesa portion 71, the first mesa portion 91-1, the second mesa portion 91-2, and the first mesa portion 81. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0103] The emitter region 12 is provided above the base region 14 in the first mesa portion 71. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 does not need to be provided in the first mesa portion 91-1 and the second mesa portion 91-2.

[0104] The contact area 15 is provided above the base area 14 in the first mesa section 91-1 and the second mesa section 91-2. In the first mesa section 91-1, the contact area 15 is provided in contact with the dummy trench section 30 and the trench-type lifetime control unit 60. In the second mesa section 91-2, the contact area 15 is provided in contact with the trench-type lifetime control unit 60. In other sections, the contact area 15 may be provided on the front surface 21 of the first mesa section 71.

[0105] The storage region 16 is a first conductivity type region located on the front surface 21 side of the semiconductor substrate 10, relative to the drift region 18. In this example, the storage region 16 is N-type. The storage region 16 is provided in the transistor section 70 and the diode section 80. In this example, the storage region 16 is not provided in the boundary region 90.

[0106] The storage region 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the storage region 16 is higher than the doping concentration of the drift region 18. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0107] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and storage region 16 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to cases where the doping region is formed before the trenches are formed. Cases where doping regions are formed between the trenches after the trenches have been formed are also included in cases where the trenches penetrate a doping region.

[0108] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0109] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces the adjacent base region 14 on the first mesa portion 71-1 side, with the gate insulating film 42 in between. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is created on the surface layer of the interface in contact with the gate trench within the base region 14.

[0110] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 by an interlayer insulating film 38.

[0111] The interlayer insulating film 38 is provided above the front surface 21. A front surface electrode portion 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the front surface electrode portion 52 and the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided penetrating the interlayer insulating film 38.

[0112] The trench-type lifetime control unit 60 is provided extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The trench-type lifetime control unit 60 extends from the front surface 21 of the semiconductor substrate 10, through the second conductivity type region 19, and into the interior of the drift region 18. The trench-type lifetime control unit 60 includes polycrystalline silicon in direct contact with the semiconductor substrate 10. The polycrystalline silicon has multiple grain boundaries, and these grain boundaries can function as lifetime killers. Here, the trench-type lifetime control unit 60 can be formed in any region of the semiconductor substrate 10, and the number and depth of the trenches can be adjusted as appropriate. Therefore, the trench-type lifetime control unit 60 can control the lifetime of carriers not only in the depth direction of the semiconductor substrate 10, but also in directions perpendicular to the depth direction (for example, in the X-axis direction or Y-axis direction). The trench-type lifetime control unit 60 has a first polycrystalline silicon region 151.

[0113] The first polycrystalline silicon region 151 is polycrystalline silicon filled in the trench-type lifetime control unit 60. The first polycrystalline silicon region 151 is in direct contact with the semiconductor substrate 10. By the first polycrystalline silicon region 151 being in direct contact with the semiconductor substrate 10, carriers in the semiconductor substrate 10 can be captured, thereby shortening the carrier lifetime. The first polycrystalline silicon region 151 may be in direct contact with the drift region 18.

[0114] The trench-type lifetime control unit 60 is provided at a depth Dp in the depth direction of the semiconductor substrate 10. The depth Dp of the trench-type lifetime control unit 60 may be the distance from the front surface 21 of the semiconductor substrate 10 to the lower end of the trench-type lifetime control unit 60. The depth Dp of the trench-type lifetime control unit 60 may be the same as or different from the depth Dt of the multiple trench sections, including the gate trench section 40 and the dummy trench section 30. In this example, the depth Dp of the trench-type lifetime control unit 60 is the same as the depth Dt of the multiple trench sections.

[0115] The depth position of the lower end of the trench-type lifetime control unit 60 in the depth direction of the semiconductor substrate 10 may be 1 μm or more and 20 μm or less from the top surface 21 of the semiconductor substrate 10. Since the trench-type lifetime control unit 60 does not participate in channel formation, it can be installed at a desired depth to control the lifetime of carriers.

[0116] The trench-type lifetime control unit 60 has a trench width Wp. The trench width may be the distance from one trench side wall to the other trench side wall in the direction of arrangement of the multiple trench sections and the trench-type lifetime control unit 60. The trench width Wp of the trench-type lifetime control unit 60 may be the same as or different from the trench width Wt of the multiple trench sections, including the gate trench section 40 and the dummy trench section 30. In this example, the trench width Wp of the trench-type lifetime control unit 60 is the same as the trench width Wt of the multiple trench sections.

[0117] The trench width Wp of the trench-type lifetime control unit 60 may be smaller than the mesa width Wm2 of the second mesa section 91-2. The mesa width may be the distance from one trench sidewall adjacent to a mesa section to the other opposing trench sidewall in the direction of arrangement of the multiple trench sections and the trench-type lifetime control unit 60. In one example, the trench width Wp of the trench-type lifetime control unit 60 is 0.5 μm or more and 2.0 μm or less.

[0118] The second mesa section 91-2 may have a mesa width Wm2, and the first mesa section 91-1 may have a mesa width Wm1. In this example, the mesa width Wm2 of the second mesa section 91-2 is the same as the mesa width Wm1 of the first mesa section 91-1. The mesa width Wm2 of the second mesa section 91-2 may be different from the mesa width Wm1 of the first mesa section 91-1.

[0119] Figure 1D shows an example of a cross-section from a-a' in Figure 1A. In this example, a cross-sectional view of the region spanning the active region 110 and the outer peripheral region 120 is shown. The active region 110 in this example has an outer peripheral lifetime control region 160 on the outer peripheral side of the transistor section 70, in which a plurality of trench-type lifetime control units 60 are arranged. The outer peripheral region 120 in this example has a guard ring structure and a channel stopper structure.

[0120] The guard ring structure may include multiple guard ring sections 92. The guard ring structure in this example includes five guard ring sections 92. Each guard ring section 92 may be provided on the front surface 21 so as to surround the active area 110.

[0121] The guard ring structure may have the function of spreading the depletion layer generated in the active region 110 to the outside of the semiconductor substrate 10. This prevents electric field concentration inside the semiconductor substrate 10. Therefore, the breakdown voltage of the semiconductor device 100 can be improved compared to when the guard ring structure is not provided.

[0122] The guard ring portion 92 is a P+ type semiconductor region formed near the front surface 21 by ion implantation. The guard ring portion 92 is electrically connected to the electrode layer 94. The electrode layer 94 may be made of the same material as the gate metal layer 50 or the front surface electrode portion 52.

[0123] Multiple guard ring portions 92 are electrically insulated from each other by an interlayer insulating film 38. The depth of the bottom of the guard ring portion 92 may be the same as the depth of the bottom of the outer peripheral well region 17. The depth of the bottom of the guard ring portion 92 may be deeper than the depth of the bottom of the gate trench portion 40 and the dummy trench portion 30.

[0124] The channel stopper structure includes a channel stopper region 96 and an electrode layer 94. The channel stopper region 96 is electrically connected to the electrode layer 94 through an opening in the interlayer insulating film 38. The conductivity type of the channel stopper region 96 may be either a first conductivity type or a second conductivity type. In this example, the conductivity type of the channel stopper region 96 is N+ type. The channel stopper region 96 has the function of terminating the depletion layer generated in the active region 110 at the outer edge of the semiconductor substrate 10.

[0125] The outer well region 17 may be provided such that the distance between the innermost guard ring portion 92 in the outer well region 120 and the outer end of the outer well region 17 is close. Above the outer well region 17, an oxide film 39 may be provided between the contact region 15 and the gate runner 51. The oxide film 39 may be formed in the same process as the dummy insulating film 32 or the gate insulating film 42. Alternatively, the oxide film 39 may be formed in a process such as forming a field oxide film with a thicker film thickness.

[0126] The outer well region 17 is provided extending from the boundary between the outer well region 120 and the active region 110 toward the active region 110. That is, the outer well region 17 is provided extending inward from the outer periphery of the transistor section 70. In this example, the outer well region 17 extends inward from the outer periphery of the transistor section 70 and terminates midway through the outer lifetime control region 160. This allows for the capture of carriers flowing inward from the outer periphery of the transistor section 70, thereby adjusting the lifetime of carriers on the outer periphery of the transistor section 70.

[0127] Figure 2A shows an example of the b-b' section in Figure 1B. We will use Figure 2A to explain the differences between it and Figure 1C.

[0128] In the example shown in Figure 2A, the depth Dp of the trench-type lifetime control unit 60 is different from the depth Dt of the multiple trenches, including the gate trench 40 and the dummy trench 30. In this example, in the depth direction of the semiconductor substrate 10, the depth Dp of the trench-type lifetime control unit 60 is deeper than the depth Dt of the multiple trenches. This suppresses hole injection from the transistor 70 to the diode 80 during the turn-off of the semiconductor device 100, thereby reducing the reverse recovery loss Err and the turn-off loss Eoff.

[0129] Figure 2B shows an example of a cross-section between b-b' in Figure 1B. The differences between Figure 2B and Figure 1C will be explained using Figure 2B.

[0130] In the example shown in Figure 2B, the depth Dp of the trench-type lifetime control unit 60 is different from the depth Dt of the multiple trenches, including the gate trench 40 and the dummy trench 30. In this example, in the depth direction of the semiconductor substrate 10, the depth Dp of the trench-type lifetime control unit 60 is shallower than the depth Dt of the multiple trenches. When it is desired to apply lifetime control only to the vicinity of the front surface 21 of the semiconductor substrate, the depth Dp of the trench-type lifetime control unit 60 can be set to a shallower depth, thereby limiting lifetime control to the vicinity of the front surface 21.

[0131] The depth Dp of the trench-type lifetime control unit 60 may be changed depending on where the trench-type lifetime control unit 60 is installed. The depth Dp of the trench-type lifetime control unit 60 may differ depending on whether it is installed in the boundary region 90 or in the outer peripheral lifetime control region 160. This allows for fine-tuning of the characteristics of the semiconductor device 100.

[0132] Figure 3 shows a modified example of the XZ cross-section of semiconductor device 100. The differences from Figure 1C will be explained using Figure 3.

[0133] In the example in Figure 3, the number of trench-type lifetime control units 60 provided in the boundary region 90 differs from that in the example in Figure 1C. In the example in Figure 3, four trench-type lifetime control units 60 are provided. By increasing the number of trench-type lifetime control units 60, the reverse recovery loss Err and turn-off loss Eoff of the semiconductor device 100 can be reduced. In the example in Figure 3, the trench width Wp of the trench-type lifetime control units 60 is the same as in the example shown in Figure 1C.

[0134] The number of trench-type lifetime control units 60 is not limited to this example. The number of trench-type lifetime control units 60 may be one or three or more. By reducing the number of trench-type lifetime control units 60, the saturation voltage Vce(sat) of the transistor unit 70 and the forward voltage Vf of the diode unit 80 can be reduced.

[0135] The mesa width Wm2 of the second mesa section 91-2 may be different from the mesa width Wm1 of the first mesa section 91-1. In this example, the mesa width Wm2 of the second mesa section 91-2 is narrower than the mesa width Wm1 of the first mesa section 91-1. The mesa width Wm2 of the second mesa section 91-2 may be narrower than the trench width Wp of the trench-type lifetime control unit 60. That is, in this example, the trench width Wp of the trench-type lifetime control unit 60 is wider than the mesa width Wm2 of the second mesa section 91-2. Since no channel is formed in the second mesa section 91-2 when the semiconductor device 100 is operating, the carrier lifetime can be adjusted without reducing the saturation current of the semiconductor device 100.

[0136] Figure 4 shows a modified example of the XZ cross-section of semiconductor device 100. The differences from Figure 1C will be explained using Figure 4.

[0137] In the example shown in Figure 4, the trench width Wp of the trench-type lifetime control unit 60 is different from the trench width Wt of the multiple trench sections, including the gate trench section 40 and the dummy trench section. In this example, the trench width Wp of the trench-type lifetime control unit 60 is smaller than the trench width Wt of the multiple trench sections. This reduces the saturation voltage Vce(sat) of the transistor section 70 and the forward voltage Vf of the diode section 80.

[0138] The trench width Wp of the trench-type lifetime control unit 60 may be 10% or more, 20% or more, or 40% or more of the trench width Wt of the multiple trench sections. The trench width Wp of the trench-type lifetime control unit 60 may be 90% or less, 80% or less, or 70% or less of the trench width Wt of the multiple trench sections. In one example, the trench width Wp of the trench-type lifetime control unit 60 is 50% of the trench width Wt of the multiple trench sections.

[0139] When the trench width Wp of the trench-type lifetime control unit 60 differs from the trench width Wt of the multiple trench sections, the depth position Dp at the lower end of the trench-type lifetime control unit 60 may be the same as or different from the depth position Dt at the lower end of the multiple trench sections. In this example, the depth position Dp at the lower end of the trench-type lifetime control unit 60 is the same as the depth position Dt at the lower end of the multiple trench sections. By adjusting the trench width Wp and the depth position Dp at the lower end of the trench-type lifetime control unit 60, the performance of the trench-type lifetime control unit 60 can be finely adjusted.

[0140] Figure 5 shows a modified example of the XZ cross-section of semiconductor device 100. The differences from Figure 1C will be explained using Figure 5.

[0141] In the example shown in Figure 5, the trench width Wp of the trench-type lifetime control unit 60 is different from the trench width Wt of the multiple trench sections, including the gate trench section 40 and the dummy trench section. In this example, the trench width Wp of the trench-type lifetime control unit 60 is larger than the trench width Wt of the multiple trench sections. This reduces the reverse recovery loss Err and the turn-off loss Eoff of the semiconductor device 100.

[0142] The trench width Wp of the trench-type lifetime control unit 60 may be 110% or more, 120% or more, or 130% or more of the trench width Wt of the multiple trench sections. The trench width Wp of the trench-type lifetime control unit 60 may be 200% or less, 190% or less, 180% or less, or 170% or less of the trench width Wt of the multiple trench sections. In one example, the trench width Wp of the trench-type lifetime control unit 60 is 150% of the trench width Wt of the multiple trench sections. Adjacent trench-type lifetime control units 60 may be separated by the semiconductor substrate 10, or they may be touching. In this example, adjacent trench-type lifetime control units 60 are separated by the semiconductor substrate 10.

[0143] Figure 6A shows an example of a cross-section between b-b' in Figure 1B. We will use Figure 6A to explain the differences between it and Figure 1C.

[0144] In the example shown in Figure 6A, the structure of the trench-type lifetime control unit 60 differs from that of the example shown in Figure 1C. The trench-type lifetime control unit 60 in this example has a first polycrystalline silicon region 151, a trench insulating film 62 provided above the first polycrystalline silicon region 151, and a non-contact polycrystalline silicon region 64 provided on the trench insulating film 62.

[0145] The trench insulating film 62 is provided on the first polycrystalline silicon region 151 inside the trench-type lifetime control unit 60. The trench insulating film 62 may be formed above the first polycrystalline silicon region 151, covering the trench sidewalls of the trench-type lifetime control unit 60.

[0146] The trench insulating film 62 may be formed by oxidizing or nitriding the inner walls of the trenches of the trench-type lifetime control unit 60 and the upper surface of the first polycrystalline silicon region 151. The trench insulating film 62 may be formed in the same process as the gate insulating film 42 and the dummy insulating film 32, or in a different process. The trench insulating film 62 may have the same film thickness as the gate insulating film 42 and the dummy insulating film 32. In this example, the film thickness of the trench insulating film 62 is the same as the film thickness of the gate insulating film 42 and the dummy insulating film 32. The film thickness of the trench insulating film 62 formed on the upper surface of the first polycrystalline silicon region 151 may be greater than the film thickness of the trench insulating film 62 formed on the trench side walls of the trench-type lifetime control unit 60.

[0147] The non-contact polycrystalline silicon region 64 is formed inside the trench of the trench-type lifetime control unit 60, on the inside of the trench insulating film 62. The trench insulating film 62 insulates the non-contact polycrystalline silicon region 64 from the semiconductor substrate 10. That is, the non-contact polycrystalline silicon region 64 is a region of polycrystalline silicon that is not in direct contact with the semiconductor substrate 10. In Figure 6A, hatching is shown on the non-contact polycrystalline silicon region 64 for illustrative purposes, but the non-contact polycrystalline silicon region 64 may be formed from the same material as the first polycrystalline silicon region 151. The material of the non-contact polycrystalline silicon region 64 may be the same as the material of the gate conductive portion 44 and the dummy conductive portion 34.

[0148] In the trench-type lifetime control unit 60, the trench interior does not need to be completely filled with the first polycrystalline silicon region 151. By providing a trench insulating film 62 and a non-contact polycrystalline silicon region 64 on the first polycrystalline silicon region 151, the upper end of the first polycrystalline silicon region 151 may be located at a predetermined distance deeper than the front surface 21 of the semiconductor substrate 10. In this example, in the depth direction of the semiconductor substrate 10, the depth position D151 of the upper end of the first polycrystalline silicon region 151 is 0 μm or more from the front surface 21 of the semiconductor substrate 10 and less than or equal to half the trench depth Dp of the trench-type lifetime control unit 60. That is, in the trench-type lifetime control unit 60, the first polycrystalline silicon region 151 may occupy an area of ​​more than half the trench depth Dp.

[0149] In the depth direction of the semiconductor substrate 10, the depth position of the upper end of the first polycrystalline silicon region 151 may be shallower than the depth position of the lower end of the second conductivity type region 19, and may be deeper than the depth position of the lower end of the second conductivity type region 19. In this example, in the depth direction of the semiconductor substrate 10, the depth position D151 of the upper end of the first polycrystalline silicon region 151 is shallower than the depth position D19 of the lower end of the second conductivity type region D19. The depth position D19 of the lower end of the second conductivity type region 19 may be the depth position of the lower end of the base region 14, or the depth position of the lower end of the anode region 11. If the depth positions of the lower ends of the base region 14 and the anode region 11 are different, the depth position of the lower end of the region that extends to a deeper position may be used as the depth position D19 of the lower end of the second conductivity type region 19.

[0150] Figure 6B shows an example of a cross-section between b-b' in Figure 1B. We will use Figure 6B to explain the differences between it and Figure 6A.

[0151] Figure 6B shows that the depth position D151 of the upper end of the first polycrystalline silicon region 151 in the depth direction of the semiconductor substrate 10 is different from that in Figure 6A. In this example, in the depth direction of the semiconductor substrate 10, the depth position D151 of the upper end of the first polycrystalline silicon region 151 is deeper than the depth position D19 of the lower end of the second conductivity type region D19. In the depth direction of the semiconductor substrate 10, the distance between the depth position D151 of the upper end of the first polycrystalline silicon region 151 and the depth position D19 of the lower end of the second conductivity type region 19 may be 0 μm or more and 1 μm or less. That is, the depth position D151 of the upper end of the first polycrystalline silicon region 151 may be set within a range of ±1 μm from the depth position D19 of the lower end of the second conductivity type region 19.

[0152] Figure 7A shows a modified top view of the semiconductor device 100. The differences between Figure 7A and Figure 1B will be explained using Figure 7A.

[0153] The semiconductor device 100 in Figure 7A has at least a diode section 80. In the example in Figure 7A, a trench-type lifetime control section 60 is provided in the diode section 80. The diode section 80 has a first mesa section 81-1 and a second mesa section 81-2.

[0154] The second mesa portion 81-2 is provided in the diode portion 80. On the front surface of the semiconductor substrate 10, the second mesa portion 81-2 has an anode region 11, a base region 14, and an outer peripheral well region 17. In this example, the second mesa portion 81-2 is adjacent to at least one trench-type lifetime control unit 60. The second mesa portion 81-2 may be in contact with the trench-type lifetime control unit 60 at both ends.

[0155] Figure 7B shows an example of a c-c' cross section in Figure 7A. The c-c' cross section is the XZ plane passing through the anode region 11. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, a front electrode portion 52, and a back electrode portion 24 in the c-c' cross section. The trench-type lifetime control unit 60 in this example has a first polycrystalline silicon region 151 and a second polycrystalline silicon region 152.

[0156] The second polycrystalline silicon region 152 is located above the first polycrystalline silicon region 151 and has a different doping concentration from the first polycrystalline silicon region 151. In this example, the doping concentration of the second polycrystalline silicon region 152 is greater than that of the first polycrystalline silicon region 151. In this example, the first polycrystalline silicon region 151 is undoped polycrystalline silicon, and the second polycrystalline silicon region 152 is polycrystalline silicon of the second conductivity type.

[0157] The second polycrystalline silicon region 152 is provided in direct contact with the first polycrystalline silicon region 151. The depth position of the boundary between the first polycrystalline silicon region 151 and the second polycrystalline silicon region 152 may be the same as the depth position of the lower end of the anode region 11. In this example, the first polycrystalline silicon region 151 is in direct contact with the drift region 18, and the second polycrystalline silicon region 152 is in direct contact with the second conductivity region 19. This makes it possible to homogenize the electric field within the semiconductor device 100.

[0158] Figure 8A shows a modified top view of the semiconductor device 100. The differences between Figure 8A and Figure 7A will be explained using Figure 8A.

[0159] In the example shown in Figure 8A, the anode region 11 is not provided on the front surface of the diode portion 80, and a region of the first conductivity type is provided. In this example, the region of the first conductivity type is the drift region 18. That is, in Figure 8A, the first mesa portion 81-1 and the second mesa portion 81-2 have a base region 14, an outer well region 17, and a drift region 18 on the front surface of the semiconductor substrate 10.

[0160] In the example shown in Figure 8A, a contact hole 56 is provided above the trench-type lifetime control unit 60. Unlike the contact hole 56 provided in the dummy trench section 30, the contact hole 56 provided in the trench-type lifetime control unit 60 does not need to have a connection section 25.

[0161] Figure 8B shows an example of the d-d' section in Figure 8A. We will use Figure 8B to explain the differences between it and Figure 7B.

[0162] In the example shown in Figure 8B, the front electrode portion 52 is in direct contact with a region of the first conductivity type provided on the front surface 21 of the semiconductor substrate 10. The region of the first conductivity type may be a drift region 18, or another region that can be formed by ion implantation of a dopant. In this example, the front electrode portion 52 is in direct contact with the drift region 18.

[0163] The front electrode portion 52 may be Schottky connected to the front surface 21 of the semiconductor substrate 10. The front electrode portion 52 may contain a material that can form a Schottky connection with the front surface 21 of the semiconductor substrate 10. For example, the front electrode portion 52 may contain Pt. As a result, when the semiconductor device 100 is in operation, holes are injected only from the first polycrystalline silicon region 151, thereby reducing the amount of holes injected in the diode portion 80.

[0164] The front electrode portion 52 is in direct contact with the first polycrystalline silicon region 151. In this example, the front electrode portion 52 is in direct contact with the first polycrystalline silicon region 151 inside the contact hole 56. The front electrode portion 52 has a plug portion 27 for contacting the first polycrystalline silicon region 151 above the trench-type lifetime control unit 60.

[0165] The plug portion 27 is embedded inside the contact hole 56 and contacts the first polycrystalline silicon region 151. The plug portion 27 is made of a conductive material. The material of the plug portion 27 may be the same as or different from the material of the front electrode portion 52. The material of the plug portion 27 may be tungsten or molybdenum.

[0166] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. At least a portion of the interlayer insulating film 38 may be provided within the trench of the trench-type lifetime control unit 60. Within the trench of the trench-type lifetime control unit 60, the interlayer insulating film 38 is provided above the first polycrystalline silicon region 151.

[0167] Figure 9 shows an example of a cross-section between b-b' in Figure 1B. Figure 9 will be used to explain the differences between it and Figure 1C.

[0168] The semiconductor device 100 in this example includes a lifetime control region 150 formed by electron beam irradiation. The lifetime control region 150 formed by electron beam irradiation is provided over the entire semiconductor substrate 10. In this example, by using a trench-type lifetime control unit 60 and the lifetime control region 150 in combination, the lifetime of carriers can be controlled more precisely compared to the case where only the lifetime control region 150 is provided.

[0169] Figure 10A shows an example of a method for manufacturing the semiconductor device 100. In this example, the order of each step may be changed as appropriate.

[0170] In step S110, a drift region 18 of the first conductivity type is provided on the semiconductor substrate 10. The drift region 18 may be a region remaining on the semiconductor substrate 10 where no other doping regions have been formed. That is, in step S110, in which the drift region 18 is provided on the semiconductor substrate 10, the semiconductor substrate 10 may be fabricated by growing single-crystal silicon.

[0171] In step S120, a trench-type lifetime control unit 60 is formed. Step S120 may include the steps of extending a lifetime control trench from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10, and filling a first polycrystalline silicon region 151, which is polycrystalline silicon that is in direct contact with the semiconductor substrate 10. Details of step S120 will be described later.

[0172] In step S130, a front electrode portion 52 is provided above the semiconductor substrate 10. In step S140, a back electrode portion 24 is provided below the semiconductor substrate 10. The order of steps S130 and S140 may be reversed.

[0173] Figure 10B shows an example of a manufacturing method for the semiconductor device 100. Using Figure 10B, we will explain in detail the step S120 in which the trench-type lifetime control unit 60 is formed.

[0174] In step S121, a hard mask 35 is formed on the front surface 21 of the semiconductor substrate 10. The hard mask 35 may be an insulating film such as silicon oxide. In step S122, a resist mask 36 is formed on the hard mask 35 and the resist mask 36 is exposed. The resist mask 36 is a photosensitive mask such as a photoresist. This allows for selective exposure of the upper surface of the hard mask 35 above the portion where the trench-type lifetime control unit 60 is formed.

[0175] In step S123, a lifetime control trench 65 is formed. The lifetime control trench 65 is formed by etching the semiconductor substrate 10. The etching may be dry etching or wet etching. In step S124, a first polycrystalline silicon region 151 is formed. The first polycrystalline silicon region 151 may be formed by filling the lifetime control trench 65 with polycrystalline silicon.

[0176] In step S125, the first polycrystalline silicon region 151 is etched back. This allows adjustment of the depth position of the upper end of the first polycrystalline silicon region 151. The depth position of the upper end of the first polycrystalline silicon region 151 may be the same as the position of the front surface 21 of the semiconductor substrate 10. That is, the lifetime control trench 65 may be completely filled with the first polycrystalline silicon region 151.

[0177] Figure 11A shows an example of a manufacturing method for the semiconductor device 100. Each step from step S110 to step S122 will be explained using Figure 11A.

[0178] In step S110, a drift region 18 is provided on the semiconductor substrate 10. In step S121, a hard mask 35 is formed on the front surface 21 of the semiconductor substrate 10. The hard mask 35 may be formed over the entire surface of the front surface 21 of the semiconductor substrate 10. Next, in step S122, a resist mask 36 is formed on the hard mask 35 and the resist mask 36 is exposed. This allows the upper surface of the hard mask 35 to be selectively exposed in the region where the trench-type lifetime control unit 60 is formed.

[0179] Figure 11B shows an example of a method for manufacturing the semiconductor device 100. Figure 11B is a continuation of step S122, which was explained using Figure 11A. Each step from step S123 to step S125 will be explained using Figure 11B.

[0180] In step S123, a lifetime control trench 65 is formed. The lifetime control trench 65 is provided extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Then, in step S124, the first polycrystalline silicon region 151 is formed by filling the lifetime control trench 65 with polycrystalline silicon. In step S124, the resist mask 36 may be removed before the polycrystalline silicon is filled. The polycrystalline silicon may be deposited not only inside the lifetime control trench 65 but also on top of the hard mask 35.

[0181] In step S125, the first polycrystalline silicon region 151 is etched back. This removes excess polycrystalline silicon that had accumulated above the hard mask 35, etc. In this example, the first polycrystalline silicon region 151 is etched back so that the depth position of the upper end of the first polycrystalline silicon region 151 is the same as the position of the front surface 21 of the semiconductor substrate 10. The first polycrystalline silicon region 151 may be etched back to a predetermined depth from the front surface 21 of the semiconductor substrate 10.

[0182] Figure 12 shows an example of a method for manufacturing the semiconductor device 100. This example shows one method for manufacturing the semiconductor device 100, and the order of each step may be changed as appropriate. Step S120 is the same as described above, so the explanation is omitted.

[0183] In step S126, a cap layer 66 is formed above the first polycrystalline silicon region 151. The cap layer 66 is used to protect the first polycrystalline silicon region 151 in the etching process for forming a plurality of trenches, which will be described later. The cap layer 66 may be a silicon oxide film, a BPSG (Boro-phospho Silicate Glass) film, a high-temperature silicon oxide (HTO) film, or a CVD (Chemical Vapor Deposition) oxide film.

[0184] In step S152, a resist mask 36 is formed on the hard mask 35, and the resist mask 36 is exposed. This allows for selective exposure of the upper surface of the hard mask above the portion where the multiple trenches are to be formed. In step S153, the multiple trenches are formed. The multiple trenches are formed by etching the semiconductor substrate 10, similar to when forming the lifetime-controlled trenches 65.

[0185] In step S160, the hard mask 35 is removed. The hard mask 35 may be removed by wet etching. In step S160, the cap layer 66 formed above the first polycrystalline silicon region 151 may be removed.

[0186] In step S161, a trench insulating film 62 is formed. In step S161, the trench insulating film 62 is formed on the front surface 21 of the semiconductor substrate 10, the inner walls and bottoms of the trenches of the plurality of trenches, and the inner walls of the lifetime control trench 65 and the upper surface of the first polycrystalline silicon region 151. In step S161, a gate insulating film 42 or a dummy insulating film 32 may be formed.

[0187] In step S154, a non-contact polycrystalline silicon region 64 is filled onto the trench insulating film 62. In step S154, a gate conductive portion 44 or a dummy conductive portion 34 may be formed. In step S154, the trench insulating film 62 formed on the front surface 21 of the semiconductor substrate 10 may be removed.

[0188] Figure 13A shows an example of a manufacturing method for the semiconductor device 100. Using Figure 13A, each step from step S120 to step S152 in Figure 12 will be explained.

[0189] In Figure 13A, step S120 shows the state after the etch-back of the first polycrystalline silicon region 151 has been completed. In this example, the upper end of the first polycrystalline silicon region 151 is located at a predetermined distance below the front surface 21 of the semiconductor substrate 10.

[0190] In step S126, a cap layer 66 is formed above the first polycrystalline silicon region 151. Step S126, in which the cap layer 66 is formed above the first polycrystalline silicon region 151, is performed after step S125, in which the first polycrystalline silicon region 151 is etched back, and before step S152, in which multiple trenches are formed. This protects the first polycrystalline silicon region 151 from plasma damage that may occur in step S152, in which multiple trenches are formed.

[0191] In step S152, a resist mask 36 is formed on the hard mask 35, and the resist mask 36 is exposed to light. Step S152 is the same as step S122 which has already been described, so the explanation is omitted.

[0192] Figure 13B shows an example of a method for manufacturing the semiconductor device 100. Figure 13B is a continuation of step S152, which was explained using Figure 13A. Each step from step S153 to step S154 will be explained using Figure 13B.

[0193] In step S153, multiple trenches are formed. In this example, the case in which the trench 45 of the gate trench 40 is formed is illustrated. The multiple trenches are provided extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Step S153, in which the multiple trenches are formed, is performed after step S125, in which the first polycrystalline silicon region 151 is etched back. As a result, plasma damage that may occur in the step of forming the trench-type lifetime control unit 60 does not affect the multiple trenches, thereby improving the operational reliability of the semiconductor device 100.

[0194] In step S160, the hard mask 35 is removed. In step S160, the cap layer 66 provided above the first polycrystalline silicon region 151 may also be removed at the same time. In step S160, the resist mask 36 formed on the hard mask 35 may also be removed at the same time.

[0195] In step S161, a trench insulating film 62 is formed. In step S161, the bottom and side walls of multiple trenches are oxidized or nitrided to form a trench insulating film 62. In step S161, the side walls of the lifetime-controlled trench 65 and the upper surface of the first polycrystalline silicon region 151 may be oxidized or nitrided to form a trench insulating film 62. The gate insulating film 42 formed in the trench 45 is an example of the trench insulating film 62.

[0196] In step S154, a non-contact polycrystalline silicon region 64 is filled on the trench insulating film 62. In step S154, a gate conductive portion 44 may be filled on the gate insulating film 42. In Figure 13B, hatching is shown on the non-contact polycrystalline silicon region 64 for illustrative purposes, but the material of the first polycrystalline silicon region 151 and the material of the non-contact polycrystalline silicon region 64 may be the same.

[0197] Figure 14A shows an example of a method for manufacturing a semiconductor device 100. In this example, an example of a method for manufacturing a semiconductor device 100 is shown, and the order of each step may be changed as appropriate. Figure 14A is an example of a method for manufacturing a semiconductor device 100 that includes at least a diode section 80.

[0198] In step S115, the anode region 11 is formed. The anode region 11 is formed above the drift region 18 provided on the semiconductor substrate 10. The anode region 11 is an example of a second conductivity type region 19. Next, in step S120, the trench-type lifetime control unit 60 is formed. The trench-type lifetime control unit 60 is formed so as to extend from the front surface 21 of the semiconductor substrate 10, through the anode region 11, to the drift region 18. The details of step S120 are the same as before, so the explanation is omitted.

[0199] In step S160, the hard mask 35 is removed. Then, in step S170, an interlayer insulating film 38 is formed on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be formed such that at least a portion of it is located inside the trench-type lifetime control unit 60. Thereafter, a semiconductor device 100 having at least a diode portion 80 is manufactured through known processes.

[0200] Figure 14B shows an example of a method for manufacturing the semiconductor device 100. In this example, only one method for manufacturing the semiconductor device 100 is shown, and the order of each step may be changed as appropriate. Figure 14B is an example of a method for manufacturing the semiconductor device 100, which includes at least a transistor section 70. Using Figure 14B, we will explain the differences from the method for manufacturing the semiconductor device 100 described so far.

[0201] Steps S121 through S154 are the same as before, so the explanation will be omitted. In step S155, the non-contact polycrystalline silicon region 64 is etched back. This allows adjustment of the depth position of the upper end of the non-contact polycrystalline silicon region 64 in the depth direction of the semiconductor substrate 10. Step S155 may be omitted.

[0202] In step S180, a base region 14 is formed. The base region 14 is formed above a drift region 18 provided on the semiconductor substrate 10. The base region 14 is an example of a second conductivity region 19. Thus, the step of forming the second conductivity region 19 may be performed before the step of manufacturing the trench-type lifetime control unit 60, or it may be performed after the step of manufacturing the trench-type lifetime control unit 60. Thereafter, a semiconductor device 100 having at least a transistor section 70 is manufactured through known processes.

[0203] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0204] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0205] 10...Semiconductor substrate, 11...Anode region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Peripheral well region, 18...Drift region, 19...Second conductivity type region, 20...Field stop region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Back surface electrode portion, 25...Connection portion, 27...Plug portion, 30...Dummy trench portion, 31...Extended portion 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 35...Hard mask, 36...Resist mask, 38...Interlayer insulating film, 39...Oxide film, 40...Gate trench portion, 41...Stretched portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 45...Trench, 50...Gate metal layer, 51...Gate runner, 52...Front electrode portion, 54...Contact hole, 55...Contact Hole, 56... Contact hole, 60... Trench-type lifetime control section, 61... Extending section, 62... Trench insulating film, 63... Connection section, 64... Non-contact polycrystalline silicon region, 65... Lifetime control trench, 66... ​​Cap layer, 70... Transistor section, 71... First mesa section, 71-1... First mesa section, 75... Main region, 80... Diode section, 81... First mesa section, 81-1... First mesa section, 81-2... Second Mesa region, 82... Cathode region, 90... Boundary region, 91-1... First mesa region, 91-2... Second mesa region, 92... Guard ring region, 94... Electrode layer, 96... Channel stopper region, 100... Semiconductor device, 110... Active region, 120... Peripheral region, 130... Gate pad, 150... Lifetime control region, 151... First polycrystalline silicon region, 152... Second polycrystalline silicon region, 160... Peripheral side lifetime control region

Claims

1. A first-conductivity drift region provided on the semiconductor substrate, A second conductivity type region of a second conductivity type provided above the drift region, A front surface electrode portion provided above the semiconductor substrate, A back electrode portion provided below the semiconductor substrate, A trench-type lifetime control unit is provided extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate, Equipped with, The trench-type lifetime control unit is a semiconductor device having a first polycrystalline silicon region that is in direct contact with the semiconductor substrate.

2. The first polycrystalline silicon region is in direct contact with the drift region. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1, wherein the trench-type lifetime control unit is provided extending from the front surface of the semiconductor substrate, through the second conductivity type region, and into the interior of the drift region.

4. The semiconductor device according to claim 1, wherein the depth position of the lower end of the trench-type lifetime control unit in the depth direction of the semiconductor substrate is 1 μm or more and 20 μm or less from the front surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein the trench width of the trench-type lifetime control unit is 0.5 μm or more and 2.0 μm or less.

6. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the distance between the depth position of the upper end of the first polycrystalline silicon region and the depth position of the lower end of the second conductivity type region is 0 μm or more and 1 μm or less.

7. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth position of the upper end of the first polycrystalline silicon region is deeper than the depth position of the lower end of the second conductivity type region.

8. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth position of the upper end of the first polycrystalline silicon region is shallower than the depth position of the lower end of the second conductivity type region.

9. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth position of the upper end of the first polycrystalline silicon region is 0 μm or more from the front surface of the semiconductor substrate and 0 μm or less from half the trench depth of the trench-type lifetime control unit.

10. The semiconductor device according to claim 1, wherein the trench-type lifetime control unit is provided above the first polycrystalline silicon region and has a second polycrystalline silicon region having a different doping concentration from the first polycrystalline silicon region.

11. The first polycrystalline silicon region is undoped polycrystalline silicon. The semiconductor device according to claim 10, wherein the second polycrystalline silicon region is a second conductivity type polycrystalline silicon.

12. The first polycrystalline silicon region is in direct contact with the drift region, The semiconductor device according to claim 11, wherein the second polycrystalline silicon region is in direct contact with the second conductivity type region.

13. The system comprises multiple trench sections, each including at least one of a gate trench section or a dummy trench section. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth of the trench-type lifetime control unit is the same as the depth of the plurality of trenches.

14. The system comprises multiple trench sections, each including at least one of a gate trench section or a dummy trench section. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth of the trench-type lifetime control unit is greater than the depth of the plurality of trenches.

15. The system comprises multiple trench sections, each including at least one of a gate trench section or a dummy trench section. The semiconductor device according to claim 1, wherein, in the depth direction of the semiconductor substrate, the depth of the trench-type lifetime control unit is shallower than the depth of the plurality of trenches.

16. The system comprises multiple trench sections, each including at least one of a gate trench section or a dummy trench section. The semiconductor device according to claim 1, wherein the trench width of the trench-type lifetime control unit is the same as the trench width of the plurality of trench sections.

17. The system comprises multiple trench sections, each including at least one of a gate trench section or a dummy trench section. The semiconductor device according to claim 1, wherein the trench width of the trench-type lifetime control unit is greater than the trench width of the plurality of trench sections.

18. The system comprises multiple trench sections, each including at least one of a gate trench section or a dummy trench section. The semiconductor device according to claim 1, wherein the trench width of the trench-type lifetime control unit is smaller than the trench width of the plurality of trench sections.

19. A plurality of trench sections, including at least one of a gate trench section or a dummy trench section, A first mesa portion is provided between the plurality of trench portions, At least one trench-type lifetime control unit and an adjacent second mesa section Equipped with, The semiconductor device according to any one of claims 1 to 18, wherein the mesa width of the second mesa portion is narrower than the mesa width of the first mesa portion.

20. The semiconductor device according to claim 19, wherein the trench width of the trench-type lifetime control unit is narrower than the mesa width of the second mesa portion.

21. The semiconductor device according to claim 19, wherein the trench width of the trench-type lifetime control unit is wider than the mesa width of the second mesa portion.

22. The diode portion is a region on the back surface of the semiconductor substrate in which a first conductive cathode region is provided, The transistor section is a region on the back surface of the semiconductor substrate in which a second-conducting collector region is provided. Equipped with, The transistor section has a main region and a boundary region provided between the main region and the diode section. The semiconductor device according to claim 19, wherein the trench-type lifetime control unit is provided in the boundary region.

23. The semiconductor device according to any one of claims 1 to 18, wherein the trench-type lifetime control unit has a trench insulating film provided above the first polycrystalline silicon region.

24. The semiconductor device according to claim 23, wherein the trench insulating film is provided on the first polycrystalline silicon region inside the trench-type lifetime control unit.

25. The semiconductor device according to claim 23, wherein the trench insulating film is provided on the trench sidewall of the trench-type lifetime control unit above the first polycrystalline silicon region.

26. The semiconductor device according to claim 23, wherein the trench-type lifetime control unit has a non-contact polycrystalline silicon region provided on the trench insulating film.

27. The semiconductor substrate is provided with a diode portion which is a region on the back surface of which a first conductive cathode region is provided. The semiconductor device according to any one of claims 1 to 18, wherein in the diode portion, the front electrode portion is in direct contact with a region of a first conductivity type provided on the front surface of the semiconductor substrate.

28. The semiconductor device according to claim 27, wherein the diode portion is connected to the front surface electrode portion via a Schottky connection with the front surface of the semiconductor substrate.

29. The semiconductor substrate comprises a transistor section, which is a region on the back surface of which a second conductive collector region is provided. The semiconductor device according to any one of claims 1 to 18, wherein the transistor portion has an outer peripheral lifetime control region in which a plurality of trench-type lifetime control units are arranged.

30. The transistor section is provided with a second conductivity type outer well region on its outer periphery, The semiconductor device according to claim 29, wherein the outer peripheral well region is provided extending inward from the outer periphery of the transistor portion and terminates in the middle of the outer peripheral lifetime control region.

31. The semiconductor device according to claim 27, wherein in the diode portion, the front electrode portion and the first polycrystalline silicon region are in direct contact.

32. The semiconductor device according to claim 31, wherein the front electrode portion has a plug portion for contacting the first polycrystalline silicon region above the trench-type lifetime control unit.

33. The semiconductor device according to any one of claims 1 to 18, comprising a lifetime control region provided on the semiconductor substrate and formed by electron beam irradiation.

34. The semiconductor device according to any one of claims 1 to 18, further comprising an interlayer insulating film provided above the first polycrystalline silicon region within the trench of the trench-type lifetime control unit.

35. The steps include providing a drift region of a first conductivity type on a semiconductor substrate, The steps include forming a trench-type lifetime control unit having a first polycrystalline silicon region that extends from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate and is in direct contact with the semiconductor substrate, and which is made of polycrystalline silicon. The step of providing a front surface electrode portion above the semiconductor substrate, The step of providing a back surface electrode portion below the semiconductor substrate. A method for manufacturing a semiconductor device, comprising:

36. The step comprises etching back the first polycrystalline silicon region, After the step of etching back the first polycrystalline silicon region, The steps include forming a plurality of trenches that extend from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate, The steps include oxidizing the bottom and side walls of the plurality of trench portions to form a trench insulating film, The steps include filling a non-contact polycrystalline silicon region onto the trench insulating film. A method for manufacturing a semiconductor device according to claim 35, comprising:

37. The method for manufacturing a semiconductor device according to claim 36, further comprising the step of forming a cap layer above the first polycrystalline silicon region after the step of etching back the first polycrystalline silicon region and before the step of forming the plurality of trenches.

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