Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device capable of forming a suitable electrode layer. [Solution] According to one embodiment, the semiconductor device comprises a laminated film including a plurality of electrode layers and a plurality of first insulating films arranged alternately in a first direction. The device further comprises a columnar portion extending in the first direction within the laminated film, the columnar portion including a charge storage layer provided on the side surface of the laminated film via a second insulating film, and a semiconductor layer provided on the side surface of the charge storage layer via a third insulating film. The first electrode layer among the plurality of electrode layers includes a first layer containing molybdenum, nitrogen, and a group 14 element, and a second layer containing molybdenum.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] In 3D semiconductor memory, the electrode material layer within the electrode layer, such as the word line, is formed from, for example, a molybdenum (Mo) layer. In this case, the question arises as to what kind of layer should be used to form the barrier metal layer within the electrode layer. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2014-053557 [Patent Document 2] Japanese Patent Publication No. 2023-044849 [Patent Document 3] Japanese Patent Publication No. 2023-183052 [Patent Document 4] Special Publication No. 2022-536795 [Overview of the project] [Problems that the invention aims to solve]

[0004] The present invention provides a semiconductor device capable of forming a suitable electrode layer and a method for manufacturing the same. [Means for solving the problem]

[0005] According to one embodiment, the semiconductor device comprises a laminated film including a plurality of electrode layers and a plurality of first insulating films arranged alternately in a first direction. The device further comprises a columnar portion extending in the first direction within the laminated film, the columnar portion including a charge storage layer provided on the side surface of the laminated film via a second insulating film, and a semiconductor layer provided on the side surface of the charge storage layer via a third insulating film. The first electrode layer among the plurality of electrode layers includes a first layer containing molybdenum, nitrogen, and a group 14 element, and a second layer containing molybdenum. [Brief explanation of the drawing]

[0006] [Figure 1] This is a perspective view showing the structure of the semiconductor device of the first embodiment. [Figure 2] This is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view (2 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view (3 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view (4 / 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view showing the structure of a comparative example semiconductor device of the first embodiment and the structure of the semiconductor device of the first embodiment. [Figure 7] This is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 8] This is an enlarged cross-sectional view showing the structure of the semiconductor device of the second embodiment. [Figure 9] This is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 10] This is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 10, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a perspective view showing the structure of a semiconductor device according to the first embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0009] The semiconductor device of this embodiment includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a block insulating film 5, and an electrode layer 6. The block insulating film 5 includes an insulating film 5a and an insulating film 5b, and the electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The barrier metal layer 6a and the electrode material layer 6b are examples of the first and second layers, respectively. The channel semiconductor layer 2 is an example of a semiconductor layer. The insulating film 5a, the tunnel insulating film 3, and the insulating film 5b are examples of the second, third, and fourth insulating films, respectively.

[0010] In FIG. 1, a plurality of electrode layers and a plurality of insulating films are alternately stacked on a substrate, and memory holes MH are provided in these electrode layers and insulating films. FIG. 1 shows one electrode layer 6 among these electrode layers. Each of these electrode layers functions as, for example, a word line or a selection line of a three-dimensional semiconductor memory. FIG. 1 shows an X direction and a Y direction that are parallel to the surface of the substrate and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may coincide with the direction of gravity or may not coincide with the direction of gravity. The Z direction is an example of the first direction, and the memory hole MH is an example of the first recess. In FIG. 1, the memory hole MH extends in the Z direction and has a circular shape in plan view.

[0011] The core insulating film 1, the channel semiconductor layer 2, the tunnel insulating film 3, the charge storage layer 4, and the insulating film 5a are formed in the memory hole MH and constitute the memory cell of the three-dimensional semiconductor memory. The insulating film 5a is formed on the side surfaces of the electrode layer and the insulating film in the memory hole MH, and the charge storage layer 4 is formed on the side surface of the insulating film 5a. The charge storage layer 4 is capable of storing the signal charges of the three-dimensional semiconductor memory. The tunnel insulating film 3 is formed on the side surface of the charge storage layer 4, and the channel semiconductor layer 2 is formed on the side surface of the tunnel insulating film 3. The channel semiconductor layer 2 functions as the channel of the three-dimensional semiconductor memory. The core insulating film 1 is formed on the side surface of the channel semiconductor layer 2.

[0012] The insulating film 5a is, for example, a SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, a SiO2 film. The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulating film 1 is, for example, a SiO2 film. In FIG. 1, a columnar portion CL including the core insulating film 1, the channel semiconductor layer 2, the tunnel insulating film 3, the charge storage layer 4, and the insulating film 5a is formed in the memory hole MH. In FIG. 1, the columnar portion CL extends in the Z direction and has a circular shape in plan view.

[0013] The insulating film 5b, the barrier metal layer 6a, and the electrode material layer 6b are formed between two of the plurality of insulating films, and are sequentially formed on the upper surface of the lower insulating film, the lower surface of the upper insulating film, and the side surface of the insulating film 5a. Specifically, the barrier metal layer 6a is formed between the lower and upper insulating films via the insulating film 5b and is formed on the upper surface, lower surface, and side surface of the insulating film 5b. Also, the electrode material layer 6b is formed between the lower and upper insulating films via the insulating film 5b and the barrier metal layer 6a and is formed on the upper surface, lower surface, and side surface of the barrier metal layer 6a. The plurality of insulating films are examples of a first insulating film, the lower insulating film is an example of a lower insulating film, the upper insulating film is an example of an upper insulating film. Also, the electrode layer 6 shown in FIG. 1 is an example of a first electrode layer.

[0014] The insulating film 5b is, for example, an Al2O3 film (Al represents aluminum, O represents oxygen). The barrier metal layer 6a is, for example, a MoSiN film (Mo represents molybdenum, Si represents silicon, N represents nitrogen). The electrode material layer 6b is, for example, a Mo (molybdenum) layer.

[0015] Next, with reference to Figure 1, further details of the barrier metal layer 6a and electrode material layer 6b of this embodiment will be described.

[0016] The barrier metal layer 6a contains molybdenum, silicon, and nitrogen, and may also contain one or more other elements. Examples of such elements are oxygen and hydrogen. The barrier metal layer 6a is, for example, a MoSiN film containing oxygen and / or hydrogen as impurity elements. However, it is preferable that the barrier metal layer 6a of this embodiment contains molybdenum as the main component element. For example, the barrier metal layer 6a may contain elements E1, E2, ... E N If (N is an integer greater than or equal to 2), the atomic concentration of molybdenum in the barrier metal layer 6a is equal to the atomic concentration of elements E1, E2, ..., E in the barrier metal layer 6a. N Atomic concentrations of C1, C2, ...C N It is desirable that the concentration be the highest among them.

[0017] The atomic concentration of nitrogen in the barrier metal layer 6a is, for example, 20% or more of the total atomic concentration of molybdenum, silicon, and nitrogen in the barrier metal layer 6a. The atomic concentration of silicon in the barrier metal layer 6a is, for example, 5% or more of the total atomic concentration of molybdenum, silicon, and nitrogen in the barrier metal layer 6a. Furthermore, if the barrier metal layer 6a contains hydrogen, the atomic concentration of hydrogen in the barrier metal layer 6a is, for example, 1.0 × 10⁻¹⁶. 20 atoms / cm 3 That's all.

[0018] The barrier metal layer 6a is, for example, an amorphous layer. The thickness of the barrier metal layer 6a is, for example, 3 nm or less. According to this embodiment, by making the barrier metal layer 6a thinner, it is possible to make, for example, the electrode layer 6 thinner. In this embodiment, because the barrier metal layer 6a is thin, the barrier metal layer 6a, which is formed as an amorphous layer, does not change into a polycrystalline layer by annealing, and remains an amorphous layer even after annealing. However, the barrier metal layer 6a may also be a polycrystalline layer.

[0019] The barrier metal layer 6a may contain a Group 14 element other than silicon instead of silicon. An example of such a Group 14 element is carbon. The above and below descriptions regarding the barrier metal layer 6a are also applicable when the barrier metal layer 6a contains a Group 14 element other than silicon instead of silicon.

[0020] The electrode material layer 6b contains molybdenum and may also contain one or more other elements. An example of such elements is hydrogen. The electrode material layer 6b is, for example, a Mo layer containing hydrogen as an impurity element. However, it is preferable that the electrode material layer 6b of this embodiment contains molybdenum as the main component element. For example, the electrode material layer 6b may contain elements e1, e2, ... e n If n is an integer greater than or equal to 2, the atomic concentration of molybdenum in the electrode material layer 6b is equal to the element e1, e2, ... e in the electrode material layer 6b. n Atomic concentrations c1, c2, ... c n It is desirable that the concentration be the highest among them.

[0021] The atomic concentration of hydrogen in the electrode material layer 6b is higher than, for example, the atomic concentration of hydrogen in the insulating film 5a. Further details of this relationship will be discussed later.

[0022] The barrier metal layer 6a and the electrode material layer 6b both contain molybdenum. The barrier metal layer 6a and the electrode material layer 6b are formed, for example, using a source gas containing molybdenum and chlorine. In this case, the barrier metal layer 6a and the electrode material layer 6b may contain chlorine as an impurity element. Note that hydrogen and oxygen in the barrier metal layer 6a are mixed into the barrier metal layer 6a, for example, derived from the source gas used when forming the barrier metal layer 6a or other layers. Similarly, hydrogen in the electrode material layer 6b is mixed into the electrode material layer 6b, for example, derived from the source gas used when forming the electrode material layer 6b or other layers. However, the impurity elements in the barrier metal layer 6a and the electrode material layer 6b may be derived from causes other than the source gas, for example, may be derived from the gas for annealing.

[0023] As described above, the electrode material layer 6b of the present embodiment is formed using molybdenum. Thereby, it becomes possible to reduce the electrical resistance of the electrode material layer 6b. For example, by forming the electrode material layer 6b using molybdenum, it becomes possible to lower the electrical resistance of the electrode material layer 6b compared to the case where the electrode material layer 6b is formed using tungsten or aluminum.

[0024] Furthermore, the barrier metal layer 6a of the present embodiment is formed using molybdenum, silicon, and nitrogen. Thereby, it becomes possible to suppress the diffusion of N (nitrogen) atoms from the barrier metal layer 6a to the electrode material layer 6b, and it becomes possible to suppress an increase in the electrical resistance of the electrode material layer 6b due to N atoms. Furthermore, it becomes possible to suppress the diffusion of O (oxygen) atoms, H (hydrogen) atoms, Cl (chlorine) atoms, etc. through the barrier metal layer 6a to the block insulating film 5 and the charge storage layer 4, and it becomes possible to suppress a decrease in the data retention of the three-dimensional semiconductor memory due to these atoms.

[0025] Note that oxygen and hydrogen in the barrier metal layer 6a are derived, for example, from O atoms and H atoms that remained in the barrier metal layer 6a without passing through the barrier metal layer 6a. The barrier metal layer 6a is, for example, due to such H atoms, 1.0×10 20atoms / cm 3 In some cases, the material may contain high concentrations of hydrogen atoms. Furthermore, the relationship that the hydrogen atomic concentration in the electrode material layer 6b is higher than that in the insulating film 5a stems, for example, from the fact that a large number of hydrogen atoms remained in the electrode material layer 6b without passing through the barrier metal layer 6a. Further details regarding the diffusion of these atoms will be discussed later.

[0026] Figures 2 to 5 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment.

[0027] First, a multilayer film 12 is formed on the substrate 11 (Figure 2). The multilayer film 12 includes a plurality of sacrificial layers 13 and a plurality of insulating films 14 that are alternately formed in the Z direction. The multilayer film 12 is formed by alternately stacking these sacrificial layers 13 and insulating films 14 on the substrate 11. The multilayer film 12 may be formed directly on the substrate 11 or on the substrate 11 via other layers. The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The sacrificial layer 13 is, for example, a SiN film. The insulating film 14 is, for example, an SiO2 film. The sacrificial layer 13 is an example of a third layer. The insulating film 14 is an example of a first insulating film.

[0028] Next, multiple memory holes MH are formed within the laminated film 12 by photolithography and RIE (Reactive Ion Etching) (Figure 2). Figure 2 shows one of these memory holes MH. Each memory hole MH in this embodiment extends in the Z direction and penetrates the laminated film 12. Each memory hole MH is an example of a first recess.

[0029] Next, an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are formed sequentially on the side surface of the laminated film 12 within each memory hole MH (Figure 3). As a result, multiple columnar portions CL are formed within multiple memory holes MH. Figure 3 shows one of these columnar portions CL. Each columnar portion CL in this embodiment extends in the Z direction and penetrates the laminated film 12. In each columnar portion CL, the charge storage layer 4 is formed on the side surface of the multiple sacrificial layers 13 and multiple insulating films 14 via the insulating film 5a, and the channel semiconductor layer 2 is formed on the side surface of the charge storage layer 4 via the tunnel insulating film 3.

[0030] Next, multiple slits (not shown) are formed within the laminated film 12, and the sacrificial layer 13 is removed from these slits using a chemical solution such as an aqueous phosphoric acid solution. As a result, multiple cavities RC are formed within the laminated film 12 (Figure 4).

[0031] Next, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are sequentially formed on the surfaces of the insulating films 5a and 14 within each cavity RC (Figure 5). As a result, a block insulating film 5 including insulating films 5a and 5b is formed. Furthermore, an electrode layer 6 including a barrier metal layer 6a and an electrode material layer 6b is formed within each cavity RC. Furthermore, a laminated film 12 is formed on the substrate 11, which alternately includes multiple electrode layers 6 and multiple insulating films 14. In this way, a replacement process is performed in which the sacrificial layer 13 is replaced with the electrode layer 6.

[0032] Each cavity RC is formed between two insulating films 14 adjacent to each other in the Z direction. Within each cavity RC, the insulating film 5b, barrier metal layer 6a, and electrode material layer 6b are formed sequentially on the upper surface of the lower insulating film 14, the lower surface of the upper insulating film 14, and the side surface of the insulating film 5a. The lower insulating film 14 is an example of a lower insulating film, and the upper insulating film 14 is an example of an upper insulating film. Also, each electrode layer 6 shown in Figure 5 is an example of a first electrode layer.

[0033] In this way, the semiconductor device of this embodiment is manufactured (Figure 5). Figure 1 shows a part of the semiconductor device shown in Figure 5.

[0034] Figure 6 is a cross-sectional view showing the structure of a comparative example of the first embodiment and the structure of the semiconductor device of the first embodiment.

[0035] Figure 6(a) shows the charge storage layer 4, block insulating film 5, and electrode layer 6 in the semiconductor device of the comparative example. The electrode layer 6 of the comparative example includes a barrier metal layer 6a' instead of the barrier metal layer 6a of the first embodiment, and also includes an electrode material layer 6b similar to that of the first embodiment. The barrier metal layer 6a' of the comparative example is, for example, a MoN film. The electrode material layer 6b of the comparative example is, for example, a Mo layer.

[0036] When the barrier metal layer 6a' is a MoN film, as shown in Figure 6(a), N atoms contained in the barrier metal layer 6a' easily diffuse into the electrode material layer 6b. This leads to the problem of increased electrical resistance in the electrode material layer 6b.

[0037] Furthermore, when the barrier metal layer 6a' is a MoN film, as shown in Figure 6(a), O atoms and H atoms easily diffuse through the barrier metal layer 6a to the block insulating film 5 and charge storage layer 4. The same applies to Cl atoms, etc. This poses a problem because these atoms can reduce the data retention of the 3D semiconductor memory. For example, OH groups are generated within the block insulating film 5, and electrons (e) are released from the charge storage film 4 via the OH groups. - The problem arises when the ) is omitted.

[0038] Figure 6(b) shows the charge storage layer 4, block insulating film 5, and electrode layer 6 in the semiconductor device of the first embodiment. As described above, the electrode layer 6 of this embodiment includes a barrier metal layer 6a and an electrode material layer 6b. The barrier metal layer 6a of this embodiment is, for example, a MoSiN film. The electrode material layer 6b of this embodiment is, for example, a Mo layer.

[0039] In this embodiment, the barrier metal layer 6a contains Si atoms in addition to N atoms. As a result, as shown in Figure 6(b), it is possible to suppress the diffusion of N atoms contained in the barrier metal layer 6a into the electrode material layer 6b, thereby suppressing the increase in the electrical resistance of the electrode material layer 6b due to N atoms.

[0040] Furthermore, according to this embodiment, as shown in Figure 6(b), it is possible to trap H atoms and the like with the barrier metal layer 6a containing Si atoms. This makes it possible to suppress the diffusion of H atoms and the like through the barrier metal layer 6a to the block insulating film 5 and the charge storage layer 4, thereby suppressing the decrease in data retention of the 3D semiconductor memory due to H atoms and the like. For example, it becomes possible to suppress the generation of OH groups in the block insulating film 5, and electrons (e) from the charge storage film 4 via the OH groups. - This makes it possible to prevent the ) from falling out.

[0041] As described above, each electrode layer 6 in this embodiment includes a barrier metal layer 6a containing molybdenum, silicon, and nitrogen, and an electrode material layer 6b containing molybdenum. Therefore, according to this embodiment, it is possible to form a suitable electrode layer 6, such as suppressing performance degradation of the semiconductor device caused by the barrier metal layer 6a.

[0042] Furthermore, if the semiconductor device of this embodiment is manufactured by bonding together two or more substrates, including the substrate 11, the semiconductor device of this embodiment does not necessarily have to include the substrate 11. An example of such a semiconductor device will be described in the second embodiment.

[0043] (Second Embodiment) Figure 7 is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0044] The semiconductor device of this embodiment comprises an array chip 21 and a circuit chip 22 bonded together. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer containing the array chip 21 and a circuit wafer containing the circuit chip 22 together.

[0045] The array chip 21 comprises a memory cell array 31 containing a plurality of memory cells, an insulating film 32 on the memory cell array 31, and an interlayer insulating film 33 below the memory cell array 31. The insulating film 32 is, for example, an SiO2 film. The interlayer insulating film 33 is, for example, a laminated film containing an SiO2 film and other insulating films. A portion of the memory cell array 31 in this embodiment corresponds to the laminated film 12 in the first embodiment.

[0046] The circuit chip 22 is located beneath the array chip 21. The symbol S indicates the bonding surface between the array chip 21 and the circuit chip 22. The circuit chip 22 comprises an interlayer insulating film 34 beneath the interlayer insulating film 33 and a substrate 35 beneath the interlayer insulating film 34. The interlayer insulating film 34 is, for example, a multilayer film including an SiO2 film and other insulating films. The substrate 35 is, for example, a semiconductor substrate such as a Si substrate.

[0047] Figure 7 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate 35, and the Z direction, which is perpendicular to the surface of the substrate 35. The X, Y, and Z directions intersect each other. In this embodiment, as in the first embodiment, the +Z direction is treated as the upward direction and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0048] The array chip 21 includes multiple word lines WL as multiple electrode layers within the memory cell array 31. Figure 7 shows a stepped structure 41 within the memory cell array 31 and multiple beam sections 42 provided within the stepped structure 41. Each word line WL extends in the X direction and is electrically connected to the word wiring layer 44 via a contact plug 43. Each columnar section CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 45 and is also electrically connected to the source line SL. The bit line BL extends in the Y direction and is located below the multiple word lines WL. The source line SL extends in the X direction and is located above the multiple word lines WL.

[0049] The circuit chip 22 comprises a plurality of transistors 51. Each transistor 51 includes a gate insulating film 51a and a gate electrode 51b, which are sequentially provided on the substrate 35, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 35. The circuit chip 22 also comprises a plurality of contact plugs 52 provided on the gate electrode 51b, source diffusion layer, or drain diffusion layer of the plurality of transistors 51. The circuit chip 22 also comprises a wiring layer 53, a wiring layer 54, and a wiring layer 55. The wiring layer 53 contains a plurality of wires and is provided on the plurality of contact plugs 52. The wiring layer 54 contains a plurality of wires and is provided on the wiring layer 53. The wiring layer 55 contains a plurality of wires and is provided on the wiring layer 54.

[0050] The circuit chip 22 further comprises a plurality of via plugs 56 provided on the wiring layer 55, and a plurality of metal pads 57 provided on the plurality of via plugs 56. The metal pads 57 are, for example, metal layers including a Cu (copper) layer. The circuit chip 22 functions as a logic circuit that controls the operation of the array chip 21. This logic circuit is composed of transistors 51 and the like, and is electrically connected to the metal pads 57.

[0051] The array chip 21 comprises a plurality of metal pads 61 provided on the plurality of metal pads 57, and a plurality of via plugs 62 provided on the plurality of metal pads 61. The metal pads 61 are, for example, metal layers including a Cu layer. The array chip 21 also comprises a wiring layer 63 and a wiring layer 64. The wiring layer 63 includes a plurality of wires and is provided on the plurality of via plugs 62. The wiring layer 64 includes a plurality of wires and is provided on the wiring layer 63. The bit line BL is contained within the wiring layer 64. The logic circuit is electrically connected to the memory cell array 31 via the metal pads 61, 57, etc., and controls the operation of the memory cell array 31 via the metal pads 61, 57, etc.

[0052] The array chip 21 further comprises a plurality of via plugs 65 provided on the wiring layer 64, and metal pads 66 provided on the plurality of via plugs 65 and on the insulating film 32. The array chip 21 also comprises a passivation insulating film 67 provided on the metal pads 66 and on the insulating film 32. The metal pads 66 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device in this embodiment. The passivation insulating film 67 is, for example, a multilayer film including an SiO2 film and a SiN film, and has an opening P that exposes the upper surface of the metal pads 66. The metal pads 66 can be electrically connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, etc. through the opening P.

[0053] Figure 8 is an enlarged cross-sectional view showing the structure of the semiconductor device of the second embodiment.

[0054] Figure 8 shows the memory cell array 31 shown in Figure 7. The memory cell array 31 comprises a laminated film 71 including a plurality of electrode layers 71a and a plurality of insulating films 71b that are alternately stacked in the Z direction. The plurality of electrode layers 71a function, for example, as the word lines WL described above. Each electrode layer 71a is a metal layer including, for example, a MoSiN film (barrier metal layer) and a Mo layer (electrode material layer). Each insulating film 71b is, for example, an SiO2 film. The laminated film 71, electrode layers 71a, and insulating films 71b in this embodiment correspond to the laminated film 12, electrode layer 6, and insulating film 14 of the first embodiment, respectively.

[0055] Figure 8 further shows one of the multiple columnar portions CL shown in Figure 7. Each columnar portion CL includes a memory insulating film 72, a channel semiconductor layer 73, and a core insulating film 74, arranged sequentially on the side surface of the laminated film 71. The memory insulating film 72 includes a block insulating film 72a, a charge storage layer 72b, and a tunnel insulating film 72c, arranged sequentially on the side surface of the laminated film 71. The block insulating film 72a is, for example, an SiO2 film. The charge storage layer 72b is, for example, an insulating film such as a SiN film. The charge storage layer 72b may also be a semiconductor layer such as a polysilicon layer. The charge storage layer 72b is capable of storing signal charges for a three-dimensional semiconductor memory. The tunnel insulating film 72c is, for example, an SiO2 film. The channel semiconductor layer 73 is, for example, a polysilicon layer. The channel semiconductor layer 73 functions as a channel for the three-dimensional semiconductor memory. The core insulating film 74 is, for example, an SiO2 film. The columnar portions CL of this embodiment correspond to the columnar portions CL of the first embodiment.

[0056] Furthermore, the semiconductor device of this embodiment may also include an insulating film corresponding to the insulating film 5b of the first embodiment.

[0057] Figures 9 and 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to a second embodiment.

[0058] Figure 9 shows an array wafer W1 containing multiple array chips 21 and a circuit wafer W2 containing multiple circuit chips 22. The orientation of the array wafer W1 in Figure 9 is the opposite of the orientation of the array chips 21 in Figure 7. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 9 shows the array wafer W1 before its orientation is reversed for bonding, and Figure 7 shows the array chips 21 after their orientation has been reversed for bonding, and after bonding and dicing.

[0059] In Figure 9, the numeral S1 indicates the upper surface of the array wafer W1, and the numeral S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 36 provided beneath the insulating film 32. The substrate 36 is, for example, a semiconductor substrate such as a Si substrate. The substrate 36 in this embodiment corresponds to the substrate 11 in the first embodiment.

[0060] In this embodiment, first, as shown in Figure 9, a memory cell array 31, insulating film 32, interlayer insulating film 33, metal pads 61, via plugs 65, etc. are formed on the substrate 36 of the array wafer W1, and an interlayer insulating film 34, transistors 51, metal pads 57, etc. are formed on the substrate 35 of the circuit wafer W2. Next, as shown in Figure 10, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that surfaces S1 and S2 face each other. This bonds the interlayer insulating film 33 and the interlayer insulating film 34. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pads 61 and 57. In this way, the substrates 36 and 35 are bonded together via the interlayer insulating films 33 and 34.

[0061] Subsequently, the substrate 36 is removed by CMP (Chemical Mechanical Polishing), and the substrate 35 is thinned by CMP. Then, the array wafer W1 and the circuit wafer W2 are cut into multiple chips (dicing). In this way, the semiconductor device shown in Figure 7 is manufactured. The metal pad 66 and the passivation insulating film 67 are formed on the insulating film 32 after the removal of the substrate 36 and the thinning of the substrate 35.

[0062] Figure 7 shows the interface between the interlayer insulating film 33 and the interlayer insulating film 34, and the interface between the metal pad 61 and the metal pad 57. However, after the annealing described above, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces were located can be estimated, for example, by detecting the inclination of the side surfaces of the metal pad 61 and the metal pad 57, or by detecting the positional displacement between the side surfaces of the metal pad 61 and the metal pad 57.

[0063] According to this embodiment, the semiconductor device and its manufacturing method of the first embodiment can be applied to this embodiment.

[0064] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and methods described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the embodiments of the apparatus and methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that are included in the scope and spirit of the invention. [Explanation of symbols]

[0065] 1: Core insulating film, 2: Channel semiconductor layer, 3: Tunnel insulating film, 4: Charge storage layer, 5: Block insulating film, 5a: Insulating film, 5b: Insulating film, 6: Electrode layer, 6a: Barrier metal layer, 6a': Barrier metal layer, 6b: Electrode material layer, 11: Substrate, 12: Multilayer film, 13: Sacrificial layer, 14: Insulating film 21: Array chip, 22: Circuit chip, 31: Memory cell array, 32: Insulating film, 33: Interlayer insulating film, 34: Interlayer insulating film, 35: Substrate, 36: Substrate, 41: Staircase structure, 42: Beam section, 43: Contact plug, 44: Word wiring layer, 45: Via plug, 51: Transistor, 51a: Gate insulating film, 51b: Gate electrode, 52: Contact plug, 53: Wiring layer, 54: Wiring layer, 55: Wiring layer, 56: Via plug, 57: Metal pad, 61: Metal pad, 62: Via plug, 63: Wiring layer, 64: Wiring layer, 65: Via plug, 66: Metal pad, 67: Passivation insulating film, 71: Multilayer film, 71a: Electrode layer, 71b: Insulating film, 72: Memory insulating film, 72a: Block insulating film, 72b: Charge storage layer, 72c: Tunnel insulating film, 73: Channel semiconductor layer, 74: Core insulating film

Claims

1. A laminated film comprising a plurality of electrode layers and a plurality of first insulating films arranged alternately in a first direction, A columnar portion extending in the first direction within the laminated film, comprising a columnar portion including a charge storage layer provided on the side surface of the laminated film via a second insulating film, and a semiconductor layer provided on the side surface of the charge storage layer via a third insulating film, The first electrode layer among the plurality of electrode layers is A first layer containing molybdenum, nitrogen, and Group 14 elements, Including a second layer containing molybdenum, Semiconductor equipment.

2. The semiconductor device according to claim 1, wherein the first layer further contains oxygen.

3. The semiconductor device according to claim 1, wherein the first layer further comprises hydrogen.

4. The semiconductor device according to claim 1, wherein the first layer comprises carbon or silicon as a group 14 element.

5. The semiconductor device according to claim 1, wherein the first layer is a MoSiN film (Mo represents molybdenum, Si represents silicon, and N represents nitrogen).

6. The semiconductor device according to claim 5, wherein the first layer is a MoSiN film containing oxygen as an impurity element.

7. The semiconductor device according to claim 5, wherein the first layer is a MoSiN film containing hydrogen as an impurity element.

8. The semiconductor device according to claim 1, wherein the atomic concentration of nitrogen in the first layer is 20% or more of the atomic concentrations of molybdenum, nitrogen, and group 14 elements in the first layer.

9. The semiconductor device according to claim 1, wherein the atomic concentration of group 14 elements in the first layer is 5% or more of the atomic concentration of molybdenum, nitrogen, and group 14 elements in the first layer.

10. The atomic concentration of hydrogen in the first layer is 1.0 × 10⁻⁶. ２０ atoms / cm ３ The semiconductor device according to claim 1.

11. The semiconductor device according to claim 1, wherein the first layer contains molybdenum as a main component element.

12. The semiconductor device according to claim 1, wherein the thickness of the first layer is 3 nm or less.

13. The semiconductor device according to claim 1, wherein the first layer is an amorphous layer.

14. The semiconductor device according to claim 1, wherein the second layer contains molybdenum as a main component element.

15. The semiconductor device according to claim 1, wherein the second layer is a molybdenum (Mo) layer.

16. The semiconductor device according to claim 1, wherein the atomic concentration of hydrogen in the second layer is higher than the atomic concentration of hydrogen in the second insulating film.

17. The semiconductor device according to claim 1, wherein the first layer is a barrier metal layer and the second layer is an electrode material layer.

18. The first electrode layer is provided between the lower insulating film and the upper insulating film of the plurality of first insulating films. The first layer is provided on the upper surface of the lower insulating film, the lower surface of the upper insulating film, and the side surface of the second insulating film. The second layer is provided on the top, bottom, and side surfaces of the first layer. The semiconductor device according to claim 1.

19. The semiconductor device according to claim 18, wherein the first layer is provided on the upper surface of the lower insulating film, the lower surface of the upper insulating film, and the side surface of the second insulating film via a fourth insulating film.

20. A laminated film is formed which includes a plurality of third layers and a plurality of first insulating films arranged alternately in the first direction. A first recess is formed within the laminated film, extending in the first direction. A charge storage layer is formed on the side surface of the laminated film within the first recess via a second insulating film, and a semiconductor layer is formed on the side surface of the charge storage layer within the first recess via a third insulating film, thereby forming a columnar portion extending in the first direction within the laminated film. The plurality of third layers are replaced with a plurality of electrode layers. This includes, The first electrode layer among the plurality of electrode layers is A first layer containing molybdenum, nitrogen, and Group 14 elements, The second layer contains molybdenum, Formed to include, A method for manufacturing a semiconductor device.

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