Method and apparatus relating to a package substrate having a stack of glass layers with different coefficients of thermal expansion.

Abstract

The embodiments provide systems, apparatus, manufactured products, and methods relating to package substrates having stacks of glass layers with different coefficients of thermal expansion. [Solution] An example of a package substrate includes: a first glass layer which includes a first glass through via extending through the first glass layer and has a first coefficient of thermal expansion (CTE); and a second glass layer which includes a second glass through via extending through the second glass layer and has a second CTE different from the first CTE, and the first glass through via is electrically coupled to the second glass through via.

Description

Background Art

[0001] Integrated circuit (IC) chips and / or semiconductor dies are typically connected via a package substrate to a larger circuit board such as, for example, a motherboard and other types of printed circuit boards (PCBs). As the size of IC chips and / or dies shrinks and the interconnect density increases, alternatives to traditional substrate layers have been developed to provide stable transmission of high-frequency data signals and / or increased power delivery between different circuits. One option being pursued is the implementation of package substrates with glass cores. Generally, glass core implementations offer several advantages including higher plated through hole (PTH) density, lower signal loss, and lower total thickness variation compared to implementations using conventional epoxy cores.

Brief Description of the Drawings

[0002] [Figure 1] An example of an integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown. [Figure 2] An example of a substrate core that can be used to implement the substrate core example of FIG. 1 is shown. [Figure 3] FIGS. 3-11 show various stages in an example manufacturing process for manufacturing the substrate core example of FIG. 2. [Figure 4] [[ID=Z2]]FIGS. 3-11 show various stages in an example manufacturing process for manufacturing the substrate core example of FIG. 2. [Figure 5] FIGS. 3-11 show various stages in an example manufacturing process for manufacturing the substrate core example of FIG. 2. [Figure 6] FIGS. 3-11 show various stages in an example manufacturing process for manufacturing the substrate core example of FIG. 2. [Figure 7] FIGS. 3-11 show various stages in an example manufacturing process for manufacturing the substrate core example of FIG. 2. [Figure 8]Figures 3-11 show the various steps in an example manufacturing process for producing the substrate core example shown in Figure 2. [Figure 9] Figures 3-11 show the various steps in an example manufacturing process for producing the substrate core example shown in Figure 2. [Figure 10] Figures 3-11 show the various steps in an example manufacturing process for producing the substrate core example shown in Figure 2. [Figure 11] Figures 3-11 show the various steps in an example manufacturing process for producing the substrate core example shown in Figure 2. [Figure 12] Other examples of board cores that can be used to mount the example board core in Figure 1 are shown. [Figure 13] Other examples of board cores that can be used to mount the example board core in Figure 1 are shown. [Figure 14] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 15] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 16] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 17] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 18] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 19] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 20] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 21]Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 22] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 23] Figures 14-23 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 13. [Figure 24] Other package substrate examples that can be used to mount the substrate core example in Figure 1 are shown. [Figure 25] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 26] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 27] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 28] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 29] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 30] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 31] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 32] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 33] Figures 25-35 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 24. [Figure 34]Figures 25 - 35 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 24. [Figure 35] Figures 25 - 35 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 24. [Figure 36] Another example of a package substrate that can be used to implement the package substrate example of FIG. 1 is shown. [Figure 37] Another example of a package substrate that can be used to implement the package substrate example of FIG. 1 is shown. [Figure 38] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 39] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 40] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 41] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 42] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 43] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 44] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 45] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 46] Figures 38 - 48 show various stages in another manufacturing process example for manufacturing the substrate core example of FIG. 37. [Figure 47]Figures 38-48 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 37. [Figure 48] Figures 38-48 show various steps in other manufacturing process examples for producing the substrate core example shown in Figure 37. [Figure 49] This flowchart illustrates an example of a method that may be performed to manufacture one of the package substrate examples and / or related substrate core examples shown in Figures 1-48. [Figure 50] This is a top view of a wafer containing a die that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 51] This is a side cross-sectional view of an IC device that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 52] This is a side cross-sectional view of an IC device assembly that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 53] This is a block diagram of an example of electrical equipment that may be included in an IC package constructed according to the teachings disclosed herein.

[0003] Generally, throughout the drawings and accompanying descriptions, the same or similar parts are referred to using the same reference numerals. Drawings are not necessarily to scale. Rather, the thickness of layers or areas may be enlarged in the drawings. Drawings show layers and areas with clear lines and boundaries, but some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, blended, and / or uneven. [Modes for carrying out the invention]

[0004] Figure 1 shows an example integrated circuit (IC) package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of contacts 104 on the mounting surface 105 of the package (e.g., the outer surface of the bottom). In the illustrated example, the contacts 104 are represented as pads or lands. However, in some examples, the IC package 100 may include, in addition to or instead of, the pads or lands shown, balls, pins, and / or any other type of contacts to enable the electrical coupling of the IC package 100 to the circuit board 102. In this example, the IC package 100 includes two semiconductor (e.g., silicon) dies 106, 108 (sometimes referred to as chips or chiplets) mounted on a package substrate 110 and surrounded by a package lid 112 (e.g., a mold compound, integrated heat spreader, IHS). Thus, the package substrate 110 is an example of means for supporting the semiconductor dies. The IC package example 100 in Figure 1 includes two dies 106 and 108, but in other examples, the IC package 100 may have only one die or three or more dies. In some examples, one of the dies 106 and 108 (or separate dies) is embedded in the package substrate 110. The dies 106 and 108 can provide any preferred type of function (e.g., data processing, memory storage, etc.).

[0005] As shown in the illustrated example, each of the dies 106 and 108 is electrically and mechanically coupled to the package substrate 110 via a corresponding array of interconnects 114. In Figure 1, the interconnects are shown as bumps. However, the interconnects 114 may be any other type of electrical connection (e.g., balls, pins, pads, wire bonding, etc.) in addition to or instead of the bumps shown. The electrical connection between the dies 106 and 108 and the package substrate 110 (e.g., interconnect 114) may be referred to as a first-level interconnect. In contrast, the electrical connection between the IC package 100 and the circuit board 102 (e.g., contact 104) may be referred to as a second-level interconnect. In some examples, one or both of the dies 106 and 108 may be stacked on top of one or more other dies and / or interposers. In such an example, dies 106, 108 may be coupled to a lower die and / or interposer via a first set of first-level interconnects, and the lower die and / or interposer may be connected to the package substrate 110 via another set of first-level interconnects associated with the lower die and / or interposer. Thus, as used herein, the first-level interconnect refers to an interconnect (e.g., ball, bump, pin, pad, wire bonding, etc.) between the die and the package substrate, or between the die and the lower die and / or interposer.

[0006] As shown in Figure 1, the interconnect 114 of the first level interconnect includes two different types of bumps corresponding to core bumps 116 and bridge bumps 118. When used here, the core bump 116 is a bump on the dies 106, 108 through which electrical signals pass between the dies 106, 108 and external components of the IC package 100. More specifically, as shown in the illustrated example, when the dies 106, 108 are mounted on the package substrate 110, the core bump 116 is physically connected and electrically coupled to a contact pad 120 on the inner surface 122 of the package substrate 110 (e.g., the upper, inner surface, top surface, etc.). The contact pad 120 on the inner surface 122 of the package substrate 110 is electrically coupled to a contact 104 on the mounting surface 105 of the package substrate 110 (e.g., the bottom, outer surface) (e.g., the surface opposite to the inner surface 122) via an internal interconnect 124 within the package substrate 110. As a result, a continuous electrical signal path exists between the core bumps 116 of dies 106 and 108 and the contacts 104 attached to the circuit board 102, passing through the contact pads 120 and interconnect 124 provided between them.

[0007] When used here, the bridge bump 118 is a bump on dies 106, 108 through which electrical signals pass between different dies 106, 108 within the IC package 100. Thus, as shown in the illustrated example, the bridge bump 118 of the first die 106 is electrically coupled to the bridge bump 118 of the second die 108 via an interconnect bridge 126 (e.g., a silicon-based interconnect bridge, interconnect die, or embedded interconnect bridge (EMIB)) embedded in the package substrate 110. As shown in Figure 1, the core bump 116 is typically larger than the bridge bump 118. In some examples, the interconnect bridge 126 and its associated bridge bump 118 are omitted.

[0008] In some examples, underfill material 119 is provided between dies 106, 108 and the package substrate 110, around and / or between the first level interconnect 114 (for example, around and / or between the core bump 116 and / or bridge bump 118). In the illustrated example, only the first die 106 is accompanied by underfill material 119. However, in other examples, both dies 106 and 108 are accompanied by underfill material 119. In other examples, the underfill material 119 is omitted. In some examples, the mold compound used for the package lid 112 is used as the underfill material surrounding the first level interconnect 114.

[0009] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors, which are located on the mounting surface 105 and / or the inner surface 122 of the package substrate 110.

[0010] In Figure 1, the substrate 110 of the IC package example 100 includes a substrate core 128 (e.g., main core, overall core) between two separate build-up layers or regions 130, 131 (e.g., redistribution layers or regions). As shown in the illustrated example, the substrate core 128 includes a plurality of separate glass cores (e.g., a plurality of glass layers, a plurality of glass core layers, etc.), namely, a top glass core example 132 (e.g., a first glass core), an intermediate glass core example 134 (e.g., a second glass core), and a bottom glass core example 136 (e.g., a third glass core). In the illustrated example of Figure 1, the glass cores 132, 134, and 136 (e.g., subcores, glass substrates, glass layers, glass sheets) are stacked on top of each other.

[0011] In some examples, cores 132, 134, and 136 contain at least one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and / or fused silica. In some examples, cores 132, 134, and 136 contain one or more additives including aluminum oxide (Al2O3), boron trioxide (B2O3), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, cores 132, 134, and 136 contain silicon and oxygen. In some examples, cores 132, 134, and 136 contain one or more of silicon, oxygen, and / or aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, cores 132, 134, and 136 contain at least 23 weight percent silicon and at least 26 weight percent oxygen. In some examples, glass cores 132, 134, and 136 are separate layers of glass containing silicon, oxygen, and aluminum. In some examples, cores 132, 134, and 136 contain at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum.

[0012] In some examples, cores 132, 134, and 136 are amorphous solid glass layers. In some examples, cores 132, 134, and 136 are glass layers that do not contain organic adhesives or organic materials. In some examples, cores 132, 134, and 136 are solid glass layers that have a rectangular shape in plan view. In some examples, cores 132, 134, and 136 include at least one glass layer as a glass substrate, but do not contain epoxy or glass fibers (e.g., they do not contain an epoxy prepreg layer with glass cloth). In some examples, cores 132, 134, and 136 correspond to a single piece of glass extending across the total height / thickness of each corresponding core.

[0013] In some examples, cores 132, 134, and 136 have a rectangular shape in plan view, having substantially the same extent as the layers above and / or below the core. In some examples, cores 132, 134, and 136 have a thickness ranging from approximately 25 micrometers (μm) to approximately 400 μm (with the total thickness of the substrate core 128 ranging from approximately 50 μm to approximately 1.4 millimeters (mm)). In some examples, cores 132, 134, and 136 can have dimensions ranging from approximately 10 mm to approximately 250 mm on each side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some examples, cores 132, 134, and 136 correspond to rectangular prism volumes from which sections (e.g., vias) have been removed and filled with other materials (e.g., metal).

[0014] In Figure 1, the build-up regions 130, 131 are represented as lumps / blocks having internal interconnects 124 extending linearly through the build-up regions 130, 131 (and the glass cores 132, 134, 136). However, Figure 1 is simplified for clarity and illustrative purposes. In reality, the interconnects are not necessarily linear. More specifically, in some examples, the build-up regions 130, 131 are defined by alternating layers of dielectric material and layers of conductive material (e.g., metal such as copper). The conductive (metal) layers serve as the basis for the internal interconnects 124, which are represented in a simplified linear form as shown in Figure 1. In some examples, the metal layers are patterned to define electrical wiring or conductive traces that are electrically coupled between different metal layers by conductive (e.g., metal) vias extending through the intervening dielectric layers. Furthermore, electrical wiring or traces on either side of the substrate core 128 may be electrically coupled by through-glass vias (TGVs) (e.g., copper-plated vias) extending through the glass cores 132, 134, and 136.

[0015] In some examples, one or both of the build-up regions 130 and 131 may be omitted. That is, in some examples, the stack of glass cores 132, 134, and 136 defines most of the thickness of the package substrate 110 (e.g., all or substantially all) (e.g., all except the outer solder resist layer, all except the reduced set of metallization layers in the build-up regions 130 and 131). In some such examples, the stack of glass cores 132, 134, and 136 includes four or more glass layers, and the rerouting of the electrical path defined by the interconnect 124 is achieved by traces or wiring running parallel to those glass layers and between adjacent glass layers among those glass layers.

[0016] In particular, glass cores are advantageous over epoxy-based cores because glass is harder and therefore provides greater mechanical support or strength to the package substrate. Thus, the substrate core 128, and more specifically the individual glass cores 132, 134, and 136, are examples of means for reinforcing the package substrate. In addition to mechanical benefits, glass cores also offer other advantages, including higher plated through-hole (PTH) density, lower signal loss, and lower overall thickness variation. Furthermore, glass can be manufactured with a much flatter surface than is possible with epoxy-based materials. As a result, glass can serve as a foundation for the development of thinner and more controlled dielectric layers and / or metallization layers within build-up regions. In some examples, the higher PTH density available with glass cores, and greater control in developing layers of material on the relatively flat surface of the glass core, can enable build-up regions (e.g., redistribution layers or regions) with finer line spaces. For example, some known epoxy-based package substrates include a dielectric layer with a thickness of approximately 25 μm. In contrast, some of the examples disclosed herein may include dielectric layers with thicknesses such as approximately 10 μm or less, approximately 5 μm or less, and approximately 1 μm or less.

[0017] While the above advantages can be realized in the disclosed examples, glass cores also present challenges due to the fragile (e.g., brittle) nature of glass and the potential for defects to develop into cracks propagating through the glass. A common type of failure of known glass cores is called seware failure. Seware results in the separation of the glass core along a crack propagating from the edge of the glass core along its length and width between the main outer surfaces of the glass core (e.g., top and bottom, front and back). That is, seware is characterized by the glass core splitting into two separate glass sheets along a line extending generally parallel to the main surface of the glass core.

[0018] Factors contributing to seware include defects on the edges of the glass core resulting from fragmentation, and internal stresses induced by the mismatch between the coefficient of thermal expansion (CTE) of the glass core (e.g., CTE of approximately 3 ppm / °C to 10 ppm / °C) and the CTE of the build-up region material (e.g., approximately 39 ppm / °C for the organic dielectric layer, approximately 17 ppm / °C for copper, and approximately 2.6 ppm / °C for silicon) during the thermal cycling of the package substrate 110 (either during the manufacturing process or during subsequent use). More specifically, package substrates, such as the package substrate 110 in Figure 1, are often manufactured on large panels that are later fragmented or cut into individual units with a saw. Accordingly, in the example shown in Figure 1, the package substrate 110, including the substrate core 128 (and associated subcores 132, 134, 136) and build-up regions 130, 131, includes an opposite edge 138 created by sawing. Such sawing can lead to the growth of defects at the edges of the glass core (e.g., the edges 138 of the glass cores 132, 134, 136 in Figure 1), which can cause cracks to propagate across the center of the glass core, splitting it into two main pieces. Such crack growth and propagation are exacerbated by stresses induced by temperature fluctuations and the difference in CTE between the glass core and the build-up regions. Generally, the materials of the build-up regions 130, 131 have a higher CTE than the glass. As a result, the materials of the build-up regions 130, 131 expand and contract more than the glass core in response to thermal fluctuations, thereby creating internal stresses within the glass core that can promote crack propagation.

[0019] The examples disclosed herein reduce (e.g., minimize) concerns about sewaring by mounting a substrate core 128 of a substrate with multiple separate (e.g., separate) glass cores (e.g., glass cores 132, 134, 136) stacked on top of each other, as shown in Figure 1. More specifically, in the examples disclosed herein, different laminated cores are mounted by different materials (or different compositions of the same material) associated with different material properties (e.g., different CTEs). That is, in some examples, different CTEs of different glass cores 132, 134, 136 can be tuned by adjusting (e.g., changing, altering, etc.) the relative ratios of Al2O3, B2O3, Li2O, Na2O, K2O, Sb2O3, and / or other additives in each layer, and / or by variations in processing (e.g., lamination coating, heat treatment, etc.). In some cases, glass cores closer to build-up regions 130 and 131 are manufactured to have a CTE closer to the CTE of build-up regions 130 and 131 than glass cores further away from build-up regions 130 and 131 (e.g., closer to the center of the glass core stack). Thus, the substrate core 128 is defined by a gradual or progressive change in CTE (e.g., between adjacent glass cores 132, 134, and 136 in the stack) that provides interlayer transitions within the package substrate 110 to reduce stress at any given location.

[0020] For example, in some cases, the intermediate glass core 134 has a lower CTE than the top glass core 132 and a lower CTE than the bottom glass core 136. In some cases, the CTEs of the top glass core 132 and the bottom glass core 136 are the same. Thus, in some cases, the different CTEs of the glass cores 132, 134, and 136 are symmetrical across the entire thickness of the substrate core 128. That is, the stack of glass cores 132, 134, and 136 and the arrangement or order of their associated CTEs define a symmetrical sequence of CTEs (e.g., a symmetrical CTE gradient) from the bottom glass core (e.g., the third glass core 136) to the top glass core (e.g., the first glass core 132). In some such cases, the lowest CTE value in the symmetrical CTE gradient is closer to the center of the stack of glass cores than the highest CTE value in the symmetrical CTE gradient (closer to the top and bottom of the stack). In other examples, the different CTEs do not have to be symmetrical. For example, in some examples, the top glass core 132 (e.g., the glass core closest to dies 106, 108) has the highest CTE in the stack, the bottom glass core 136 (e.g., the glass core furthest from dies 106, 108) has the lowest CTE, and the intermediate glass core 134 has a CTE between the other two. In other examples, the top glass core 132 (e.g., the glass core closest to dies 106, 108) has the lowest CTE in the stack, and the bottom glass core 136 has the highest CTE in the stack. Any other preferred configuration can be implemented to achieve any preferred CTE gradient across the entire substrate core 128, or additionally, or instead, to make the CTE values ​​different across any preferred number of stacked glass cores.

[0021] In addition to implementing multiple glass cores with different CTEs (e.g., glass cores 132, 134, 136) to reduce stress, in some examples, as already mentioned above, one or both of the build-up regions 130, 131 are omitted or their thickness is significantly reduced (e.g., the number of metallization layers contained within them is reduced and / or they are implemented with much thinner layers). As a result, the stress generated on glass cores 132, 134, 136 due to the mismatch in CTEs between the glass and the build-up regions 130, 131 is reduced.

[0022] Furthermore, in some examples, a buffer material 140 (e.g., buffer layer, adhesive material / layer) is placed between adjacent glass cores 132, 134, and 136 to hold the glass cores together. In some such examples, the buffer material 140 has a relatively low modulus of elasticity to absorb thermal fluctuations and stresses arising from the different CTEs of the different glass cores 132, 134, and 136, thereby further reducing the stress inside the substrate core 128. In some examples, the buffer material 140 is an organic dielectric material (e.g., polyimide, parylene, etc.). In some examples, the buffer material 140 is an inorganic dielectric material (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN x)) In some examples, the buffer material 140 includes carbon-doped oxide (CDO). In some examples, the buffer material 140 includes the same or similar dielectric material used in the build-up regions 130 and 131. In some examples, the layers of the buffer material 140 include a conductive material that facilitates the redistribution of electrical paths between the glass cores 132, 134, and 136. Thus, the material between the glass cores is also referred to here as the redistribution material. The redistribution material may include one or more redistribution layers within the package substrate 110. Similarly, in such examples, the stack of glass cores 132, 134, and 136 may be referred to here as the redistribution region or redistribution layer. In some examples, one or more layers of the buffer material 140 may be omitted so that different glass cores 132, 134, and 136 are in direct contact with each other. In some such examples, the stack of glass cores 132, 134, and 136 can still function as a redistribution region or layer, based on the fact that traces or wirings are located within trenches etched along the plane of one or more of the glass cores 132, 134, and 136.

[0023] The higher PTH density and finer line spacing in some examples are associated with higher IO density, which in turn involves a greater amount of heat that needs to be dissipated. In many known IC packages, heat is dissipated from the back surface of the semiconductor die (e.g., the side not facing the package substrate) through an integrated heat spreader IHS (e.g., similar to the package lid 112). In some examples disclosed herein, the IC package 100 includes one or more metal slags 142 located within and / or extending through one or more of the glass cores 132, 134, and 136. In such examples, the (one or more) metal slags 142 extend to the package lid 112 and / or other outer portions of the IC package 100 and / or are thermally bonded to them in other ways. As a result, the (one or more) slags 142 provide a heat conduction path from inside the stack of glass cores 132, 134, 136 (e.g., adjacent to the front surfaces of the semiconductor dies 106, 108) to the outer surface of the IC package 100, facilitating heat dissipation. In some examples, the (one or more) metal slags 142 consist of the same metal (e.g., copper) used in the interconnect 124. In the illustrated example, the metal slag 142 is thermally bonded to the top wall 144 of the lid 112. In other examples, the metal slag 142 is thermally bonded to the side wall 146 of the lid 112. In some examples, the metal slag 142 is bonded to both the top wall 144 and the side wall 146. In some examples, the metal slag 142 is omitted.

[0024] Three different glass cores (e.g., glass cores 132, 134, and 136) are shown in example substrate core 128 of Figure 1, but any other suitable number of glass cores may be mounted having corresponding CTEs such that they define a particular CTE gradient across the entire thickness of the substrate core 128. Thus, in some examples, only two glass cores, each having a different CTE, are used. In other examples, more than three glass cores are used. In some such examples, each glass core is different from all the other glass cores in the core stack. In other examples, two or more of the glass cores may have the same CTE (e.g., made from the same material of the same composition), and at least one glass core may have a different CTE from the others.

[0025] In the example shown in Figure 1, the glass cores 132, 134, and 136 are shown as having the same thickness (e.g., approximately equal thickness). However, in some examples, the thicknesses of the glass cores 132, 134, and 136 may differ from each other. For example, in some examples, the intermediate glass core 134 is thicker than the top glass core 132 and thicker than the bottom glass core 136. In other examples, the intermediate glass core 134 is thinner than the top glass core 132 and thinner than the bottom glass core 136. Any preferred thickness of the glass cores can be implemented to provide sufficient rigidity to the package substrate while achieving a suitable CTE gradient for reducing stress to mitigate sewerage.

[0026] Figure 2 shows an example board core 200 that may be used to mount the example board core 128 of Figure 1. Similar to Figure 1, the board core 200 of Figure 2 includes a first glass core 202 (e.g., top glass core), a second glass core 204 (e.g., middle glass core), and a third glass core 206 (e.g., bottom glass core) stacked on top of each other. In other examples, a different number of glass cores may be included in the stack. In this example, the different glass cores 202, 204, and 206 correspond to the glass cores 132, 134, and 136 of Figure 1. Thus, the glass cores 202, 204, and 206 have different CTEs as described above. For example, in some examples, the second glass core 204 (e.g., middle glass core) has a lower CTE than either the first glass core 202 or the third glass core 206. In this example, each of the glass cores 202, 204, and 206 has approximately the same thickness. In some examples, the thickness is approximately 350 μm. In other examples, the thickness may be greater or less than 350 μm. Also, in some examples, different glass cores 202, 204, and 206 may have different thicknesses. Furthermore, although three glass cores are shown, in some examples, any other preferred number of glass cores (e.g., 2, 4, 5, 6, 7, etc.) may be used. In such examples, the stack of glass cores can define any preferred CTE gradient based on the difference in CTE of each glass core in the stack. In some examples, the CTE gradient is symmetrical across the entire thickness of the substrate core 200. In other examples, the CTE gradient is not symmetrical.

[0027] In the illustrated example, the different glass cores 202, 204, and 206 are separated by an intervening layer of dielectric material 208 (e.g., adhesive material, adhesive resin). In some examples, the dielectric material 208 includes an organic epoxy dielectric. However, any other suitable dielectric may be used in addition or in place.

[0028] In some examples, a liner 210 is placed between the dielectric material 208 and the interface of the glass cores 202, 204, and 206. Furthermore, in this example, the liner 109 also covers the outermost surface of the outermost glass core (e.g., the first glass core 202 and the third glass core 206). Thus, in this example, the liner 210 defines the first and second outer surfaces 212 and 214 of the entire substrate core 200. However, in some examples, the outermost layer of the liner 210 is omitted. In such examples, the outer surfaces of the first and third glass cores 202 and 206 define the first and second outer surfaces 212 and 214 of the entire substrate core 200.

[0029] In some examples, the liner 210 comprises the same or similar material as the dielectric material 208. Therefore, in some such examples, the liner 210 has a relatively low modulus of elasticity, which helps absorb thermal fluctuations and stresses arising from the different CTEs of the different glass cores 202, 204, and 206. In some examples, the liner 210 is an organic dielectric material (e.g., polyimide, parylene, etc.). In some examples, the liner 210 is an inorganic dielectric material (e.g., silicon oxide (SiO₂)). x ), silicon nitride (SiN x In some cases, liner 210 contains carbon-doped oxide (CDO).

[0030] In the illustrated example in Figure 2, the glass cores 202, 204, and 206 include glass through-vias (TGVs) 216 electrically coupled by an additional conductive material 218 extending through an intervening layer of dielectric material 208. In some examples, the TGVs 216 are plated with the same material used for the additional conductive material 218 (e.g., copper, aluminum, nickel, tin, etc.). In some examples, at least a portion of the additional conductive material 218 contains a different material from the TGVs 216. Furthermore, as shown in the illustrated example, a conductive pad 220 is positioned at one end of each TGV 216 (e.g., adjacent to the surfaces on both sides of the corresponding glass cores 202, 204, and 206). In some examples, the conductive pad 220 is an integral extension of the TGVs 216 within the glass cores 202, 204, and 206. Thus, as shown in the illustrated example, the conductive pad 220 electrically couples the TGVs 216 with the additional conductive material 218. In this example, the outermost conductive pads 220 (for example, along the first and second outer surfaces 212, 214) define both ends of an interconnect (for example, portion of interconnect 124 in Figure 1) that extends through the entire thickness of the substrate core 200. Although three TGVs 216 are shown within each glass core 202, 204, 206, any preferred number of TGVs 216 can be present and they can be positioned at any preferred location across the planes of the glass cores 202, 204, 206.

[0031] In some examples, as shown in Figure 2, the liner 210 lines the inner walls of openings that penetrate the glass cores 202, 204, and 206 defining the TGV216. That is, in some examples, the liner 210 surrounds the TGV216, separating the glass cores 202, 204, and 206 from the TGV216. In some examples, the liner 210 extends along the entire length of the TGV216 (e.g., the total thickness of the corresponding glass cores 202, 204, and 206) so that there is no contact between the glass cores 202, 204, and 206 and the TGV216. In other examples, the liner 210 is shorter than the entire length of the TGC (e.g., shorter than the total thickness of the glass cores 202, 204, and 206) and partially extends within the glass cores 202, 204, and 206. More specifically, as shown in the example in Figure 2, the liner 210 is located within the glass cores 202, 204, and 206, adjacent to both ends of the TGV 216 and separated from the central portion of the TGV 216. Thus, the liner 210 is positioned at known stress concentration points (for example, points on the glass cores 202, 204, and 206 adjacent to where the TGV 216 intersects with the conductive pads (sometimes referred to as triple points)) and acts as a buffer to reduce stress at those locations. In some examples, the liner 210 is omitted within the openings of the glass cores 202, 204, and 206 that define the TGV 216. In some examples, the liner 210 is omitted at all points on the substrate core 200.

[0032] Figures 3-11 illustrate various stages in an example manufacturing process for producing the substrate core example 200 of Figure 2. Figure 3 represents a glass panel 300 corresponding to the initial state of one of the glass cores 202, 204, or 206. For illustrative purposes, the glass panel 300 is illustrated and described as corresponding to the second glass core 204 (for example, the intermediate glass core in the substrate core 200 of Figure 2). In some examples, the glass panel 300 is manufactured to a thickness corresponding to the final thickness of the glass core 204. However, in some examples, the glass panel 300 is initially slightly larger than the final thickness of the glass core 204 to allow some amount of glass to be removed during subsequent polishing or planarization processes, which will be described further later.

[0033] Figure 4 shows the manufacturing stage after the glass core 204 of Figure 3 is exposed to a laser, as part of the laser-induced deep etching (LIDE) process. The laser is focused on defined regions 402 of the glass core 204, modifying the optical and chemical properties of the glass core 204 in those regions 402. Figure 5 shows the manufacturing stage after a chemical etching process to remove material from the modified regions 402 of the glass core 204 shown in Figure 4, thereby defining the aperture 502 (e.g., hole) for the TGV 216 shown in Figure 2. In this example, the aperture 502 has a cross-sectional profile that generally corresponds to an hourglass shape, and the width (e.g., diameter) of the aperture 502 is narrower near the midpoint of the aperture between the first and second surfaces 504, 506 on both sides of the glass core 204. In other examples, one or more of the apertures 502 may have different cross-sectional shapes. For example, in some examples, one or more of the openings 502 may be generally conical or tapered, with the width (e.g., diameter) being smallest on one of the two surfaces 504, 506 of the glass core 204 and the width (e.g., diameter) being largest on the opposite surface 504, 506. In other examples, the width (e.g., diameter) of one or more of the openings 502 is substantially constant along the entire length of the opening 502 between the two surfaces 504, 506 of the glass core 204.

[0034] Figure 6 shows the manufacturing stage of the glass core 204 of Figure 5 after coating with the liner 210 of Figure 2. In some examples, the liner 210 is deposited using omnidirectional thin film deposition techniques (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). In such examples, all exposed surfaces of the glass core 204 are coated. In other examples, as shown in the illustrated example, directional thin film deposition techniques (e.g., physical vapor deposition (PVD), spray coating, etc.) may be used to deposit the liner 210 on either side (e.g., each outer surface 504, 506), and only the inner wall of the opening 502 may be partially coated.

[0035] Figure 7 illustrates the manufacturing stage after a conductive material 702 (e.g., copper, aluminum, nickel, tin, etc.) has been deposited (e.g., plated) within the opening 502 to define the TGV 216 extending through the glass core 204. In some examples, the conductive material 702 is also deposited on the outer surfaces 504, 506 of the glass core 204, as shown in Figure 7. In some examples, the conductive material 702 is deposited via an electroplating process after the deposition of a metal seed layer (e.g., on the liner 210 and the exposed portion of the glass core 204 within the opening 502). In other examples, the TGV 216 is plated from bottom to top. In such examples, the glass core 204 of Figure 5 is first mounted on a conductive carrier to provide metal at the bottom of the opening 502 to enable the start of the plating process. In such examples, the seed layer may be omitted. The manufacturing stage shown in Figure 7 is also after a polishing process (e.g., a CMP process) to flatten or planarize the conductive material 702 on the outer surfaces 504 and 506 of the glass core.

[0036] Figure 8 shows the manufacturing stage after the removal (e.g., by etching) of a selected portion of the conductive material 702 for defining the conductive pad 220. In some examples, the selected portion of the conductive material 702 to be removed is defined by a photolithography process. In some examples, the second surface 506 of the glass core undergoes a polishing process (e.g., a CMP process) to make both the dielectric material 208 and TGV 216 coplanar with the second surface 506. In some examples, the assembly also undergoes a cleaning process to remove any remaining material.

[0037] Figure 9 shows the manufacturing steps after the addition of the dielectric material 208 adjacent to the first surface 504 of the glass core 204. In some examples, the dielectric material 208 is added through a lamination process. Figure 9 also shows the result of adding an opening 902 (e.g., a hole) through the dielectric material 208 to expose the underlying conductive pad 220 associated with the TGV 216. More specifically, in some examples, the opening 902 is created by a drilling process (e.g., laser drilling).

[0038] Figure 10 illustrates the manufacturing steps after the deposition of additional conductive material 218 into the opening 902 of the assembly shown in Figure 9. In some examples, the additional conductive material 218 is dispensed into the opening 902 as a liquid metal and / or paste (e.g., copper paste and / or other suitable metals (e.g., aluminum, nickel, tin, etc.)). In some examples, the additional conductive material 218 is deposited by a plating process. In some examples, any excess amount of additional conductive material 218 (e.g., extending beyond and / or above the outer surface of the dielectric material 208) is removed through a polishing process (e.g., a CMP process) so that both the dielectric material 208 and the additional conductive material 218 are coplanar with each other.

[0039] Figure 11 illustrates the manufacturing process in which the three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining the respective glass core assemblies 1102, 1104, and 1106. In this example, the glass core assemblies 1102, 1104, and 1106 in Figure 11 are the result of processing the corresponding glass cores 202, 204, and 206 through the manufacturing process shown in Figure 3-10. That is, the second glass core 204 processed up to the point shown in Figure 10 corresponds to the second glass core assembly 1104 shown in Figure 11. Furthermore, as shown in Figure 11, the third glass core assembly 1106 is substantially the same as or equivalent to the second glass core assembly 1104, except that it has a different glass core with a different CTE (for example, the third glass core 206 instead of the second glass core 204). Similarly, the first glass core assembly 1102 is similar to the other two glass core assemblies 1104 and 1106, except that it has a different glass core 202 (having a different CTE) and lacks a buffer layer 208 in which an additional conductive material 218 is placed. That is, in some examples, the first glass core assembly 1102 in Figure 11 is completed by the manufacturing steps shown in Figure 8 (for example, the manufacturing processes described in relation to Figures 9 and 10 may be omitted). In some examples, once the different glass core assemblies 1102, 1104, and 1106 are assembled (as shown in Figure 11), the stack is pressed (e.g., subjected to compression) and undergoes a curing process to bond the assemblies. The final result of combining or bonding the different glass core assemblies 1102, 1104, and 1106 produces the substrate core 200 shown in Figure 2.

[0040] Figure 12 shows another example substrate core 1200 that may be used to mount the example substrate core 128 of Figure 1. The example substrate core 1200 of Figure 12 is substantially the same as the example substrate core 200 of Figure 2, except as described below or otherwise evident from the context. Thus, features shown in Figure 12 that are the same or similar as the corresponding features in Figure 2 (and related Figures 3-11) are identified by the same reference numerals. Also, the descriptions of features described above in relation to Figure 2 (and related Figures 3-11) apply similarly to the corresponding features in Figure 12. For example, as shown in Figure 12, the example substrate core 1200 includes glass cores 202, 204, and 206, through which a TGV 216 extends, including conductive pads 220 at both ends. Upper and lower adjacent TGVs 216 are electrically coupled by an additional conductive material 218 extending through an intervening layer of dielectric material 208.

[0041] One difference between Figure 12 and Figure 2 is the omission of the liner 210. That is, in the illustrated example of Figure 12, the TGV216 is plated directly onto the glass cores 202, 204, and 206. In some such examples, the TGV216 includes a seed layer in direct contact with the surfaces of the glass cores 202, 204, and 206 to facilitate the bulk plating of the TGV216. In other examples, the seed layer is omitted (for example, when the TGV216 is plated from bottom to top). In some examples, the substrate core 1200 in Figure 12 includes the liner 210 as described above in relation to Figure 2.

[0042] Figure 12 also differs from Figure 2 in that it includes a metal slag 1202 in which glass cores 202, 204, and 206 are arranged. When used here, the metal slag is a relatively large mass (e.g., greater than TGV216) of metal that can facilitate heat dissipation by providing a heat conduction path for heat within the package substrate (e.g., package substrate 110 in Figure 1) to be transferred away from the substrate (e.g., towards an integrated heat spreader such as the package lid 112 in Figure 1). The metal slag 1202 can be used to implement the metal slag example 142 in Figure 1. In the illustrated example of Figure 12, the metal slag 1202 in separate glass cores 202, 204, and 206 is thermally bonded by an additional conductive material 1204 extending through an intervening layer of dielectric material 208. In this example, the additional conductive material 1204 that bonds the metal slags 1202 together is substantially the same as or equivalent to the additional conductive material 218 that bonds the TGVs 216 together.

[0043] In the example shown in Figure 12, the portion of additional conductive material 1204 between adjacent metal slags 1202 is shown to be substantially the same size as and substantially the same distance apart as the portion of additional conductive material 218 between adjacent TGVs 216. However, in other examples, the portion of additional conductive material 1204 between adjacent metal slags 1202 may be larger or smaller than shown, and may be located closer or further away than shown. Furthermore, although Figure 12 shows two portions of additional conductive material 1204 between adjacent metal slags 1202, in other examples, any other suitable number (e.g., 1, 2, 3, 4, 5, etc.) may be used (this may depend on the size of the additional conductive material 1204 and the size of the associated metal slags 1202).

[0044] In some examples, the manufacturing of the substrate core example 1200 in Figure 12 follows the same general process corresponding to the manufacturing steps shown in Figures 2-13. However, the laser-induced deep etching (LIDE) process described above in relation to Figures 4 and 5 is modified to etch a larger opening 502 within the glass core 204, corresponding to the size of the metal slag 1202. The process proceeds as outlined above, except that the addition of a liner (detailed in relation to Figure 6) is omitted. In particular, the deposition (e.g., plating) of conductive material 702 within the opening 502 to provide the TGV 216 (as detailed in relation to Figure 7) simultaneously provides the metal slag 1202. Also, in the manufacturing step shown in Figure 8, the portion of conductive material 702 to be removed is selected to define both the conductive pad 220 (at the end of the TGV 216 adjacent to the outer surface of the second glass core 204) and an additional conductive pad 1206 at the end of the metal slag 1202 shown in Figure 12.

[0045] Figure 13 shows another example substrate core 1300 that may be used to mount the example substrate core 128 of Figure 1. The example substrate core 1300 in Figure 13 is substantially the same as the examples substrate cores 200 and 1200 in Figures 2 and 12, except as described below or otherwise evident from the context. Accordingly, features shown in Figure 13 that are the same as or similar to the corresponding features in Figures 2 and 12 (and related Figures 3-11) are identified by the same reference numerals. Furthermore, the feature descriptions described above in relation to Figures 2 and 12 (and related Figures 3-11) apply similarly to the corresponding features in Figure 13.

[0046] The example in Figure 13 differs from the example in Figure 12 in that a buffer layer 1302 is added to the outer surface of each glass core 202, 204, 206, separating the conductive pads 220, 1206 from the surfaces of the glass cores 202, 204, 206. Furthermore, as shown in the illustrated example, the buffer layer 1302 is positioned between the glass cores 202, 204, 206 and the adjacent dielectric material 208 used to connect the different glass cores 202, 204, 206 together. In some examples, the buffer layer 1302 contains dielectric material that is imparted through a lamination process. In some examples, the buffer layer 1302 is made of the same material as the dielectric material 208. In other examples, the buffer layer 1302 is made of a different material than the dielectric material 208.

[0047] As shown in Figure 13, the conductive pad 1206 associated with the metal slag 1202 is thermally (e.g., electrically) coupled to the body of the metal slag 1202 by one or more conductive vias 1304 (e.g., copper vias) extending through the corresponding buffer layers of the buffer layer 1302. Similarly, in this example, the conductive pad 220 associated with the TGV 216 is electrically coupled to the body of the TGV 216 in the glass cores 202, 204, and 206 by additional conductive vias 1306 (e.g., copper vias) extending through the corresponding buffer layers of the buffer layer 1302. In the example shown in Figure 13, the metal slag 1202 is thermally coupled to the conductive pad 1206 via two conductive vias 1304. However, in other examples, any preferred number (e.g., 1, 2, 3, 4, 5, etc.) of conductive vias 1304 can be placed between the metal slag 1202 and the corresponding conductive pad 1206. Furthermore, the conductive via 1304 can be any suitable size, which is the same size as or smaller than the metal slag 1202. In some examples, the buffer layer 1302 within the conductive via 1306, as shown in Figure 13, can be mounted together with the substrate core example 200 shown in Figure 2.

[0048] Figures 14–22 illustrate various stages in an example manufacturing process for producing the substrate core example 1300 of Figure 13. Many of the manufacturing stages shown in Figures 14–22 are similar to or identical to the manufacturing stages described above in relation to Figures 3–11. Therefore, similar features will be given similar reference numerals, and the descriptions provided above apply to Figures 14–22, except where otherwise evident from the context. Figure 14 represents a glass panel 1400 corresponding to one of the initial states of glass cores 202, 204, and 206. For illustrative purposes, glass panel 1400 is illustrated and described as corresponding to a second glass core 204 (e.g., the intermediate glass core in the substrate core 1300 of Figure 13), and is similar to glass panel 300 in Figure 3.

[0049] Figure 15 shows the manufacturing stage after the glass core 204 has been exposed to a laser as part of a laser-induced deep etching (LIDE) process similar to that described above in relation to Figure 4. The laser is focused on defined regions 402 of the glass core 204, modifying the optical and chemical properties of the glass core 204 in those regions 402. Figure 16 shows the manufacturing stage after a chemical etching process to remove the material within the modified regions 402 of the glass core 204 shown in Figure 15, thereby defining the aperture 502 for TGV216. Furthermore, unlike those shown in Figures 4 and 5, one of the regions 402 in Figure 15 is much larger, resulting in a larger second aperture 1602 shown in Figure 16. The larger second aperture 1602 serves as the base for the metal slag 1202 in Figure 13.

[0050] Figure 17 shows the manufacturing stage after the glass core 204 has been attached to the conductive carrier 1702. In this example, the conductive carrier includes a conductive layer 1704 (e.g., a copper layer) and a release layer 1706 (e.g., an adhesive dielectric layer). Figure 18 shows the manufacturing stage after an etching process (e.g., plasma etching, dry etching) to remove the portion of the release layer 1706 exposed within the openings 502, 1602 of the glass core 204, thereby exposing the underlying conductive layer 1704.

[0051] Figure 19 shows the manufacturing stage after the deposition (e.g., plating) of conductive material 1902 (e.g., copper, aluminum, nickel, tin, etc.) within the openings 502, 1602 to define the TGV 216 and metal slag 1202 extending through the glass core 204. In this example, the TGV 216 and metal slag 1202 are plated from the exposed portion of the conductive layer 1704 upwards. Therefore, in this example, there is no seed layer deposited along the walls of the openings 502, 1602 prior to the plating process. However, in other examples, a seed layer may be used to facilitate the plating of the TGV 216 and metal slag 1202. The manufacturing stage shown in Figure 19 is also after a subsequent polishing process (e.g., a CMP process) to remove any excess conductive material 1902 extending above the first surface 504 of the glass core 204. Therefore, in some cases, both TGV216 and the metal slag 1202 are coplanar with the first surface 604.

[0052] Figure 20 shows the manufacturing stage after the removal of the conductive carrier 1702, which includes both the conductive layer 1704 and the release layer 1706. In some examples, the second surface 506 of the glass core undergoes a polishing process (e.g., a CMP process) to make both the TGV216 and the metal slag 1202 coplanar with the second surface 506. In some examples, this assembly also undergoes a cleaning process to remove any residual material.

[0053] Figure 21 illustrates the manufacturing steps after the application of buffer layers 1302 (e.g., adhesive layers, dielectric layers) to the first and second surfaces 504 and 506 of the glass core 204, respectively. In some examples, the buffer layers 1302 are applied through a lamination process. Figure 21 also illustrates the result of adding conductive vias 1304 and 1306 through the buffer layers 1302 to bond the underlying TGV 216 and metal slag 1202 to accompanying conductive pads 220 and 1206. More specifically, holes (e.g., openings) are drilled through the buffer layers 1302 to expose the ends of the TGV 216 and metal slag 1202, and then the holes are filled (e.g., plated) to define the material for the conductive vias 1304 and 1306 and to generate the conductive pads 220 and 1206.

[0054] Figure 22 shows the manufacturing stage after the dielectric material 208 has been applied adjacent to the first surface 504 of the glass core 204, similar to the process described above in relation to Figure 9. Figure 22 also shows additional conductive material 218 within the dielectric material 208, similar to those described above in relation to Figures 9 and 10.

[0055] Figure 23 illustrates the manufacturing process in which the three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining the respective glass core assemblies 2302, 2304, and 2306. In this example, the glass core assemblies 2302, 2304, and 2306 in Figure 23 are the result of processing the corresponding glass cores 202, 204, and 206 through the manufacturing processes shown in Figures 14-22, similar to those described above in relation to Figure 11.

[0056] Figure 24 shows a portion of package substrate example 2400 that may be used to mount package substrate example 110 of Figure 1. Package substrate example 2400 of Figure 24 includes substrate core example 2402 and fine line spacing (FLS) build-up region or layer example 2404 (e.g., FLS redistribution region or layer). Substrate core example 2402 can be used to mount substrate core example 128 of Figure 1, and FLS build-up region example 2404 can be used to mount the first build-up region example 130 of Figure 1. In this example, the second build-up region 131 of Figure 1 is omitted. In other examples, the second build-up region 131 may be included (either by using the current lamination process to add a dielectric layer, or by implementing the teachings disclosed herein to mount an FLS build-up region similar to the FLS build-up region 2404 shown in Figure 24).

[0057] The substrate core example 2402 in Figure 24 includes a stack of multiple different (e.g., separate) glass cores (e.g., multiple glass layers, multiple glass core layers, etc.). More specifically, in this example, the stack includes five glass cores: a first glass core 2406 (e.g., top glass core), a second glass core 2408, a third glass core 2410 (e.g., middle glass core), a fourth glass core 2412, and a fifth glass core 2414 (e.g., bottom glass core). In other examples, a different number of glass cores can be included in the stack. The different glass core examples 2406, 2408, 2410, 2412, and 2414 in Figure 24 correspond to the glass cores 132, 134, and 136 in Figure 1 (and / or the glass cores 202, 204, 206, 2406, 2408, 2410, 2412, and 2414 in Figures 2, 12, 13, 24, and / or 36). Thus, the glass cores 2406, 2408, 2410, 2412, and 2414 include different CTEs as described above to provide any preferred CTE gradient across the entire thickness of the substrate core 2402.

[0058] In the illustrated example of Figure 24, the glass cores 2406, 2408, 2410, 2412, and 2414 include the same or similar TGV216 as described above in relation to Figures 2-23. Thus, as shown in the illustrated example, the TGV216 includes conductive pads 220 at both ends of the TGV216 (adjacent to the outer surfaces on both sides of each glass core 2406, 2408, 2410, 2412, and 2414). Adjacent pairs of the glass cores 2406, 2408, 2410, 2412, and 2414 are separated by a layer of dielectric material 208 (e.g., adhesive material, adhesive resin) as described above in relation to Figure 2. In some examples, as described above, the layers of dielectric material 208 between the glass cores 2406, 2408, 2410, 2412, and 2414 function as redistribution layers having a metallization layer that provides traces or wiring extending between the glass cores (e.g., substantially parallel to the main surface of the glass cores) to define or redistribute electrical paths through the substrate core 2402. In this example, the redistribution layer defined by the metal in the dielectric material 208 includes conductive vias 2416 (e.g., copper vias) that penetrate the dielectric material 208 and electrically couple the TGVs 216 together. In some examples, the conductive vias 2416 can be implemented by additional conductive material 218 as described above in relation to Figure 2.

[0059] Example 2404 of the FLS build-up region includes alternating metal layers 2418 and thin-film dielectric layers 2420. In some examples, the thin-film dielectric layer 2420 contains the same material as the dielectric material 208 between the glass cores 2406, 2408, 2410, 2412, and 2414. In other examples, different dielectric materials are used. More specifically, in some examples, the thin-film dielectric layer 2420 can be a nanopacked ABF, a high-resolution thin-film dry-film photo-imageable dielectric (PID), or a liquid-film PID. In some examples, the thin-film dielectric layer 2420 contains polyimide. As described above, currently known techniques for fabricating build-up regions involve laminating layers of epoxy-based dielectric material with a metal interposition layer (e.g., copper foil). The thickness of the dielectric layer in such known techniques is approximately 25 μm. Unlike these technologies, the dielectric material within the thin-film dielectric layer 2420 is significantly less (e.g., thicknesses of approximately 10 μm or less, approximately 5 μm or less, approximately 2 μm or less, approximately 1 μm or less, etc.). In some examples, such thin layers are achieved by depositing the dielectric material using thin-film deposition techniques (e.g., PVD, CVD, ALD, etc.). These thin layers not only position the metal layers 2418 closer to each other but also enable the formation of traces or wiring with relatively fine line spaces (e.g., 2 μm / 2 μm line spaces, 1 μm / 1 μm line spaces, etc.) to provide electrical paths (e.g., die interconnects) within the build-up region 2404 without requiring silicon-based interconnect bridges (e.g., interconnect bridge 126 in Figure 1). That is, in some examples, the package substrate 2400 does not contain silicon-based interconnect bridges embedded within it to provide die interconnects.

[0060] As shown in the illustrated example, a solder resist layer 2422 is added on the FLS build-up region 2404. In this example, the solder resist layer 2422 defines the uppermost surface of the package substrate 2400. That is, the solder resist layer 2422 defines the inner surface 122 of the package substrate 110 in Figure 1 (for example, one of the outer surfaces on both sides of the package substrate 110). In this example, the FLS build-up region 2404 extends over the entire distance between the first glass core 2406 and the solder resist layer 2422. In some examples, a contact pad 2424 is provided along the outer surface of the solder resist layer 2422, electrically coupled to a metal layer 2418 in the FLS build-up region 2404. In this example, the contact pad 2424 corresponds to the contact pad 120 in Figure 1.

[0061] Figures 25–35 illustrate various stages in an example manufacturing process for producing the package substrate example 2400 of Figure 24. Many of the manufacturing stages shown in Figures 25–35 are similar to or identical to the manufacturing stages described above in relation to Figures 3–11 and 14–23. Therefore, similar features will be given similar reference numerals, and the descriptions provided above apply to Figures 25–35, except where otherwise evident from the context. Figure 25 represents a glass panel 2500 corresponding to one of the initial states of glass cores 2406, 2408, 2410, 2412, and 2414. For illustrative purposes, the glass panel 2500 is illustrated and described as corresponding to a third glass core 2410 (e.g., the intermediate glass core in substrate core 2402 in Figure 24).

[0062] Figure 26 shows the manufacturing stage after the TGV216 and associated conductive pad 220 have been added to the third glass core 2410 of Figure 25. In some examples, the process of adding the TGV216 and conductive pad 220 shown in Figure 26 corresponds to the process detailed above in relation to Figures 4-8 and / or Figures 15-21.

[0063] Figure 27 shows the manufacturing stage after the dielectric material 208 has been deposited on both sides of the third glass core 2410 in Figure 26. Furthermore, Figure 27 shows the manufacturing stage after conductive vias 2416 have been added to the dielectric material. In some examples, the process of adding the dielectric material 208 and conductive vias 2416 corresponds to the process detailed above in relation to Figures 9, 10 and / or 22.

[0064] Figure 28 illustrates the manufacturing process in which each of the glass cores (e.g., the three internal glass cores 2408, 2410, and 2412 of the substrate core 2402 in Figure 24), excluding the outermost (e.g., top and bottom) glass cores, is assembled or stacked together by combining or joining the associated glass core assemblies 2802, 2804, and 2806. In this example, the glass core assemblies 2802, 2804, and 2806 in Figure 28 are the result of processing the corresponding glass cores 2408, 2410, and 2412 through the manufacturing processes shown in Figures 25-27. That is, the third glass core 2410 processed up to the point shown in Figure 27 corresponds to the first glass core assembly 2802 shown in Figure 28. Also, as shown in Figure 24, the dielectric material 208 added to the second glass core assembly 2804 is thinner and does not contain conductive vias 2416. Another difference between the first glass core assembly 2802 and the second glass core assembly 2804 is the position of the TGV 216 and the associated conductive pad 220 (and any other metallization on the outer surface of the glass core).

[0065] The third glass core assembly 2806 is similar to the second glass core assembly 2804, except for a different arrangement of different glass cores 2412 (having different CTEs) and TGV 216 and associated conductive pads 220 (and any other metallization). In some examples, when the different glass core assemblies 2802, 2804, and 2806 are assembled (as shown in Figure 28), the stack is pressed (e.g., subjected to compression) and undergoes a curing process to bond the assemblies. The final result of combining or bonding the different glass core assemblies 2802, 2804, and 2806 produces the internal glass core stacked assembly 2900 shown in Figure 29.

[0066] In some examples, the second and third glass core assemblies 2804 and 2806 are combined with the first glass core assembly 2802 before conductive vias 2416 are added to the second and third glass core assemblies 2804 and 2806. That is, in some examples, the outermost layer of dielectric material 208 and the accompanying conductive vias 2416 shown in Figure 29 can be added after the three glass cores 2408, 2410, and 2412 have been joined together.

[0067] Figure 30 shows the manufacturing stages after processing another glass panel related to the first glass core 2406 up to the stage shown in Figure 26 for the third glass core 2410, except for different glass materials (having different CTEs) and different arrangements of TGV 216 and associated conductive pads 220 (and any other metallizations). In this example, the first glass core 2406 serves as a base substrate on which FLS build-up regions 2404 are fabricated layer by layer. Using glass as a base substrate allows for a relatively flat surface (e.g., relatively small total thickness variation of less than 10 μm) that can be precisely controlled to achieve relatively thin layers within the build-up regions, which can meet the stringent via-to-pad overlay requirements for fine pitch scaling.

[0068] Figure 31 shows the manufacturing stage after the first layer of the thin-film dielectric layer 2420 has been added to the first glass core 2406 of Figure 30. As described above, the thin-film dielectric layer 2420 is added using thin-film deposition to achieve a thickness of less than 10 μm (e.g., 5 μm or less, 2 μm or less, 1 μm or less, etc.). Figure 32 shows the manufacturing stage after the addition of additional conductive vias 3202 within the first layer of the thin-film dielectric layer 2420 and the first layer of the metal layer 2418 on the first layer of the thin-film dielectric layer 2420. The addition of alternating layers of thin-film dielectric and metal can be repeated as many times as necessary to complete the FLS build-up region 2404. Figure 33 shows the manufacturing stage after all layers within the FLS build-up region 2404 have been completed.

[0069] Figure 34 shows the manufacturing stage after the addition of the solder resist layer 2422 and the associated contact pad 2424. Furthermore, in this example, a portion of the dielectric material 208 is added to the bottom surface of the glass core 2406 in Figure 30 in preparation for bonding with the other glass cores 2408, 2410, 2412, and 2414.

[0070] Figure 35 shows the manufacturing steps when each of the glass cores 2406, 2408, 2410, 2412, and 2414 is assembled or stacked together (together with the FLS build-up region 2404) by combining or joining the associated build-up region assembly 3502 with the internal glass core stacking assembly 2900 and another glass core assembly 3504 in Figure 29. In this example, the build-up region assembly 3502 in Figure 35 corresponds to the final result of the process shown in Figure 34. The glass core assembly 3504 is the result of processing the fifth glass core 2414 through the manufacturing steps shown in Figures 25 and 26, and then adding a portion of dielectric material 208 to facilitate the joining of the different assemblies 2900, 3502, and 3504. The final result of combining or joining the different assemblies 2900, 3502, and 3504 is the production of the package substrate 2400 shown in Figure 24. In some examples, assemblies 2900, 3502, and 3504 may include glass cores 2406, 2408, 2410, 2412, and 2414 that are different from those shown in the illustrated examples. For example, in some examples, the first glass core 2406 may be combined with one or more glass cores located underneath prior to the fabrication of the FLS build-up region 2404. That is, in some examples, some or all of the glass cores 2406, 2408, 2410, 2412, and 2414 within the substrate core 2402 may be combined to collectively serve as the base substrate for the FLS build-up region 2404.

[0071] Figure 36 shows another example package substrate 3600 that may be used to mount the example package substrate 110 of Figure 1. The example package substrate 3600 in Figure 36 is substantially the same as the example substrate core 2400 in Figure 24, except as described below or otherwise evident from the context. Thus, features shown in Figure 36 that are the same or similar as the corresponding features in Figure 24 (and related Figures 25-35) are identified by the same reference numerals. Also, the descriptions of features described above in relation to Figure 24 (and related Figures 25-35) apply similarly to the corresponding features in Figure 36. For example, as shown in Figure 36, the example package substrate 3600 includes an example substrate core 2402 having a stack of five glass cores 2406, 2408, 2410, 2412, and 2414 as described above in relation to Figure 24 (and related Figures 25-35). Furthermore, in this example, the glass cores 2406, 2408, 2410, 2412, and 2414 include a TGV 216 extending through them, having conductive pads 220 at both ends. The TGV 216 is electrically coupled by conductive vias 2416 extending through layers of dielectric material 208 (e.g., adhesive resin) between the different glass cores 2406, 2408, 2410, 2412, and 2414.

[0072] The example in Figure 36 differs from the example in Figure 24 in that the package substrate example 3600 in Figure 36 does not include the FLS build-up region example 2404 shown in Figure 24. In fact, in the illustrated example in Figure 36, there is no build-up region on either side of the substrate core 2402. Rather, as shown in the illustrated example in Figure 36, a solder resist layer 2422 is provided adjacent to the surface facing outward of the first glass core 2406. The solder resist layer 2422 defines the first outer surface 3602 of the package substrate 3600 (corresponding, for example, to the inner surface 122 of the package substrate 110 in Figure 1). Furthermore, in this example, a second solder resist layer 3604 is provided adjacent to the fifth glass core 2414, defining the second outer surface 3606 of the package substrate 3600 (corresponding, for example, to the outer surface 105 of the package substrate 110 in Figure 1). In some examples, contacts 3608 (represented as bumps in this example) electrically coupled to the TGV 216 are provided along both solder resist layers 2422 and 3604. As shown in the figure, in this example, the stack of glass cores (e.g., substrate core 2402) extends over the entire distance between the solder resist layers 2422 and 3604 on the outer surface of the package substrate 3600. In other words, in this example, there is no organic build-up region between the outermost glass cores (e.g., the first glass core 2406 and the fifth glass core 2414) and the corresponding outer surfaces 3602 and 3606 of the package substrate 3600.

[0073] In some examples, the method for manufacturing the package substrate example 3600 in Figure 36 generally follows the process detailed above in relation to Figures 25-30, 34, and 35 (for example, the manufacturing steps related to the fabrication of the FLS build-up region 2404 are omitted). In the example of Figure 36, the stack of glass cores 2406, 2408, 2410, 2412, and 2414 with an intervening layer of dielectric material 208 functions as a redistribution layer for redistributing electrical paths in the package substrate 3600. Thus, as shown in the illustrated example, the TGV 216 in different glass cores 2406, 2408, 2410, 2412, and 2414 may not necessarily be aligned vertically, but may be offset and electrically coupled by a metallization layer extending horizontally within the layer of dielectric material 208 (for example, along both sides of the glass cores 2406, 2408, 2410, 2412, and 2414).

[0074] Figure 37 shows another example package substrate 3700 that may be used to mount the example package substrate 110 of Figure 1. The example package substrate 3700 of Figure 37 includes a substrate core 3702 that includes a stack of multiple different (e.g., separate) glass cores (e.g., multiple glass layers, multiple glass core layers, etc.). More specifically, in this example, the stack includes eight glass cores, including a first glass core 3704 (e.g., top glass core), a second glass core 3706, a third glass core 3708, a fourth glass core 3710, a fifth glass core 3712, a sixth glass core 3714, a seventh glass core 3716, and an eighth glass core 3718 (e.g., bottom glass core). In other examples, a different number of glass cores may be included in the stack. The different glass core examples 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 in Figure 37 may correspond to the glass cores 132, 134, and 136 in Figure 1 (and / or the glass cores 202, 204, 206, 2406, 2408, 2410, 2412, and 2414 in Figures 2, 12, 13, 24, and / or Figure 36). Accordingly, the glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 include different CTEs as described above to provide any preferred CTE gradient across the entire thickness of the substrate core 3702. However, unlike the examples shown in Figures 1-36, the glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 are in direct contact or abutment without an intervening layer of dielectric material or adhesive resin. In the illustrated examples, alternating glass cores among the glass cores are shown with different shading or fill patterns to help distinguish between the different layers.

[0075] The package substrate example 3700 in Figure 37 is similar to the package substrate example 3600 in Figure 36 in that the package substrate 3700 does not include any build-up regions or redistribution layers on the outside of the glass-based substrate core 3702. Furthermore, unlike that shown in Figure 36, the package substrate example 3700 in Figure 37 does not include a solder resist layer on its outer surface. Rather, the surface 3720 facing outward of the first glass core 3704 defines the outer surface of the package substrate 3700 (for example, corresponding to the inner surface 122 of the package substrate 110 in Figure 1). In this example, the surface 3720 facing outward of the first glass core 3704 includes a contact pad 3722 corresponding to the contact pad 120 in Figure 1. Similarly, the surface 3724 facing outward of the eighth glass core 3718 defines the outer surface of the package substrate 3700 (for example, corresponding to the outer surface 105 of the package substrate 110 in Figure 1). In this example, the eighth glass core 3718 includes a recess that exposes an additional contact pad 3726 corresponding to the contact 104 in Figure 1.

[0076] In the example shown in Figure 37, the contact pads 3722 and 3726 on both sides of the package substrate 3700 are electrically coupled by a series of TGV 3728 and metal traces 3730 (e.g., metal wiring) defined within a stack of glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718. The TGV 3728 and metal traces 3730 together define an interconnect 124 that extends through the package substrate 110 in Figure 1. Thus, in this example, the substrate core 3702 functions as a redistribution layer for redistributing the electrical paths between the contact pads 3722 and 3726 on both sides of the package substrate 3700.

[0077] Figures 38–48 show various stages in an example manufacturing process for producing the package substrate example 3700 of Figure 37. Many of the manufacturing stages shown in Figures 38–48 are the same as or identical to the manufacturing stages described above in relation to Figures 3–11, 14–22, and 25–35. Therefore, similar reference numerals are used for similar features, and the descriptions provided above apply to Figures 38–48, except where otherwise evident from the context. Figure 38 shows a glass panel 3800 corresponding to a fourth glass core 3710. The glass panel 3800 may be the same as or identical to any of the glass panels 300 in Figure 3. Figure 39 shows a manufacturing stage after a through-hole 3902 has been added to the glass core 3710 (e.g., through a LIDE process). As shown, the through-hole 3902 extends through the entire glass core 3710 between the first and second surfaces 3904, 3906 on both sides of the glass core 3170. Figure 40 shows the manufacturing stage after a conductive metal 4002 (e.g., copper, aluminum, nickel, tin, etc.) has been deposited into the through-hole 3902 to define TGV3728. The conductive metal 4002 can be deposited using any preferred process (e.g., depositing a seed layer before plating, bottom-up plating (without a seed layer), etc.). In some examples, a liner (e.g., liner 210) is added to (partially or completely) line the through-hole 3902 prior to the deposition of the conductive metal 4002.

[0078] In some examples, the glass core 3710 having TGV3728 (or through-holes 3902 before being filled with metal 4002) is manufactured by 3D printing. That is, in some examples, a fine layer of glass powder is coated onto a substrate located below to a thickness set for the glass core, and the glass powder is then heated to melt and form a solid piece of glass. In some examples, the glass powder is layered or dispensed with open spaces corresponding to the locations of the through-holes 3902. In addition, or alternatively, in some examples, the 3D printing process includes depositing metal powder at the locations corresponding to the TGV3728 at the same time as the glass powder is dispensed, so that when the glass and metal powder patterns are heated, a solid sheet of glass already containing the TGV3728 provided inside is formed by the bonding of the metal powder. In other examples, a glass core can be fabricated on a surface located below by a spin coating process using a liquid containing glass particles, which are then heated and bonded together to define a solid sheet of glass for the fourth glass core 3710. In some examples, a CMP process is used to smooth the surface of the glass core.

[0079] Figure 41 shows a post-processing manufacturing stage of another glass panel 4100 corresponding to the third glass core 3708. More specifically, at this stage of manufacturing, the third glass core 3708 already includes additional through-holes 4102 that define the location of additional TGV 3728. Furthermore, in this example, the third glass core 3708 includes channels 4104 (e.g., trenches) extending laterally along (e.g., parallel to) one or both of the outer surfaces 4106, 4108 of the third glass core 3708. In some examples, the fourth glass core 3710 may also include channels filled with conductive metal 4002.

[0080] As shown in Figure 37, the third and fourth glass cores 3708 and 3710 are in direct contact with each other, and the lower surface 4108 of the third glass core 3708 forms a boundary with the upper surface 3904 of the fourth glass core 3710. Thus, Figure 42 represents the manufacturing stage in which the boundary-forming surfaces are subjected to acid cleaning to remove impurities. Figure 43 represents the manufacturing stage in which the cleaned glass cores 3708 and 3710 are assembled and fitted together by pre-bonding immersion with increasing temperature. Figure 44 represents the manufacturing stage in which the assembled glass cores 3708 and 3710 are compressed with increasing temperature to complete the fusion process of the two glass cores. In some examples, the glass cores 3708 and 3710 are joined using ultrasonic bonding technology.

[0081] Figure 45 shows the manufacturing stage after an additional amount of conductive metal 4002 has been added to fill the openings (e.g., through-holes 4102 and channels 4104) in the third glass core 3708. Thus, TGV 3728 and trace 3730 are defined in the third glass core 3708. In some examples, the openings in the third glass core 3708 can be filled with conductive metal 4002 prior to joining the third glass core 3708 to the fourth glass core 3710. In some such examples, the metals in the separate glass cores 3708 and 3710 can also form a fusion during the joining process shown in Figure 44. In other examples, both glass cores 3708 and 37190 can be joined together before either glass core 3708 or 3710 contains the conductive metal 4002. In some such examples, the conductive metal 4002 can be added simultaneously to the openings of both glass cores 3708 and 3710 after they have been assembled together.

[0082] In some examples, the third glass core 3708 is manufactured and processed independently of the fourth glass core 3710. Therefore, in some examples, the different glass cores 3708 and 3710 are manufactured and processed in parallel before being joined together, as shown in Figure 44. In other examples, the third glass core 3708 is manufactured directly on a pre-manufactured fourth glass core 3710 (e.g., by 3D printing, spin coating). In some examples, the method by which the individual glass cores are manufactured and assembled (starting with a solid glass panel, or whether the glass cores are manufactured by 3D printing or spin coating, and whether such is done on a pre-manufactured glass core) may depend on the relevant material stress state requirements and the nature of the overall stack intended as a thermally affected zone. For example, relatively thin glass layers (e.g., less than 50 μm) can be more easily achieved using 3D printing. However, 3D printing can contribute unfavorably to thermally affected zones. Therefore, trade-offs may arise between different processing technologies.

[0083] Figure 46 shows the manufacturing stage after the fifth glass core 3712 has been joined to the fourth glass core 3710 on the opposite side from the third glass core 3708. In some examples, the addition of the fifth glass core 3712 follows the process for the third glass core 3708, which is detailed above in relation to Figures 41-45. This process can be repeated for each other glass core until a complete stack of all glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 is formed, as shown in Figure 47. As mentioned above, in some examples, openings within individual glass cores can be filled with metal before or after the individual glass cores are combined with other glass cores. In some examples, by adding metal after multiple (e.g., some or all) glass cores have been combined together, the multiple glass cores can later be metal-added (e.g., plated) in a single plating process. Figure 47 also shows the result of the subsequent addition of conductive pads 3722 and 3726. In some examples, the conductive pads 3722 and 3726 are added before the complete stack of glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 is assembled or bonded together.

[0084] In some examples, different sets or groups of glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 may be combined together before being assembled into a complete stack. That is, one additional glass core can be added to all glass cores that have been combined up to that point until a complete stack is formed, while in other examples, multiple different groups of glass cores can be combined together and then combined to form a complete stack. In addition, or instead, in some examples, three or more separate glass cores and / or joined glass cores of different groups can be combined and joined together at once. For example, in some examples, instead of joining two glass cores first and then joining the third to the other two, the third, fourth, and fifth glass cores 3708, 3710, and 3712 can each be manufactured separately and then compressed together at once (as in Figure 44). In some cases, glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718 are all manufactured separately and then stacked and joined together simultaneously.

[0085] Figure 48 illustrates the manufacturing steps involved in separating a stack of glass panels (corresponding to different glass cores 3704, 3706, 3708, 3710, 3712, 3714, 3716, and 3718) into individual units. Specifically, Figure 48 shows a saw line 4802 (e.g., saw street, cutting line, etc.) along which the separation saw runs to separate the different units. One of the resulting units corresponds to the package substrate example 3700 shown in Figure 37.

[0086] The above-mentioned examples of package substrates 110, 2400, 3600, 3700 and associated substrate cores 128, 200, 1200, 1300, 2402, 3702 in Figures 1-48 teach or suggest different features and illustrate different manufacturing methods. While each of the package substrates 110, 2400, 3600, 3700 and associated substrate cores 128, 200, 1200, 1300, 2402, 3702 disclosed above has certain features, it should be understood that certain features of one example are not necessarily used exclusively with that example. Instead, any of the features described above and / or shown in the drawings can be combined with any of those examples, in addition to or substituting for any of the other features of those examples. Features of one example are not mutually exclusive with features of another example. Instead, the scope of this disclosure encompasses any combination of any of the features. Furthermore, any of the manufacturing process examples used to manufacture any of the package substrate examples 110, 2400, 3600, 3700 and / or associated substrate cores 128, 200, 1200, 1300, 2402, 3702 can be appropriately adapted to manufacture any of the other package substrates 110, 2400, 3600, 3700 and / or associated substrate cores 128, 200, 1200, 1300, 2402, 3702.

[0087] Figure 49 is a flowchart illustrating an example method for manufacturing one of the package substrate examples 110, 2400, 3600, or 3700, which includes one of the substrate core examples 128, 200, 1200, 1300, 2402, or 3702 shown in Figures 1-48. In some examples, some or all of the operations outlined in the example method in Figure 49 are performed automatically by manufacturing equipment programmed to perform those operations. While the example manufacturing method is described with reference to the flowchart shown in Figure 49, numerous other methods may be used instead. For example, the execution order of blocks may be changed, and / or some of the blocks described may be combined, divided, rearranged, omitted, removed, and / or implemented in some other way. Also, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks shown in the illustrated examples.

[0088] The example method in Figure 49 begins in block 4902 by preparing a glass core having a given coefficient of thermal expansion (CTE) (e.g., any one of glass core examples 202, 204, 206, 2406, 2408, 2410, 2412, 2414, 3704, 3706, 3708, 3710, 3712, 3714, 3716, 3718). In some examples, the composition of the material used for the glass core is selected to achieve the intended CTE for a particular glass layer within the entire substrate core, which includes multiple glass cores laminated together. In block 4904, the example method includes adding an opening through the glass core (e.g., as shown in Figures 5, 16, 39, and 41). The opening may include openings for TGV (e.g., TGV238, 3728), metal slag (e.g., metal slag 1202), and / or metal trace (e.g., metal trace 3730).

[0089] In block 4906, the method example includes adding a liner (e.g., liner 210 as described in relation to Figure 6) to the sidewall of the opening. In some examples, block 4906 is omitted. In block 4908, the method example includes depositing a conductive material in the opening (e.g., as described in relation to Figures 7, 17-20, and 40). In some examples, this includes depositing a seed layer and subsequent additional plating processes. In some examples, this includes a bottom-up plating process without a seed layer (e.g., from a conductive carrier located below). In some examples, blocks 4902, 4904, and 4908 are performed simultaneously as part of a 3D printing process. In block 4910, the method example includes determining whether the glass core should be directly bonded to a different glass core (e.g., via fusion bonding, ultrasonic bonding, etc.). If so, the method proceeds to block 4924. Otherwise, the method proceeds to block 4912.

[0090] In block 4912, the method example includes determining whether to add a buffer layer (e.g., buffer layer 1302 in Figure 13). If so, the method proceeds to block 4914, where the buffer layer is added (e.g., laminated) onto the glass core (e.g., as described in relation to Figures 9, 22, 27, 34, and 35). The method then proceeds to block 4916. If the method decides not to add a buffer layer (in block 4912), the method proceeds directly to block 4916.

[0091] In block 4916, the example method includes providing a conductive pad (e.g., conductive pad 220) at the end of the conductive material within the opening of the glass core. In some examples, this is accomplished by selectively removing the excess conductive material deposited in block 4908 (e.g., by etching), as described (e.g., in relation to Figures 7 and 8). In other examples, block 4916 includes the deposition of further conductive material (e.g., plating), as described (e.g., in relation to Figure 21).

[0092] In block 4918, the example method includes depositing an adhesive resin (e.g., dielectric material 208) on one or both of the outer surfaces of a glass core (as described, for example, in relation to Figures 9, 22, 27, and 35). In block 4920, the example method includes adding holes (e.g., openings 902) to the adhesive resin to expose a conductive pad (as described, for example, in relation to Figure 9). In block 4922, the example method includes depositing additional conductive material (e.g., conductive material 218 and / or metal vias 2416) in the holes (as described, for example, in relation to Figures 10, 22, and 27). In some examples, the additional conductive material is a liquid metal or paste dispensed into the holes. In other examples, the additional conductive material is plated into the holes.

[0093] In block 4924, the method example includes determining whether another glass core should be manufactured. If so, the method returns to block 4902 and repeats the process for the different glass core. In some examples, the different glass cores may consist of different CTEs. In some examples, the next glass core is manufactured directly on top of a previously manufactured glass core (e.g., by 3D printing, spin coating, etc.). In other examples, the next glass core is manufactured independently of the previously manufactured glass core. Thus, in some examples, separate iterations through the process example may be performed in parallel rather than sequentially. When there are no further glass cores to manufacture, the method example proceeds to block 4926, which includes combining the glass cores. In some examples, when the glass cores are joined directly (as determined in block 4910), the glass cores are cleaned, pre-soaked, and compressed by heating (e.g., as described in relation to Figures 42-43) to create a fusion. In other examples, an adhesive resin (added in block 4918) is used to bond different glass cores together (as described, for example, in relation to Figures 10, 11, 23, 24, 27-29, and 35). In some examples, two or more glass cores are assembled (in block 4926) before it is decided (in block 4924) whether additional glass cores should be manufactured. In some examples, at least some of the conductive material added in block 4908 and / or block 4916 may be added after the glass cores are assembled in block 4926.

[0094] In block 4928, the example method includes determining whether build-up regions (e.g., build-up regions 130, 131, FLS build-up region 2404) should be added. If so, the method proceeds to block 4930, where a dielectric layer is added. In some examples, the dielectric layer is an organic epoxy dielectric laminated onto a glass core. In some examples, the dielectric layer is a thin film dielectric layer (e.g., dielectric layer 2420) for generating FLS build-up regions (e.g., FLS build-up region 2404, as described in relation to Figures 24 and 31-33).

[0095] In block 4932, the method example includes adding a metal layer (e.g., metal layer 2418) on top of a dielectric layer. In some examples, the metal layer is patterned to define traces or wiring. In some examples, metal vias are added so as to extend through the underlying dielectric layer in order to electrically couple the metal layer to the metal beneath the underlying dielectric layer. In block 4934, the method example includes determining whether to extend (one or more) build-up regions (e.g., whether to add another metallization layer using the intervening dielectric layer). If so, the method returns to block 4930. Otherwise, the method proceeds to block 4936. Returning to block 4928, if the method determines not to add build-up regions (e.g., as in package substrate examples 3600 and 3700 in Figures 36 and 37), the method proceeds directly to block 4936.

[0096] In block 4936, the example method includes completing the package substrate. In some examples, this includes combining different parts of the package substrate (e.g., not combined in block 4926). For example, in some examples, an FLS build-up region is manufactured on one or more glass cores manufactured independently of other glass cores in the stack of the entire substrate core. In such examples, one or more glass cores having the FLS build-up region can be combined with other glass cores that have been combined up to that point (e.g., as described in relation to Figure 35). Furthermore, in some examples, completing the package substrate includes adding a solder resist layer (e.g., solder resist layers 2422, 3604 as described in relation to Figures 24, 34, and 36). In addition, or instead, in some examples, completing the package substrate includes adding contacts (e.g., conductive pad 2424 in Figure 24, contact 3608 in Figure 36, and / or contact pads 3722, 3726 in Figure 37) to the outer surface of the package substrate. In some examples, the method is carried out at the panel level. Thus, in block 4938, the example method includes separating a complete package substrate assembly into individual units (as described, for example, with respect to Figure 48). The example method then concludes in Figure 49.

[0097] The IC package example 100 disclosed herein (including package substrate examples 110, 2400, 3600, 3700 and any one of the associated substrate cores 128, 200, 1200, 1300, 2402, 3702) can be incorporated into any suitable electronic component. Figures 50–53 show various examples of devices that include or may include the IC package 100 disclosed herein.

[0098] Figure 50 is a top view of a wafer 5000 and die 5002 that may be included in the IC package 100 of Figure 1 (for example, as any preferred die among dies 106, 108). The wafer 5000 comprises a semiconductor material and one or more dies 5002 having circuits. Each die 5002 may be a repeating unit of a semiconductor product. After the manufacturing of the semiconductor product is complete, the wafer 5000 may undergo a fragmentation process in which the dies 5002 are separated from each other to provide individual “chips”. The die 5002 includes one or more transistors (for example, some of the transistors 5140 in Figure 51 described below), support circuits for routing electrical signals to the transistors, passive components (for example, traces, resistors, capacitors, inductors, and / or other circuits), and / or any other components. In some examples, die 5002 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridging RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuits or electronics. Multiple of these devices may be combined on a single die 5002. For example, a memory array of multiple memory circuits may be formed on the same die 5002 as a programmable circuit (e.g., the processor circuit 5302 in Figure 53) and / or other logic circuits. Such memory may store information for use by the programmable circuit. The IC package example 100 disclosed herein may be manufactured using die-to-wafer assembly technology, in which some dies are mounted on a wafer 5000 containing other dies, and the wafer 5000 is then sectionalized.

[0099] Figure 51 is a side cross-sectional view of an IC device 5100 that may be included in an example IC package 100 disclosed herein (e.g., any of dies 106, 108). One or more of the IC devices 5100 may be included in one or more dies 5002 (Figure 50). The IC device 5100 may be formed on a die substrate 5102 (e.g., wafer 5000 in Figure 50) and may be included in a die (e.g., die 5002 in Figure 50). The die substrate 5102 may be a semiconductor substrate containing a semiconductor material including, for example, an n-type or p-type material system (or a combination of both). The die substrate 5102 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 5102 may be formed using alternative materials that may or may not be combined with silicon, and such alternative materials may include, but are not limited to, germanium, indium antimony, lead telluride, indium arsenide, indium phosphorus, gallium arsenide, or gallium antimony. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 5102. A few examples of materials on which the die substrate 5102 may be formed are described here, but any material that can function as the basis for the IC device 5100 may be used. The die substrate 5102 may be part of a detached die (e.g., die 5002 in Figure 50) or a wafer (e.g., wafer 5000 in Figure 50).

[0100] The IC device 5100 may include one or more device layers 5104 disposed on and / or on the die substrate 5102. The device layer 5104 may include features of one or more transistors 5140 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 5102. The device layer 5104 may include, for example, one or more source and / or drain (S / D) regions 5120, a gate 5122 for controlling the current between the S / D regions 5120, and one or more S / D contacts 5124 for routing electrical signals to and from the S / D regions 5120. The transistor 5140 may include further features not shown for clarity, such as element isolation regions and gate contacts. The transistor 5140 is not limited to the type and configuration shown in Figure 51 and may include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include, for example, FinFET transistors such as double-gate transistors or tri-gate transistors, as well as wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0101] Each transistor 5140 may include a gate 5122 comprising a gate dielectric and a gate electrode. The gate dielectric may include one or more layers in a stack. These one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material. High-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some cases, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0102] The gate electrode can be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 5140 is a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one which is a filler metal layer. Further metal layers, such as a barrier layer, may also be included. In PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals described below with reference to NMOS transistors (e.g., with regard to work function tuning). In NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any of the metals mentioned above with reference to PMOS transistors (e.g., with respect to work function tuning).

[0103] In some examples, when viewed as a cross-section of transistor 5140 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom substantially parallel to the surface of the die substrate 5102 and two sidewalls substantially perpendicular to the top surface of the die substrate 5102. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the top surface of the die substrate 5102 and not comprising sidewalls substantially perpendicular to the top surface of the die substrate 5102. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0104] In some examples, a pair of sidewall spacers may be formed on the sides of the gate stack, flanking the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. The process for forming the sidewall spacers is well known in the art and generally involves deposition and etching processes. In some examples, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on both sides of the gate stack.

[0105] The S / D region 5120 may be formed in the die substrate 5102 adjacent to the gate 5122 of the corresponding (one or more) transistors 5140. The S / D region 5120 may be formed, for example, using an ion implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 5102 to form the S / D region 5120. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the die substrate 5102. In the latter process, the die substrate 5102 may first be etched to form a recess at the location of the S / D region 5120. Then, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 5120. In some implementations, the S / D region 5120 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D region 5120 may be formed using one or more alternative semiconductor materials such as germanium or III-V material or alloy. In further examples, one or more layers of metal and / or metallic alloy may be used to form the S / D region 5120.

[0106] For example, electrical signals such as power and / or input / output (I / O) signals can be routed to and from devices in device layer 5104 (e.g., transistor 5140) through one or more interconnect layers (shown in Figure 51 as interconnect layers 5106-5110) located on device layer 5104. For example, conductive features of device layer 5104 (e.g., gate 5122 and S / D contact 5124) can be electrically coupled to interconnect structures 5128 of interconnect layers 5106-5110. One or more interconnect layers 5106-5110 can form a metallization stack (also referred to as an "ILD stack") 5119 of the IC device 5100.

[0107] The interconnect structure 5128 can be configured within the interconnect layers 5106-5110 to route electrical signals according to a wide variety of designs (in particular, its configuration is not limited to the interconnect structure 5128 in the specific configuration depicted in Figure 51). Although Figure 51 depicts a specific number of interconnect layers 5106-5110, examples of the present disclosure include IC devices with more or fewer interconnect layers than those depicted.

[0108] In some examples, the interconnect structure 5128 may include lines 5128a and / or vias 5128b filled with a conductive material, such as metal. Lines 5128a may be configured to route electrical signals in a plane substantially parallel to the surface of the die substrate 5102 on which the device layer 5104 is formed. For example, lines 5128a may route electrical signals in and / or out of the plane of the paper from the viewpoint of Figure 51. Vias 5128b may be configured to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 5102 on which the device layer 5104 is formed. In some examples, vias 5128b may electrically couple lines 5128a of different interconnect layers 5106-5110 together.

[0109] The interconnect layers 5106-5110 may include dielectric material 5126 disposed between interconnect structures 5128, as shown in Figure 51. In some examples, the dielectric material 5126 disposed between interconnect structures 5128 in different layers of the interconnect layers 5106-5110 may have different compositions, while in other examples, the composition of the dielectric material 5126 between different interconnect layers 5106-5110 may be the same.

[0110] The first interconnect layer 5106 (referred to as metal 1 or “M1”) may be formed directly on the device layer 5104. In some examples, the first interconnect layer 5106 may include lines 5128a and / or vias 5128b, as shown in the figure. Lines 5128a of the first interconnect layer 5106 may be coupled to contacts of the device layer 5104 (e.g., S / D contacts 5124).

[0111] The second interconnect layer 5108 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 5106. In some examples, the second interconnect layer 5108 may include vias 5128b for connecting lines 5128a of the second interconnect layer 5108 to lines 5128a of the first interconnect layer 5106. For clarity, lines 5128a and vias 5128b are structurally contoured by lines within each interconnect layer (e.g., within the second interconnect layer 5108), although lines 5128a and vias 5128b may, in some examples, be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0112] A third interconnect layer 5110 (referred to as metal 3 or “M3”) (and, if applicable, additional interconnect layers) may be formed successively on the second interconnect layer 5108, in accordance with the same techniques and / or configurations described in relation to the second interconnect layer 5108 or the first interconnect layer 5106. In some examples, “higher” interconnect layers (i.e., further away from the device layer 5104) in the metallization stack 5119 within the IC device 5100 can be thicker.

[0113] The IC device 5100 may include a solder resist material 5134 (e.g., polyimide or similar material) formed on interconnect layers 5106-5110 and one or more conductive contacts 5136. In Figure 51, the conductive contacts 5136 are shown as bond pads. The conductive contacts 5136 may be electrically coupled to an interconnect structure 5128 and configured to route electrical signals from (one or more) transistors 5140 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 5136 to mechanically and / or electrically couple a chip containing the IC device 5100 to another component (e.g., a circuit board). The IC device 5100 may include additional or alternative structures for routing electrical signals from interconnect layers 5106-5110; for example, the conductive contacts 5136 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0114] Figure 52 is a side cross-sectional view of an IC device assembly 5200 which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 5200 includes several components arranged on a circuit board 5202 (which may be, for example, a motherboard). The IC device assembly 5200 includes components arranged on a first surface 5240 of the circuit board 5202 and a second opposite surface 5242 of the circuit board 5202, and generally, components may be arranged on one or both of surfaces 5240 and 5242. Any of the IC packages described later with reference to the IC device assembly 5200 may take the form of the IC package example 100 shown in Figure 1.

[0115] In some examples, the circuit board 5202 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. One or more of the metal layers may be formed with a desired circuit pattern for routing electrical signals (optionally together with other metal layers) between components coupled to the circuit board 5202. In other examples, the circuit board 5202 may be a non-PCB package substrate.

[0116] The IC device assembly 5200 shown in Figure 52 may include a package-on-interposer structure 5236 coupled to a first surface 5240 of a circuit board 5202 by a coupling component 5216. The coupling component 5216 can electrically and mechanically couple the package-on-interposer structure 5236 to the circuit board 5202 and may also include solder balls (as shown in Figure 52), male and female parts of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0117] The package-on-interposer structure 5236 may include an IC package 5220 coupled to an interposer 5204 by a coupling component 5218. The coupling component 5218 can take any form suitable for the application, such as the form described above with reference to coupling component 5216. Although one IC package 5220 is shown in Figure 52, multiple IC packages may be coupled to the interposer 5204, and in fact, additional interposers may be coupled to the interposer 5204. The interposer 5204 can provide an intervening substrate used to bridge the circuit board 5202 and the IC package 5220. The IC package 5220 may be, for example, a die (die 5002 in Figure 50), an IC device (e.g., IC device 5100 in Figure 51), or any other suitable component, or may include such a component. Generally, the interposer 5204 can spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 5204 may couple an IC package 5220 (e.g., a die) to a set of BGA conductive contacts of a coupling component 5216 for coupling to a circuit board 5202. In the example shown in Figure 52, the IC package 5220 and the circuit board 5202 are mounted on opposite sides of the interposer 5204, while in other examples, the IC package 5220 and the circuit board 5202 may be mounted on the same side of the interposer 5204. In some examples, three or more components may be interconnected by the interposer 5204.

[0118] In some examples, the interposer 5204 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 5204 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer material such as polyimide. In some examples, the interposer 5204 may be formed of another rigid or flexible material, which may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, other Group IV materials, and Group III-V materials. The interposer 5204 may include, but is not limited to, through-silicon vias (TSVs) 5206, metal interconnects 5208, and vias 5210. The interposer 5204 may further include embedded devices 5214, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 5204. The package-on-interposer structure 5236 may take any form of package-on-interposer structure known in the art.

[0119] The IC device assembly 5200 may include an IC package 5224 coupled to the first surface 5240 of the circuit board 5202 by a coupling component 5222. The coupling component 5222 can take any form of the examples described above with reference to coupling component 5216, and the IC package 5224 can take any form of the examples described above with reference to IC package 5220.

[0120] The IC device assembly 5200 shown in Figure 52 includes a package-on-package structure 5234 coupled to a second surface 5242 of a circuit board 5202 by a coupling component 5228. The package-on-package structure 5234 may include a first IC package 5226 and a second IC package 5232 coupled together by a coupling component 5230 such that the first IC package 5226 is positioned between the circuit board 5202 and the second IC package 5232. The coupling components 5228 and 5230 can take any form of one of the examples of coupling components 5216 described above, and the IC packages 5226 and 5232 can take any form of one of the examples of IC packages 5220 described above. The package-on-package structure 5234 may be configured according to any package-on-package structure known in the art.

[0121] Figure 53 is a block diagram of an electrical device example 5300 which may include one or more of the IC package examples 100. For example, any preferred components of the electrical device 5300 may include one or more of the device assemblies 5200, IC devices 5100, or dies 5002 disclosed herein, which may be placed within the IC package example 100. Although several components are shown in Figure 53 to be included in the electrical device 5300, one or more of these components may be omitted or repeated as appropriate for the application. In some examples, some or all of the components included in the electrical device 5300 may be mounted on one or more motherboards. In some examples, some or all of these components are manufactured on a single system-on-a-chip (SOC) die.

[0122] Furthermore, in various embodiments, the electrical device 5300 may not include one or more of the components shown in Figure 53, but may include interface circuits for coupling to such one or more components. For example, the electrical device 5300 may not include the display 5306, but may include a display interface circuit (e.g., a connector and a drive circuit) to which the display 5306 can be coupled. In another set of examples, the electrical device 5300 may not include the audio input device 5318 (e.g., a microphone) or the audio output device 5308 (e.g., a speaker, headset, earphone, etc.), but may include an audio input or output device interface circuit (e.g., a connector and a support circuit) to which the audio input device 5318 or the audio output device 5308 can be coupled.

[0123] The electrical device 5300 may include a programmable circuit 5302 (e.g., one or more processing devices). The programmable circuit 5302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing devices. The electrical device 5300 may include a memory 5304 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some examples, the memory 5304 may include memory that shares a die with the programmable circuit 5302. This memory can be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0124] In some examples, the electrical device 5300 may include a communication chip 5312 (e.g., one or more communication chips). For example, the communication chip 5312 may be configured to manage wireless communication for the transmission of data to and from the electrical device 5300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium using modulated electromagnetic radiation. This term does not mean that the devices in question do not include any wires, although in some examples they may not include any wires.

[0125] The communication chip 5312 may implement any of the many wireless standards or protocols. These wireless standards or protocols include, but are not limited to, WiFi (IEEE 802.11 family), IEEE standards including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), the Long-Term Evolution (LTE) project and its amendments, updates and / or revisions (e.g., the Advanced LTE project), the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc. Broadband wireless access (BWA) networks compliant with IEEE 802.16 are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformity and interoperability testing of the IEEE 802.16 standard. The communication chip 5312 may operate in accordance with Global System for Mobile Communications (GSM; registered trademark), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 5312 may also operate in accordance with Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Telescopic Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 5312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as other radio protocols designated as 3G, 4G, 5G, and later. In other examples, the communication chip 5312 may operate in accordance with other radio protocols.The electrical device 5300 may include an antenna 5322 for assisting and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0126] In some examples, the communication chip 5312 may manage wired communication, such as electrical, optical, or other suitable communication protocols (e.g., Ethernet®). As described above, the communication chip 5312 may include multiple communication chips. For example, a first communication chip 5312 may be used for shorter-range wireless communication, such as Wi-Fi® and / or Bluetooth®, and a second communication chip 5312 may be used for longer-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, or others. In some examples, the first communication chip 5312 may be used for wireless communication and the second communication chip 5312 for wired communication.

[0127] The electrical equipment 5300 may include a battery / power circuit 5314. The battery / power circuit 5314 may include a circuit for connecting components of the electrical equipment 5300 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the electrical equipment 5300 (e.g., AC line power).

[0128] The electrical device 5300 may include a display 5306 (or, as described above, a corresponding interface circuit). The display 5306 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0129] The electrical device 5300 may include an audio output device 5308 (or, as described above, a corresponding interface circuit). The audio output device 5308 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0130] The electrical device 5300 may include an audio input device 5318 (or, as described above, a corresponding interface circuit). The audio input device 5318 may include any device that generates a sound signal representation, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a MIDI (musical instrument digital interface; MIDI) output).

[0131] The electrical device 5300 may include a GPS circuit 5316. The GPS circuit 5316 is capable of communicating with a satellite-based system and can receive the position of the electrical device 5300 as is technically known.

[0132] The electrical device 5300 may include any other output device 5310 (or, as described above, a corresponding interface circuit). Examples of other output devices 5310 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or further storage devices.

[0133] The electrical device 5300 may include any other input device 5320 (or, as described above, a corresponding interface circuit). Examples of other input devices 5320 may include an accelerometer, gyroscope, compass, image capture device, keyboard, cursor control device such as a mouse, stylus, touchpad, barcode reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

[0134] The electrical device 5300 may have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, netbooks, ultrabooks, personal digital assistants (PDAs), ultramobile personal computers, etc.), desktop electrical devices, servers or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, vehicle control units, digital cameras, digital video recorders, or wearable electrical devices. In some examples, the electrical device 5300 may also be any other computing device that processes data.

[0135] The terms “contain” and “have” (and all their forms and tenses) are used here as open-ended terms. Therefore, whenever a claim uses any form of “contain” or “have” (e.g., have, contain, possess, contained, had, etc.) as a preamble to or within any kind of claim statement, it should be understood that additional elements, clauses, etc., may exist without deviating from the scope of the corresponding claim or statement. When used here, the phrase “at least” is open-ended, for example, when used as a transitional clause in the claim preamble, just as the terms “have” and “contain” are open-ended. For example, the term “and / or” when used in the form A, B, and / or C refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. When used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in a context describing a process, instruction, action, activity, etc., or the execution thereof, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, when used herein in a context describing the performance or execution of a process, command, action, activity, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0136] Where used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude plurals. Where used herein, the term “a” or “an” object refers to one or more of those objects. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably here. Furthermore, even if listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. In addition, individual features may be included in different examples or claims, but these may be combined in some cases, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or advantageous.

[0137] As used herein, unless otherwise specified, the term “above” describes the relationship between the two parts to the Earth. The first part is above the second part if the second part has at least one part between the Earth and the first part. Similarly, as used herein, the first part is “below” the second part if the first part is closer to the Earth than the second part. As described above, the first part can be above or below the second part in one or more of the following conditions: there is another part between them, there is no other part between them, the first and second parts are in contact, or the first and second parts are not in direct contact with each other.

[0138] Notwithstanding the foregoing, when referring to semiconductor devices under construction or production (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies, “on” is not relative to the earth, but rather to the substrate on which the components in question are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise noted or indicated by the context, a first component in a semiconductor die (e.g., a transistor or other semiconductor device) is “on” a second component in a semiconductor die when, during manufacturing / production, the first component is further from the substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided than the second component. Similarly, unless otherwise noted or indicated by the context, a first component in an IC package (e.g., a semiconductor die) is “on” a second component in an IC package when, during manufacturing / production, the first component is further from the printed circuit board (PCB) on which the IC package is mounted or attached. It should be understood that semiconductor devices are often used in a orientation different from the orientation in which they were manufactured. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in use, the definition of “above” in the previous paragraph (i.e., that the term “above” describes the relationship between two parts relative to the earth) may be governed by the context of use.

[0139] When used in this patent, any statement that any part (e.g., a layer, film, area, region, or plate) is in any way on another part (e.g., positioned on, located on, placed on, or formed on) indicates either that the part in question is in contact with the other part, or that the part in question is above the other part and one or more intermediate parts are located between them.

[0140] When used herein, references to connections (e.g., attached, joined, connected, and joined) may include intermediate members between the elements referred to by the reference to connections and / or relative movement between those elements, unless otherwise specified. Thus, a reference to a connection does not necessarily mean that two elements are directly connected and / or are in a fixed relationship with one another. When used herein, the statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between those two parts.

[0141] Unless otherwise specified, descriptors such as “first,” “second,” and “third” are used here without any implication or indication of any meaning of priority, physical order, placement in a list, and / or ordering, but merely as labels and / or arbitrary names to distinguish elements for the sake of clarity in the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, but the same element may be referred to in the claims using different descriptors such as “second” or “third.”

[0142] When used herein, “approximately” and “about” modify the subject / value to acknowledge the potential existence of variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world imperfections, as understood by those skilled in the art. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance of + / - 10%, unless otherwise specified herein.

[0143] When used here, "virtually real-time" refers to an event occurring in a nearly instantaneous manner, acknowledging that real-world delays such as computation time and transmission may exist. Therefore, unless otherwise specified, "virtually real-time" means real-time plus 1 second.

[0144] As used herein, the phrase “communicate,” including its variations, encompasses direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but rather further includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events.

[0145] As used herein, “programmable circuit” is defined to include (i) one or more dedicated electrical circuits (e.g., application-specific circuits (ASICs)) configured to perform a specific (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a specific (one or more) function and / or (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include, for example, a programmable microprocessor such as a central processor unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to produce an FPGA configuration and / or structuring to instantiate one or more operations and / or functions corresponding to a first instruction; a graphics processor unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) capable of executing a first instruction to perform one or more operations and / or functions; one or more microcontrollers capable of executing a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof) and orchestration techniques (e.g., one or more application programming interfaces (APIs)) that allow one or more computing tasks to be assigned to one or more of the multiple types of programmable circuits that are suitable and available for performing said computing tasks.

[0146] As used herein, an integrated circuit (circuit / circuitry) is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, and diodes. For example, an integrated circuit can be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit, semiconductor substrate combining multiple circuit elements, or a system-on-a-chip (SoC).

[0147] From the above, it can be understood that examples of systems, apparatus, products, and methods are disclosed that include a package substrate containing a substrate core comprising a stack of individual glass layers or glass cores having different CTEs. These different CTEs define a CTE gradient that reduces stress within the package substrate, and in particular mitigates seware known to occur in substrates having a single solid glass core with a single CTE. As a result, the examples disclosed herein improve yield losses in the manufacture of package substrates and improve the reliability and / or useful life of IC packages compared to known techniques. Some of the examples disclosed herein also include a metal slag constructed within such a stack of glass cores, providing a heat conduction path to facilitate heat dissipation that may arise from the higher IO density made possible through the use of glass-based package substrates. Furthermore, in some examples, a fine line-space redistribution layer (e.g., build-up region) is achieved by using a glass core as a base layer. Some of the build-up region on the outside of the glass substrate is completely omitted, and the stack of glass layers functions as a redistribution layer for the package substrate.

[0148] Further examples and combinations thereof include the following:

[0149] Example 1 includes a substrate for an integrated circuit package, the substrate having a first glass layer having a first coefficient of thermal expansion (CTE) and a second glass layer having a second CTE, wherein the second CTE is different from the first CTE.

[0150] Example 2 includes the substrate of Example 1, wherein the first glass layer and the second glass layer are included in a stack of glass layers, and the stack of glass layers includes at least one further glass layer, the at least one further glass layer having a third CTE.

[0151] Example 3 includes the substrate of Example 2, wherein the stack of glass layers defines the core of the substrate.

[0152] Example 4 includes the substrate of Example 2, wherein the third CTE is higher than the second CTE, the second CTE is higher than the first CTE, and the second glass layer is located between the first glass layer and the at least one further glass layer.

[0153] Example 5 includes the substrate of Example 2, wherein the third CTE is approximately equal to the first CTE, and the second glass layer is located between the first glass layer and the at least one further glass layer.

[0154] Example 6 includes any one of the substrates from Examples 1 to 5, further comprising an adhesive resin between the first glass layer and the second glass layer.

[0155] Example 7 includes the substrate of Example 6, further comprising a first glass via (TGV) penetrating the first glass layer, a second TGV penetrating the second glass layer, and a conductive material in the adhesive resin, wherein the first TGV is electrically coupled to the second TGV via the conductive material.

[0156] Example 8 includes the substrate of Example 7, wherein the conductive material is a different material from the material of the first TGV.

[0157] Example 9 includes the substrate of Example 7, wherein the conductive material is the same material as the material of the first TGV.

[0158] Example 10 includes a substrate according to any one of Examples 7 to 9, further comprising a buffer layer between the adhesive resin and the first glass layer.

[0159] Example 11 further includes liners on both sides of the first glass layer, the liners including a substrate from any one of Examples 1 to 10 that surrounds at least a portion of the first TGV.

[0160] Example 12 includes the substrate of Example 11, wherein the liner extends to a length shorter than the total length of the TGV.

[0161] Example 13 includes a substrate of Example 11 or 12, the liner extending along both sides of the first glass layer.

[0162] Example 14 includes any one of the substrates from Examples 1 to 13, further comprising a metal slag in the first glass layer.

[0163] Example 15 includes an integrated circuit (IC) package having a semiconductor die and a stack of glass layers, wherein different glass layers have different compositions.

[0164] Example 16 includes the IC package of Example 15, wherein the different compositions are associated with different coefficients of thermal expansion (CTE), and the different CTEs of different glass layers among the glass layers define a symmetrical CTE gradient.

[0165] Example 17 includes the IC package of Example 16, wherein the lowest CTE value in the symmetric CTE gradient is closer to the center of the stack of glass layers than the highest CTE value in the symmetric CTE gradient.

[0166] Example 18 further includes a metal slag within the stack of the plurality of glass layers, the metal slag defining a heat conduction path from the inside of the stack of the plurality of glass layers to the outside of the IC package, comprising any one of Examples 15 to 17.

[0167] Example 19 includes an apparatus having a semiconductor chip and a package substrate, wherein the semiconductor chip is mounted on the package substrate, and the package substrate includes a first glass sheet and a second glass sheet, the first glass sheet having a different coefficient of thermal expansion (CTE) than the second glass sheet.

[0168] Example 20 further includes an integrated heat spreader, wherein the package substrate contains a metal slag within the glass sheet, and the metal slag is thermally bonded to the integrated heat spreader, the apparatus of Example 19.

[0169] Example 21 is a first glass layer, which includes a first glass through via extending through the first glass layer and having a first coefficient of thermal expansion (CTE), A package substrate comprising: a second glass layer, which includes a second glass through-via extending through the second glass layer, having a second CTE different from the first CTE, and the first glass through-via being electrically coupled to the second glass through-via.

[0170] Example 22 includes the package substrate of Example 21, further comprising a fine line space build-up region adjacent to the first glass layer.

[0171] Example 23 further includes the package substrate of Example 22, wherein the fine line space build-up region extends over the distance between the first glass layer and the solder resist layer, and further includes a solder resist layer defining the outer surface of the package substrate.

[0172] Example 24 includes a package substrate, either one of Example 22 or 23, wherein the fine line space build-up region comprises a plurality of thin film dielectric layers, the thin film dielectric layers of the plurality of thin film dielectric layers having a thickness of less than 10 μm.

[0173] Example 25 includes any one of Examples 21 to 24, further comprising a redistribution layer defined by a metal in a dielectric material between the first glass layer and the second glass layer.

[0174] Example 26 includes the package substrate of Example 21, wherein the first glass layer and the second glass layer are included in a stack of glass layers, and the stack of glass layers includes at least one other glass layer.

[0175] Example 27 includes the package substrate of Example 26, where the stack of glass layers extends over the distance between solder resist layers on the outer surface of the package substrate.

[0176] Example 28 includes a package substrate according to any one of Examples 21 to 27, wherein there is no organic build-up region between the first glass layer and the outer surface of the package substrate.

[0177] Example 29 includes a package substrate according to any one of Examples 21 to 28, wherein the first glass layer defines the outer surface of the package substrate.

[0178] Example 30 includes a package substrate according to any one of Examples 21 to 29, wherein the first glass layer is in direct contact with the second glass layer.

[0179] Example 31 includes the package substrate of Example 30, wherein the second glass layer includes a metal trace defined by a trench extending along the interface between the first glass layer and the second glass layer.

[0180] Example 32 includes the package substrate of Example 31, wherein the first glass through-via is electrically coupled to the second glass through-via by the metal trace.

[0181] Example 33 includes an integrated circuit (IC) package having a semiconductor die and a package substrate including a stack of glass sheets, wherein different sheets within the stack of glass sheets have different coefficients of thermal expansion (CTE) to define a CTE gradient across the stack.

[0182] Example 34 includes the IC package of Example 33, wherein the semiconductor die is a first semiconductor die, and the package substrate includes a build-up region between the stack of glass sheets and the first semiconductor die, the build-up region providing an inter-die interconnect having a line space of 2 μm / 2 μm or less between the first semiconductor die and the second semiconductor die.

[0183] Example 35 includes the IC package of Example 34, wherein the package substrate does not include a silicon-based interconnect bridge embedded in the package substrate to provide the die interconnect.

[0184] Example 36 includes an IC package according to any one of Examples 33 to 35, wherein the package substrate does not include a build-up region on at least one side of the stack of glass sheets.

[0185] Example 37 includes any one of Examples 33 to 36, in which different sheets within the stack of glass sheets are fused together.

[0186] Example 38 includes a semiconductor chip and a substrate on which the semiconductor chip is mounted, the substrate including a substrate core, the substrate core including a first glass layer and a second glass layer, the first glass layer being closer to the semiconductor chip than the second glass layer, and the first glass layer having different material properties than the second glass layer.

[0187] Example 39 includes the apparatus of Example 38, wherein the first glass layer is in contact with the second glass layer.

[0188] Example 40 includes the apparatus of Example 38 or 39, further comprising a conductive trace between the first glass layer and the second glass layer, extending parallel to the first glass layer and the second glass layer.

[0189] The following claims are incorporated by this reference into this detailed description. While specific systems, apparatus, articles, and methods are disclosed herein, the scope of this patent is not limited to them. Rather, this patent extends to all systems, apparatus, articles, and methods that fairly fall within the scope of the claims herein.

Claims

1. A first glass layer comprising a first glass through via extending through the first glass layer and having a first coefficient of thermal expansion (CTE), A second glass layer comprising a second glass through via extending through the second glass layer, having a second CTE different from the first CTE, and the first glass through via being electrically coupled to the second glass through via, A package substrate having [a certain feature].

2. The package substrate according to claim 1, further comprising a fine line space build-up region adjacent to the first glass layer.

3. The package substrate according to claim 2, further comprising a solder resist layer defining the outer surface of the package substrate, wherein the fine line space build-up region extends over the distance between the first glass layer and the solder resist layer.

4. The package substrate according to claim 2, wherein the fine line space build-up region includes a plurality of thin film dielectric layers, and the thin film dielectric layers of the plurality of thin film dielectric layers have a thickness of less than 10 μm.

5. The package substrate according to any one of claims 1 to 4, further comprising a redistribution layer defined by a metal in the dielectric material between the first glass layer and the second glass layer.

6. The package substrate according to any one of claims 1 to 4, wherein the first glass layer and the second glass layer are included in a stack of glass layers, and the stack of glass layers includes at least one other glass layer.

7. The package substrate according to claim 6, wherein the stack of glass layers extends over the distance between the solder resist layers on both outer surfaces of the package substrate.

8. The package substrate according to any one of claims 1 to 4, wherein there is no organic build-up region between the first glass layer and the outer surface of the package substrate.

9. The package substrate according to claim 1, wherein the first glass layer defines the outer surface of the package substrate.

10. The package substrate according to any one of claims 1 to 4, wherein the first glass layer is in direct contact with the second glass layer.

11. The package substrate according to claim 10, wherein the second glass layer includes a metal trace defined by a trench extending along the interface between the first glass layer and the second glass layer.

12. The package substrate according to claim 11, wherein the first glass through-via is electrically coupled to the second glass through-via by the metal trace.

13. Semiconductor die and A package substrate comprising a stack of glass sheets, wherein different sheets within the stack of glass sheets have different coefficients of thermal expansion (CTE), thereby defining a CTE gradient across the stack; An integrated circuit (IC) package having [a specific feature / feature].

14. The IC package according to claim 13, wherein the semiconductor die is a first semiconductor die, the package substrate includes a build-up region between the stack of glass sheets and the first semiconductor die, and the build-up region provides an inter-die interconnect having a line space of 2 μm / 2 μm or less between the first semiconductor die and the second semiconductor die.

15. The IC package according to claim 14, wherein the package substrate does not include a silicon-based interconnect bridge embedded in the package substrate to provide the die interconnect.

16. The IC package according to any one of claims 13 to 15, wherein the package substrate does not include a build-up region on at least one side of the stack of glass sheets.

17. The IC package according to any one of claims 13 to 15, wherein the different sheets in the stack of glass sheets are fused together.

18. Semiconductor chips and A substrate on which the aforementioned semiconductor chip is mounted, the substrate includes a substrate core, the substrate core includes a first glass layer and a second glass layer, the first glass layer is closer to the semiconductor chip than the second glass layer, and the first glass layer has different material properties than the second glass layer, and the substrate is... A device having.

19. The apparatus according to claim 18, wherein the first glass layer is in contact with the second glass layer.

20. The apparatus according to claim 18 or 19, further comprising a conductive trace between the first glass layer and the second glass layer, extending parallel to the first glass layer and the second glass layer.

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