Method and apparatus relating to a stack of glass layers including a deep trench capacitor

Abstract

The present invention provides systems, apparatus, products, and methods relating to stacks of glass layers including deep trench capacitors. [Solution] An example of a substrate for an integrated circuit package disclosed herein includes a first glass layer, a second glass layer bonded to the first glass layer, and a deep trench capacitor embedded in the first glass layer.

Description

Background Art

[0001] Integrated circuit (IC) chips and / or semiconductor dies are typically connected via a package substrate to a larger circuit board such as, for example, a motherboard and other types of printed circuit boards (PCBs). As the size of IC chips and / or dies shrinks and the interconnect density increases, alternatives to traditional substrate layers have been developed to provide stable transmission of high-frequency data signals and / or increased power delivery between different circuits. One option being pursued is the implementation of a package substrate with a glass core. Generally, glass core implementations offer several advantages including higher plated through hole (PTH) density, lower signal loss, and lower total thickness variation compared to implementations using conventional epoxy cores.

Brief Description of the Drawings

[0002] [Figure 1] An example of an integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown. [Figure 2A] A first example of a substrate core that can be used to implement the example substrate core of FIG. 1 is shown. [Figure 2B] A second example of a substrate core that can be used to implement the example substrate core of FIG. 1 is shown. [Figure 3] FIGS. 3-13 show various intermediate stages in an example manufacturing process for manufacturing the example substrate cores of FIGS. 2A and 2B. [Figure 4] FIGS. 3-13 show various intermediate stages in an example manufacturing process for manufacturing the example substrate cores of FIGS. 2A and 2B. [Figure 5] FIGS. 3-13 show various intermediate stages in an example manufacturing process for manufacturing the example substrate cores of FIGS. 2A and 2B. [Figure 6] FIGS. 3-13 show various intermediate stages in an example manufacturing process for manufacturing the example substrate cores of FIGS. 2A and 2B. [Figure 7]Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 8] Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 9] Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 10] Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 11] Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 12] Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 13] Figures 3-13 show various intermediate steps in an example manufacturing process for producing the substrate core examples shown in Figures 2A and 2B. [Figure 14] Figure 2A shows an intermediate stage in an example manufacturing process for producing the first substrate core example. [Figure 15] Figure 2B shows an intermediate stage in an example manufacturing process for producing the second substrate core example. [Figure 16] This flowchart illustrates an example of a method that may be used to manufacture one of the substrate cores shown in Figures 2A-2B. [Figure 17] This is a top view of a wafer containing a die that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 18] This is a side cross-sectional view of an IC device that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 19] This is a side cross-sectional view of an IC device assembly that may be included in an IC package constructed according to the teachings disclosed herein. [Figure 20] This is a block diagram of an example of electrical equipment that may be included in an IC package constructed according to the teachings disclosed herein.

[0003] Generally, throughout the drawings and accompanying descriptions, the same or similar parts are referred to using the same reference numerals. Drawings are not necessarily to scale. Rather, the thickness of layers or areas may be enlarged in the drawings. Drawings show layers and areas with clear lines and boundaries, but some or all of these lines and / or boundaries may be idealized. In reality, boundaries and / or lines may be unobservable, blended, and / or uneven. [Modes for carrying out the invention]

[0004] Figure 1 shows an example integrated circuit (IC) package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of lands 104 (also referred to herein as contact pads) on the bottom surface 105 of the package (e.g., the outer surface of the bottom, the mounting surface, etc.). In some examples, the IC package 100 may include, in addition to or instead of, the lands 104, balls, pins, and / or pads to enable the electrical coupling of the IC package 100 to the circuit board 102. In this example, the IC package 100 includes two semiconductor dies 106, 108 (e.g., silicon dies, etc.) (sometimes referred to as chips or chiplets) mounted on a package substrate 110 and surrounded by a package lid or mold compound 112. Thus, the package substrate 110 is an example of means for supporting the semiconductor dies. The IC package example 100 in Figure 1 includes two dies 106 and 108, but in other examples, the IC package 100 may have only one die or three or more dies. In some examples, one of the dies 106 and 108 (or separate dies) is embedded in the package substrate 110. The dies 106 and 108 can provide any preferred type of function (e.g., data processing, memory storage, etc.).

[0005] As shown in the illustrated example, each of the dies 106 and 108 is electrically and mechanically coupled to the package substrate 110 via a corresponding array of interconnects 114. In Figure 1, the interconnects are shown as bumps. However, the interconnects 114 may be any other type of electrical connection (e.g., balls, pins, pads, wire bonding, etc.) in addition to or instead of the bumps shown. The electrical connection between the dies 106 and 108 and the package substrate 110 (e.g., interconnect 114) may be referred to as a first-level interconnect. In contrast, the electrical connection between the IC package 100 and the circuit board 102 (e.g., land 104, etc.) may be referred to as a second-level interconnect. In some examples, one or both of the dies 106 and 108 may be stacked on top of one or more other dies and / or interposers. In such an example, dies 106, 108 may be coupled to a lower die and / or interposer via a first set of first-level interconnects, and the lower die and / or interposer may be connected to the package substrate 110 via another set of first-level interconnects associated with the lower die and / or interposer. Thus, as used herein, the first-level interconnect refers to an interconnect (e.g., ball, bump, pin, pad, wire bonding, etc.) between the die and the package substrate, or between the die and the lower die and / or interposer.

[0006] As shown in Figure 1, the interconnect 114 of the first level interconnect includes two different types of bumps corresponding to core bumps 116 and bridge bumps 118. When used here, the core bump 116 is a bump on the dies 106, 108 through which electrical signals pass between the dies 106, 108 and external components of the IC package 100. More specifically, as shown in the illustrated example, when the dies 106, 108 are mounted on the package substrate 110, the core bump 116 is physically connected and electrically coupled to contact pads 120 on the inner surface 122 of the package substrate 110. The contact pads 120 on the inner surface 122 of the package substrate 110 are electrically coupled to lands 104 on the bottom surface 105 of the package substrate 110 (e.g., the outer surface of the bottom) (e.g., the surface opposite to the inner surface 122) via an internal interconnect 124 within the package substrate 110. As a result, a continuous electrical signal path exists between the core bumps 116 of dies 106 and 108 and the land 104 attached to the circuit board 102, passing through the contact pad 120 and interconnect 124 provided between them.

[0007] When used here, the bridge bump 118 is a bump on dies 106, 108 through which electrical signals pass between different dies 106, 108 within the IC package 100. Thus, as shown in the illustrated example, the bridge bump 118 of the first die 106 is electrically coupled to the bridge bump 118 of the second die 108 via an interconnect bridge 126 (e.g., a silicon-based interconnect die) embedded in the package substrate 110. As shown in Figure 1, the core bump 116 is typically larger than the bridge bump 118. In some examples, the interconnect bridge 126 and its associated bridge bump 118 are omitted.

[0008] In some examples, underfill material 119 is provided between dies 106, 108 and the package substrate 110, around and / or between the first level interconnect 114 (for example, around and / or between the core bump 116 and / or bridge bump 118). In the illustrated example, only the first die 106 is accompanied by underfill material 119. However, in other examples, both dies 106 and 108 are accompanied by underfill material 119. In other examples, the underfill material 119 is omitted. In some examples, mold compound 112 is used as the underfill material surrounding the first level interconnect 114.

[0009] In some examples, the IC package 100 includes additional passive components, such as surface-mount resistors, capacitors, and / or inductors, which are located on the bottom surface 105 and / or the inner surface 122 (e.g., the top surface) of the package substrate 110.

[0010] In Figure 1, the package substrate 110 of IC package example 100 includes a substrate core 128 (e.g., main core, overall core) between two separate build-up regions 130 (e.g., build-up layer, buffer layer). As shown in the illustrated example, the substrate core 128 includes a plurality of separate glass cores (e.g., a plurality of glass layers, a plurality of glass core layers, etc.), namely, a top glass core example 132 (e.g., a first glass core, etc.), an intermediate glass core example 134 (e.g., a second glass core, etc.), and a bottom glass core example 136 (e.g., a third glass core, etc.). In the illustrated example of Figure 1, the glass cores 132, 134, and 136 (e.g., subcores, glass substrates, glass layers, glass sheets, etc.) are stacked on top of each other.

[0011] In some examples, glass cores 132, 134, and 136 contain at least one of aluminosilicate, borosilicate, aluminoborosilicate, silica, and / or fused silica. In some examples, glass cores 132, 134, and 136 contain one or more additives, including aluminum oxide (Al2O3), boron trioxide (B2O3), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon oxide (SrO), barium oxide (BaO), tin oxide (SnO2), nickel alloy (Na2O), potassium oxide (K2O), phosphorus trioxide (P2O3), zirconium dioxide (ZrO2), lithium oxide (Li2O), titanium (Ti), and / or zinc (Zn). In some examples, glass cores 132, 134, and 136 contain silicon and oxygen. In some examples, glass cores 132, 134, and 136 contain one or more of silicon, oxygen, and / or aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In some examples, glass cores 132, 134, and 136 contain at least 23 weight percent silicon and at least 26 weight percent oxygen. In some examples, glass cores 132, 134, and 136 are separate layers of glass containing silicon, oxygen, and aluminum. In some examples, glass cores 132, 134, and 136 contain at least 23 weight percent silicon, at least 26 weight percent oxygen, and at least 5 weight percent aluminum.

[0012] In some examples, the glass cores 132, 134, 136 are amorphous solid glass layers. In some examples, the glass cores 132, 134, 136 are glass layers that do not contain organic adhesives or organic materials. In some examples, the glass cores 132, 134, 136 are solid glass layers having the same rectangular shape in plan view. In other examples, some or all of the glass cores 132, 134, 136 have different shapes. In some examples, the glass cores 132, 134, 136, as a glass substrate, include at least one glass layer, do not contain epoxy, and do not contain glass fibers (for example, do not include an epoxy prepreg layer having glass cloth). In some examples, the glass cores 132, 134, 136 correspond to a single glass piece extending across the full height / full thickness of each corresponding core.

[0013] In some examples, the glass cores 132, 134, 136 have a rectangular shape having a spread substantially the same as the layer above and / or below the core in plan view. In some examples, the glass cores 132, 134, 136 have a thickness within the range of about 25 micrometers (μm) to about 400 μm (assuming the full thickness of the substrate core 128 ranges from about 50 μm to about 1.4 millimeters (mm)). In some examples, the glass cores 132, 134, 136 can have dimensions from about 10 mm on a side to about 250 mm on a side (for example, from 10 mm ×  10 mm to 250 mm × 250 mm). In some examples, the glass cores 132, 134, 136 correspond to a rectangular prism volume in which a section (for example, a via) has been removed and filled with another material (for example, metal).

[0014] Build-up region 130 is represented in FIG. 1 as a mass / block having an internal interconnect 124 that extends linearly through the build-up region 130 (and glass cores 132, 134, 136). However, FIG. 1 is simplified for clarity and for the purpose of explanation. In reality, the interconnect is not necessarily linear. More specifically, in some examples, the build-up region 130 is defined by alternating layers of dielectric material and layers of conductive material (such as a metal like copper). The conductive (metal) layers function as the basis for the internal interconnect 124 represented in a simplified, linear form as shown in FIG. 1. In some examples, the metal layers are patterned to define electrical wiring or conductive traces that are electrically coupled between different metal layers by conductive (such as metal) vias that extend through intervening dielectric layers. Further, electrical wiring or traces on either side of the substrate core 128 can be electrically coupled by through-glass vias (TGVs) (such as copper-plated vias) that extend through the glass cores 132, 134, 136.

[0015] In particular, glass is harder and thus provides greater mechanical support or strength to the package substrate, so the glass cores are more advantageous than epoxy-based cores. Thus, the substrate core 128, and more specifically, the individual glass cores 132, 134, 136, are examples of means for strengthening the package substrate. In addition to the mechanical benefits, the glass cores also provide other advantages including a higher plated-through hole (PTH) density, lower signal loss, and lower total thickness variation. However, the glass cores also present challenges due to the brittle (e.g., fragile) nature of glass and the potential for defects that can develop into cracks propagating through the glass.

[0016] A common type of glass core failure is called seware failure. Seware results in the separation of a glass core along a crack that propagates from the edge of the glass core along its length and width between the main outer surfaces of the glass core (e.g., top and bottom, front and back). In other words, seware is characterized by the glass core splitting into two separate glass sheets along a line that generally runs parallel to the main surface of the glass core.

[0017] Factors contributing to seware include defects on the edges of the glass core resulting from fragmentation, and internal stresses induced by the mismatch between the coefficient of thermal expansion (CTE) of the glass core and the CTE of the build-up region material during the thermal cycling of the package substrate 110. More specifically, package substrates, such as the package substrate 110 in Figure 1, are often manufactured on large panels that are later fragmented or cut into individual units with a saw. Thus, in the illustrated example of Figure 1, the package substrate 110, including the substrate core 128 (and associated glass cores 132, 134, 136) and the build-up region 130, includes an opposite edge 138 created by sawing. Such sawing can lead to the growth of defects on the edges of the glass core (e.g., the edges 138 of the glass cores 132, 134, 136 in Figure 1), which can propagate across the center of the glass core, causing a crack that splits the glass core in two. Such crack growth and propagation are exacerbated by stresses induced by temperature fluctuations and differences in the CTE of the build-up region compared to that of the glass core. Generally, the material in the build-up region 130 has a higher CTE than the glass. As a result, the material in the build-up region 130 expands and contracts more than the glass core in response to thermal fluctuations, thereby creating internal stresses within the glass core that can promote crack propagation.

[0018] The examples disclosed herein reduce (minimize) concerns about sewaring by mounting the substrate core 128 of the substrate with multiple separate (e.g., separate, etc.) glass cores (e.g., glass cores 132, 134, 136, etc.) stacked on top of each other, as shown in Figure 1. More specifically, in the examples disclosed herein, glass cores 132, 134, 136 are mounted with different materials (or different compositions of the same material) associated with different CTEs. In some examples, glass cores closer to the build-up region 130 are manufactured to have a CTE closer to the CTE of the build-up region 130 than glass cores further from the build-up region 130 (e.g., closer to the center of the stack of glass cores). Thus, the substrate core 128 is defined by a gradual or incremental change in CTE (between each of the glass cores 132, 134, 136) that provides interlayer transitions within the package substrate 110 to reduce stress at any given location. Therefore, in some examples, the intermediate glass core 134 has a lower CTE than the top glass core 132 and a lower CTE than the bottom glass core 136. In some examples, the CTEs of the top glass core 132 and the bottom glass core 136 are the same. Therefore, in some examples, the different CTEs of the glass cores 132, 134, and 136 are symmetrical across the entire thickness of the substrate core 128. That is, the stacking of the glass cores 132, 134, and 136 and the arrangement or order of their associated CTEs define a symmetrical sequence of CTEs from the bottom glass core (e.g., the bottom glass core 136) to the top glass core (e.g., the top glass core 132). In other examples, the different CTEs may not be symmetrical.

[0019] In addition to implementing multiple glass cores with different CTEs to reduce stress, in some examples, a buffer material 140 (e.g., adhesive material) is placed between adjacent glass cores 132, 134, and 136 to hold the glass cores together. In some such examples, the buffer material 140 has a relatively low modulus of elasticity to absorb thermal fluctuations and stresses arising from the different CTEs of the glass cores 132, 134, and 136, thereby further reducing stress inside the substrate core 128. In some examples, the buffer material is an organic dielectric material (e.g., polyimide, parylene, etc.). In some examples, the buffer material is an inorganic dielectric material (e.g., silicon oxide (SiO2)). x ), silicon nitride (SiN x )) In some examples, the buffer material includes carbon-doped oxide (CDO). In some examples, one or more layers of the buffer material 140 may be omitted, resulting in different glass cores among the glass cores 132, 134, and 136 being in direct contact. In some examples, the layers of buffer material 140 include a conductive material that facilitates the rewiring of electrical paths between the glass cores 132, 134, and 136. Thus, the material between the glass cores is also referred to here as the rewiring material that defines one or more buffer layers within the package substrate 110.

[0020] Three different glass cores (e.g., glass cores 132, 134, 136, etc.) are shown in example substrate core 128 of Figure 1, but any other suitable number of glass cores may be mounted having corresponding CTEs such that they define a particular CTE gradient across the entire thickness of the substrate core 128. Thus, in some examples, only two glass cores, each having a different CTE, are used. In other examples, more than three glass cores are used. In some such examples, each glass core is different from all the other glass cores in the core stack. In other examples, two or more of the glass cores may have the same CTE (e.g., made from the same material of the same composition), and at least one glass core may have a different CTE from the others.

[0021] In the example shown in Figure 1, the glass cores 132, 134, and 136 are shown as having the same thickness (e.g., approximately equal thickness). However, in some examples, the thicknesses of the glass cores 132, 134, and 136 may differ from each other. For example, in some examples, the intermediate glass core 134 is thicker than the top glass core 132 and thicker than the bottom glass core 136. In other examples, the intermediate glass core 134 is thinner than the top glass core 132 and thinner than the bottom glass core 136. Any preferred thickness of the glass cores can be implemented to provide sufficient rigidity to the package substrate while achieving a suitable CTE gradient for reducing stress to mitigate sewerage.

[0022] Stacking multiple glass cores 132, 134, 136 having different CTEs as disclosed herein can act to reduce stresses that could otherwise lead to seware. The substrate core examples disclosed herein also include deep trench capacitors embedded therein. The substrate core examples disclosed herein, by including deep trench capacitors, improve power supply to components coupled to the package substrate, such as dies 106, 108 in Figure 1. Some of the substrate core examples disclosed herein include deep trenches embedded in (e.g., placed within) the topmost glass core of the stacked glass cores. Other substrate core examples disclosed herein include one or more deep trench capacitors placed within other glass cores of the stacked glass cores. Other substrate core examples disclosed herein include deep trench capacitors placed within two or more of the stacked glass cores. Examples of substrate cores including embedded deep trench capacitors are described below with reference to Figures 2A-2B.

[0023] Figure 2A shows a first substrate core example 200 that may be used to mount the substrate core example 128 of Figure 1. Similar to Figure 1, the first substrate core 200 of Figure 2 includes a first glass core example 202, a second glass core example 204, and a third glass core example 206 stacked on top of each other. In this example, glass cores 202, 204, and 206 correspond to glass cores 132, 134, and 136 of Figure 1, respectively. Thus, glass cores 202, 204, and 206 have different CTEs as described above. For example, in some examples, the second glass core 204 (e.g., an intermediate glass core) has a lower CTE than either the first glass core 202 or the third glass core 206. In this example, each of the glass cores 202, 204, and 206 has approximately the same thickness. In some examples, that thickness is approximately 350 micrometers (μm). In other examples, the thickness may be greater or less than 350 μm. Also, in some examples, different glass cores 202, 204, and 206 may have different thicknesses. Furthermore, although three glass cores are shown, in some examples any other preferred number of glass cores (e.g., 2, 4, 5, 6, 7, etc.) may be used. In such examples, the stack of glass cores can define any preferred CTE gradient based on the CTE difference of each glass core in the stack. In some examples, the CTE gradient is symmetrical over the entire thickness of the first substrate core 200. In other examples, the CTE gradient may not be symmetrical.

[0024] In the example shown in Figure 2A, the glass cores 202, 204, and 206 are separated by an intervening layer of adhesive dielectric 208 (e.g., buffer material, adhesive material, adhesive layer, etc.). In some examples, the adhesive dielectric 208 includes an organic epoxy dielectric. However, any other suitable dielectric may be used in addition or in place. In some examples, the adhesive dielectric 208 bonds corresponding glass cores 202, 204, and 206 together. For example, a layer of adhesive dielectric 208 between the first glass core 202 and the second glass core 204 adhesively bonds the first glass core 202 to the second glass core 204, and so on.

[0025] In the example shown in Figure 2A, the first substrate core 200 includes a first buffer layer example 210A, a second buffer layer example 210B, a third buffer layer example 210C, a fourth buffer layer example 210D, a fifth buffer layer example 210E, and a sixth buffer layer example 210F. The buffer layers 210A, 210B, 210C, 210D, 210E, and 210F include (e.g., are composed of) a dielectric filler material (e.g., Ajinomoto Build-Up Film (ABF)) and may include one or more conductive interconnects (e.g., vias, pads, bumps) disposed inside. The conductive interconnects of the buffer layers 210A, 210B, 210C, 210D, 210E, and 210F transmit power and / or electrical signals between adjacent glass cores 202, 204, and 206. In some examples, some or all of buffer layers 210A, 210B, 210C, 210D, 210E, and 210F are redistribution layers. In some such examples, the interconnects of some or all of buffer layers 210A, 210B, 210C, 210D, 210E, and 210F may connect TGV222 and TSV223 that are not aligned vertically.

[0026] In the illustrated example of Figure 2A, the first buffer layer 210A and the sixth buffer layer 210F are located on the outermost surfaces of the outermost glass cores (e.g., the first glass core 202 and the third glass core 206). Thus, in the illustrated example of Figure 2A, the first buffer layer 210A and the sixth buffer layer 210F define the first outer surface example 211 and the second outer surface example 212 of the first substrate core 200. In some examples, some or all of the buffer layers 210A, 210B, 210C, 210D, 210E, and 210F are absent. In such examples, the corresponding glass cores 202, 204, and 206 are in direct contact with the corresponding adhesive dielectric 208. Examples of substrate cores without the second buffer layer 210B, the third buffer layer 210C, the fourth buffer layer 210D, the fifth buffer layer 210E, and the sixth buffer layer 210F will be described later in conjunction with Figure 2B. In some such examples, the first buffer layer 210A and the sixth buffer layer 210F shown in Figure 2A may be omitted and / or correspond to the first layer of the build-up region on both sides of the first substrate core 200 (e.g., the build-up region 130 in Figure 1). In such examples, the outer surfaces of the first glass core 202 and the third glass core 206 define the first outer surface 211 and the second outer surface 212 of the first substrate core 200.

[0027] In the illustrated example of Figure 2A, the first substrate core 200 includes a deep trench capacitor example 214 embedded in an opening example 216A (e.g., a cavity). The deep trench capacitor 214 includes the structure of a capacitor fabricated on a semiconductor (e.g., silicon) substrate. Thus, the deep trench capacitor 214 is a semiconductor die example embedded in the opening 216A. The deep trench capacitor 214 is used to enable efficient power supply to a fully integrated voltage regulator within a die mounted on the first substrate core 200 (e.g., the first die 106 of the IC package 100 in Figure 1). In the illustrated example of Figure 2A, the deep trench capacitor 214 has a smaller thickness than the first glass core 202 and is electrically coupled to the surface of the first glass core 202 via an interconnect example 218. In other examples, the deep trench capacitor 214 has the same thickness as the first glass core 202 and is substantially coplanar with the outer surface of the first glass core 202. In other examples, the deep trench capacitor 214 is placed on a spacer (e.g., a pedestal). The examples described herein are explained with reference to (one or more) deep trench capacitors (e.g., deep trench capacitor 214), but the examples disclosed herein are also applicable to other embedded semiconductor devices (e.g., EMIBs, dies, etc.).

[0028] In the example shown in Figure 2A, the first substrate core 200 includes a single deep trench capacitor (e.g., deep trench capacitor 214). In other examples, the first substrate core 200 may include additional deep trench capacitors (e.g., two deep trench capacitors, three deep trench capacitors, etc.) within the first glass core 202. In some such examples, separate deep trench capacitors are located within the same opening 216A of the first glass core 202. In other examples, different deep trench capacitors are located within different openings of the first glass core 202. In addition, or instead, the first substrate core 200 may include additional deep trench capacitors embedded in one or more openings of the second glass core 204 and / or the third glass core 206. An example of a substrate core including deep trench capacitors embedded in the second glass core 204 and the third glass core 206 will be described later in conjunction with Figure 2B.

[0029] In the illustrated example of Figure 2A, the glass cores 202, 204, and 206 also include a first glass through-via (TGV) example 222 electrically coupled by an additional conductive material 224 extending through the intervening adhesive dielectric layer 208. In the illustrated example of Figure 2A, the TGV 222 is adjacent to a lateral edge of the first substrate core 200. That is, in the illustrated example of Figure 2A, the central part of the first substrate core 200 does not contain a TGV. In other examples, the first substrate core 200 may include other arrangements of the TGV 222 and deep trench capacitors (e.g., deep trench capacitor 214). For example, the deep trench capacitor 214 may be located near one of the lateral edges, and the TGV 222 may be located near the center of the first substrate core 200. In such examples, as in the illustrated example in Figure 2A, the TGV222 is not aligned vertically with the region of the first substrate core 200 containing the deep trench capacitor (e.g., deep trench capacitor 214). In the illustrated example in Figure 2A, the interconnects of buffer layers 210B, 210C, 210D, and 210E connect the vertically aligned TGV222s. In other examples, the interconnects of buffer layers 210B, 210C, 210D, and 210E can rewire (e.g., split, merge, redirect, etc.) the electrical connections between the TGV222s. That is, the buffer layers 210B, 210C, 210D, and 210E allow the vertically unaligned TGV222s to be electrically coupled. In some examples, the TGV222 is plated with the same material used for the additional conductive material 224 (e.g., copper paste, plated copper pad, liquid metal (LM) paste, etc.). In some examples, at least a portion of the additional conductive material 224 may contain a material different from TGV222. In the example shown in Figure 2A, the first substrate core 200 includes a first conductive pad example 226 disposed on the outer surfaces 211, 212 of the first substrate core 200 and electrically coupled to TGV222 and the additional conductive material 224.In this example, the first conductive pad 226 defines both ends of an interconnect (e.g., the portion of interconnect 124 in Figure 1) that extends the entire thickness of the first substrate core 200. In the illustrated example in Figure 2A, the first substrate core 200 includes a second conductive pad example 228 electrically coupled to the interconnect 218 of the deep trench capacitor 214. In some examples, the second conductive pad 228 can be coupled to the corresponding interconnect in the build-up region 130 in Figure 1 to enhance power distribution to dies 106, 108. In some examples, one or more of the second conductive pads 228 and one or more of the first conductive pads 226 can be mounted by one or more identical electrical pads. That is, a single electrical pad can be coupled to at least one of the interconnects 218 of the deep trench capacitor 214 and at least one of the TGV 222.

[0030] Figure 2B shows a second substrate core example 230 that may be used to mount the substrate core example 128 of Figure 1. In the illustrated example of Figure 2B, the second substrate core 230 includes the glass cores 202, 204, 206 of Figure 2A, the adhesive dielectric 208 of Figure 2A, the buffer layers 210A, 210B, 210C, 210D, 210E, 210F of Figure 2A, the outer surfaces 211, 212 of Figure 2A, the opening 216A of Figure 2A (referred to as the first opening 216A in Figure 2B), the TGV 222 of Figure 2A, the additional conductive material 224 of Figure 2A, and the conductive pads 226, 228 of Figure 2A. The second substrate core 230 in Figure 2B is similar to the first substrate core 200 in Figure 2A, except that the second substrate core 230 includes a first deep trench capacitor example 232A embedded in the first opening 216A of the first glass core 202, a second deep trench capacitor example 232B embedded in the second opening example 216B of the second glass core 204, and a third deep trench capacitor example 232C embedded in the third opening example 216C of the third glass core 206.

[0031] In the illustrated example of Figure 2B, the second substrate core 230 includes a through-silicon via (TSV) example 223. The TSV 223 is similar to the first TGV 222, except as otherwise mentioned. In the illustrated example of Figure 2B, the second TGV is electrically coupled to the interconnect 218 of Figure 2A. The TSV 223 extends through the central openings 216A, 216B, and 216C of the glass cores 202, 204, and 206, electrically coupling the deep trench capacitors 232A, 232B, and 232C in series. In other examples, the TSV 223 can be located at different locations within the second substrate core 230 (depending on the location of, for example, the deep trench capacitors 232A, 232B, and 232C). In the illustrated example of Figure 2B, the corresponding TSVs 223 are coupled via an additional conductive material 224. In some examples, a portion of the TSV223 is electrically coupled to a first TGV222 via interconnects of buffer layers 210A, 210B, 210C, 210D, 210E, and 210F.

[0032] In the illustrated example in Figure 2B, the deep trench capacitors 232A, 232B, and 232C are similar to the deep trench capacitor 214 in Figure 2A, except that the TSV 223 extends through the deep trench capacitors 232A, 232B, and 232C. That is, the deep trench capacitors 232A, 232B, and 232C include an interconnect that enables the transmission of power through the deep trench capacitors 232A, 232B, and 232C. In other examples, the deep trench capacitors 232A, 232B, and 232C do not include the internal interconnect associated with the TSV 223. In some examples, the TSV 223 is located outside the deep trench capacitors 232A, 232B, and 232C within openings 216A, 216B, and 216C. In some such examples, the TSV 223 is referred to here as a through-dielectric via (TDV). In the illustrated example of Figure 2B, the deep trench capacitors 232A, 232B, and 232C have the same size and shape as the deep trench capacitor 214 in Figure 2A. In other examples, the deep trench capacitors 232A, 232B, and 232C may have different sizes, shapes, and / or configurations than the first deep trench capacitor 214. In the illustrated example of Figure 2B, the deep trench capacitors 232A, 232B, and 232C are located within openings 216A, 216B, and 216C, respectively (e.g., embedded). In other examples, some or all of the deep trench capacitors 232A, 232B, and 232C are absent. In the illustrated example of Figure 2B, the deep trench capacitors 232A, 232B, and 232C are electrically coupled in series. In other examples, the deep trench capacitors 232A, 232B, and 232C may be arranged in parallel and / or in any other preferred configuration. In the example shown in Figure 2B, the second substrate core 230 includes an equal number of glass core layers (e.g., a first number of layers, three layers, etc.) and deep trench capacitors (e.g., a second number of deep trench capacitors, three deep trench capacitors, etc.). In other examples, the second substrate core 230 may include more deep trench capacitors than glass core layers.In some such examples, each of the glass cores 202, 204, and 206 can contain multiple deep trench capacitors.

[0033] Figures 3–13 show various steps in an example manufacturing process for producing a glass core subassembly that can be used in conjunction with the first substrate core example 200 in Figure 2A and / or the second substrate core example 230 in Figure 2B. As used herein, the term “glass core subassembly” refers to the glass core of a substrate core, including a stack of glass cores and any associated components embedded within or placed on it (e.g., TGV, deep trench capacitors, buffer layers, etc.). Figure 14 shows an intermediate step in another example manufacturing process for producing the first substrate core 200 in Figure 2A, which may follow the various intermediate steps in Figures 3–13. Figure 15 shows an intermediate step in another example manufacturing process for producing the second substrate core 230 in Figure 2B, which may follow the various intermediate steps in Figures 3–13. It should be understood that other processes and / or intermediate steps may also be used to produce the first substrate core example 200 in Figure 2A and / or the second substrate core example 230 in Figure 2B. An example of the process for manufacturing the substrate cores 200 and 230 shown in Figures 2A and 2B via some or all of the intermediate stages shown in Figures 3-13 will be described later in conjunction with Figure 16.

[0034] Figure 3 is a schematic cross-sectional view of a first intermediate stage example 300 of the assembly / manufacturing of a glass core subassembly related to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In the first intermediate stage 300, a glass panel example 302 is prepared. The glass panel 302 may correspond to the initial state of any one of the glass cores 202, 204, or 206. For illustrative purposes, the glass panel 302 is illustrated and described as corresponding to the second glass core 204 (e.g., the intermediate glass core in the substrate cores 200 and 230 in Figures 2A and 2B). In some examples, the glass panel 302 is manufactured to a thickness corresponding to the final thickness of the glass core 204. However, in some examples, the glass panel 302 is initially slightly larger than the final thickness of the second glass core 204 to allow some amount of glass to be removed during a subsequent polishing or planarization process, which will be described further later.

[0035] Figures 4-8 illustrate the formation of glass through-vias (TGVs) within the second glass core 204. The intermediate steps shown in Figures 4-8 show the formation of lateral TGVs in the second glass core 204 (e.g., the first TGV 222 in Figures 2A and 2B) and central openings in the second glass core 204 (e.g., openings 216A, 216B, 216C in Figure 2B). When glass cores related to glass core subassemblies that do not include deep trench capacitors (e.g., glass cores 204, 206 in the first substrate core 200 in Figure 2A) are manufactured, the processing of the central part of the glass core can be omitted in the intermediate steps shown in Figures 4-8. In addition, or instead, depending on the planned location of the deep trench capacitors to be embedded in the second glass core 204, the first TGV 222 can be created at a different location within the second glass core 204 (e.g., within the center of the second glass core 204).

[0036] Figure 4 is a schematic cross-sectional view of a second intermediate stage example 400 of the assembly / manufacturing of a glass core subassembly related to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the second intermediate stage 400 can be performed after the first intermediate stage 300 in Figure 3. In the second intermediate stage 400, the second glass core 204 is exposed to a laser as part of a laser-induced deep etching (LIDE) process. The laser is focused on defined regions 402 of the glass core 204, modifying the optical and chemical properties of the glass core 204 in those regions 402.

[0037] Figure 5 is a schematic cross-sectional view of a third intermediate stage example 500 of the assembly / manufacturing of a glass core subassembly related to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the third intermediate stage 500 may be performed after the second intermediate stage 400 in Figure 4. In the third intermediate stage 500, the second glass core 204 is subjected to a chemical etching process to remove material in the modified region 402 of the glass core 204 shown in Figure 4 in order to define the opening 216A for the TGV222 shown in Figures 2A and 2B and an additional opening example 502. In the illustrated example of Figure 5, the openings 216A, 502 have a cross-sectional profile that generally corresponds to an hourglass shape, and the width (e.g., diameter) of the openings 216A, 502 narrows near the midpoint of the opening between the first surface 504 and the second surface 506 of the glass core 204. In other examples, one or more of the openings 216A, 502 may have different cross-sectional shapes. For example, in some examples, one or more of the openings 216A, 502 may be generally conical or tapered, with the width (e.g., diameter) being smallest on one of the two surfaces 504, 506 of the second glass core 204 and the width (e.g., diameter) being largest on surfaces 504, 506. In other examples, the width (e.g., diameter) of one or more of the openings 216A, 502 is substantially constant along the entire length of the opening 502 between the two surfaces 504, 506 of the second glass core 204.

[0038] Figure 6 is a schematic cross-sectional view of a fourth intermediate stage example 600 of the assembly / manufacturing of a glass core subassembly related to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the fourth intermediate stage 600 may be performed after the third intermediate stage 500 in Figure 5. In the fourth intermediate stage 600, a conductive carrier example 602 is attached to the second surface 506. In the illustrated example of Figure 6, the conductive carrier includes a conductive layer 604 (e.g., a copper layer) and a release layer 606 (e.g., an adhesive dielectric layer).

[0039] Figure 7 is a schematic cross-sectional view of a fifth intermediate stage example 700 of the assembly / manufacturing of a glass core subassembly relating to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the fifth intermediate stage 700 may be performed after the fourth intermediate stage 600 in Figure 6. In the fifth intermediate stage 700, a first deep trench capacitor 232A is provided on the conductive carrier 602 within the first opening 216A. In the illustrated example of Figure 7, the first deep trench capacitor 232A includes a first DTC pad example 702 and a second DTC pad example 704, which enable the first deep trench capacitor 232A to be electrically coupled to an external component (e.g., dies 106, 108 in Figure 1). In the example shown in Figure 7, the second deep trench capacitor 232B is positioned within the first opening 216A such that the first DTC pad 702 is substantially coplanar with the first surface 504, and the second DTC pad 704 is in contact with (e.g., abuts against) the conductive carrier 602 and substantially coplanar with the second surface 506. Although Figure 7 illustrates the placement of the second deep trench capacitor 232B within the first opening 216A, other deep trench capacitors (e.g., the deep trench capacitor 214 in Figure 2A, the first deep trench capacitor 232A, the third deep trench capacitor 232C, etc.) can be similarly placed within the glass core. For example, the deep trench capacitor 214 in Figure 2A can be placed within the first opening 216A such that the pads of the deep trench capacitor 214 abut against the conductive carrier 602 and substantially coplanar with the second surface 506.

[0040] Figure 8 is a schematic cross-sectional view of a sixth intermediate stage example 800 of the assembly / manufacturing of a glass core subassembly relating to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the sixth intermediate stage 800 may be performed after the fifth intermediate stage 700 in Figure 7. In the sixth intermediate stage 800, the first opening 216A of the second glass core 204 is filled with dielectric material 802. In the illustrated example of Figure 8, the dielectric material 802 surrounds and / or encloses the first deep trench capacitor 232A. In some examples, the dielectric material 802 is dispensed into the opening as a liquid or paste and then cured. In some examples, excess dielectric material 802 extending beyond the first surface 504 of the second glass core 204 is removed by a polishing process (e.g., chemical mechanical planarization (CMP)). In some examples, this polishing process slightly thins the second glass core 204.

[0041] Figure 9 is a schematic cross-sectional view of a seventh intermediate step example 900 of the assembly / manufacturing of a glass core subassembly related to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the seventh intermediate step 900 may be performed after the sixth intermediate step 800 in Figure 8. In the seventh intermediate step 900, a mask example 902 is applied (e.g., via photolithography) to cover the first surface 504 of the glass core except for the opening 502. Furthermore, the manufacturing step shown in Figure 9 is after an etching process (e.g., plasma etching, dry etching) to remove the portion of the delamination layer 606 exposed within the opening 502 of the glass core 204, thereby exposing the underlying conductive layer 604. The mask 902 protects the dielectric material 802 during the etching process.

[0042] Figure 10 is a schematic cross-sectional view of an eighth intermediate stage example 1000 of the assembly / manufacturing of a glass core subassembly relating to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the eighth intermediate stage 1000 may be performed after the seventh intermediate stage 900 in Figure 9. In the eighth intermediate stage 1000, a conductive material (e.g., copper) is deposited (e.g., plated) within the opening 502 to define a TGV 222 extending through the second glass core 204. In this example, the TGV 222 is plated from the exposed portion of the conductive layer 604 upwards. Therefore, in this example, no seed layer is deposited along the walls of the opening 502 prior to the plating process. However, in other examples, a seed layer may be used to facilitate the plating of the TGV 222.

[0043] Figure 11 is a schematic cross-sectional view of an example 1100 of the ninth intermediate stage of assembly / manufacturing of a glass core subassembly relating to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the ninth intermediate stage 1100 may be performed after the eighth intermediate stage 1000 in Figure 10. In the ninth intermediate stage 1100, the conductive carrier 602, including both the conductive layer 604 and the release layer 606, is removed. In some examples, the second surface 506 of the glass core undergoes a polishing process (e.g., a CMP process) to make the TGV 222 and TSV 223 coplanar with the second surface 506. In some examples, the second glass core 204 also undergoes a cleaning process to remove any residual material.

[0044] Figure 12 is a schematic cross-sectional view of a 10th intermediate stage example 1200 of the assembly / manufacturing of a glass core subassembly related to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the 10th intermediate stage 1200 can be performed after the 9th intermediate stage 1100 in Figure 11. In the 10th intermediate stage 1200, a third buffer layer example 210C and a fourth buffer layer example 210D are deposited on the first surface 504 and the second surface 506 of the second glass core 204, respectively. The buffer layers 210C and 210D include (or are composed of) a dielectric material such as ABF and a conductive material such as copper. In the illustrated example, the buffer layers 210C and 210D are patterned such that TGV222 and TSV223 extend through the buffer layers 210C and 210D. For example, buffer layers 210C and 210D can be perforated to create openings aligned with TGV222 and TSV223, and conductive material can be deposited within the created openings.

[0045] Furthermore, in the tenth intermediate step 1200, the first pad example 1206 and the second pad example 1208 are patterned on the third buffer layer 210C and the fourth buffer layer 210D. In the example shown in Figure 12, the first pad 1206 is patterned on buffer layers 210A and 210B so as to be aligned with the first TGV 222, and the second pad 1208 is patterned on buffer layers 210A and 210B so as to be aligned with the TSV 223. In some examples, the pads 1206 and 1208 are applied via lithography. In addition, or instead, the pads 1206 and 1208 may be applied via other preferred processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), electroplating, etc.) or a combination thereof.

[0046] Figure 13 is a schematic cross-sectional view of the 11th intermediate stage example 1300 of the assembly / manufacturing of the first glass core subassembly example 1302, relating to the first substrate core 200 in Figure 2A and the second substrate core 230 in Figure 2B. In some examples, the 11th intermediate stage 1300 may be performed after the 10th intermediate stage 1200 in Figure 12. In the 11th intermediate stage 1300, an adhesive dielectric 208 is applied to the first buffer layer 210A. Furthermore, in the 11th intermediate stage 1300, additional conductive material 224 (e.g., liquid metal, copper paste, etc.) is deposited between the portions of the interface defined by the conductive material in order to electrically couple the conductive material in the stack. In other examples, the intermediate stage 1300 is omitted. In some such examples, adjacent glass core subassemblies in the stack may be coupled by other means (e.g., fusion bonding, etc.). After the execution of the processes related to the intermediate stage 1300, the manufacturing of the first glass core subassembly example 1302 is completed.

[0047] Figure 14 is a schematic cross-sectional view of a 12th intermediate step example 1400 related to the assembly / manufacturing of the first substrate core 200 of Figure 2A. In some examples, the 12th intermediate step 1400 may be carried out after the manufacturing of the second glass core subassembly example 1402, the third glass core subassembly example 1404, and the fourth glass core subassembly example 1406. The glass core subassemblies 1402, 1404, and 1406 are similar to the first glass core subassembly 1302 of Figure 13, except as otherwise mentioned. In the illustrated example of Figure 14, the second glass core subassembly 1402, the third glass core subassembly 1404, and the fourth glass core subassembly 1406 include the first glass core 202, the second glass core 204, and the third glass core 206 of Figure 2A, respectively.

[0048] In some examples, the glass core subassemblies 1402, 1404, and 1406 can be manufactured via some or all of the intermediate steps 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 shown in Figures 3-13. For example, the first glass core subassembly 1302 can be manufactured via each of the intermediate steps 300, 400, 500, 600, 700, 800, 900, 1000, 1100, and 1200 shown in Figures 3-12 (for example, the deposition of the adhesive dielectric 208 and the additional conductive material 224 in intermediate step 1300 of Figure 13 is omitted). In some such examples, the deep trench capacitor 214 in Figure 2A is deposited in the first opening 216A during the execution of intermediate step 700 in Figure 7. The third glass core subassembly 1404 and the fourth glass core subassembly 1406 can be manufactured via intermediate steps 300, 400, 500, 600, 900, 1100, and 1200 in Figures 3-6, 9, 11, and 12 (for example, the deposition of deep trench capacitors such as the deep trench capacitor 214 in intermediate step 700 in Figure 7, and the subsequent processing in intermediate step 800 in Figure 8 are omitted). In other examples, the glass core subassemblies 1402, 1404, and 1406 in Figure 14 can be manufactured by any other preferred process. In the twelfth intermediate step 1400, the three glass cores 202, 204, and 206 are assembled or laminated together by combining or joining the glass core subassemblies 1402, 1404, and 1406. The result of combining or bonding the glass core subassemblies 1402, 1404, and 1406 is the generation of the first substrate core 200 shown in Figure 2A.

[0049] Figure 15 is a schematic cross-sectional view of a 13th intermediate step example 1500 related to the assembly / manufacturing of the second substrate core 230 in Figure 2B. In some examples, the 13th intermediate step 1500 may be performed after the manufacturing of the first glass core subassembly 1302, the fourth glass core subassembly example 1502, and the fifth glass core subassembly example 1504 in Figure 13. In the illustrated example of Figure 15, the fourth glass core subassembly 1502 and the fifth glass core subassembly 1504 include the second glass core 204 in Figure 2B and the third glass core 206 in Figures 2A and 2B, respectively. The fourth glass core subassembly 1502 can be manufactured via each of the intermediate steps 300, 400, 500, 600, 700, 800, 900, 1000, 1100, and 1200 in Figures 3-12 (for example, the deposition of the adhesive dielectric 208 and the additional conductive material 224 in intermediate step 1300 in Figure 13 may be omitted). The fifth glass core subassembly 1504 can be manufactured via each of the intermediate steps 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, and 1300 in Figures 3-13. In other examples, the glass core subassemblies 1302, 1502, and 1504 in Figure 15 can be manufactured by any other preferred process. In the 13th intermediate stage 1500, the three glass cores 202, 204, and 206 are assembled or stacked together by combining or joining the glass core subassemblies 1302, 1502, and 1504. The glass core subassemblies 1302, 1502, and 1504 in Figure 15 can be stacked / assembled in a similar manner to the stacking of the glass core subassemblies 1402, 1404, and 1406 in Figure 14, as described in relation to Figure 14. The result of combining or joining the glass core subassemblies 1302, 1502, and 1504 is the generation of the second substrate core 230 in Figure 2B.

[0050] Figure 16 is a flowchart illustrating an exemplary method that may be performed to manufacture either the first substrate core example 200 in Figure 2A or the second substrate core example 230 in Figure 2B, via intermediate steps 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, and 1500 of Figures 3-15. In some examples, some or all of the operations outlined in the method example in Figure 16 are performed automatically by equipment programmed to perform those operations. The method example is described with reference to the flowchart shown in Figure 16, but numerous other methods may be used instead. For example, the execution order of the blocks may be changed, and / or some of the blocks described may be combined, divided, rearranged, omitted, removed, and / or implemented in some other way. Also, in some examples, additional processing operations may be performed before, between, and / or after any of the blocks represented in the illustrated example.

[0051] The example method in Figure 16 begins in block 1602 by preparing a glass core (e.g., one of glass cores 202, 204, or 206) having a given coefficient of thermal expansion (CTE). For example, the coefficient of thermal expansion of each of the glass cores 202, 204, and 206 can be adjusted by adjusting (e.g., changing, altering, etc.) the composition of each of the glass in these layers. For example, the coefficient of thermal expansion of each of the glass cores 202, 204, and 206 can be adjusted by changing the relative ratios of Al2O3, B2O3, Li2O, Na2O, K2O, Sb2O3, and / or other additives in each of these layers, and / or by processing variations (e.g., lamination cladding, heat treatment, etc.). In some examples, the composition of the material used for the glass core is selected to achieve the intended CTE for a particular glass layer within the entire substrate core, which includes multiple glass cores laminated together. In some examples, the composition of the material used for the glass core is selected to achieve the intended CTE for a particular glass layer within the entire substrate core, which includes multiple glass cores stacked together. The manufacturing point after completion of block 1602 corresponds to the structure of the first intermediate stage 300 in Figure 3. In block 1604, the method example includes adding an opening that penetrates the glass core. For example, an opening corresponding to the first TGV 222 and / or one of the openings 216A, 216B, 216C may be formed within the glass core 204. In some examples, if the glass core subassembly does not include a DTC, an opening in the center of the second glass core 204 (e.g., one of the openings 216A, 216B, 216C) is not added. For example, these openings can be formed by laser exposure and / or etching. The manufacturing point after completion of block 1602 corresponds to the structure of the third intermediate stage 500 in Figure 5. In block 1606, the method example includes attaching a carrier to the glass core 202. For example, the second glass core 204 can be attached to the conductive carrier 602 in Figure 6 via the release layer 606. The manufacturing stage after the completion of block 1606 corresponds to the structure of the fourth intermediate stage 600 in Figure 6.

[0052] In block 1608, the method includes determining whether one or more deep trench capacitors (e.g., one of the deep trench capacitors 214, 232A, 232B, 232C, etc.) should be deposited in the second opening 216B of the second glass core 204. If a deep trench capacitor is to be deposited on the second glass core 204, the method proceeds to block 1610. If a deep trench capacitor is not to be deposited in the second opening 216B of the second glass core 204, the method proceeds to block 1614. In block 1610, a deep trench capacitor 232B on the carrier 602 is deposited in the opening 216B. For example, the second deep trench capacitor 232B (and / or one of the deep trench capacitors 214, 232A, 232B, etc., in Figures 2A and 2B) can be deposited in the second opening 216B via a mechanical deposition technique (e.g., pick and place). In other examples, the second deep trench capacitor 232B can be deposited within the openings 216A, 216B, and 216C via other techniques and / or fabricated via multiple semiconductor manufacturing techniques. The manufacturing stage after the completion of block 1610 corresponds to the structure of the fifth intermediate stage 700 in Figure 7. In block 1612, the second opening 216B of the second glass core 204 is filled with dielectric material 802. For example, the dielectric material 802 can be deposited within the second opening 216B such that the dielectric material surrounds and / or encloses the second deep trench capacitor 232B. The manufacturing stage after the completion of block 1612 corresponds to the structure of the seventh intermediate stage 900 in Figure 9.

[0053] In block 1614, conductive material is deposited in the opening to form a first TGV 222 that penetrates the second glass core 204. For example, the TGV 222 can be formed in the opening via electroplating from the conductive layer of the attached carrier (e.g., full bottom-up plating, partial bottom-up plating, etc.). In some examples, a mask (e.g., mask 902 in Figure 9) can be deposited on the second glass core 204 to shield other components of the glass core 204 during the deposition of the conductive material. The manufacturing point after completion of block 1614 corresponds to the structure of the eighth intermediate stage 1000 in Figure 10. In block 1616, the method example includes removing the conductive carrier 602 from the second glass core 204. In some examples, the second glass core 204 is polished and cleaned after the removal of the conductive carrier 602. The manufacturing point after completion of block 1616 corresponds to the structure of the ninth intermediate stage 1100 in Figure 11.

[0054] In block 1618, the method includes determining whether one or more build-up layers (e.g., buffer layers 210A, 210B, etc.) should be deposited on the second glass core 204. If build-up layers are to be deposited on the second glass core 204, the method proceeds to block 1620. If build-up layers are not to be deposited on the second glass core 204, the method proceeds to block 1622. In block 1620, the method includes depositing buffer layers on the top and / or bottom surfaces of the second glass core 204. For example, material for additional (one or more) redistribution layers (e.g., dielectric layers, interconnects, etc.) can be deposited on the second glass core 204. In some examples, buffer layers 210A, 210B may be processed (e.g., drilling, patterning via lithography, etc.) to form openings aligned with TGV222 and TSV223. In some such examples, a conductive material is placed within it to extend the TGV to the outer surface of buffer layers 210A and 210B.

[0055] In block 1622, the method includes patterning pads on TGV222 and TSV223. For example, the first pad 1206 in Figure 12 can be patterned on buffer layers 210A, 210B so as to be aligned with TGV222, and the second pad 1208 in Figure 12 can be patterned on buffer layers 210A, 210B so as to be aligned with TSV223. In some examples, pads 1206, 1208 are deposited via lithography. In addition, or instead, pads 1206, 1208 may be deposited via other preferred processes (e.g., ALD, CVD, electroplating, etc.) or a combination thereof. The manufacturing stage after the completion of block 1622 corresponds to the structure of the 10th intermediate stage 1200 in Figure 12.

[0056] In block 1624, the method includes the application of an adhesive dielectric 208. For example, the adhesive dielectric 208 can be applied on the first buffer layer 210A (e.g., via spin coating, via lamination, etc.). In some examples, additional conductive material 224 (e.g., liquid metal, copper paste, etc.) is deposited between portions of the interface defined by the conductive material to electrically couple the conductive material in the stack. The manufacturing stage after the completion of block 1626 corresponds to the structure of the 11th intermediate stage 1300 in Figure 13.

[0057] In block 1626, the method example includes determining whether another glass core assembly (e.g., glass core subassemblies 1302, 1402, 1404, 1406, 1502, 1504, etc.) should be manufactured. If so, the process returns to block 1602 and repeats the process for the different glass core subassemblies. In some examples, the different glass core subassemblies may be constructed with different CTEs, may include deep trench capacitors of different configurations (e.g., with or without them), and / or may include buffer layers of different configurations. In some examples, separate iterations throughout the process example may be performed in parallel rather than sequentially. When there are no further glass core assemblies to manufacture, the process example proceeds to block 1628, which includes stacking (e.g., combining) the glass core assemblies. In some examples, the glass core assemblies completed up to block 1626 are directly bonded together to form the corresponding substrate cores of the substrate cores 200 and 230 in Figures 2A and 2B. Completion of the process example in Figure 16 results in a finished substrate core (e.g., either substrate core 200 or 230). The finished substrate core can then undergo any suitable subsequent processing (e.g., adding a build-up layer, mounting one or more dies, and performing other packaging processes).

[0058] While the operation example has been explained with reference to the flowchart shown in Figure 16, numerous other methods for assembling / manufacturing the board cores 200 and 230 in Figures 2A and 2B may be used instead. For example, the execution order of the blocks may be changed, and / or some of the described blocks may be modified, deleted, or combined.

[0059] The IC package example 100 shown herein in Figure 1 (for example, having one of the substrate core examples 200, 230, etc.) can be incorporated into any suitable electronic component. Figures 17–20 show various examples of devices that include or may include the IC package 100 disclosed herein.

[0060] Figure 17 is a top view of a wafer 1700 and die 1702 that may be included in the IC package 100 of Figure 1 (for example, as any preferred die among dies 106, 108). The wafer 1700 comprises a semiconductor material and one or more dies 1702 having circuits. Each die 1702 may be a repeating unit of a semiconductor product. After the manufacturing of the semiconductor product is complete, the wafer 1700 may undergo a fragmentation process in which the dies 1702 are separated from each other to provide individual “chips”. The die 1702 includes one or more transistors (for example, some of the transistors 1840 in Figure 18 described below), support circuits for routing electrical signals to the transistors, passive components (for example, traces, resistors, capacitors, inductors, and / or other circuits), and / or any other components. In some examples, die 1702 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuits or electronics. Multiple of these devices may be combined on a single die (e.g., die 1702). For example, a memory array of multiple memory circuits may be formed on the same die (e.g., die 1702) as a programmable circuit (e.g., processor circuit 2002 in Figure 20) and / or other logic circuits. Such memory may store information for use by the programmable circuit. The IC package example 100 disclosed herein may be manufactured using die-to-wafer assembly technology, in which some dies are mounted on a wafer 1700 containing other dies, and then the wafer 1700 is pieced.

[0061] Figure 18 is a side cross-sectional view of an IC device 1800 that may be included in one of the IC package examples 100 disclosed herein (e.g., any of dies 106 or 108). One or more of the IC devices 1800 may be included in one or more dies 1702 (Figure 17). The IC device 1800 may be formed on a die substrate 1802 (e.g., wafer 1700 in Figure 17) and may be included in a die (e.g., die 1702 in Figure 17). The die substrate 1802 may be a semiconductor substrate containing a semiconductor material including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1802 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1802 may be formed using alternative materials that may or may not be combined with silicon, and such alternative materials may include, but are not limited to, germanium, indium antimony, lead telluride, indium arsenide, indium phosphorus, gallium arsenide, or gallium antimony. Further materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the die substrate 1802. A few examples of materials on which the die substrate 1802 may be formed are described here, but any material that can function as the basis for the IC device 1800 may be used. The die substrate 1802 may be part of a detached die (e.g., die 1702 in Figure 17) or a wafer (e.g., wafer 1700 in Figure 17).

[0062] The IC device 1800 may include one or more device layers 1804 disposed on and / or on the die substrate 1802. The device layer 1804 may include features of one or more transistors 1840 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1802. The device layer 1804 may include, for example, one or more source and / or drain (S / D) regions 1820, a gate 1822 for controlling the current between the S / D regions 1820, and one or more S / D contacts 1824 for routing electrical signals to and from the S / D regions 1820. The transistor 1840 may include further features not shown for clarity, such as element isolation regions and gate contacts. The transistor 1840 is not limited to the type and configuration shown in Figure 18 and may include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include, for example, FinFET transistors such as double-gate transistors or tri-gate transistors, as well as wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0063] Each transistor 1840 may include a gate 1822 comprising a gate dielectric and a gate electrode. The gate dielectric may include one or more layers in a stack. These one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material. High-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that can be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some cases, when high-k materials are used, an annealing process may be performed on the gate dielectric to improve its quality.

[0064] The gate electrode can be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 1840 is a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one which is a filler metal layer. Further metal layers, such as a barrier layer, may also be included. In PMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and / or any of the metals described below with reference to NMOS transistors (e.g., with regard to work function tuning). In NMOS transistors, the metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and / or aluminum carbide), and / or any of the metals mentioned above with reference to PMOS transistors (e.g., with respect to work function tuning).

[0065] In some examples, when viewed as a cross-section of transistor 1840 along the source-channel-drain direction, the gate electrode may include a U-shaped structure comprising a bottom substantially parallel to the surface of the die substrate 1802 and two sidewalls substantially perpendicular to the top surface of the die substrate 1802. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer substantially parallel to the top surface of the die substrate 1802 and not comprising sidewalls substantially perpendicular to the top surface of the die substrate 1802. In other examples, the gate electrode may include a combination of a U-shaped structure and / or a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0066] In some examples, a pair of sidewall spacers may be formed on the sides of the gate stack, flanking the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. The process for forming the sidewall spacers is well known in the art and generally involves deposition and etching processes. In some examples, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on both sides of the gate stack.

[0067] The S / D region 1820 may be formed within the die substrate 1802 adjacent to the gate 1822 of the corresponding (one or more) transistors 1840. The S / D region 1820 may be formed, for example, using an ion implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1802 to form the S / D region 1820. An annealing process may follow the ion implantation process to activate the dopants and further diffuse them into the die substrate 1802. In the latter process, the die substrate 1802 may first be etched to form a recess at the location of the S / D region 1820. Then, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 1820. In some implementations, the S / D region 1820 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be in situ doped with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D region 1820 may be formed using one or more alternative semiconductor materials such as germanium or III-V material or alloy. In further examples, one or more layers of metal and / or metallic alloy may be used to form the S / D region 1820.

[0068] For example, electrical signals such as power and / or input / output (I / O) signals may be routed to and from a device on device layer 1804 (e.g., transistor 1840) through one or more interconnect layers (shown in Figure 18 as interconnect layers 1806-1810) located on device layer 1804. For example, conductive features on device layer 1804 (e.g., gate 1822 and S / D contact 1824) may be electrically coupled to an interconnect structure 1828 of interconnect layers 1806-1810. One or more interconnect layers 1806-1810 may form a metallization stack (also referred to as an "ILD stack") 1819 of the IC device 1800.

[0069] The interconnect structure 1828 can be configured within the interconnect layers 1806-1810 to route electrical signals according to a wide variety of designs (in particular, its configuration is not limited to the interconnect structure 1828 in the specific configuration depicted in Figure 18). Although Figure 18 depicts a specific number of interconnect layers 1806-1810, examples of the present disclosure include IC devices with more or fewer interconnect layers than those depicted.

[0070] In some examples, the interconnect structure 1828 may include lines 1828A and / or vias 1828B filled with a conductive material, such as metal. Lines 1828A may be configured to route electrical signals in a plane substantially parallel to the surface of the die substrate 1802 on which the device layer 1804 is formed. For example, lines 1828A may route electrical signals in and / or out of the plane of the paper from the viewpoint of Figure 18. Vias 1828B may be configured to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1802 on which the device layer 1804 is formed. In some examples, vias 1828B may electrically couple lines 1828A of different interconnect layers 1806-1810 together.

[0071] The interconnect layers 1806-1810 may include dielectric material 1826 disposed between interconnect structures 1828, as shown in Figure 18. In some examples, the dielectric material 1826 disposed between interconnect structures 1828 in different layers of the interconnect layers 1806-1810 may have different compositions, while in other examples, the composition of the dielectric material 1826 between different interconnect layers 1806-1810 may be the same.

[0072] The first interconnect layer 1806 (referred to as metal 1 or “M1”) may be formed directly on the device layer 1804. In some examples, the first interconnect layer 1806 may include lines 1828A and / or vias 1828B, as shown in the figure. Lines 1828A of the first interconnect layer 1806 may be coupled to contacts of the device layer 1804 (e.g., S / D contacts 1824).

[0073] The second interconnect layer 1808 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1806. In some examples, the second interconnect layer 1808 may include vias 1828B for connecting line 1828A of the second interconnect layer 1808 to line 1828A of the first interconnect layer 1806. For clarity, line 1828A and via 1828B are structurally contoured by lines within each interconnect layer (e.g., within the second interconnect layer 1808), although line 1828A and via 1828B may, in some examples, be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0074] A third interconnect layer 1810 (referred to as metal 3 or “M3”) (and, if applicable, additional interconnect layers) may be formed successively on the second interconnect layer 1808, in accordance with the same techniques and / or configurations described in relation to the second interconnect layer 1808 or the first interconnect layer 1806. In some examples, “higher” interconnect layers (i.e., further away from device layer 1804) in the metallization stack 1819 within the IC device 1800 can be thicker.

[0075] The IC device 1800 may include a solder resist material 1834 (e.g., polyimide or similar material) formed on interconnect layers 1806-1810 and one or more conductive contacts 1836. In Figure 18, the conductive contacts 1836 are shown as bond pads. The conductive contacts 1836 may be electrically coupled to the interconnect structure 1828 and configured to route electrical signals from (one or more) transistors 1840 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 1836 to mechanically and / or electrically couple a chip containing the IC device 1800 to another component (e.g., a circuit board). The IC device 1800 may include additional or alternative structures for routing electrical signals from the interconnect layers 1806-1810; for example, the conductive contacts 1836 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0076] Figure 19 is a side cross-sectional view of an IC device assembly 1900 which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 1900 includes a number of components arranged on a circuit board 1902 (which may be, for example, a motherboard). The IC device assembly 1900 includes components arranged on a first surface 1940 of the circuit board 1902 and a second opposite surface 1942 of the circuit board 1902, and generally, components may be arranged on one or both of surfaces 1940 and 1942. Any of the IC packages described later with reference to the IC device assembly 1900 may take the form of the IC package example 100 shown in Figure 1.

[0077] In some examples, the circuit board 1902 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. One or more of the metal layers may be formed with a desired circuit pattern for routing electrical signals (optionally together with other metal layers) between components coupled to the circuit board 1902. In other examples, the circuit board 1902 may be a non-PCB package substrate.

[0078] The IC device assembly 1900 shown in Figure 19 may include a package-on-interposer structure 1936 coupled to a first surface 1940 of a circuit board 1902 by a coupling component 1916. The coupling component 1916 can electrically and mechanically couple the package-on-interposer structure 1936 to the circuit board 1902 and may also include solder balls (as shown in Figure 19), male and female parts of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0079] The package-on-interposer structure 1936 may include an IC package 1920 coupled to an interposer 1904 by a coupling component 1918. The coupling component 1918 can take any form suitable for the application, such as the form described above with reference to coupling component 1916. Although one IC package 1920 is shown in Figure 19, multiple IC packages may be coupled to the interposer 1904, and in fact, additional interposers may be coupled to the interposer 1904. The interposer 1904 can provide an intervening substrate used to bridge the circuit board 1902 and the IC package 1920. The IC package 1920 may be, for example, a die (die 1702 in Figure 17), an IC device (e.g., IC device 1800 in Figure 18), or any other suitable component, or may include such a component. Generally, the interposer 1904 can spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 1904 may couple an IC package 1920 (e.g., a die) to a set of BGA conductive contacts of a coupling component 1916 for coupling to a circuit board 1902. In the example shown in Figure 19, the IC package 1920 and the circuit board 1902 are mounted on opposite sides of the interposer 1904, while in other examples, the IC package 1920 and the circuit board 1902 may be mounted on the same side of the interposer 1904. In some examples, three or more components may be interconnected by the interposer 1904.

[0080] In some examples, the interposer 1904 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some examples, the interposer 1904 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer material such as polyimide. In some examples, the interposer 1904 may be formed of another rigid or flexible material, which may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, other Group IV materials, and Group III-V materials. The interposer 1904 may include, but is not limited to, through-silicon vias (TSVs) 1906, metal interconnects 1908 and vias 1910. The interposer 1904 may further include embedded devices 1914, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the interposer 1904. The package-on-interposer structure 1936 may take any form of package-on-interposer structure known in the art.

[0081] The IC device assembly 1900 may include an IC package 1924 coupled to the first surface 1940 of the circuit board 1902 by a coupling component 1922. The coupling component 1922 can take any form of the examples described above with reference to the coupling component 1916, and the IC package 1924 can take any form of the examples described above with reference to the IC package 1920.

[0082] The IC device assembly 1900 shown in Figure 19 includes a package-on-package structure 1934 coupled to the second surface 1942 of a circuit board 1902 by a coupling component 1928. The package-on-package structure 1934 may include a first IC package 1926 and a second IC package 1932 coupled together by a coupling component 1930 such that the first IC package 1926 is positioned between the circuit board 1902 and the second IC package 1932. The coupling components 1928 and 1930 can take any form of the examples of coupling components 1916 described above, and the IC packages 1926 and 1932 can take any form of the examples of IC packages 1920 described above. The package-on-package structure 1934 may be configured according to any package-on-package structure known in the art.

[0083] Figure 20 is a block diagram of an example electrical device 2000 which may include one or more of the example IC packages 100. For example, any preferred components of the electrical device 2000 may include one or more of the device assemblies 1900, IC devices 1800, or dies 1702 disclosed herein, which may be placed within the example IC package 100. Although several components are shown to be included in the electrical device 2000, one or more of these components may be omitted or repeated as appropriate for the application. In some examples, some or all of the components included in the electrical device 2000 may be mounted on one or more motherboards. In some examples, some or all of these components are manufactured on a single system-on-a-chip (SoC) die.

[0084] Furthermore, in various embodiments, the electrical device 2000 may not include one or more of the components shown in Figure 20, but may include interface circuits for coupling to such one or more components. For example, the electrical device 2000 may not include the display 2006, but may include a display interface circuit (e.g., a connector and a drive circuit) to which the display 2006 can be coupled. In another set of examples, the electrical device 2000 may not include an audio input device 2018 (e.g., a microphone) or an audio output device 2008 (e.g., a speaker, headset, earphone, etc.), but may include an audio input or output device interface circuit (e.g., a connector and a support circuit) to which the audio input device 2018 or audio output device 2008 can be coupled.

[0085] The electrical equipment 2000 may include a programmable circuit 2002 (e.g., one or more processing devices). The programmable circuit 2002 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or other suitable processing devices. The electrical equipment 2000 may also include a memory 2004 which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some examples, the memory 2004 may include memory that shares a die with the programmable circuit 2002. This memory can be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0086] In some examples, electrical equipment 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, the communication chip 2012 may be configured to manage wireless communication for the transmission of data to and from electrical equipment 2000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data over a non-solid medium using modulated electromagnetic radiation. This term does not mean that the device in question does not include any wires, although in some examples it may not include any wires.

[0087] The Communication Chip 2012 may implement any of the many wireless standards or protocols. These wireless standards or protocols include, but are not limited to, WiFi (IEEE 802.11 family), IEEE standards including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), the Long-Term Evolution (LTE) project and its amendments, updates and / or revisions (e.g., the Advanced LTE project), the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc. Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformity and interoperability testing of the IEEE 802.16 standard. The communication chip 2012 may operate in accordance with Global System for Mobile Communications (GSM; registered trademark), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2012 may also operate in accordance with Enhanced Data Rate for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Telescopic Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as other radio protocols designated as 3G, 4G, 5G, and later. In other examples, the communication chip 2012 may operate in accordance with other radio protocols.The electrical device 2000 may include an antenna 2022 for supporting and / or receiving other wireless communications (e.g., AM or FM radio transmissions).

[0088] In some examples, the communication chip 2012 may manage wired communication, such as electrical, optical, or other suitable communication protocols (e.g., Ethernet®). As described above, the communication chip 2012 may include multiple communication chips. For example, the first communication chip 2012 may be used for shorter-range wireless communication, such as Wi-Fi® and / or Bluetooth®, and the second communication chip 2012 may be used for longer-range wireless communication, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, or others. In some examples, the first communication chip 2012 may be used for wireless communication and the second communication chip 2012 for wired communication.

[0089] The electrical equipment 2000 may include a battery / power circuit 2014. The battery / power circuit 2014 may include a circuit for connecting components of the electrical equipment 2000 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the electrical equipment 2000 (e.g., AC line power).

[0090] The electrical device 2000 may include a display 2006 (or, as described above, a corresponding interface circuit). The display 2006 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0091] The electrical equipment 2000 may include an audio output device 2008 (or, as described above, a corresponding interface circuit). The audio output device 2008 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0092] The electrical equipment 2000 may include an audio input device 2018 (or, as described above, a corresponding interface circuit). The audio input device 2018 may include any device that generates a sound signal representation, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a MIDI (musical instrument digital interface; MIDI) output).

[0093] The electrical device 2000 may include a GPS circuit 2016. The GPS circuit 2016 is capable of communicating with a satellite-based system and can receive the position of the electrical device 2000 as is technically known.

[0094] The electrical equipment 2000 may include any other output devices 2010 (or, as described above, corresponding interface circuits). Examples of other output devices 2010 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or further storage devices.

[0095] The electrical device 2000 may include any other input device 2020 (or, as described above, a corresponding interface circuit). Examples of other input devices 2020 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0096] The electrical device 2000 may have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, netbooks, ultrabooks, personal digital assistants (PDAs), ultramobile personal computers, etc.), desktop electrical devices, servers or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, vehicle control units, digital cameras, digital video recorders, or wearable electrical devices. In some examples, the electrical device 2000 may also be any other computing device that processes data.

[0097] The terms “contain” and “have” (and all their forms and tenses) are used here as open-ended terms. Therefore, whenever a claim uses any form of “contain” or “have” (e.g., have, contain, possess, contained, had, etc.) as a preamble to or within any kind of claim statement, it should be understood that additional elements, clauses, etc., may exist without deviating from the scope of the corresponding claim or statement. When used here, the phrase “at least” is open-ended, for example, when used as a transitional clause in the claim preamble, just as the terms “have” and “contain” are open-ended. For example, the term “and / or” when used in the form A, B, and / or C refers to any combination or subset of A, B, and C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A, B, and C. When used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, when used herein in a context describing a structure, component, item, object, and / or thing, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. When used herein in a context describing a process, instruction, action, activity, etc., or the execution thereof, the phrase “at least one of A and B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.Similarly, when used herein in a context describing the performance or execution of a process, command, action, activity, etc., the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0098] Where used herein, singular references (e.g., “a,” “an,” “first,” “second,” etc.) do not exclude plurals. Where used herein, the term “a” or “an” object refers to one or more of those objects. The terms “a” (or “an”), “one or more,” and “at least one” are used interchangeably here. Furthermore, even if listed individually, multiple means, elements, or actions may be implemented, for example, by the same entity or object. In addition, individual features may be included in different examples or claims, but these may be combined in some cases, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or advantageous.

[0099] As used herein, unless otherwise specified, the term “above” describes the relationship between the two parts to the Earth. The first part is above the second part if the second part has at least one part between the Earth and the first part. Similarly, as used herein, the first part is “below” the second part if the first part is closer to the Earth than the second part. As described above, the first part can be above or below the second part in one or more of the following conditions: there is another part between them, there is no other part between them, the first and second parts are in contact, or the first and second parts are not in direct contact with each other.

[0100] Notwithstanding the foregoing, when referring to semiconductor devices under construction or production (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies, “on” is not relative to the earth, but rather to the substrate on which the components in question are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, unless otherwise noted or indicated by the context, a first component in a semiconductor die (e.g., a transistor or other semiconductor device) is “on” a second component in a semiconductor die when, during manufacturing / production, the first component is further from the substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided than the second component. Similarly, unless otherwise noted or indicated by the context, a first component in an IC package (e.g., a semiconductor die) is “on” a second component in an IC package when, during manufacturing / production, the first component is further from the printed circuit board (PCB) on which the IC package is mounted or attached. It should be understood that semiconductor devices are often used in a orientation different from the orientation in which they were manufactured. Therefore, when referring to semiconductor devices (e.g., transistors), semiconductor dies containing semiconductor devices, and / or integrated circuit (IC) packages containing semiconductor dies in use, the definition of “above” in the previous paragraph (i.e., that the term “above” describes the relationship between two parts relative to the earth) may be governed by the context of use.

[0101] When used in this patent, any statement that any part (e.g., a layer, film, area, region, or plate) is in any way on another part (e.g., positioned on, located on, placed on, or formed on) indicates either that the part in question is in contact with the other part, or that the part in question is above the other part and one or more intermediate parts are located between them.

[0102] When used herein, references to connections (e.g., attached, joined, connected, and joined) may include intermediate members between the elements referred to by the reference to connections and / or relative movement between those elements, unless otherwise specified. Thus, a reference to a connection does not necessarily mean that two elements are directly connected and / or are in a fixed relationship with one another. When used herein, the statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between those two parts.

[0103] Unless otherwise specified, descriptors such as “first,” “second,” and “third” are used here without any implication or indication of any meaning of priority, physical order, placement in a list, and / or ordering, but merely as labels and / or arbitrary names to distinguish elements for the sake of clarity in the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, but the same element may be referred to in the claims using different descriptors such as “second” or “third.”

[0104] When used herein, “approximately” and “about” modify the subject / value to acknowledge the potential existence of variations that may occur in real-world applications. For example, “approximately” and “about” may modify dimensions that may not be precise due to manufacturing tolerances and / or other real-world imperfections, as understood by those skilled in the art. For example, “approximately” and “about” may indicate that such dimensions may be within a tolerance of + / - 10%, unless otherwise specified herein.

[0105] When used here, "virtually real-time" refers to an event occurring in a nearly instantaneous manner, acknowledging that real-world delays such as computation time and transmission may exist. Therefore, unless otherwise specified, "virtually real-time" means real-time plus 1 second.

[0106] As used herein, the phrase “communicate,” including its variations, encompasses direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but rather further includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-off events.

[0107] As used herein, “programmable circuit” is defined to include (i) one or more dedicated electrical circuits (e.g., application-specific circuits (ASICs)) configured to perform a specific (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits that are programmable with instructions to perform a specific (one or more) function and / or (one or more) operation and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuits include, for example, a programmable microprocessor such as a central processor unit (CPU) capable of executing a first instruction to perform one or more operations and / or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to produce an FPGA configuration and / or structuring to instantiate one or more operations and / or functions corresponding to a first instruction; a graphics processor unit (GPU) capable of executing a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP), XPU, network processing unit (NPU) capable of executing a first instruction to perform one or more operations and / or functions; one or more microcontrollers capable of executing a first instruction to perform one or more operations and / or functions; and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system that includes multiple types of programmable circuits (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, and / or any combination thereof) and orchestration techniques (e.g., one or more application programming interfaces (APIs)) that allow one or more computing tasks to be assigned to one or more of the multiple types of programmable circuits that are suitable and available for performing said computing tasks.

[0108] As used herein, an integrated circuit (circuit / circuitry) is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, and diodes. For example, an integrated circuit can be implemented as one or more of the following: an ASIC, FPGA, chip, microchip, programmable circuit, semiconductor substrate combining multiple circuit elements, or a system-on-a-chip (SoC).

[0109] From the above, it can be understood that examples of systems, apparatus, articles, and methods are disclosed that enable the formation of deep trench capacitors in a substrate core comprising a stack of multiple separate glass cores having different CTEs. The deep trench capacitors of the substrate core examples disclosed herein provide enhanced power supply, energy storage, signal coupling, and filtering for such substrate cores. The different CTEs define a CTE gradient that reduces stress within the package substrate, and in particular mitigates seware, which is known to occur in substrates having a single solid glass core with a single CTE. As a result, the examples disclosed herein improve yield losses in the manufacture of package substrates and also improve the reliability and / or useful life of IC packages compared to known techniques.

[0110] Systems, apparatus, manufactures, and methods relating to stacks of glass layers including deep trench capacitors are disclosed. Further examples and combinations thereof include:

[0111] Example 1 includes a substrate comprising a first glass layer, a second glass layer bonded to the first glass layer, and a capacitor embedded in the first glass layer.

[0112] Example 2 includes the substrate of Example 1, wherein the first glass core has a first coefficient of thermal expansion, and the second glass core has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

[0113] Example 3 includes the substrate of Example 1, further comprising an adhesive layer between the first glass layer and the second glass layer.

[0114] Example 4 includes the substrate of Example 1, further comprising a buffer layer between the first glass layer and the second glass layer.

[0115] Example 5 includes the substrate of Example 1, wherein the capacitor is a deep trench capacitor.

[0116] Example 6 includes the substrate of Example 5, wherein the deep trench capacitor is a first deep trench capacitor, and the substrate further includes a second deep trench capacitor embedded in the second glass layer, and the first deep trench capacitor is electrically coupled to the second deep trench capacitor.

[0117] Example 7 is a third glass layer, with the second glass layer between the first glass layer and the third glass layer, a first layer between the second glass layer and the first glass layer, and a second layer between the third glass layer and the second glass layer. Includes the substrate of Example 1, which further includes the following.

[0118] Example 8 includes the substrate of Example 7, wherein the first layer is a buffer layer and the second layer is an adhesive layer.

[0119] Example 9 includes the substrate of Example 8, further comprising a second deep trench capacitor in the third glass layer.

[0120] Example 10 includes the substrate of Example 7, wherein the first glass layer, the second glass layer, and the third glass layer have the same shape and thickness.

[0121] Example 11 includes an integrated circuit package comprising a first build-up region, a second build-up region, and a core between the first and second build-up regions, the core comprising a stack of multiple glass layers and a capacitor.

[0122] Example 12 includes the integrated circuit package of Example 11, wherein the plurality of glass layers include a first glass layer having a first coefficient of thermal expansion and a second glass layer having a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

[0123] Example 13 includes the integrated circuit package of Example 12, wherein the plurality of glass layers further include a third glass layer, the second glass layer is located between the first glass layer and the third glass layer, and the third glass layer has the first coefficient of thermal expansion.

[0124] Example 14 includes the integrated circuit package of Example 11, wherein the capacitor is a deep trench capacitor.

[0125] Example 15 includes the integrated circuit package of Example 14, wherein the deep trench capacitor is a first deep trench capacitor, the core further includes a second deep trench capacitor, and the first deep trench capacitor is electrically coupled to the second deep trench capacitor.

[0126] Example 16 includes the integrated circuit package of Example 11, wherein the stack comprises a first number of glass layers, and the core further comprises a second number of deep trench capacitors, the second number being greater than or equal to the first number.

[0127] Example 17 includes the integrated circuit package of Example 11, wherein the core further includes an adhesive layer between a first glass layer and a second glass layer, and a buffer layer between the second glass layer and a third glass layer.

[0128] Example 18 includes a device comprising a semiconductor die, a package substrate on the semiconductor die which includes a plurality of glass layers arranged vertically, and a capacitor included in one of the glass layers in the stack of glass layers.

[0129] Example 19 includes the apparatus of Example 18, wherein the capacitor is a first deep trench capacitor, and the apparatus further includes a second deep trench capacitor coupled to the first deep trench capacitor.

[0130] Example 20 includes the apparatus of Example 19, wherein the first deep trench capacitor is aligned with the second deep trench capacitor in a direction perpendicular to the glass layer in the stack.

[0131] The following claims are incorporated by this reference into this detailed description. While specific systems, apparatus, articles, and methods are disclosed herein, the scope of this patent is not limited to them. Rather, this patent extends to all systems, apparatus, articles, and methods that fairly fall within the scope of the claims herein.

Claims

1. The first glass layer, A second glass layer bonded to the first glass layer, A capacitor embedded in the first glass layer, A substrate containing a substrate.

2. The substrate according to claim 1, wherein the first glass layer has a first coefficient of thermal expansion, and the second glass layer has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.

3. The substrate according to claim 1, further comprising an adhesive layer between the first glass layer and the second glass layer.

4. The substrate according to claim 1, further comprising a buffer layer between the first glass layer and the second glass layer.

5. The substrate according to claim 1, wherein the capacitor is a deep trench capacitor.

6. The substrate according to claim 5, wherein the deep trench capacitor is a first deep trench capacitor, and the substrate further includes a second deep trench capacitor embedded in the second glass layer, and the first deep trench capacitor is electrically coupled to the second deep trench capacitor.

7. A third glass layer, wherein the second glass layer is located between the first glass layer and the third glass layer. The first layer between the second glass layer and the first glass layer, A second layer between the third glass layer and the second glass layer, The substrate according to claim 1, further comprising:

8. The substrate according to claim 7, wherein the first layer is a buffer layer and the second layer is an adhesive layer.

9. The substrate according to claim 8, further comprising a second deep trench capacitor in the third glass layer.

10. The substrate according to claim 7, wherein the first glass layer, the second glass layer, and the third glass layer have the same shape and thickness.

11. An integrated circuit package comprising a substrate according to any one of claims 1 to 10.

12. An electronic device comprising the integrated circuit package according to claim 11.

13. The first build-up area and The second build-up area, This is the core between the first build-up region and the second build-up region. A stack of multiple glass layers, and Capacitor, A core that includes, An integrated circuit package that includes this.

14. The aforementioned multiple glass layers are A first glass layer having a first coefficient of thermal expansion, A second glass layer having a second coefficient of thermal expansion different from the first coefficient of thermal expansion, The integrated circuit package according to claim 13, including the following:

15. The integrated circuit package according to claim 14, wherein the plurality of glass layers further include a third glass layer, the second glass layer is located between the first glass layer and the third glass layer, and the third glass layer has a first coefficient of thermal expansion.

16. The integrated circuit package according to any one of claims 13 to 15, wherein the capacitor is a deep trench capacitor.

17. The integrated circuit package according to claim 16, wherein the deep trench capacitor is a first deep trench capacitor, the core further includes a second deep trench capacitor, and the first deep trench capacitor is electrically coupled to the second deep trench capacitor.

18. The integrated circuit package according to any one of claims 13 to 15, wherein the stack comprises a first number of glass layers, and the core further comprises a second number of deep trench capacitors, the second number being equal to or greater than the first number.

19. The aforementioned core further, An adhesive layer between the first glass layer and the second glass layer among the plurality of glass layers, A buffer layer between the second glass layer and the third glass layer among the plurality of glass layers, The integrated circuit package according to any one of claims 13 to 15, including the following:

20. Semiconductor die and The package substrate on the semiconductor die includes a package substrate which includes a plurality of glass layers arranged vertically, A capacitor included in one of the glass layers among the plurality of glass layers arranged vertically, A device having.

21. The apparatus according to claim 20, wherein the capacitor is a first deep trench capacitor, and the apparatus further includes a second deep trench capacitor coupled to the first deep trench capacitor.

22. The apparatus according to claim 21, wherein the first deep trench capacitor is aligned with the second deep trench capacitor in a direction perpendicular to the plurality of vertically arranged glass layers.

23. The aforementioned multiple glass layers arranged vertically are A first glass layer having a first coefficient of thermal expansion, A second glass layer having a second coefficient of thermal expansion different from the first coefficient of thermal expansion, The apparatus according to claim 20, including the apparatus described in claim 20.

24. The apparatus according to claim 23, further comprising an adhesive layer between the first glass layer and the second glass layer.

25. An integrated circuit package comprising the apparatus according to any one of claims 20 to 24.

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