Multilayer ceramic capacitors and mounting structures for multilayer ceramic capacitors

Abstract

To provide a multilayer ceramic capacitor that fully achieves the effect of low ESL. [Solution] A multilayer ceramic capacitor 10 comprising a laminate including a plurality of dielectric layers 14 and internal electrode layers 16, and external electrodes 30 disposed on both end faces and both sides of the laminate, wherein the plurality of internal electrode layers have a first internal electrode layer 16a exposed on both end faces and a second internal electrode layer 16b exposed on both sides. The laminate further has a capacitance forming portion 18 where the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, and a first outer layer portion 20a and a second outer layer portion 20b located between the first and second main faces and the capacitance forming portion, wherein a third internal electrode layer 16c located in the outer layer has a facing portion 22 that faces the first internal electrode layer and is disposed on at least one of the first and second outer layer portions, and the length of the third internal electrode layer in the first direction y is smaller than the length of the second internal electrode layer in the first direction.

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic capacitor and a mounting structure of the multilayer ceramic capacitor.

Background Art

[0002] For example, a decoupling capacitor used to stabilize the power supply voltage supplied to an integrated circuit component (IC) operating at high speed, and a through-type multilayer ceramic capacitor used to countermeasure noise in the power supply line supplied to the integrated circuit component (IC) are known. For example, a through-type multilayer ceramic capacitor generally includes a ceramic substrate (laminated body) having an outer surface composed of a first and a second main surfaces facing each other, a first and a second side surfaces facing each other, and a first and a second end surfaces facing each other. Inside the ceramic substrate, a plurality of first internal electrodes and second internal electrodes are alternately arranged in the stacking direction. The both ends of the first internal electrode are led out to the first end surface and the second end surface, and are connected to a first external electrode and a second external electrode, respectively. Also, the both ends of the second internal electrode are led out to the first side surface and the second side surface, and are connected to a third external electrode and a fourth external electrode, respectively.

[0003] As such a through-type multilayer ceramic capacitor, as disclosed in Patent Document 1, there is provided a through-type three-terminal electronic component including a laminated body having a structure in which one or more sets of signal internal electrodes and ground internal electrodes are stacked so as to face each other through a dielectric layer, a pair of signal external electrodes to which lead-out portions of the signal internal electrodes are connected, and a ground external electrode to which the ground internal electrodes are connected.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] However, in structures like the one described in Patent Document 1, as thin-layer, high-capacity designs become more common, the outer layer needs to be of a certain thickness or more to ensure moisture resistance reliability. A problem arises when the outer layer thickness increases, as the current path for the high-frequency current flowing to GND becomes longer, increasing the ESL (Electromagnetic Slip Level).

[0006] Therefore, the main objective of this invention is to provide a multilayer ceramic capacitor and a mounting structure for a multilayer ceramic capacitor that can accommodate thin-layer, high-capacity capacitors while also achieving a low ESL effect. [Means for solving the problem]

[0007] The multilayer ceramic capacitor according to this invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, having a first surface and a second surface facing each other in the lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction, and a first external electrode disposed on the third surface, a second external electrode disposed on the fourth surface, a third external electrode disposed on the fifth surface, and a fourth external electrode disposed on the sixth surface, wherein the plurality of internal electrode layers are disposed on the plurality of dielectric layers and the first internal electrode is exposed on the third surface and the fourth surface The laminate has a subelectrode layer, a second internal electrode layer disposed on a plurality of dielectric layers and exposed on a fifth and a sixth surface, and a third internal electrode layer disposed on a plurality of dielectric layers and exposed on a fifth and a sixth surface, and the laminate has a capacitance forming portion where the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, a first outer layer portion located between the first surface and the capacitance forming portion, and a second outer layer portion located between the second surface and the capacitance forming portion, and the third internal electrode layer has a facing portion disposed on at least one of the first outer layer portion and the second outer layer portion that faces the first internal electrode layer, and the length of the third internal electrode layer in the first direction is smaller than the length of the second internal electrode layer in the first direction, which is a multilayer ceramic capacitor.

[0008] According to the multilayer ceramic capacitor of this invention, the laminate has a third internal electrode layer arranged on a plurality of dielectric layers and exposed on a fifth and a sixth surface, the laminate has a capacitance forming portion where a first internal electrode layer and a second internal electrode layer face each other to form a capacitance, a first outer layer portion located between the first surface and the capacitance forming portion, and a second outer layer portion located between the second surface and the capacitance forming portion, the third internal electrode layer has a facing portion that faces the first internal electrode layer and is located on at least one of the first outer layer portion and the second outer layer portion, and the length of the third internal electrode layer in the first direction is smaller than the length of the second internal electrode layer in the first direction, so that the current path of the high-frequency current flowing to GND is shortened while ensuring good moisture resistance reliability, thereby achieving low ESL.

[0009] Furthermore, the mounting structure for a multilayer ceramic capacitor according to this invention comprises a mounting substrate and a multilayer ceramic capacitor mounted on the mounting substrate, wherein the multilayer ceramic capacitor is the multilayer ceramic capacitor according to this invention, and the mounting substrate has a core material of the substrate, a first connecting conductor connected to a first external electrode disposed on the core material, a second connecting conductor connected to a second external electrode disposed on the core material, a third connecting conductor connected to a third external electrode disposed on the core material, and a fourth connecting conductor connected to a fourth external electrode disposed on the core material, wherein the multilayer ceramic capacitor is mounted so that the first or second surface faces the mounting substrate side.

[0010] According to the mounting structure of the multilayer ceramic capacitor of this invention, the third internal electrode layer has a facing portion that faces the first internal electrode layer, which is located in at least one of the first outer layer and the second outer layer, and the length of the third internal electrode layer in the first direction is smaller than the length of the second internal electrode layer in the first direction, and the first surface having the first outer layer or the second surface having the second outer layer is mounted facing the mounting substrate, so that the current path from the third internal electrode layer of the multilayer ceramic capacitor to the mounting substrate can be shortened. As a result, according to the mounting structure of the multilayer ceramic capacitor of this invention, the current path of the high-frequency current flowing to GND is shortened, and low ESL can be achieved. [Effects of the Invention]

[0011] According to this invention, it is possible to provide a multilayer ceramic capacitor and a mounting structure for a multilayer ceramic capacitor that can accommodate thin-layer, high-capacity capacitors while also achieving a sufficiently low ESL effect.

[0012] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of this invention. [Figure 2] This is a top view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 3] This is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 4] This is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. [Figure 5] This is a cross-sectional view along line VV in Figure 1. [Figure 6] This is a cross-sectional view along line VI-VI in Figure 1. [Figure 7] It is a cross-sectional view taken along line VII-VII of FIG. 4. [Figure 8] It is a cross-sectional view taken along line VIII-VIII of FIG. 4. [Figure 9] It is a cross-sectional view taken along line IX-IX of FIG. 4. [Figure 10] A modified example of the third internal electrode constituting the multilayer ceramic capacitor according to the embodiment of the present invention is shown. [Figure 11] It is a cross-sectional view in the first direction showing an example of the mounting structure of the multilayer ceramic capacitor according to the first embodiment of the present invention. [Figure 12] It is a cross-sectional view in the second direction showing an example of the mounting structure of the multilayer ceramic capacitor according to the embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0014] 1. Multilayer Ceramic Capacitor The multilayer ceramic capacitor 10 according to the first embodiment of the present invention will be described. The multilayer ceramic capacitor 10 is a through-type multilayer ceramic capacitor (a 3-terminal multilayer ceramic capacitor).

[0015] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a top view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line V-V of FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 4. FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 4. FIG. 10 shows a modified example of a third internal electrode constituting the multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 11 is a cross-sectional view in a first direction showing an example of a mounting structure of the multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 12 is a cross-sectional view in a second direction showing an example of a mounting structure of the multilayer ceramic capacitor according to an embodiment of the present invention.

[0016] As shown in FIGS. 1 to 9, the multilayer ceramic capacitor 10 includes, for example, a laminate 12 and external electrodes 30.

[0017] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. The internal electrode layer 16 has a first internal electrode layer 16a, a second internal electrode layer 16b, and a third internal electrode layer 16c. Details of the first internal electrode layer 16a, the second internal electrode layer 16b, and the third internal electrode layer 16c will be described later.

[0018] The laminate 12 has a first surface 12a and a second surface 12b facing each other in the stacking direction x, a third surface 12c and a fourth surface 12d facing each other in a first direction y orthogonal to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing each other in a second direction z orthogonal to the stacking direction x and the first direction y.

[0019] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f may have irregularities or other features formed on them.

[0020] Here, the dimension of the laminate 12 in the first direction y is denoted as dimension l, the dimension of the laminate 12 in the second direction z is denoted as dimension w, and the dimension of the laminate 12 in the stacking direction x is denoted as dimension t.

[0021] The laminate 12 includes a volume-forming portion 18, and a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged to sandwich the volume-forming portion 18 in the stacking direction x.

[0022] In the capacitance forming section 18, a first internal electrode layer 16a and a second internal electrode layer 16b are alternately stacked via a dielectric layer 14.

[0023] The first outer layer 20a is located on the side of the first surface 12a of the laminate 12, and is situated between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The first outer layer 20a is an assembly of multiple dielectric layers 14, including a first internal electrode layer 16a and a third internal electrode layer 16c. The second outer layer 20b is located on the side of the second surface 12b of the laminate 12, and is situated between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. The second outer layer 20b is an assembly of multiple dielectric layers 14, including a first internal electrode layer 16a and a third internal electrode layer 16c. Furthermore, the region sandwiched between the first outer layer 20a and the second outer layer 20b is the capacitance forming portion 18.

[0024] The thickness of the first outer layer 20a and the second outer layer 20b is 20 μm or more.

[0025] As shown in Figure 6, the laminate 12 is located between the capacitance forming portion 18 and the fifth surface 12e, and between the capacitance forming portion 18 and the sixth surface 12f, and has side portions (W gaps) 23a, 23b of the laminate 12 including the first extension portion 27a and the second extension portion 27b of the second internal electrode layer 16b.

[0026] Furthermore, as shown in Figure 5, the laminate 12 is located between the volume-forming portion 18 and the third surface 12c, and between the volume-forming portion 18 and the fourth surface 12d, and has ends (L gaps) 24a, 24b of the laminate 12 that include the first lead portion 26a and the second lead portion 26b of the first internal electrode layer 16a.

[0027] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0028] The thickness of the dielectric layer 14 is preferably 0.44 μm or more and 0.60 μm or less. Furthermore, the number of dielectric layers 14 to be stacked is preferably 325 or more and 660 or less. Note that this number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the capacitance forming section 18 and the number of dielectric layers 14 in the first outer layer section 20a and the second outer layer section 20b.

[0029] (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a, a second internal electrode layer 16b, and a third internal electrode layer 16c.

[0030] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14. The first internal electrode layer 16a is also extended to a third surface 12c and a fourth surface 12d.

[0031] More specifically, as shown in Figure 7, the first internal electrode layer 16a extends between the third surface 12c and the fourth surface 12d of the laminate 12 and has a first opposing electrode portion 25a located in its central part, a first leading portion 26a extending from the first opposing electrode portion 25a and leading out to the third surface 12c of the laminate 12, and a second leading portion 26b extending from the first opposing electrode portion 25a and leading out to the fourth surface 12d of the laminate 12. The first opposing electrode portion 25a is located in the central part of the dielectric layer 14. The first leading portion 26a is exposed to the third surface 12c of the laminate 12, and the second leading portion 26b is exposed to the fourth surface 12d of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the fifth surface 12e and the sixth surface 12f of the laminate 12.

[0032] The shape of the first internal electrode layer 16a is not particularly limited, but it is preferably rectangular in plan view. Similarly, the shapes of the first opposing electrode portion 25a, the first lead portion 26a, and the second lead portion 26b of the first internal electrode layer 16a are not particularly limited, but they are preferably rectangular in plan view. However, the corners may be rounded.

[0033] The second internal electrode layer 16b is arranged on a plurality of dielectric layers 14. Furthermore, the second internal electrode layer 16b is extended to the fifth surface 12e and the sixth surface 12f. The second internal electrode layer 16b is arranged on a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged.

[0034] More specifically, as shown in Figure 8, the second internal electrode layer 16b extends between the fifth surface 12e and the sixth surface 12f of the laminate 12 and has a second opposing electrode portion 25b located in its central part, a first extension portion 27a extending from the second opposing electrode portion 25b and drawn out to the fifth surface 12e, and a second extension portion 27b extending from the second opposing electrode portion 25b and drawn out to the sixth surface 12f. The second opposing electrode portion 25b is formed in a rectangular shape so as to extend in the direction of the third surface 12c and in the direction of the fourth surface 12d. The second opposing electrode portion 25b is located in the central part of the dielectric layer 14. The first extension portion 27a is exposed to the fifth surface 12e of the laminate 12, and the second extension portion 27b is exposed to the sixth surface 12f of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed to the third surface 12c and the fourth surface 12d of the laminate 12.

[0035] The shapes of the second opposing electrode portion 25b, the first extension portion 27a, and the second extension portion 27b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded.

[0036] The first counter electrode portion 25a of the first internal electrode layer 16a and the second counter electrode portion 25b of the second internal electrode layer 16b are facing each other. In this embodiment, the first counter electrode portion 25a of the first internal electrode layer 16a and the second counter electrode portion 25b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0037] The third internal electrode layer 16c is arranged on a plurality of dielectric layers 14. Furthermore, the third internal electrode layer 16c is extended to the fifth surface 12e and the sixth surface 12f. The third internal electrode layer 16c is arranged on a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged.

[0038] More specifically, as shown in Figure 9, the third internal electrode layer 16c extends between the fifth surface 12e and the sixth surface 12f of the laminate 12 and has a third opposing electrode portion 25c located in its central part, a third extension portion 28a extending from the third opposing electrode portion 25c and drawn out to the fifth surface 12e, and a fourth extension portion 28b extending from the third opposing electrode portion 25c and drawn out to the sixth surface 12f. The third opposing electrode portion 25c is formed in a rectangular shape so as to extend in the direction of the third surface 12c and in the direction of the fourth surface 12d. The third opposing electrode portion 25c is located in the central part of the dielectric layer 14. The third extension portion 28a is exposed to the fifth surface 12e of the laminate 12, and the fourth extension portion 28b is exposed to the sixth surface 12f of the laminate 12. Therefore, the third internal electrode layer 16c is not exposed to the third surface 12c and the fourth surface 12d of the laminate 12.

[0039] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 160 to 328. Similarly, the number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 160 to 328. Therefore, the combined number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 320 to 656.

[0040] The number of third internal electrode layers 16c is not particularly limited, but is preferably one to two.

[0041] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.55 μm or less. The thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.55 μm or less. The thickness of the third internal electrode layer 16c is not particularly limited, but is preferably, for example, 0.38 μm or more and 0.55 μm or less.

[0042] The third internal electrode layer 16c has a facing portion 22 that faces the first internal electrode layer 16a, which is located on the first outer layer 20a and the second outer layer 20b. The third internal electrode layer 16c may be located on at least one of the first outer layer 20a and the second outer layer 20b. In this case, the first internal electrode layer 16a is located on the first outer layer 20a or the second outer layer 20b where the third internal electrode layer 16c is located, and the facing portion 22 is formed between the first internal electrode layer 16a and the third internal electrode layer 16c.

[0043] The length of the third internal electrode layer 16c in the first direction y is smaller than the length of the second internal electrode layer 16b in the first direction y. In other words, the L-gap dimension l1 in the capacitance forming portion 18 is smaller than the L-gap dimension l2 of the third internal electrode layer 16c.

[0044] The thickness of the dielectric layer 14 located in the opposing portion 22 is more than twice the thickness of the dielectric layer 14 located in the capacitance forming portion 18.

[0045] The coverage of the third internal electrode layer 16c located at the opposing portion 22 to the dielectric layer 14 is preferably 90% or more.

[0046] The third internal electrode layer 16c is preferably located on the first surface 12a side of the first outer layer 20a. Furthermore, the third internal electrode layer 16c is preferably located on the second surface 12b side of the second outer layer 20b.

[0047] For example, as shown in Figure 10, as a modified example of the third internal electrode layer 16c, the third opposing electrode portion 25c of the third internal electrode layer 16c does not extend in the direction of the third surface 12c and the fourth surface 12d, and the width of the first direction y connecting the third surface 12c and the fourth surface 12d in the third opposing electrode portion 25c of the third internal electrode layer 16c may be the same as the width of the first direction y connecting the third surface 12c and the fourth surface 12d in the third extension portion 28a and the fourth extension portion 28b of the third internal electrode layer 16c.

[0048] Furthermore, by including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0049] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0050] (external electrode) External electrodes 30 are arranged on the third surface 12c and the fourth surface 12d, as well as the fifth surface 12e and the sixth surface 12f of the laminate 12. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0051] The first external electrode 30a is positioned on the third surface 12c. Furthermore, the first external electrode 30a is connected to the first internal electrode layer 16a. It may also be positioned on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0052] The second external electrode 30b is positioned on the fourth surface 12d. The second external electrode 30b is also connected to the first internal electrode layer 16a. Furthermore, it may also be positioned on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f.

[0053] The third external electrode 30c is positioned on the fifth surface 12e. The third external electrode 30c is also connected to the second internal electrode layer 16b. Furthermore, the third external electrode 30c may have a first covering portion 30c1 that covers the second internal electrode layer 16b exposed on the fifth surface 12e, a first folded portion 30c2 formed on the first surface 12a parallel to the second internal electrode layer 16b, and a second folded portion 30c3 formed on the second surface 12b parallel to the second internal electrode layer 16b. Having the second folded portion 30c3 allows for better maintenance of electrical connection reliability with the mounting substrate 50.

[0054] The fourth external electrode 30d is positioned on the sixth surface 12f. The fourth external electrode 30d is also connected to the second internal electrode layer 16b. Furthermore, the fourth external electrode 30d may have a second covering portion 30d1 (not shown) that covers the second internal electrode layer 16b exposed on the sixth surface 12f, a third folded portion 30d2 formed on the first surface 12a parallel to the second internal electrode layer 16b, and a fourth folded portion 30d3 formed on the second surface 12b parallel to the second internal electrode layer 16b. Having the fourth folded portion 30d3 allows for better maintenance of electrical connection reliability with the mounting substrate 50.

[0055] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0056] The base electrode layer 32 comprises a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0057] The plating layer 34 has a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0058] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b. The third external electrode 30c has a third base electrode layer 32c and a third plating layer 34c. The fourth external electrode 30d has a fourth base electrode layer 32d and a fourth plating layer 34d.

[0059] The first underlay electrode layer 32a is positioned on the surface of the third surface 12c of the laminate 12 and is formed to extend from the third surface 12c and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The second base electrode layer 32b is positioned on the surface of the fourth surface 12d of the laminate 12 and is formed to extend from the fourth surface 12d and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The first base electrode layer 32a may be placed only on the surface of the third surface 12c of the laminate 12, and the second base electrode layer 32b may be placed only on the surface of the fourth surface 12d of the laminate 12.

[0060] The third underlay electrode layer 32c is positioned on the surface of the fifth surface 12e of the laminate 12 and is formed to extend from the fifth surface 12e and cover a portion of the first surface 12a and the second surface 12b, respectively. The fourth base electrode layer 32d is positioned on the surface of the sixth surface 12f of the laminate 12 and is formed to extend from the sixth surface 12f and cover a portion of the first surface 12a and the second surface 12b, respectively.

[0061] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer described above.

[0062] (In the case of a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material with a dielectric material added instead of a glass component.

[0063] The thickness of the first underlay electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d in the central part of the lamination direction x is preferably 10 μm or more and 30 μm or less. Furthermore, the thickness of the second underlayment electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x is preferably 10 μm or more and 30 μm or less.

[0064] When the first base electrode layer 32a is provided on a portion of the first surface 12a and a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the first surface 12a and the second surface 12b is preferably, for example, 3 μm or more and 10 μm or less. Furthermore, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 3 μm or more and 10 μm or less.

[0065] Furthermore, when a second base electrode layer 32b is provided on a part of the first surface 12a and a part of the second surface 12b, and a part of the fifth surface 12e and a part of the sixth surface 12f, the thickness in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the first surface 12a and the second surface 12b is preferably, for example, 3 μm or more and 10 μm or less. Moreover, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 3 μm or more and 10 μm or less.

[0066] The thickness in the second direction z, which connects the fifth surface 12e and the sixth surface 12f, located on the fifth surface 12e and in the central part of the first direction y, which connects the third surface 12c and the fourth surface 12d of the third underlay electrode layer 32c, is preferably 10 μm or more and 30 μm or less. Furthermore, the thickness in the second direction z, which connects the fifth surface 12e and the sixth surface 12f, located at the center of the first direction y, which connects the third surface 12c and the fourth surface 12d of the fourth underlay electrode layer 32d, is preferably 10 μm or more and 30 μm or less.

[0067] The thickness of the third underlay electrode layer 32c located on the first surface 12a in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 3 μm or more and 10 μm or less. Furthermore, the thickness of the fourth underlay electrode layer 32d located on the first surface 12a in the central part of the first direction y connecting the third surface 12c and the fourth surface 12d, in the lamination direction x connecting the first surface 12a and the second surface 12b, is preferably, for example, 3 μm or more and 10 μm or less.

[0068] The thickness of the third underlay electrode layer 32c located on the second surface 12b in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 3 μm or more and 10 μm or less. Furthermore, the thickness of the fourth underlay electrode layer 32d located on the second surface 12b in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 3 μm or more and 10 μm or less.

[0069] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover it, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a portion of it. In addition, there may be multiple conductive resin layers.

[0070] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 10.

[0071] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0072] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0073] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0074] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0075] Various known thermosetting resins can be used as the resin for the conductive resin layer, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0076] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0077] The thickest part of the conductive resin layer is preferably, for example, 20 μm or more and 40 μm or less.

[0078] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0079] The plating layer 34 is positioned to cover the underlying electrode layer 32.

[0080] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0081] The plating layer 34 may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0082] Alternatively, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. Although not shown in the diagrams below, a structure in which a plating layer is provided without a base electrode layer 32 will be described.

[0083] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d, or each of them, may have a plating layer directly formed on the surface of the laminate 12 without providing an underlay electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 12 as a pretreatment.

[0084] Furthermore, if the plating layer is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be converted into a lower profile, i.e., a thinner design, or into the thickness of the laminate 12, i.e., the thickness of the capacitance forming section 18, thereby improving the design flexibility of the thin chip.

[0085] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper plating electrode is preferably formed using Sn or Au, which has good solder wettability.

[0086] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may each consist only of the lower plated electrode. The plating layer may have the upper plated electrode as the outermost layer, or other plated electrodes may be formed on the surface of the upper plated electrode.

[0087] In this case, when the external electrode 30 is formed using only the plating layer without providing the underlayer electrode layer 32, it is preferable that the thickness of each plating layer placed without the underlayer electrode layer 32 is 1 μm or more and 15 μm or less.

[0088] Furthermore, it is preferable that the plating layer does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0089] The dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, in the first direction y is defined as dimension L. Dimension L is preferably 1.00 mm or more and 1.30 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, including the laminated body 12 and the external electrodes 30, is defined as dimension T. Dimension T is preferably 0.40 mm or more and 0.65 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrodes 30, is defined as the W dimension. The W dimension is preferably 0.40 mm or more and 0.95 mm or less.

[0090] The multilayer ceramic capacitor 10 shown in Figure 1 has a first outer layer 20a with a facing portion 22 where the first internal electrode layer 16a and the third internal electrode layer 16c face each other, and a second outer layer 20b with a facing portion 22 where the first internal electrode layer 16a and the third internal electrode layer 16c face each other. As a result, the current path of the high-frequency current flowing to GND is shortened, and low ESL can be achieved.

[0091] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, the L-gap dimension l2 of the opposing portion 22 located in the first outer layer 20a and the second outer layer 20b is larger than the L-gap dimension l1 of the capacitance forming portion 18, thus improving moisture resistance reliability.

[0092] Furthermore, in the multilayer ceramic capacitor 10 shown in Figure 1, if the thickness of the dielectric layer 14 constituting the opposing portion 22 is made more than twice as thick as the thickness of the dielectric layer 14 constituting the capacitance forming portion 18, the moisture resistance reliability can be further improved.

[0093] 2. Mounting structure of multilayer ceramic capacitors Next, the mounting structure of the multilayer ceramic capacitor according to an embodiment of this invention will be described with reference to Figures 11 and 12.

[0094] The mounting structure 100 for the multilayer ceramic capacitor according to this embodiment includes the multilayer ceramic capacitor 10 according to this embodiment and a mounting substrate 50, as shown in Figures 11 and 12. The mounting substrate 50 includes a substrate core material 51 and conductor lands 52. The substrate core material 51 is, for example, made of a substrate made of a material impregnated with epoxy resin or polyimide resin on a base material which is a mixture of glass cloth and glass nonwoven fabric, or a ceramic substrate manufactured by baking a sheet which is a mixture of ceramics and glass. The substrate core material 51 may be a single-layer substrate or a substrate which is made up of multiple layers.

[0095] The thickness of the core material 51 of the substrate is not particularly limited, but it is preferably, for example, 0.2 mm or more and 1.6 mm or less.

[0096] One main surface of the core material 51 of the substrate constitutes the substrate-side mounting surface 51a, on which conductive lands 52 are arranged and which serves as the mounting surface for the multilayer ceramic capacitor 10.

[0097] The conductor land 52 includes a first conductor land 52a, a second conductor land 52b, a third conductor land 52c, and a fourth conductor land 52d.

[0098] The first conductor land 52a is electrically connected to and mechanically joined with the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 54. The second conductor land 52b is electrically connected to and mechanically joined with the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 54. The third conductor land 52c is electrically connected to and mechanically joined with the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 54. The fourth conductor land 52d is electrically connected to and mechanically joined with the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 54.

[0099] The conductive land 52 may also be provided on the main surface of the core material 51 of the substrate opposite to the substrate-side mounting surface 51a.

[0100] The material of the conductor land 52 is not particularly limited, but metals such as copper, gold, palladium, and platinum can be used. The thickness of the conductor land 52, i.e., the dimension in the lamination direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less. The bonding material 54 can be solder or a high-temperature resistant epoxy adhesive.

[0101] In the above description, the mounting substrate 50 corresponds to the mounting substrate of the present invention. The core material 51 of the substrate corresponds to the core material of the substrate of the present invention. The mounting surface 51a on the substrate side corresponds to the mounting surface of the present invention. The plurality of conductor lands 52 correspond to the plurality of connecting conductors of the present invention. However, the connecting conductor of the present invention is not limited to so-called lands, but is any conductor that is provided between a multilayer ceramic capacitor and a mounting substrate and is capable of electrically connecting the two, and is not limited by other uses, functions, shapes, names, etc.

[0102] The mounting structure 100 for the multilayer ceramic capacitor shown in Figures 11 and 12 is mounted on the mounting substrate 50 such that the second surface 12b of the multilayer ceramic capacitor 10 faces the substrate-side mounting surface 51a. Alternatively, the multilayer ceramic capacitor 10 may be mounted on the mounting substrate 50 such that the first surface 12a faces the substrate-side mounting surface 51a.

[0103] Accordingly, the mounting structure 100 of the multilayer ceramic capacitor 10 shown in Figures 11 and 12 directly reflects the various functions of the multilayer ceramic capacitor 10 according to this embodiment of the present invention described above. The third internal electrode layer 16c has a facing portion 22 that faces the first internal electrode layer 16a, which is located on at least one of the first outer layer portion 20a and the second outer layer portion 20b. The first surface 12a having such a first outer layer portion 20a or the second surface 12b having such a second outer layer portion 20b is mounted facing the mounting substrate. As a result, the current path from the third internal electrode layer 16c of the multilayer ceramic capacitor 10 to the mounting substrate 50 can be shortened. Consequently, reflecting the various effects of the multilayer ceramic capacitor 10 according to this embodiment of the present invention, the mounting structure of the multilayer ceramic capacitor has the effect of improving the low ESL characteristics.

[0104] 3. Manufacturing method of multilayer ceramic capacitors Next, a method for manufacturing a multilayer ceramic capacitor 10 according to an embodiment of this invention will be described.

[0105] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances.

[0106] A conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it.

[0107] More specifically, the internal electrode layers of the present invention can be formed by separately preparing a gravure printing plate for forming the first internal electrode layer and the second internal electrode layer, and a gravure printing process for forming the first internal electrode layer and the third internal electrode layer.

[0108] Here, to obtain the desired structure, a portion that will become the capacitance forming portion 18 is formed by alternately stacking a sheet printed with the first internal electrode layer and a sheet printed with the second internal electrode layer. Additionally, a portion that will become the opposing portion to be placed in the first outer layer or the second outer layer is formed by stacking a sheet printed with the first internal electrode layer and a sheet printed with the third internal electrode layer.

[0109] Next, a predetermined number of dielectric sheets without printed patterns for the internal electrode layers are stacked to form a portion that will become the second outer layer on the second surface side. During the stacking of the second outer layer, the first internal electrode layer and the third internal electrode layer are stacked adjacent to each other via dielectric sheets, thereby arranging an opposing portion in the second outer layer. Subsequently, the portion that will become the capacitance forming portion, formed by the above process, is stacked on top of the portion that will become the second outer layer. Then, a predetermined number of dielectric sheets without printed patterns for the internal electrode layers are stacked on top of the portion that will become the capacitance forming portion to form a portion that will become the first outer layer 20a on the first surface 12a side. During the stacking of the first outer layer, the first internal electrode layer and the third outer electrode layer are stacked adjacent to each other via dielectric sheets, thereby arranging an opposing portion in the first outer layer. This completes the production of the laminated sheet.

[0110] Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block.

[0111] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0112] The laminated chips that have been cut out are then fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0113] (base electrode layer) Next, a third base electrode layer 32c of the third external electrode 30c is formed on the fifth surface 12e of the laminate 12 obtained by firing, and a fourth base electrode layer 32d of the fourth external electrode 30d is formed on the sixth surface 12f of the laminate 12.

[0114] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0115] Here, various methods can be used for forming the baked layer. For example, a method can be used in which the orientation of the laminate 12 is aligned using a camera or magnet so that the fifth surface 12e or the sixth surface 12f is facing downwards, and then the laminate 12 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the fifth surface 12e and the sixth surface 12f, but also on parts of the first surface 12a and parts of the second surface 12b.

[0116] Next, a first base electrode layer 32a of the first external electrode 30a is formed on the third surface 12c of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on the fourth surface 12d of the laminate 12. In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using a dip method so as to extend not only to the third surface 12c and the fourth surface 12d, but also to a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0117] The baking process may involve baking the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d simultaneously, or the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d separately.

[0118] (Conductive resin layer) Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0119] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0120] Furthermore, the conductive resin paste can be applied using methods similar to those used to form the base electrode layer 32 with a baked layer, such as a dipping method, a method of applying the conductive resin paste by extruding it through a slit, or a roller transfer method.

[0121] (thin film layer) Furthermore, when forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer 32 can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness with metal particles deposited on it.

[0122] (Plating layer) Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. In that case, it can be formed by the following method.

[0123] Plating is applied to the third surface 12c and the fourth surface 12d of the laminate 12 to form a lower layer plated electrode on the exposed portion of the first internal electrode layer 16a. Similarly, plating is applied to the fifth surface 12e and the sixth surface 12f of the laminate 12 to form a lower layer plated electrode on the exposed portion of the second internal electrode layer 16b. When performing the plating, either electrolytic plating or electroless plating may be used, but electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. As for the plating method, barrel plating is preferred. Also, if necessary, the upper layer plated electrode formed on the surface of the lower layer plated electrode may be formed in the same manner.

[0124] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer, and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0125] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0126] 4. Experimental Examples Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention as described above, a multilayer ceramic capacitor was manufactured as an experimental sample, and the L-gap dimension of the third internal electrode layer and the thickness of the dielectric layer located opposite the first internal electrode layer and the third internal electrode layer were varied, and a moisture resistance reliability test and evaluation by ESL were performed.

[0127] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experimental example Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors, which are the samples for Comparative Examples 1 to 3 and Examples 1 to 4, were fabricated. • Structure of multilayer ceramic capacitor: 3 terminals (see Figure 1) • Dimensions (L) of the multilayer ceramic capacitor: 1.25 mm • Dimensions of the multilayer ceramic capacitor (W): 0.85mm • Dimensions (T) of the multilayer ceramic capacitor: 0.45mm • Thickness of the dielectric layer located in the capacitance formation area: 0.46 μm • Thickness of the internal electrode layer: 0.40 μm • Number of first internal electrode layers: 230 • Number of layers in the second internal electrode layer: 230 • Thickness of the first outer layer: 20 μm • Thickness of the second outer layer: 20 μm • L-gap dimension of the volume-forming section: 38 μm • W-gap dimension: 45 μm • L-gap dimensions of the third internal electrode layer: 38 μm, 48 μm, 59 μm, 67 μm • Thickness of the dielectric layer located in the opposing portion, which is composed of the first internal electrode layer and the third internal electrode layer: 0.46 μm, 0.92 μm • Structure of the external electrodes • First external electrode and second external electrode • Underlay electrode layer: A baked layer containing conductive metal (Cu) and glass components. • Plating layer: Two-layer structure consisting of a Ni plating layer and a Sn plating layer. • Third external electrode and fourth external electrode • Underlay electrode layer: A baked layer containing conductive metal (Cu) and glass components. • Plating layer: Two-layer structure consisting of a Ni plating layer and a Sn plating layer.

[0128] Each sample in the examples has a third internal electrode layer in the first and second outer layers, and the L-gap dimension of the third internal electrode layer located in the outer layer is varied within a range greater than the L-gap dimension of the capacitance forming section. Furthermore, in each sample in Examples 2 to 4, the thickness of the dielectric layer located in the opposing part of the outer layer is twice the thickness of the dielectric layer located in the capacitance forming section.

[0129] The sample according to Comparative Example 1 is a three-terminal type multilayer ceramic capacitor identical to the multilayer ceramic capacitor of the Example, except that it does not have a third internal electrode layer in the first and second outer layers. The samples in Comparative Example 2 and Comparative Example 3 have a third internal electrode layer in the first and second outer layers, respectively. However, in Comparative Example 2 and Comparative Example 3, the L-gap dimension of the capacitance forming portion and the L-gap dimension of the third internal electrode layer arranged in the outer layer were the same.

[0130] (2) Humidity resistance reliability test Humidity resistance reliability was tested using the PCBT (Pressure Cooker Bias Test). The test conditions were 125°C and 95% RH relative humidity. Under these conditions, a 4V DC voltage was applied between the external electrodes of each multilayer ceramic capacitor for 72 hours to perform the insulation test. The insulation resistance value of each multilayer ceramic capacitor was then measured after this insulation test. A sample was considered defective (NG) if the insulation resistance value after the humidity test was more than an order of magnitude lower than the insulation resistance value before the insulation test. 72 samples were used for each test. (3) Method for measuring ESL Samples for each sample number were mounted on mounting boards with mounting surfaces to create circuit board samples. The ESL value was measured by measuring the impedance between external electrodes via the lands of these circuit boards. Specifically, the ESL value of each sample at a frequency of 1 GHz was measured using a network analyzer (Agilent Corporation, model number: E5080A) between the first or second external electrode and the third or fourth external electrode. There were 10 samples for each sample number. The ESL value for each sample number was calculated as the average of the 10 samples.

[0131] (5) Results Table 1 shows the results of humidity resistance reliability tests and ESL evaluations for changes in the L-gap dimension of the third internal electrode layer and the thickness of the dielectric layer located opposite the first and third internal electrode layers.

[0132] [Table 1]

[0133] According to Table 1, in each of the samples from Examples 1 to 4, the L-gap dimension of the third internal electrode layer placed in the outer layer was larger than the L-gap dimension of the capacitance forming portion. In other words, the length of the third internal electrode layer in the first direction y was smaller than the length of the second internal electrode layer in the first direction y. As a result, the moisture resistance reliability test results were good, and it was confirmed that the ESL could be reduced compared to the ESL measurement results of Comparative Example 1. This is thought to be because by placing opposing portions in the outer layer where the first internal electrode layer and the third internal electrode layer face each other, the current path of the high-frequency current flowing to GND was shortened, and the ESL was reduced.

[0134] Furthermore, in each of the samples from Examples 2 to 4, the thickness of the dielectric layer located in the opposing part of the outer layer was set to twice the thickness of the dielectric layer located in the capacitance forming part, which was confirmed to further improve the moisture resistance reliability test results.

[0135] On the other hand, in Comparative Examples 2 and 3, a third internal electrode layer is placed in the outer layer. However, in Comparative Examples 2 and 3, the L-gap dimension of the capacitance forming portion and the L-gap dimension of the third internal electrode layer placed in the outer layer are the same. As a result, many samples were judged to be defective based on the moisture resistance reliability test results.

[0136] As a result of the above findings, it became clear that by providing a third internal electrode layer in the outer layer and making the length of the third internal electrode layer in the first direction y smaller than the length of the second internal electrode layer in the first direction y, it is possible to achieve both moisture resistance reliability and low ESL (Electrolytic Slip Loss).

[0137] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. In other words, various modifications can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and objectives of the present invention, and these modifications are included in the present invention.

[0138] <1> A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode disposed on the third surface, A second external electrode is disposed on the fourth surface, A third external electrode disposed on the fifth surface, A fourth external electrode disposed on the sixth surface, A multilayer ceramic capacitor comprising, The plurality of internal electrode layers are A first internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the third and fourth surfaces, A second internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the fifth and sixth surfaces, A third internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the fifth and sixth surfaces, It has, The laminated body is A capacitance forming section in which the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, A first outer layer located between the first surface and the volume forming portion, A second outer layer located between the second surface and the volume-forming portion, It has, The third internal electrode layer has a facing portion that is located on at least one of the first outer layer and the second outer layer and faces the first internal electrode layer. A multilayer ceramic capacitor in which the length of the third internal electrode layer in the first direction is smaller than the length of the second internal electrode layer in the first direction.

[0139] <2> The thickness of the dielectric layer located in the opposing portion is at least twice the thickness of the dielectric layer located in the capacitance forming portion. <1> The multilayer ceramic capacitor described above.

[0140] <3> The thickness of the first outer layer and the second outer layer is 20 μm or more. <1> or <2> The multilayer ceramic capacitor described above.

[0141] <4> The third internal electrode layer is located on the first or second surface side of the first and second outer layers, <1> or <3> A multilayer ceramic capacitor as described in any of the following.

[0142] <5> The thickness of the dielectric layer located in the capacitance forming portion is 0.44 μm or more and 0.60 μm or less, and the thickness of the internal electrode layer located in the capacitance forming portion is 0.38 μm or more and 0.55 μm or less. <1> or <4> A multilayer ceramic capacitor as described in any of the following.

[0143] <6> The coverage of the dielectric layer of the internal electrode layer located in the opposing portion is 90% or more. <1> or <5> A multilayer ceramic capacitor as described in any of the following.

[0144] <7> Implemented circuit board and A multilayer ceramic capacitor mounted on the aforementioned mounting substrate, Equipped with, The aforementioned multilayer ceramic capacitor is <1> or <6> A multilayer ceramic capacitor as described in any of the following: The aforementioned mounting board is The core material of the circuit board, A first connecting conductor connected to the first external electrode disposed on the core material, A second connecting conductor connected to the second external electrode disposed on the core material, A third connecting conductor connected to the third external electrode disposed on the core material, A fourth connecting conductor connected to the fourth external electrode, which is disposed on the core material, It has, A mounting structure for a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor is mounted such that the first surface or the second surface faces the mounting substrate. [Explanation of Symbols]

[0145] 10 Multilayer ceramic capacitors 12-layer structure 12a First face 12b Second face 12c Third side 12d Fourth face 12e Fifth side 12f Sixth face 14 Dielectric layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18 Capacity forming part 20a First outer layer 20b Second outer layer 22. Opposing part 23a, 23b W gap 24a, 24b L gap 25a First counter electrode portion 25b Second counter electrode section 25c Third counter electrode section 26a First drawer 26b Second drawer section 27a First extension 27b Second extension 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 30c1 First covering part 30c2 First fold 30c3 Second fold 30d1 Second covering portion 30d2 Third folded part 30d3 Fourth fold 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 32c Third Underlay Electrode Layer 32d Fourth underlay electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 50 mounted circuit boards 51 Core material of the substrate 51a PCB-side mounting surface 52 Conductor Lands 52a First Conductor Land 52b Second Conductor Land 52c Third Conductor Land 52d Fourth Conductor Land 54 Bonding material 100 Mounting Structure of Multilayer Ceramic Capacitors x stacking direction y First direction z Second direction L is the dimension of the multilayer ceramic capacitor in the first direction. W Dimensions of the second direction of the multilayer ceramic capacitor T Dimensions in the stacking direction of a multilayer ceramic capacitor l Dimensions of the laminate in the first direction w Dimensions of the laminate in the second direction t Dimensions in the stacking direction of the laminate

Claims

1. A laminate comprising a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, A first external electrode is disposed on the third surface, A second external electrode is disposed on the fourth surface, A third external electrode disposed on the fifth surface, A fourth external electrode is disposed on the sixth surface, A multilayer ceramic capacitor comprising, The plurality of internal electrode layers are A first internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the third and fourth surfaces, A second internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the fifth and sixth surfaces, A third internal electrode layer is disposed on the plurality of dielectric layers and is exposed on the fifth and sixth surfaces, It has, The laminated body is A capacitance forming section in which the first internal electrode layer and the second internal electrode layer face each other to form a capacitance, A first outer layer located between the first surface and the volume forming portion, A second outer layer located between the second surface and the volume-forming portion, It has, The third internal electrode layer has a facing portion that is located on at least one of the first outer layer and the second outer layer and faces the first internal electrode layer. A multilayer ceramic capacitor in which the length of the third internal electrode layer in the first direction is smaller than the length of the second internal electrode layer in the first direction.

2. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the dielectric layer located in the opposing portion is at least twice the thickness of the dielectric layer located in the capacitance forming portion.

3. The multilayer ceramic capacitor according to claim 2, wherein the thickness of the first outer layer and the second outer layer is 20 μm or more.

4. The multilayer ceramic capacitor according to claim 3, wherein the third internal electrode layer is located on the first surface side or the second surface side of the first outer layer and the second outer layer.

5. The multilayer ceramic capacitor according to claim 4, wherein the thickness of the dielectric layer located in the capacitance forming portion is 0.44 μm or more and 0.60 μm or less, and the thickness of the internal electrode layer located in the capacitance forming portion is 0.38 μm or more and 0.55 μm or less.

6. The multilayer ceramic capacitor according to claim 5, wherein the coverage of the dielectric layer of the internal electrode layer located in the opposing portion is 90% or more.

7. Implemented circuit board and A multilayer ceramic capacitor mounted on the aforementioned mounting substrate, Equipped with, The multilayer ceramic capacitor is the multilayer ceramic capacitor described in claim 1, The aforementioned mounting board is The core material of the circuit board, A first connecting conductor connected to the first external electrode disposed on the core material, A second connecting conductor connected to the second external electrode disposed on the core material, A third connecting conductor connected to the third external electrode disposed on the core material, A fourth connecting conductor connected to the fourth external electrode, which is arranged on the core material, It has, A mounting structure for a multilayer ceramic capacitor, wherein the multilayer ceramic capacitor is mounted such that the first surface or the second surface faces the mounting substrate.

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