Semiconductor devices, power supply devices, and vehicles

Abstract

Ensure the safety of equipment equipped with semiconductor devices. [Solution] In the semiconductor device (10), the diagnostic circuit (113) is capable of performing on-demand diagnostics (ABIST on demand) by operating the error detection units (11P, 11D) while the analog circuits (131, 132) are operating, and has a mask circuit (114) that masks the input of error detection signals (SEP, SED) to the judgment circuits (111, 112) when on-demand diagnostics (ABIST on demand) are being performed.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a power supply device, and a vehicle.

Background Art

[0002] In recent years, in in-vehicle ICs (Integrated Circuits), a configuration having a self-diagnosis function called BIST (Built-In Self Test) for confirming normal operation has been adopted (see Patent Document 1, etc.).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] Ensuring the safety of equipment on which semiconductor devices such as in-vehicle ICs are mounted is required.

[0005] A semiconductor device according to an aspect of the present disclosure includes an analog circuit, an analog circuit, a control circuit configured to control the analog circuit, an error detection unit disposed in the control circuit and configured to detect an error in a signal or voltage and output an error detection signal, a determination circuit configured to determine whether or not the error has occurred based on the error detection signal, and a diagnosis circuit configured to diagnose the quality of the error detection unit based on the error detection signal. The diagnosis circuit can perform an in-operation diagnosis of operating the error detection unit while the analog circuit is operating. When performing the in-operation diagnosis, it has a configuration of a mask circuit that masks the input of the error detection signal to the determination circuit.

Brief Description of Drawings

[0006] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a power supply device using a semiconductor device. [Figure 2]Figure 2 shows a detailed configuration of the semiconductor device. [Figure 3] Figure 3 shows ASIL. [Figure 4] Figure 4 shows the signal states in On-Demand ABIST when there are no malfunctions in the protection and detection elements. [Figure 5] Figure 5 shows the signal states when there is a malfunction in the detection system element. [Figure 6] Figure 6 shows the signal states when there is a malfunction in the protection system element. [Figure 7] Figure 7 shows the signal states when there is a malfunction in the detection system element and the protection system element. [Figure 8] Figure 8 is a flowchart showing the processing of on-demand ABIST. [Figure 9] Figure 9 shows the configuration of the power supply unit according to a modified example. [Figure 10] Figure 10 shows an example of the configuration of a vehicle including a power supply unit.

[0007] [Detailed explanation] In this specification, a MOS (Metal Oxide Semiconductor) field-effect transistor refers to a transistor whose gate structure consists of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with low resistance," "an insulating layer," and "a P-channel, N-channel, or intrinsic semiconductor layer." In other words, the gate structure of a MOS field-effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor. Furthermore, a MOS field-effect transistor may be simply referred to as a MOS transistor. In addition, a P-channel MOS transistor will be referred to as a PMOS transistor, and an N-channel MOS transistor as an NMOS transistor.

[0008] In relation to any element, line, or other part forming a circuit, "connection" includes both mechanical connection and electrical connection, in other words, a state in which electricity flows. Therefore, "to connect" includes "to connect electrically."

[0009] <Power supply device 100> Figure 1 shows the overall configuration of the power supply unit 100 using the semiconductor device 10. Figure 2 shows the detailed configuration of the semiconductor device 10. In Figure 2, the connection between the control circuit 11 and the driver circuit 131 is shown, but the driver circuit 132 is assumed to have the same connection configuration as the driver circuit 131.

[0010] The power supply unit 100 is a switching power supply unit. The power supply unit 100 is configured to be controlled based on instructions from the MCU (Motor Control Unit) 200. The power supply unit 100 is used, for example, as the power supply for a vehicle.

[0011] As shown in Figure 1, the MCU 200 is connected to the semiconductor device 10, which will be described later, of the power supply unit 100. The standby signal STBY, enable signal EN, clock signal SCL, data signal SDA, and reset signal PRSTB are input to the semiconductor device 10 from the MCU 200. The standby signal STBY, enable signal EN, clock signal SCL, data signal SDA, and reset signal PRSTB are supplied to each circuit of the semiconductor device 10 via the external terminals provided on the semiconductor device 10 of the power supply unit 100.

[0012] Furthermore, the semiconductor device 10 outputs an error signal ERRB, an interrupt signal INTB, and a data signal SDA to the MCU 200 via the external terminals of the semiconductor device 10. The data signal SDA is transmitted and received bidirectionally between the MCU 200 and the semiconductor device 10 via I2C (Inter-Integrated Circuit) wiring. Other signals may also be transmitted using the same I2C configuration.

[0013] As shown in Figure 1, the power supply unit 100 is a power supply LSI (Large Scale Integration) capable of outputting output voltage and output current from multiple channels. The power supply unit 100 shown in Figure 1 has two channels. The power supply unit 100 has a configuration in which the semiconductor device 10, the output unit 20 (described later), and the rectifier / smoothing circuit (described later) are integrated in a single package. The output unit 20 may be connected externally to the power supply LSI. Similarly, the rectifier / smoothing circuit may be connected externally to the power supply LSI.

[0014] Furthermore, the power supply unit 100 is an analog circuit that operates with analog signals. The power supply unit 100 includes a semiconductor device 10 and an output unit 20. In the power supply unit 100 shown in Figure 1, the first channel is configured to output an output voltage VOUT1 from the output unit 20 located outside the semiconductor device 10, and the second channel is configured to output an output voltage VOUT2 from a bridge circuit 142, which will be described later, located inside the semiconductor device 10.

[0015] <Semiconductor device 10> The semiconductor device 10 controls the power supply unit 100 (a so-called PMIC [power management integrated circuit]). As shown in Figure 1, the semiconductor device 10 includes a control circuit 11, an internal voltage generation circuit 12, driver circuits 131 and 132, and bridge circuits 141 and 142. The semiconductor device 10 also has other components, and has a configuration in which multiple components are integrated into a single package.

[0016] <Internal voltage generation circuit 12> The internal voltage generation circuit 12 is a circuit that generates and outputs an internal voltage VREG based on an input voltage VIN, and is configured by, for example, an LDO (Low Drop-Out). A standby signal STBY and an enable signal EN are input to the internal voltage generation circuit 12. When the standby signal STBY or the enable signal EN rises to a high level, the internal voltage generation circuit 12 generates the internal voltage VREG. The internal voltage generation circuit 12 is connected to an output capacitor provided externally. The internal voltage VREG is supplied to the output capacitor. Then, the internal voltage VREG based on the charge stored in the output capacitor is input again to the inside and supplied to the control circuit 11 and the driver circuits 131 and 132. Thereby, the operations of the control circuit 11 and the driver circuits 131 and 132 are started.

[0017] <Bridge circuits 141 and 142> The bridge circuit 141 and the bridge circuit 142 are both configurations included in the semiconductor device 10. The bridge circuit 141 and the bridge circuit 142 have substantially the same configuration. Therefore, the detailed configuration will be described with reference to the bridge circuit 141, and the detailed description of the same parts as the bridge circuit 141 in the bridge circuit 142 will be omitted.

[0018] As shown in FIG. 1, the bridge circuit 141 has a high-side switching element M1 and a low-side switching element M2. The high-side switching element M1 and the low-side switching element M2 are connected in series. The high-side switching element M1 and the low-side switching element M2 are NMOS transistors. The drain of the high-side switching element M1 is connected to the application end of the input voltage VIN. That is, the input voltage VIN is supplied to the drain of the high-side switching element M1. Also, the source of the low-side switching element M2 is connected to the application end of the ground voltage.

[0019] The gate of the high-side switching element M1 is connected to the driver circuit 131, and the high-side drive signal HG is supplied. Also, the gate of the low-side switching element M2 is connected to the driver circuit 131, and the low-side drive signal LG is supplied.

[0020] In the bridge circuit 141, the high-side switching element M1 and the low-side switching element M2 are controlled so that both are in the off state or one of them is in the on state and the other is in the off state. Note that they are controlled so that the high-side switching element M1 and the low-side switching element M2 are not both in the on state.

[0021] In the bridge circuit 141, the high-side switching element M1 is an NMOS transistor, but it may be a PMOS transistor.

[0022] A switching voltage VSW1 is generated at the connection point between the source of the high-side switching element M1 and the drain of the low-side switching element M2. The switching voltage VSW1 is output to the outside.

[0023] When the bridge circuit 141 is used to output an output voltage and an output current to a load, an output voltage VOUT1 corresponding to the switching voltage VSW1 is output. Also, when the output unit 20 is connected and the output unit 20 outputs an output voltage and an output current, the switching voltage VSW1 is supplied to the output unit 20 as a sense voltage.

[0024] Similar to the bridge circuit 141, the bridge circuit 142 has a high-side switching element M1 and a low-side switching element M2. The drain of the high-side switching element M1 is connected to the application end of the input voltage VIN. Also, the source of the low-side switching element M2 is connected to the application end of the ground voltage.

[0025] The gate of the high-side switching element M1 of the bridge circuit 142 is connected to the driver circuit 132, and a high-side drive signal HG is supplied to it. The gate of the low-side switching element M2 is also connected to the driver circuit 132, and a low-side drive signal LG is supplied to it.

[0026] In the bridge circuit 142, a switch voltage VSW2 is generated at the connection point between the source of the high-side switching element M1 and the drain of the low-side switching element M2. The switch voltage VSW2 is output to the outside.

[0027] <Output section 20> The output unit 20 has a configuration in which the drive unit 21 and the bridge circuit 22 are integrated into a single package. The bridge circuit 22 of the output unit 20 has a high-side switching element N1 and a low-side switching element N2. The high-side switching element N1 and the low-side switching element N2 have the same configuration as the high-side switching element M1 and the low-side switching element M2 of the bridge circuits 141 and 142.

[0028] The drive unit 21 has the same configuration as the part that drives the bridge circuits 141 and 142 of the driver circuits 131 and 132. In other words, the drive unit 21 is supplied with a drive signal Spwm1. Based on the drive signal Spwm1, the drive unit 21 generates a high-side drive signal HG to be supplied to the gate of the high-side switching element N1, and also generates a low-side drive signal LG to be supplied to the gate of the low-side switching element N2.

[0029] The first terminal of inductor L1 is connected to the connection point between the high-side switching element N1 and the low-side switching element N2 of the bridge circuit 22 of the output unit 20. The second terminal of inductor L1 is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is connected to the terminal to which the ground voltage is applied. The connection point between inductor L1 and capacitor C1 is output externally as the output of the output unit 20. In other words, in the power supply unit 100, the switch voltage at the connection point of the bridge circuit is rectified and smoothed by a rectifier and smoothing circuit composed of inductor L1 and capacitor C1, and the output voltage VOUT1 and output current IOUT1 are output.

[0030] Furthermore, when outputting output voltage VOUT1 and output current IOUT1 based on the switch voltage VSW1 at the connection point between the high-side switching element M1 and the low-side switching element M2 of the bridge circuit 141, the first end of inductor L1 is connected to the connection point between the high-side switching element M1 and the low-side switching element M2 of the bridge circuit 141. In addition, in the power supply unit 100, a rectifier and smoothing circuit consisting of inductor L2 and capacitor C2 is connected to the connection point between the high-side switching element M1 and the low-side switching element M2 of the bridge circuit 142.

[0031] <Driver circuit 131, driver circuit 132> The driver circuits 131 and 132 receive drive signals Spwm1 and Spwm2 from the control circuit 11. Drive signal Spwm1 is a signal that determines the on-period of the high-side switching element M1 of the bridge circuit 141. Drive signal Spwm2 is a signal that determines the on-period of the high-side switching element M1 of the bridge circuit 142.

[0032] Based on the drive signal Spwm1, the driver circuit 131 generates a high-side drive signal HG to be supplied to the gate of the high-side switching element M1 of the bridge circuit 141, and also generates a low-side drive signal LG to be supplied to the gate of the low-side switching element M2. Furthermore, based on the drive signal Spwm2, the driver circuit 132 generates a high-side drive signal HG to be supplied to the gate of the high-side switching element M1 of the bridge circuit 142, and also generates a low-side drive signal LG to be supplied to the gate of the low-side switching element M2.

[0033] Furthermore, the driver circuits 131 and 132 are configured to be connectable to an external output unit 20. In this case, the driver circuits 131 and 132 are configured to output drive signals Spwm1 and Spwm2 to the output unit 20. In the power supply device 100 of this disclosure, the output unit 20 is connected to the driver circuit 131.

[0034] Driver circuits 131 and 132 have essentially the same configuration. Therefore, in the following explanation, driver circuit 131 and bridge circuit 141 will be described in detail as representatives, and then the differences between driver circuit 132 and driver circuit 131 will be explained.

[0035] The driver circuit 131 outputs a high-side drive signal HG to the gate of the high-side switching element M1 of the bridge circuit 141, and outputs a low-side drive signal LG to the gate of the low-side switching element M2.

[0036] In the bridge circuit 141, the high-side switching element M1 is turned on when the high-side drive signal HG is at a high level, and turned off when the high-side drive signal HG is at a low level. Similarly, the low-side switching element M2 is turned on when the low-side drive signal LG is at a high level, and turned off when the low-side drive signal LG is at a low level.

[0037] The driver circuit 131 outputs a high-side drive signal HG and a low-side drive signal LG such that both the high-side switching element M1 and the low-side switching element M2 are in the off state, or one of them is in the on state and the other is in the off state. The driver circuit 131 also outputs a high-side drive signal HG and a low-side drive signal LG such that both the high-side switching element M1 and the low-side switching element M2 are not in the on state.

[0038] The control circuit 11 is configured to obtain feedback signals FB1P and FB1N from the voltage across the capacitor C1 of the rectifier and smoothing circuit. Based on the feedback signals FB1P and FB1N, the control circuit 11 obtains a voltage corresponding to the output voltage VOUT1 and outputs a drive signal Spwm1 so that the output voltage VOUT1 becomes a predetermined voltage.

[0039] Similarly, the control circuit 11 is configured to obtain feedback signals FB2P and FB2N from the voltage across the capacitor C2 of the rectifier and smoothing circuit. Based on the feedback signals FB2P and FB2N, the control circuit 11 obtains a voltage corresponding to the output voltage VOUT2 and outputs a drive signal Spwm2 so that the output voltage VOUT2 becomes a predetermined voltage.

[0040] <Control circuit 11> As shown in Figure 1, the control circuit 11 is a circuit that controls the semiconductor device 10. The control circuit 11 generates drive signals Spwm1 and Spwm2 to drive each bridge circuit 141 and 142 and outputs them to the driver circuits 131 and 132 located inside the semiconductor device 10.

[0041] In recent years, there has been an increasing demand for semiconductor devices 10 installed in vehicles to comply with the ISO 26262 standard, which is established to achieve functional safety in vehicles. The ISO 26262 standard sets out the degree of risk of errors occurring in vehicle elements in levels called ASIL (Automotive Safety Integrity Level). ASIL has four levels: A level (ASIL_A), B level (ASIL_B), C level (ASIL_C), and D level (ASIL_D), with the degree of risk of errors increasing in the order of A level.

[0042] The ISO 26262 standard stipulates that failures occurring in automotive semiconductor equipment should be evaluated using a failure frequency (failure rate) calculated by statistical methods. Figure 3 shows the ASIL (Automotive Safety Integrity Level).

[0043] As shown in Figure 3, the ISO 26262 standard sets target failure rates for each ASIL level, such as the time-averaged probability of failure over the vehicle's lifespan (PMHF [Probabilistic Metric for random Hardware Failures]). For ASIL_A, the PMHF is 1000 FIT (Failure In Time: average number of failures per billion hours). Similarly, for ASIL_B, ASIL_C, and ASIL_D, the PMHF is 100 FIT, 100 FIT, and 10 FIT, respectively.

[0044] Furthermore, it is difficult to completely prevent failures in the components that make up a vehicle. In particular, it is often difficult to manufacture semiconductor devices 10 to have an ASIL_D level failure rate. On the other hand, even if a failure occurs in the semiconductor device 10, if that failure can be detected quickly, it may be possible to suppress the occurrence of failures in the vehicle as a whole. For this reason, the ISO 26262 standard sets a failure detection rate, which is the probability of detecting a failure.

[0045] Furthermore, the ISO 26262 standard sets target failure detection rates for each ASIL level, divided into two types: SPFM (Single Point Failure Metrics) and LFM (Latent Failure Metrics). SPFM are failures that directly deviate from the safety goal due to a single occurrence. LFM, on the other hand, are failures that deviate from the safety goal due to a latent fault.

[0046] The semiconductor device 10 is equipped with an error detection unit in the control circuit 11, for example, which detects errors such as a protection element 11P and a detection element 11D in order to detect the above-mentioned failures (see, for example, Figure 2). The protection element 11P is an error detection unit that detects a signal or voltage error that would cause a malfunction of a high degree of risk if the power supply 100 were to continue operating. The detection element 11D is an error detection unit that detects a signal or voltage error that causes a malfunction of a lower degree of risk than the signal or voltage detected by the protection element 11P. The error detection unit ranks the signal or voltage errors according to their degree of risk. In the semiconductor device 10 of this disclosure, the protection element 11P can be assigned a higher risk rank than the detection element 11D.

[0047] For example, if the output voltage VOUT1 output from the output unit 20 and bridge circuit 141 exceeds a certain range, it may cause malfunction in the load to which the output voltage VOUT1 is supplied (e.g., control devices for the engine, brakes, etc.). In such cases, the output voltage VOUT1 may be output to components where malfunction is unacceptable for the safe operation of the vehicle, i.e., components with an ASIL of C or D level. Therefore, the output voltage VOUT1 of the output unit 20 and bridge circuit 141 is subject to error detection by the protection element 11P.

[0048] In the control circuit 11, the protection element 11P receives feedback signals FB1P, FB1N, FB2P, FB2N, etc. (see Figure 2). The protection element 11P detects errors in the feedback signals FB1P, FB1N, FB2P, FB2N, etc., and outputs a first error detection signal SEP to the protection system determination circuit 111, which will be described later in the control circuit 11. The first error detection signal SEP is low level when the protection element 11P does not detect an error, and high level when an error is detected. Note that the level of the first error detection signal SEP is not limited to the above.

[0049] Examples of protection elements 11P include OVP (Over Voltage Protection), which detects when the voltage or signal is greater than a certain threshold, and UVP (Under Voltage Protection), which detects when the voltage or signal is less than a certain threshold. In addition, a wide range of elements for detecting signal and voltage errors can be used.

[0050] In the semiconductor device 10, an internal voltage VREG is supplied to the control circuit 11. The detection element 11D of the control circuit 11 receives the internal voltage VREG, feedback signals FB1P, FB1N, FB2P, FB2N, etc. as inputs (see Figure 2). The detection element 11D detects whether or not there is an error in the internal voltage VREG, feedback signals FB1P, FB1N, FB2P, FB2N, etc. The detection element 11D then outputs a second error detection signal SED to the detection system determination circuit 112 of the control circuit 11, which will be described later. The second error detection signal SED is, for example, low level when the detection element 11D does not detect an error, and high level when an error is detected. Note that the level of the second error detection signal SED is not limited to the above.

[0051] Examples of detection elements 11D include OVD (Over Voltage Detection), which detects when the voltage or signal is greater than a certain threshold, and UVD (Under Voltage Detection), which detects when it is less than a certain threshold. In addition, a wide range of elements for detecting errors in signals and voltages can be used.

[0052] Furthermore, if the internal voltage VREG becomes too high, it may exceed the breakdown voltage of the semiconductor device 10, and if it becomes too low, it may cause the operation of the semiconductor device 10 to become unstable. For this reason, error detection may be performed for the internal voltage VREG using both the detection element 11D and the protection element 11P. In other words, the detection element 11D may detect when the internal voltage VREG, which operates within a first range, exceeds the first range, and the protection element 11P may detect when it exceeds a second range which is wider than the first range.

[0053] Furthermore, the control circuit 11 is configured to acquire feedback signals FB2P and FB2N by measuring the voltage across the capacitor C2 of the rectifier and smoothing circuit. The protection element 11P and detection element 11D of the control circuit 11 perform error detection on the feedback signals FB2P and FB2N in the same way as they do on the feedback signals FB1P and FB1N.

[0054] Furthermore, the control circuit 11 includes a protection system determination circuit 111, a detection system determination circuit 112, and an ABIST (Analog Built In Test) diagnostic circuit 113. The protection system determination circuit 111 receives a first error detection signal SEP output from the protection system element 11P. Based on the first error detection signal SEP, the protection system determination circuit 111 determines whether or not the protection system element 11P has detected an error.

[0055] The protection system determination circuit 111, upon determining that the protection system element 11P has detected an error, notifies the MCU 200 via the interrupt signal INTB that interrupt processing (stop or safe mode operation) is required. The interrupt signal INTB is pulled up. For example, the interrupt signal INTB may be a signal that is high when there is no error and low when an error is detected.

[0056] Furthermore, the detection system determination circuit 112 receives the second error detection signal SED output from the detection system element 11D. Based on the second error detection signal SED, the detection system determination circuit 112 determines whether or not the detection system element 11D has detected an error. If the detection system determination circuit 112 determines that the detection system element 11D has detected an error, it notifies the MCU 200 of the detection of an error using the error signal ERRB. The error signal ERRB is pulled up. For example, the error signal ERRB is high when there is no error and low when an error is detected. However, the levels of the interrupt signal INTB and the error signal ERRB when an error is detected are not limited to those described above.

[0057] In order to improve the fault detection rate mentioned above, the control circuit 11 is equipped with a self-diagnostic function called ABIST, which diagnoses whether or not the elements that detect malfunctions, such as the protection element 11P and the detection element 11D, are operating correctly.

[0058] Here, the ABIST diagnostic circuit 113 of the control circuit 11 will be described. The ABIST diagnostic circuit 113 is configured to output an ABIST enable signal ABEN to the protection element 11P and the detection element 11D. The ABIST enable signal ABEN is low level when ABIST is not performed and high level when ABIST is performed.

[0059] Furthermore, the ABIST diagnostic circuit 113 generates pseudo-error signals SVP and SVD, which include errors that can be detected in advance by the protection element 11P and detection element 11D of the driver circuits 131 and 132, and has a configuration that allows it to output to the protection element 11P and the detection element 11D, respectively.

[0060] The ABIST diagnostic circuit 113 receives the first error detection signal SEP, which is the output of the protection element 11P, and the second error detection signal SED, which is the output of the detection element 11D. Based on the first error detection signal SEP and the second error detection signal SED, the ABIST diagnostic circuit 113 diagnoses whether or not there is a malfunction in the protection element 11P and the detection element 11D.

[0061] The ABIST diagnostic circuit 113 then notifies the MCU 200 via the data signal SDA that ABIST has been performed. Furthermore, the ABIST diagnostic circuit 113 also notifies the MCU 200 via the data signal SDA of the diagnostic results of the protection element 11P and the detection element performed by ABIST.

[0062] The ABIST diagnostic circuit 113 may have signal lines connected to transmit the ABIST enable signal ABEN, the pseudo-error signals SVP and SVD individually to the driver circuit 131 and the driver circuit 132, respectively, or it may be configured to switch between signal lines to output each signal to either the driver circuit 131 or 132. Similarly, the signal lines to which the first error detection signal SEP and the second error detection signal SED are input may be configured to be receivable from either the driver circuit 131 or 132, respectively, or they may be configured to be receivable by switching between them.

[0063] The ABIST diagnostic circuit 113 performs diagnostics on the protection element 11P and the detection element 11D when performing ABIST, but is not limited to this. For example, only one of them may be performed in a single ABIST.

[0064] In conventional semiconductor devices, ABIST was performed immediately before the power supply unit 100 system itself started up. However, there is a growing demand for power supply units 100 to perform ABIST (referred to as ABIST on demand) while the semiconductor device 10 is in continuous operation, for example, while the power supply unit 100 is operating (hereinafter referred to as the on-demand state).

[0065] When ABIST on demand is implemented, if the first error detection signal SEP and the second error detection signal SED, based on the inputs of the pseudo-error signals SVP and SVD, are input to the protection system determination circuit 111 and the detection system determination circuit 112, an incorrect interrupt signal INTB and an error signal ERRB will be output to the MCU 200. Therefore, the control circuit 11 is provided with a mask circuit 114 to prevent the first error detection signal SEP from being input to the protection system determination circuit 111 and the second error detection signal SED from being input to the detection system determination circuit 112 when ABIST is being implemented.

[0066] As shown in Figure 2, the mask circuit 114 has a circuit configuration that includes AND circuits 115 and 116. One input terminal of the AND circuit 115 is input to the inverted signal ABEN_INV (see Figures 4 to 7 described later), which is the inverted version of the ABIST enable signal ABEN. The inverted signal ABEN_INV of the ABIST enable signal ABEN is low level when the ABIST enable signal ABEN is high level, and high level when the ABIST enable signal ABEN is low level. The other input terminal of the AND circuit 115 is input to the first error detection signal SEP. The AND circuit 115 outputs the logical OR of the inverted signal ABEN_INV and the first error detection signal SEP. The output of the AND circuit 115 is input to the protection system determination circuit 111.

[0067] Furthermore, the inverted signal ABEN_INV of the ABIST enable signal ABEN is input to one input terminal of the AND circuit 116. The second error detection signal SED is input to the other input terminal of the AND circuit 116. The AND circuit 116 outputs the logical OR of the inverted signal ABEN of the ABIST enable signal ABEN and the first error detection signal SEP. The output of the AND circuit 115 is input to the detection system determination circuit 112.

[0068] When ABIST is performed, a high-level ABIST enable signal ABEN is output from the ABIST diagnostic circuit 113. The inverse signal of the ABIST enable signal ABEN, ABEN_INV, becomes low level, and the outputs of both AND circuits 115 and 116 become low level. Therefore, when ABIST is performed, low-level signals are input to the protection system determination circuit 111 and the detection system determination circuit 112. In other words, the first error detection signal SEP and the second error detection signal SED are masked for the protection system determination circuit 111 and the detection system determination circuit 112.

[0069] On the other hand, if ABIST is not performed, the inverted signal ABEN_INV of the high-level ABIST enable signal ABEN is input to one of the input terminals of AND gates 115 and 116. Therefore, AND gate 115 outputs an output signal with the same logic value as the first error detection signal SEP. AND gate 116 also outputs an output signal with the same logic value as the second error detection signal SED.

[0070] The power supply unit 100 has the configuration described above.

[0071] <ABISTオンデマンド> Next, the operation of the power supply unit 100 when on-demand ABIST is performed will be explained with reference to the drawings. Figure 4 is a diagram showing the signal states when there are no malfunctions in the protection element 11P and the detection element 11D during on-demand ABIST. Figure 5 is a diagram showing the signal states when there is a malfunction in the detection element 11D. Figure 6 is a diagram showing the signal states when there is a malfunction in the protection element 11P. Figure 7 is a diagram showing the signal states when there are malfunctions in both the detection element 11D and the protection element 11P. Figure 8 is a flowchart showing the processing of on-demand ABIST.

[0072] The semiconductor device 10 can perform ABIST on demand, which is carried out while the power supply 100 is outputting an output voltage. Here, the operating modes of the semiconductor device 10 are defined as follows: Normal operation is when the power supply 100 normally outputs an output voltage. ABIST operation is when the power supply 100 performs ABIST. Safe mode operation is when the power supply 100 switches to a safer mode, such as stopping the power supply 100 or reducing its output, based on ABIST (see Figures 4 to 7).

[0073] In ABIST on-demand mode, even when ABIST operation is performed, the power supply unit 100 operates to output the same output voltage and output current as in normal operation.

[0074] As shown in Figure 8, when switching from normal operation to ABIST operation, the ABIST enable signal ABEN output from the ABIST diagnostic circuit 113 switches to a high level (step S101). The ABIST enable signal ABEN is maintained at a high level throughout the ABIST operation period. The ABIST enable signal ABEN is input to the detection element 11D and the protection element 11P. During ABIST operation, the detection element 11D and the protection element 11P are configured to mask the voltages, signals, etc. that are input to them during normal operation. In other words, during ABIST operation, error detection by the detection element 11D and the protection element 11P as it is during normal operation is not performed.

[0075] Furthermore, the AND gates 115 and 116 of the mask circuit 114 are input to the inverted signal ABEN_INV of the ABIST enable signal ABEN. In other words, a low level of ABEN_INV is input to AND gates 115 and 116. Therefore, the outputs of AND gates 115 and 116 are low level regardless of the levels of the first error detection signal SEP and the second error detection signal SED (see Figures 4 to 7). In other words, the input of the first error detection signal SEP from the protection element 11P to the protection system determination circuit 111 is masked. Similarly, the input of the second error detection signal SED from the detection element 11D to the detection system determination circuit 112 is masked.

[0076] In this state, the ABIST diagnostic circuit 113 outputs a pseudo-error signal SVD to the detection element 11D (step S102; see Figures 4 to 7). The detection element 11D outputs a second error detection signal SED, and the second error detection signal SED is input to the ABIST diagnostic circuit 113 (see Figure 2). The ABIST diagnostic circuit 113 diagnoses whether or not there is a malfunction in the detection element 11D based on the level of the second error detection signal SED. When the pseudo-error signal SVD is input, the detection element 11D outputs a high level second error detection signal SED. Therefore, the ABIST diagnostic circuit 113 checks whether or not the second error detection signal SED has switched to a high level (step S103).

[0077] When it is confirmed that the second error detection signal SED has switched to a high level (when the answer is Yes in step S103), the ABIST diagnostic circuit 113 determines that there is no malfunction in the detection element 11D and notifies the MCU 200 (step S104: see Figure 4).

[0078] Furthermore, if the ABIST diagnostic circuit 113 does not confirm that the second error detection signal SED has reached a high level (the answer is No in step S103), the ABIST diagnostic circuit 113 cannot determine whether there is a malfunction in the detection element 11D or whether it is simply the delay time until the second error detection signal SED switches to a high level. Therefore, if the ABIST diagnostic circuit 113 does not confirm that the second error detection signal SED has reached a high level (the answer is No in step S103), the ABIST diagnostic circuit 113 checks whether a certain time t1 has elapsed since outputting the pseudo-error signal SVD (step S105: see Figure 5).

[0079] If a certain time t1 has not elapsed since the output of the pseudo-error signal SVD (when the answer is No in step S105), the process returns to step S103 and continues. Also, if a certain time t1 has elapsed since the output of the pseudo-error signal SVD (when the answer is Yes in step S105), the ABIST diagnostic circuit 113 determines that there is a malfunction in the detection element 11D and notifies the MCU 200 (step S106).

[0080] In this way, the ABIST diagnostic circuit 113 performs a diagnosis of malfunction of the detection element 11D in ABIST and transmits the result. As described above, the detection element 11D is an element for detecting errors in signals or voltages supplied to elements with a low risk. Therefore, if the MCU 200 receives notification that there is a malfunction in the detection element 11D, it performs an operation to notify an external party that such notification has been received.

[0081] Furthermore, after notifying in step S104 that there is no malfunction of the detection element 11D, or after notifying in step S106 that there is a malfunction of the detection element 11D, the process transitions to ABIST of the protection element 11P. That is, the ABIST diagnostic circuit 113 outputs a pseudo-error signal SVP to the protection element 11P (step S107).

[0082] The ABIST diagnostic circuit 113 diagnoses whether there is a malfunction in the protection element 11P based on the level of the first error detection signal SEP. When a pseudo-error signal SVP is input, the protection element 11P outputs a high level of the first error detection signal SEP. Therefore, the ABIST diagnostic circuit 113 checks whether the first error detection signal SEP has switched to a high level (step S108).

[0083] When it is confirmed that the first error detection signal SEP has switched to a high level (Yes in step S108), the ABIST diagnostic circuit 113 determines that there is no malfunction in the protection element 11P and notifies the MCU 200 (step S109). Then, the ABIST diagnostic circuit 113 switches the ABIST enable signal ABEN to a low level (step S110). As a result, the operating mode switches from ABIST operation to normal operation (step S111: see Figures 4 and 5).

[0084] Furthermore, if the ABIST diagnostic circuit 113 does not confirm that the first error detection signal SEP has reached a high level (the answer is No in step S108), the ABIST diagnostic circuit 113 cannot determine whether there is a malfunction in the protection element 11P or whether it is a delay time until the first error detection signal SEP switches to a high level. Therefore, if the ABIST diagnostic circuit 113 does not confirm that the first error detection signal SEP has reached a high level (the answer is No in step S108), the ABIST diagnostic circuit 113 checks whether a certain time t2 has elapsed since outputting the pseudo-error signal SVP (step S112).

[0085] If a certain time t2 has not elapsed since the output of the pseudo-error signal SVP (when the answer is No in step S112), the process returns to step S108 and continues. Also, if a certain time t2 has elapsed since the output of the pseudo-error signal SVP (when the answer is Yes in step S112), the ABIST diagnostic circuit 113 determines that there is a malfunction in the protection element 11P and notifies the MCU 200 (step S113: Figures 6 and 7). Then, the ABIST diagnostic circuit 113 switches the ABIST enable signal ABEN to a low level (step S114).

[0086] The MCU200 changes the standby signal STBY, enable signal EN, and data signal SDA output to the control circuit 11 of the semiconductor device 10, and switches the operating mode of the power supply unit 100 from ABIST operation to safe mode operation (step S111: see Figures 6 and 7).

[0087] The ABIST diagnostic circuit 113 performs a diagnosis of malfunction of the protection element 11P in ABIST and transmits the result. As described above, the protection element 11P is an element for detecting errors in the signal or voltage supplied to high-risk elements. Therefore, if the MCU 200 receives notification of a malfunction of the protection element 11P, it switches to safe mode operation by reducing or stopping the output voltage and output current output from the power supply unit 100, thereby reducing the risk to the vehicle.

[0088] According to the semiconductor device 10, ABIST can be performed during operation as ABIST on demand, and the fault detection rate by the protection element 11P and the detection element 11D can be compensated.

[0089] Furthermore, when ABIST is performed at system startup, the ABIST enable signal ABEN may not be output. Instead, the first error detection signal SEP in ABIST may be input to the protection system determination circuit 111, and the second error detection signal SED may be input to the detection system determination circuit 112, thereby performing a diagnosis of the detection function by the protection system determination circuit 111 and the detection system determination circuit 112. Also, in the above example, the detection system element 11D is diagnosed first, followed by the protection system element 11P, but the order may be reversed. Alternatively, one or the other may be performed in a single ABIST.

[0090] <Variation> The modified power supply unit 100A will be described with reference to the drawings. Figure 9 shows the configuration of the modified power supply unit 100A. The power supply unit 100A shown in Figure 9 differs from the semiconductor device 10 in that the semiconductor device 10A has NMOS transistors 161 and 162 instead of the bridge circuits 141 and 142 that the semiconductor device 10 had. The other parts of the semiconductor device 10A have substantially the same configuration as the semiconductor device 10, and the same reference numerals are used for substantially the same parts, and detailed explanations are omitted.

[0091] As shown in Figure 9, the semiconductor device 10A has NMOS transistors 161 and 162. The drain of NMOS transistor 161 is connected to the input voltage VIN. The source voltage of NMOS transistor 161 is the output voltage VOUT1. The gate signal SG1 from the driver circuit 131 is input to the gate of NMOS transistor 161. The on-resistance of NMOS transistor 161 is controlled by the gate signal SG1. Then, the output voltage VOUT1, which is the voltage drop from the input voltage VIN due to the on-resistance of NMOS transistor 161, is output to the outside.

[0092] The control circuit 11 receives a feedback voltage FBL1 corresponding to the output voltage VOUT1. The control circuit 11 determines the voltage value of the output voltage VOUT1 from the feedback voltage FBL1. Then, the control circuit 11 controls the driver circuit 131 so that the output voltage value determined from the feedback voltage FBL1 becomes a predetermined voltage value.

[0093] Furthermore, the NMOS transistor 162 is connected to the driver circuit 132. In other words, the on-resistance is adjusted by the gate signal SG2 supplied from the driver circuit 132, and the output voltage VOUT2, which is the voltage drop across the on-resistance from the input voltage VIN, is output to the outside.

[0094] The control circuit 11 receives a feedback voltage FBL2 corresponding to the output voltage VOUT2. The control circuit 11 determines the voltage value of the output voltage VOUT2 from the feedback voltage FBL2. Then, the control circuit 11 controls the driver circuit 132 so that the output voltage value determined from the feedback voltage FBL2 becomes a predetermined voltage value.

[0095] Power supply unit 100A is a power supply unit equipped with a so-called linear regulator that generates output voltages VOUT1 and VOUT2 by utilizing the voltage drop due to the on-resistance of NMOS transistors 161 and 162. Like power supply unit 100, ABIST on-demand can be implemented with power supply unit 100A.

[0096] In this modified example, both output stages of the two channels are linear regulators, but this is not limited to this configuration; the other channel may be a switching regulator equipped with a bridge circuit. Furthermore, an output unit 20 equipped with a bridge circuit may be connected to the configuration of the semiconductor device 10A in this modified example, and the output unit 20 may be operated. In this case, the linear regulator of the channel to which the output unit 20 is connected may be stopped.

[0097] <Usage> Figure 10 shows an example configuration of a vehicle 300 including a power supply unit 100. The vehicle 300 includes a power supply unit 100, an MCU 200, a battery 400, a motor unit 500, and an automatic braking system 600. The motor unit 500 includes a motor 51 and a motor drive unit 52. The motor drive unit 52 is configured to adjust the voltage and current supplied from the battery 400 and supply them to the motor 51. The voltage and current required to operate the motor drive unit 52 are supplied from the power supply unit 100.

[0098] The automatic braking system 600 is a device that controls the brakes (not shown) installed on the vehicle 300. It performs the action of applying a predetermined brake when a wheel (not shown) slips, and the action of automatically applying the brakes when the vehicle 300 approaches an obstacle abnormally close. The automatic braking system 600 is supplied with voltage and current from the power supply unit 100, and operates using this voltage and current.

[0099] The power supply unit 100 is configured to output an output voltage of an appropriate voltage value and an output current of an appropriate current value to the motor unit 500 and the automatic braking system 600, respectively, based on the voltage supplied from the battery 400. For example, the motor unit 500 is supplied with an output voltage VOUT1 and an output current IOUT1 from the output unit 20 shown in Figure 1, and the automatic braking system 600 is supplied with an output voltage VOUT2 and an output current IOUT2 ​​from the bridge circuit 142.

[0100] In vehicle 300, the motor unit 500 is an element belonging to ASIL_C, and the automatic braking system 600 is an element belonging to ASIL_D. In the power supply unit 100, by having the protection element 11P detect voltage errors supplied to these elements, a safe mode operation can be established that supplies voltage to safely stop vehicle 300 when a voltage error occurs in the voltage supplied to these elements. Furthermore, by implementing ABIST on demand, the probability of detecting supply voltage errors is increased, and it is suppressed that vehicle 300 will be in a critical situation due to supply voltage errors.

[0101] In the above explanation, an automotive IC was used as an example of the semiconductor device 10, but it is not limited to this. For example, it can be widely used in devices and equipment such as industrial equipment, ships, and aircraft that require high-probability detection of signal or voltage errors.

[0102] <Other> The embodiments described above should be considered in all respects to be illustrative and not restrictive. Furthermore, the technical scope of this disclosure is indicated by the claims, not by the description of the embodiments above. Moreover, it should be understood that all modifications falling within the meaning and scope of equivalence to the claims are included.

[0103] <Note> The semiconductor device (10) described above includes analog circuits (131, 132) and A control circuit (11) configured to control analog circuits (131, 132), An error detection unit (11P, 11D) is located in the control circuit (11) and is configured to detect errors and output error detection signals (SEP, SED), A determination circuit (111, 112) configured to determine whether or not an error has occurred based on error detection signals (SEP, SED), It has a diagnostic circuit (113) configured to diagnose the goodness or badness of the error detection unit (11P, 11D) based on error detection signals (SEP, SED), The diagnostic circuit (113) can perform on-demand diagnostics (ABIST on demand) by operating the error detection unit (11P, 11D) while the analog circuits (131, 132) are operating. This configuration (first configuration) includes a mask circuit (114) that masks the input of error detection signals (SEP, SED) to the judgment circuits (111, 112) when performing in-operation diagnostics (ABIST on demand).

[0104] In the semiconductor device (10) of the first configuration described above, the control circuit (11) may be configured to output a notification signal (SDA) to the outside, which includes the result of the diagnosis by the diagnostic circuit (113) (second configuration).

[0105] In the semiconductor device (10) with the second configuration described above, the error detection units (11P, 11D) are ranked according to the severity of the signal or voltage error. The control circuit (11) may also be configured to output different notification signals (SDA) to the outside depending on the rank of the error detection unit (11P, 11D) (third configuration).

[0106] In a semiconductor device (10) having any of the first to third configurations described above, at least a part of the error detection unit (11P) may be configured to detect errors in the output voltages (VOUT1, VOUT2) of analog circuits (131, 132) and output the result as an error detection signal (SEP) (fourth configuration).

[0107] In a semiconductor device (10) having any of the first to fourth configurations described above, at least a part of the error detection unit (11D) may be configured to detect an error in the internal voltage (VREG) supplied to the analog circuits (131, 132) and output the result as an error detection signal (SDA) (fifth configuration).

[0108] The power supply unit (100) described above is A semiconductor device (10) having any of the above configurations 1 to 5, The configuration may also include a switching output section (141, 142, 20) operated by analog circuits (131, 132) (sixth configuration).

[0109] The power supply unit (100A) described above is A semiconductor device (100A) having any of the above configurations 1 to 5, This configuration (the seventh configuration) includes linear output sections (151, 152) operated by the aforementioned analog circuits (131, 132).

[0110] The vehicle (300) described above is A configuration having a power supply unit (100, 100A) according to the sixth or seventh configuration described above (the eighth configuration) is also possible. [Explanation of Symbols]

[0111] 100 Power supply 10 Semiconductor Devices 11 Control circuits 11D detection system elements 11P protection element 111 Protection system judgment circuit 112 Detection System Judgment Circuit 113 ABIST diagnostic circuit 114 Mask Circuit 115, 116 AND circuits 12 Internal Voltage Generation Circuit 131, 132 Driver Circuits 141, 142 Bridge Circuit 20 Output section 21 Drive unit 22 Bridge Circuits 200 MCU 300 vehicles 400 batteries 500 Motor Device 51 Motor 52 Motor drive unit 600 Automatic Braking System M1, N1 High-Side Switching Element M2, N2 Low-Side Switching Elements C1, C2 Capacitors L1, L2 Inductors IOUT1, IOUT2 ​​Output Current VIN Input Voltage VOUT1, VOUT2 Output Voltages VREG Internal Voltage VSW1, VSW2 Switch Voltage ABEN ABIST enable signal EN Enable signal ERRB Error Signal FB1P, FB1N, FB2P, FB2N feedback signals HG High-Side Drive Signal LG Low-Side Drive Signal INTB interrupt signal PRSTB reset signal SCL clock signal SDA Data Signal SED 2nd Error Detection Signal SEP (Sectional Error Detection) 1st Error Detection Signal STby Standby Signal SVP, SVD pseudo-error signals Spwm1, Spwm2 drive signals

Claims

1. Analog circuits and, A control circuit configured to control the aforementioned analog circuit, An error detection unit is arranged in the control circuit and is configured to detect a signal or voltage error and output an error detection signal. A determination circuit configured to determine whether or not the error has occurred based on the error detection signal, It includes a diagnostic circuit configured to diagnose the quality of the error detection unit based on the error detection signal, The diagnostic circuit is capable of performing in-operation diagnostics by operating the error detection unit while the analog circuit is running. A semiconductor device having a mask circuit that masks the input of the error detection signal to the determination circuit when the aforementioned in-operation diagnosis is being performed.

2. The semiconductor device according to claim 1, wherein the control circuit is configured to output a notification signal to the outside, which includes the result of the diagnosis by the diagnostic circuit.

3. The error detection unit is ranked according to the severity of the signal or voltage error. The semiconductor device according to claim 2, wherein the control circuit is configured to output different notification signals to the outside depending on the rank of the error detection unit.

4. The semiconductor device according to claim 3, wherein at least a part of the error detection unit is configured to detect an error in the output voltage of the analog circuit and output the result as the error detection signal.

5. The semiconductor device according to claim 3, wherein at least a part of the error detection unit detects an error in the internal voltage supplied to the analog circuit and outputs the result as the error detection signal.

6. A semiconductor device according to any one of claims 1 to 5, A power supply device having a switching output section operated by the aforementioned analog circuit.

7. A semiconductor device according to any one of claims 1 to 5, A power supply device having a linear output section operated by the aforementioned analog circuit.

8. A vehicle having the power supply device described in claim 6.

9. A vehicle having the power supply device described in claim 7.

Images