Semiconductor memory

Abstract

Efficiently routing bit lines. [Solution] In the semiconductor memory device of the embodiment, the second bit line has a second inter-cell module wiring that is electrically connected to the second memory cell and extends in a first direction toward the sense amplifier module from a position that overlaps the second memory cell in the vertical direction, and a second internal module wiring that extends in a second direction parallel to the first internal module wiring at a position close to the first internal module wiring and electrically connects the second inter-cell module wiring and the second sense amplifier unit.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor memory devices.

Background Art

[0002] A semiconductor memory device has, for example, a plurality of sense amplifier units that respectively read data of a plurality of memory cells. In order to electrically connect individual memory cells to corresponding sense amplifier units, the wiring structure of bit lines has become complicated.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor memory device capable of efficiently wiring bit lines.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises a memory cell array including a plurality of memory cells, a sense amplifier module including a plurality of sense amplifier units positioned to overlap the memory cell array in the vertical direction and arranged in a first direction intersecting the vertical direction, wherein the width in the first direction is narrower than that of the memory cell array, a plurality of bit lines connecting corresponding sense amplifier units among the plurality of sense amplifier units and the plurality of memory cells, wherein the plurality of bit lines include a first bit line connecting a first memory cell among the plurality of memory cells and a first sense amplifier unit corresponding to the first memory cell, and a second bit line connecting a second memory cell among the plurality of memory cells and a second sense amplifier unit corresponding to the second memory cell, wherein the first bit line is electrically connected to the first memory cell and the first memory cell The second bit line has a first inter-cell module wiring extending in the first direction toward the sense amplifier module from a position where the two cells overlap in the vertical direction, and a first in-module wiring extending in a second direction intersecting the first direction and the vertical direction, connecting the first inter-cell module wiring and the first sense amplifier unit, wherein the second bit line is electrically connected to the second memory cell and has a second inter-cell module wiring extending in the first direction toward the sense amplifier module from a position where the two memory cell overlaps in the vertical direction, and a second in-module wiring extending in the second direction parallel to the first in-module wiring at a position close to the first in-module wiring, connecting the second inter-cell module wiring and the second sense amplifier unit. [Brief explanation of the drawing]

[0006] [Figure 1] Block diagram of a semiconductor memory device according to an embodiment. [Figure 2] An equivalent circuit diagram showing an example of the configuration of a memory cell array in a semiconductor memory device according to an embodiment. [Figure 3]A circuit diagram showing an example of the configuration of a sense amplifier unit and latch circuit included in a semiconductor memory device according to an embodiment. [Figure 4] A circuit diagram showing an example of the configuration of a low decoder in a semiconductor memory device according to an embodiment. [Figure 5] A cross-sectional view showing an example of the configuration of a semiconductor memory device according to the embodiment. [Figure 6] A diagram showing an example of a wiring structure for electrically connecting the pillar and the sense amplifier unit according to the embodiment. [Figure 7] A schematic diagram showing an example of the configuration of shielded wiring placed near the internal wiring of a module according to the embodiment. [Figure 8] A schematic diagram showing another example of the configuration of shielded wiring placed near the module wiring according to the embodiment. [Figure 9] A layout diagram showing the connection relationship between the pillar and the sense amplifier unit in the comparative example. [Figure 10] A schematic diagram showing in three dimensions the connection relationship between the pillar and the sense amplifier unit according to the embodiment and comparative example. [Figure 11] This figure shows an example of a wiring structure for electrically connecting a pillar and a sense amplifier unit in a semiconductor memory device according to a modified embodiment 1. [Figure 12] This figure shows an example of a wiring structure for electrically connecting a pillar and a sense amplifier unit in a semiconductor memory device according to a modified example of the embodiment 2. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially the same.

[0008] [Circuit configuration of semiconductor memory devices] First, an example of the circuit configuration of the semiconductor memory device 1 of the embodiment will be explained using Figures 1 to 4.

[0009] (Overall configuration of semiconductor memory device) Figure 1 is a block diagram of a semiconductor memory device 1 according to an embodiment. As shown in Figure 1, the semiconductor memory device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0010] The input / output circuit 310 controls the input and output of signal DQ to an external device, such as a memory controller (not shown), which controls the semiconductor memory device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0011] The input circuit sends data DAT, such as the write data WDT, received from an external device to the data register 540, sends address ADD to the address register 340, and sends command CMD to the command register 350.

[0012] The output circuit transmits status information STS received from status register 330, data DAT such as read data RDT received from data register 540, and address ADD received from address register 340 to an external device.

[0013] The logic control circuit 320 receives signals from an external device, such as the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn. The logic control circuit 320 also controls the input / output circuit 310 and the sequencer 360 according to the received signals.

[0014] The status register 330 temporarily holds status information STS for, for example, data write, read, and erase operations, and notifies an external device whether the operation has been completed successfully.

[0015] The address register 340 temporarily holds the address ADD received from an external device via the input / output circuit 310. The address register 340 also transfers the row address RA to the row decoder 520 and the column address CA to the column decoder 550.

[0016] The command register 350 temporarily stores the command CMD received from an external device via the input / output circuit 310 and transfers it to the sequencer 360.

[0017] The sequencer 360 controls the operation of the entire semiconductor memory device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550, etc., in response to the command CMD held in the command register 350, and performs write operations, read operations, erase operations, etc.

[0018] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device depending on the operating status of the sequencer 360.

[0019] The voltage generation circuit 380 generates the voltages necessary for write, read, and erase operations in response to the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltage supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0020] The memory cell array 510 includes multiple blocks BLK (BLK0 to BLKn), where n is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cells associated with bit lines and word lines, and serves, for example, as a data erasure unit. The memory cells are configured, for example, as transistors, and hold non-volatile data.

[0021] By incorporating such memory cells, the semiconductor memory device 1 is configured as, for example, a NAND-type non-volatile memory.

[0022] The row decoder 520 decodes the row address RA. Based on the decoding result, the row decoder 520 selects one of the blocks BLK. The row decoder 520 also applies the required voltage to the block BLK.

[0023] During a read operation, the sense amplifier module 530 senses the data read from the memory cell array 510. The sense amplifier module 530 also transmits the read data RDT to the data register 540. During a write operation, the sense amplifier module 530 transmits the write data WDT to the memory cell array 510.

[0024] The data register 540 includes multiple latch circuits. The latch circuits hold the write data WDT and the read data RDT. For example, during a write operation, the data register 540 temporarily holds the write data WDT received from the input / output circuit 310 and transmits it to the sense amplifier module 530. Similarly, during a read operation, the data register 540 temporarily holds the read data RDT received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0025] The column decoder 550 decodes the column address CA during operations such as write, read, and erase, and selects a latch circuit in the data register 540 according to the decoding result.

[0026] The group of circuits arranged around the memory cell array 510 is also called the peripheral circuit. The peripheral circuit includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuit may also include a status register 330, an address register 340, a command register 350, and a sequencer 360, and may further include an input / output circuit 310, a logic control circuit 320, a ready / busy circuit 370, and a voltage generation circuit 380.

[0027] Thus, the semiconductor memory device 1 comprises a memory cell array 510 containing multiple memory cells and peripheral circuits for operating the multiple memory cells.

[0028] (Circuit configuration of a memory cell array) Figure 2 is an equivalent circuit diagram showing an example of the configuration of a memory cell array 510 provided in the semiconductor memory device 1 according to the embodiment.

[0029] The memory cell array 510 comprises multiple block BLKs as described above. Each of the multiple block BLKs comprises multiple string units SUs. Each of the multiple string units SUs comprises multiple memory strings MSs. One end of each of the multiple memory strings MSs is connected to peripheral circuits such as the sense amplifier module 530 via a bit line BL. The other end of each of the multiple memory strings MSs is connected to peripheral circuits via a common source line SL.

[0030] A memory string MS comprises a drain selection transistor STD connected in series between the bit line BL and the source line SL, a plurality of memory cells MC, and a source selection transistor STS. Hereinafter, the drain selection transistor STD and the source selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0031] A memory cell MC is, for example, a field-effect transistor (FET) that includes a charge storage layer in its gate insulating layer. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage layer. By providing one or more threshold voltages, the memory cell MC may be able to store one bit or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to a single memory string MS. These word lines WL are each connected in common to all memory string MS in a single block BLK.

[0032] The selection transistors (STD, STS) are, for example, field-effect transistors. A selection gate line (SGD, SGS) is connected to the gate electrode of each selection transistor (STD, STS). The drain selection line SGD, connected to the drain selection transistor STD, is provided corresponding to a string unit SU and is commonly connected to all memory strings MS within a single string unit SU. The source selection line SGS, connected to the source selection transistor STS, is commonly connected to all memory strings MS within a single block BLK.

[0033] One end of the word line WL and the selection gate lines (SGD, SGS) are connected to peripheral circuits such as the low decoder 520.

[0034] (Circuit configuration of the sense amplifier module) Figure 3 is a circuit diagram showing an example of the configuration of the sense amplifier unit SA and latch circuits DL and XDL included in the semiconductor memory device 1 according to the embodiment.

[0035] The sense amplifier module 530 described above consists of multiple sense amplifier units SA provided for each bit line BL. Each sense amplifier unit SA senses the data read to the corresponding bit line BL, for example, during a read operation, and determines whether the read data is "0" or "1".

[0036] The above-described data register 540 also includes a plurality of latch circuits DL and XDL respectively corresponding to the plurality of sense amplifier units SA. The latch circuit XDL is also provided for each bit line BL. On the other hand, a plurality of latch circuits DL are provided for the corresponding sense amplifier unit SA. In this case, the number of latch circuits DL is designed based on, for example, the number of bits of data that can be held by one memory cell MC. The latch circuits DL and XDL temporarily hold data related to the corresponding bit line BL.

[0037] FIG. 3 shows one sense amplifier unit SA in the sense amplifier module 530 and one latch circuit DL or XDL in the data register 540. A plurality of control signals supplied to the sense amplifier unit SA and the like are controlled by the sequencer 360.

[0038] As shown in FIG. 3, the sense amplifier unit SA includes transistors TR 31 ~TR 38 , and a capacitor CAP. In the figure, the transistor TR 31 is a low-voltage P-channel MOS (Metal-Oxide-Semiconductor) transistor. Also, the transistors TR 32 ~TR 38 are low-voltage N-channel MOS transistors.

[0039] Low-voltage CMOS transistors including low-voltage P-channel MOS transistors and low-voltage N-channel MOS transistors are transistors to which a relatively low voltage is applied, and are also called low-voltage (LV: Low Voltage, VLV: Very Low Voltage) MOS transistors.

[0040] One end of the transistor TR 31 is connected to a power supply line to which the power supply voltage Vdd is supplied, and the gate electrode of the transistor TR 31 is connected to the node INV. One end of the transistor TR 32 is connected to the transistor TR 31It is connected to the other end of the transistor TR 32 The other end is connected to node COM, and transistor TR 32 The control signal BLX is input to the gate electrode of the transistor TR. 33 One end is connected to node COM, and transistor TR 33 The other end is connected to the corresponding bit line BL, and the transistor TR 33 The control signal BLC is input to the gate electrode.

[0041] Transistor (TR) 34 One end is connected to node COM, and transistor TR 34 The other end is connected to node SRC, and transistor TR 34 The gate electrode is connected to node INV.

[0042] Transistor (TR) 35 One end is a transistor TR 31 It is connected to the other end of the transistor TR 35 The other end is connected to node SEN, and transistor TR 35 The gate electrode of the transistor TR receives the control signal HLL. 36 One end is connected to node SEN, and transistor TR 36 The other end is connected to node COM, and transistor TR 36 The control signal XXL is input to the gate electrode.

[0043] Transistor (TR) 37 A clock signal CLK is input to one end of the transistor TR 37 The gate electrode of the transistor TR is connected to node SEN. 38 One end is a transistor TR 37 It is connected to the other end of the transistor TR 38 The other end is connected to the bus LBUS, and the transistor TR 38 The gate electrode of the capacitor receives the control signal STB. One end of capacitor CAP is connected to node SEN, and the other end of capacitor CAP receives the clock signal CLK.

[0044] The latch circuit DL consists of inverters IVa and IVb, and transistor TR. 41 ,TR 42 It is equipped with a transistor TR. 41 ,TR 42 This is a low-voltage N-channel MOS transistor. The following describes the transistor TR included in data register 540. 41 ,TR 42 These are sometimes simply called transistors (TR).

[0045] Although Figure 3 shows one latch circuit DL, other latch circuits DL have a similar configuration.

[0046] Inverter IVa has its input terminal connected to node LAT and its output terminal connected to node INV. Inverter IVb has its input terminal connected to node INV and its output terminal connected to node LAT.

[0047] Transistor (TR) 41 One end of the transistor is connected to node INV, and the other end is connected to bus LBUS. The gate electrode receives the control signal STI. 42 One end is connected to node LAT, the other end is connected to bus LBUS, and the control signal STL is input to the gate electrode.

[0048] The latch circuit XDL has a configuration substantially similar to that of, for example, the latch circuit DL, and is connected to the bus LBUS to enable data transmission and reception with the sense amplifier unit SA and the latch circuit DL. The latch circuit XDL is also connected to the input / output circuit 310 described above and is used for data input and output between the sense amplifier unit SA and the input / output circuit 310.

[0049] Furthermore, the latch circuit XDL is also used for the cache operation of the semiconductor memory device 1. In other words, even if all the latch circuits DL corresponding to the sense amplifier unit SA are in use, the semiconductor memory device 1 can still receive data from the outside as long as the latch circuit XDL is available.

[0050] Thus, the sense amplifier unit SA and latch circuits DL and XDL, which belong to the peripheral circuitry, are equipped with multiple transistors TR.

[0051] Next, we will briefly explain the operation of the sense amplifier unit SA with the above configuration.

[0052] As an example of writing data to a memory cell MC, when charge is injected into the memory cell MC to raise the threshold, the node INV of the latch circuit DL stores an "H" level ("1" data). This causes the transistor TR 34 When the switch is turned on, the bit line BL is set to 0V.

[0053] Another example of writing data to a memory cell MC is when the memory cell MC charge is not injected and the threshold is not changed, in which case the node INV of the latch circuit DL stores an "L" level ("0" data). This causes the transistor TR 31 The switch is turned on, and a predetermined positive voltage is applied to the bit line BL.

[0054] During readout, node INV is set to the "L" level, and transistor TR 31 The transistor TR is turned on. 41 ,TR 42 Through the bit line BL, the transistor TR 31 It is precharged by the transistor TR. 35 The device is also turned on, and node SEN is charged to the predetermined potential.

[0055] Subsequently, the transistor TR 35 When the transistor TR is turned off, the signal XXL is set to "H" level. 36 This is turned on. As a result, if the corresponding memory cell MC is turned on, the potential of node SEN decreases, and transistor TR 37 The transistor TR is turned off. On the other hand, if the corresponding memory cell MC is turned off, the potential of node SEN remains at the "H" level, and the transistor TR 37 It will be turned on.

[0056] Furthermore, the signal STB controls the transistor TR 38 When it is turned on, the transistor TR 37 The potential corresponding to the on / off state is read to the bus LBUS and held in the latch circuit DL.

[0057] Note that the circuit configuration of the sense amplifier unit SA and latch circuits DL and XDL shown in Figure 3 is just one example, and the sense amplifier unit SA and latch circuits DL and XDL can take various other configurations. Therefore, the number and type of transistors TR included in the sense amplifier unit SA and latch circuits DL and XDL can also vary. For example, the sense amplifier unit SA and latch circuits DL and XDL may be configured to include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors.

[0058] (Raw Decoder Circuit Configuration) Figure 4 is a circuit diagram showing an example of the configuration of a low decoder 520 provided in the semiconductor memory device 1 according to the embodiment.

[0059] As shown in Figure 4, the row decoder 520 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23.

[0060] The address decoder 21 includes multiple block selection lines BLKSEL and multiple voltage selection lines VOLSEL.

[0061] The address decoder 21, for example, refers to the address data of the address register 340 included in the peripheral circuit described above, according to a control signal from the sequencer 360.

[0062] Furthermore, the address decoder 21 decodes the referenced address data and determines the transistor TR corresponding to the address data. 22 and transistor TR 23 Turn on the other transistors TR 22 and transistor TR 23 Turn it off. Note that the transistor TR22 and transistor TR 23 These are transistors included in the block selection circuit 22 and the voltage selection circuit 23, respectively, which will be described later.

[0063] Furthermore, the address decoder 21 sets the voltage of the block selection line BLKSEL and the voltage selection line VOLSEL corresponding to the address data to a "H" state, for example, and sets all other voltages to a "L" state. Note that the voltages applied to these wires will be reversed depending on whether N-channel or P-channel transistors are used in the block selection circuit 22 and the voltage selection circuit 23. The voltages described above are examples when the transistor is an N-channel type.

[0064] In the example shown in Figure 4, the address decoder 21 is provided with one block selection line BLKSEL for each block BLK in the memory cell array 510. However, this configuration can be changed as appropriate. For example, it may be provided with one block selection line BLKSEL for each of two or more block BLKs.

[0065] The block selection circuit 22 comprises a plurality of block selection units 220, each corresponding to a block BLK of the memory cell array 510. Each of these plurality of block selection units 220 comprises a plurality of transistors TR, each corresponding to a word line WL and a selection gate line (SGD, SGS). 22 It is equipped with.

[0066] Transistor (TR) 22 This is a high-voltage N-channel MOS transistor that functions as a block drive transistor. 22 The drain electrodes of each transistor are electrically connected to the corresponding word line WL or select gate line (SGD, SGS). 22 The source electrodes are electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23, respectively. Transistor TR 22 The gate electrode is commonly connected to the corresponding block selection line BLKSEL.

[0067] Furthermore, the block selection circuit 22 further comprises several transistors (not shown). These transistors are high-voltage CMOS transistors connected between the selection gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors conduct the selection gate lines (SGD, SGS) included in the unselected block BLK in the memory cell array 510 to the ground voltage supply terminal. Note that the multiple word lines WL included in the unselected block BLK are in a floating state.

[0068] The voltage selection circuit 23 includes a plurality of voltage selection units 230 corresponding to the word line WL and the selection gate lines (SGD, SGS). Each of these plurality of voltage selection units 230 is comprised of a plurality of transistors TR 23 It is equipped with.

[0069] Transistor (TR) 23 This is a high-voltage N-channel MOS transistor that functions as a voltage-selective transistor. 23 The drain terminals are electrically connected to the corresponding word line WL or selection gate line (SGD, SGS) via wiring WR and block selection circuit 22, respectively. The source terminals are electrically connected to the corresponding voltage output terminal OTM, respectively. The gate electrodes are connected to the corresponding voltage selection line VOLSEL, respectively.

[0070] High-voltage CMOS transistors, including the high-voltage P-channel MOS transistors and high-voltage N-channel MOS transistors mentioned above, are transistors to which relatively high voltages are applied, and are also called high-voltage (HV) MOS transistors.

[0071] Thus, the low decoder 520, which belongs to the peripheral circuitry, consists of multiple transistors TR 22 ,TR 23 It includes the following. However, the circuit configuration of the low decoder 520 shown in Figure 4 is just one example, and the transistor TR included in the low decoder 520 22 ,TR 23The number and types of these items can also vary considerably.

[0072] [Physical configuration of semiconductor memory devices] Next, an example of the physical configuration of the semiconductor memory device 1 according to the embodiment will be described using Figure 5. Figure 5 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0073] More specifically, Figure 5(a) is a cross-sectional view of the semiconductor memory device 1 along the X direction. Note that hatching is omitted in Figure 5(a) for the sake of readability. Figures 5(b) and 5(c) are enlarged cross-sectional views of a part of the pillar PL of the semiconductor memory device 1, where Figure 5(b) shows a cross-section at the height of the selected gate lines SGD and SGS, and Figure 5(c) shows a cross-section at the height of the word line WL.

[0074] As shown in Figure 5(a), the semiconductor memory device 1 comprises, in order from the bottom of the paper, an electrode film EL, a source line SL, one or more selection gate lines SGS, multiple word lines WL, one or more selection gate lines SGD, and a semiconductor substrate SB on which peripheral circuits CBA are provided.

[0075] A source wire SL is placed on the electrode film EL via an insulating layer 60. Multiple plugs PG are arranged in the insulating layer 60, and electrical conductivity is maintained between the source wire SL and the electrode film EL via the plugs PG. Although not shown in the diagram, electrode pads for supplying power and signals to the semiconductor memory device 1 from the outside are provided in the same layer as the electrode film EL.

[0076] On the source line SL, a selection gate line SGS, multiple word lines WL, and a selection gate line SGD are stacked in this order to form a laminate LM. The multiple word lines WL and the selection gate lines SGD and SGS are, for example, tungsten layers or molybdenum layers.

[0077] A memory cell array MR is positioned in the center of the multiple word lines WL in the X direction, and step regions SR are positioned at both ends of the multiple word lines WL in the X direction. The memory cell array MR shown in Figure 5(a) is a physical configuration corresponding to the memory cell array 510 shown in Figure 1 and other figures above.

[0078] The laminate LM, which includes the memory cell array MR and the step region SR, is covered with an insulating layer 50. The insulating layer 50 also extends around the laminate LM.

[0079] These memory cell arrays MR and step regions SR are divided into multiple blocks BLK (see Figure 1, etc.) by multiple plate-like portions (not shown) that extend along the X direction, penetrating multiple word lines WL, etc.

[0080] Furthermore, between adjacent plate-like portions in the Y direction, multiple isolation layers (not shown) extend in the direction along the X direction, penetrating the selected gate line SGD. These multiple isolation layers extend in the direction along the X direction throughout the entire memory cell array MR, and also reach a portion of the stepped region SR at both ends in the X direction.

[0081] As a result, within a single block BLK, the selected gate line SGD is separated into multiple regions. In other words, the separation layer penetrates the portion of the laminate LM above the multiple word lines WL, thereby dividing these upper portions into patterns of multiple selected gate lines SGD.

[0082] The memory cell array MR has multiple pillars PL that penetrate the word line WL and the selection gate lines SGD and SGS in the stacking direction. The lower end of each pillar PL is connected to the source line SL, and the upper end of each pillar PL is connected to the bit line BL via a plug or the like.

[0083] As shown in Figures 5(b) and 5(c), the pillar PL comprises a memory layer ME and a channel layer CN, in that order from the outer periphery of the pillar PL. The memory layer MR has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in that order from the outer periphery of the pillar PL. A core layer CR is filled further inside the channel layer CN.

[0084] The block insulating layer BK, tunnel insulating layer TN, and core layer CR are, for example, silicon oxide layers. The charge storage layer CT is, for example, a silicon nitride layer. The channel layer is a semiconductor layer, for example, a polysilicon layer or a single-crystal silicon layer.

[0085] As shown in Figure 5(c), memory cells MC are formed in the portion of the pillar PL side facing each individual word line WL with the above configuration. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word line WL. Each word line WL is insulated from each other by an insulating layer OL, which is a silicon oxide layer or the like.

[0086] Thus, by forming memory cells MC at the intersections of pillars PL and multiple word lines WL, the semiconductor memory device 1 is configured as a three-dimensional non-volatile memory, for example, in a memory cell array MR where memory cells MC are arranged in three dimensions. Furthermore, these pillars PL, where memory cells MC are formed at the intersections of multiple word lines WL, have a physical configuration corresponding to the memory string MS (see Figure 2, etc.) described above.

[0087] As shown in Figure 5(b), a selection gate STD is formed on the side of pillar PL where it faces the selection gate line SGD which is above the word line WL. Also, a selection gate STS is formed on the side of pillar PL where it faces the selection gate line SGS which is below the word line WL.

[0088] By applying predetermined voltages to the selection gate lines SGD and SGS, respectively, the selection gates STD and STS are turned on or off, thereby selecting or deselecting the memory cell MC of the pillar PL to which the selection gates STD and STS belong. The selection gate lines SGD and SGS are also insulated by the insulating layer OL, which is located on both sides of the stacking direction of the stacked body LM.

[0089] The aforementioned bit line BL spans multiple block BLKs and extends above multiple pillars PL in the Y direction, which is perpendicular to the X direction, i.e., perpendicular to the plane of the paper. As a result, multiple pillars PL belonging to different block BLKs and aligned in the Y direction are connected to a single bit line BL.

[0090] The bit wire BL is connected to the wiring M1 on the upper layer of bit wire BL via plug V1. Wiring M1 is connected to a pad PDm located on the upper surface of the insulating layer 50 covering the laminate LM via plug V2.

[0091] In the stepped region SR, multiple word lines WL and selection gate lines SGD and SGS are processed and terminated in a stepped manner. As the distance from the memory cell array MR in the X direction increases, the multiple word lines WL and selection gate lines SGD and SGS that constitute the terrace portion move from the upper layer to the lower layer, causing the height of the terrace portion to decrease towards the source line SL.

[0092] Each terrace section of a layer, composed of multiple word lines WL and selection gate lines SGD and SGS, has contact CCs connected to the word lines WL and selection gate lines SGD and SGS of each layer.

[0093] These contact CCs allow individual stacked word lines WLs to be drawn out. More specifically, these contact CCs apply write voltages and read voltages to memory cells MCs included in the memory cell array MR at the center of multiple word lines WLs, via word lines WLs located at the same height as the memory cells MCs.

[0094] The upper end of each contact CC is connected to wiring MX via a plug or the like. Wiring MX is located on the same layer as the bit line BL described above. Wiring MX is also connected to wiring M1 on the layer above wiring MX via a corresponding plug V1. Wiring M1 is connected to pad PDm located on the upper surface of the insulating layer 50 via plug V2.

[0095] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA, including transistors TR and contacts CG, CS, etc., is arranged on the surface of the semiconductor substrate SB. As described above, the peripheral circuit CBA includes a sense amplifier unit SA and a raw decoder RD, etc., which are composed of multiple transistors TR in the peripheral circuit CBA. The raw decoder RD shown in Figure 5(a) has a physical configuration corresponding to the raw decoder 520 shown in Figure 1, etc.

[0096] The peripheral circuit CBA is covered with an insulating layer 40. Wires D0 to D4 are arranged in this order on the insulating layer 40, from the peripheral circuit CBA side toward the surface of the insulating layer 40. These wires D0 to D4 each belong to a different layer.

[0097] Wires D0 to D4 are connected to each other by plugs C1 to C4, which are placed between them. Of the wires D0 to D4, wire D4, which is located closest to the surface of the insulating layer 40, is connected to pad PDc, which is located on the surface of the insulating layer 40, via plug C5.

[0098] The insulating layer 40 covering the peripheral circuit CBA and the insulating layer 50 covering the laminate LM etc. are bonded to each other's surfaces, thereby connecting the pads PDm and PDc to each other. In addition, this electrically connects the peripheral circuit CBA to the configuration of multiple word lines WL, selection gate lines SGD, SGS, pillar PL, and contact CC etc.

[0099] The various voltages applied from the contact CC to the memory cell MC are controlled by the peripheral circuit CBA, which is electrically connected to these contact CCs. More specifically, the contact CCs are electrically connected to the row decoder RD and other components included in the peripheral circuit CBA, and the various voltages supplied from the row decoder RD electrically operate the memory cell MC.

[0100] Furthermore, the data from the memory cell MC is read out to the peripheral circuit CBA, which is electrically connected to the bit line BL. More specifically, the bit line BL is electrically connected to a sense amplifier unit SA included in the peripheral circuit CBA, and the sense amplifier unit SA reads out the data from the memory cell MC.

[0101] The low decoder RD of the peripheral circuit CBA is preferably positioned so as to overlap vertically with the stepped region SR of the laminate LM to which the contact CC is connected. Furthermore, the sense amplifier unit SA is preferably positioned so as to overlap vertically with the memory cell array MR of the laminate LM to which the pillar PL is located.

[0102] However, as described above, the row decoder RD is configured to include a block selection unit 220 and a voltage selection unit 230 (see Figure 4, etc.) for each individual word line WL. For this reason, on the semiconductor substrate SB, the row decoder RD occupies a larger area than the sense amplifier module 530, which includes multiple sense amplifier units SA, etc.

[0103] As a result, the low decoder RD is positioned on the semiconductor substrate SB not only in the region that overlaps vertically with the step region SR of the stacked structure LM, but also in a portion of the region that overlaps vertically with, for example, the memory cell array MR.

[0104] As a result, the sense amplifier module 530 is concentrated and positioned on the semiconductor substrate SB in the region that overlaps with the memory cell array MR in the vertical direction, and corresponds to the central part of the memory cell array MR in the X direction. In other words, the width in the X direction of the region occupied by the sense amplifier module 530 on the semiconductor substrate SB is narrower than the width in the X direction of the region occupied by the memory cell array MR in the stacked structure LM.

[0105] Furthermore, due to the above arrangement of the sense amplifier module 530, some of the pillars PL arranged in the memory cell array MR will be positioned so as not to overlap with the sense amplifier module 530 in the vertical direction.

[0106] Therefore, in the semiconductor memory device 1 of this embodiment, the upper wiring M1 of the bit line BL connected to the upper end of these pillars PL is extended in the X direction, for example, from the position where the bit line BL is located to a position below the corresponding sense amplifier unit SA, thereby electrically connecting these pillars PL and the corresponding sense amplifier unit SA.

[0107] [Wiring structure of semiconductor memory devices] Next, the connection relationship between the pillar PL and the sense amplifier unit SA of the embodiment will be explained using Figures 6 to 8.

[0108] Figure 6 shows an example of a wiring structure for electrically connecting the pillar PL and the sense amplifier unit SA according to the embodiment.

[0109] More specifically, Figure 6(a) is a layout diagram showing the connection relationship between the pillar PL and the sense amplifier unit SA, and shows the view from the memory cell array MR side towards the sense amplifier unit SA side, where the memory cell array MR and the sense amplifier unit SA are arranged in the vertical direction.

[0110] However, in Figure 6(a), for the sake of readability, the inter-cell module wiring CBL, which is located closer to the sense amplifier unit SA than the bit line BL, is shown on the near side of the page than the bit line BL.

[0111] Figure 6(b) is a schematic diagram showing the three-dimensional connection relationship between the pillar PL and the sense amplifier unit SA.

[0112] In this specification, both the X and Y directions are directions along the orientation of the surface of the word line WL, and the X and Y directions are orthogonal to each other. The electrical extraction direction of the word line WL may be referred to as the first direction, and this first direction is along the X direction. The direction intersecting the first direction may be referred to as the second direction, and this second direction is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing tolerances, the first direction and the second direction are not necessarily orthogonal.

[0113] As shown in Figure 6, the multiple sense amplifier units SA are arranged side by side in the X direction, each extending a predetermined distance along the Y direction. From an electrical control standpoint, these sense amplifier units SA are divided into multiple groups GR, with each group consisting of two or more adjacent sense amplifier units SA in the X direction.

[0114] As an example, one group GR includes four sense amplifier units SA, and Figure 6 shows the sense amplifier units SA. <00> ~SA <03> And, the Sense Amp Unit SA <10> ~SA <13> The two Group GR <0> ,GR <1> This is shown.

[0115] Furthermore, from an electrical control standpoint, multiple sense amplifier units SA are divided into multiple regions DIV in the Y direction. As an example, multiple sense amplifier units SA are divided into two regions DIV in the Y direction. <0> ,DIV <1> These regions are divided into DIV <0> ,DIV <1> Each of these is a sub-region DIVs <00> , <01> and subdomains DIVs <10> , <11> It is divided into two parts.

[0116] Multiple bit lines BL each extend along the Y direction and are arranged side by side in the X direction. Note that the left side of Figure 6 is the region where bit lines BL that do not overlap vertically with multiple sense amplifier units SA are arranged. Therefore, the sense amplifier units SA corresponding to these bit lines BL are positioned shifted to the right relative to these bit lines BL.

[0117] Furthermore, the right side of Figure 6 is a region where multiple sense amplifier units SA and bit lines BL are arranged to overlap vertically. However, these sense amplifier units SA shown in Figure 6 are located near the X-direction end within the sense amplifier module 530 described above, and the sense amplifier units SA corresponding to the bit lines BL that overlap vertically with these sense amplifier units SA are also positioned shifted to the right relative to these bit lines BL. Note that the sense amplifier units SA corresponding to these bit lines BL are not shown in Figure 6.

[0118] These bit lines BL and the sense amplifier unit SA, which is shifted to the right relative to them on the paper, are electrically connected by inter-cell module wiring CBL, which extends in the X direction from the position of the bit lines BL toward the sense amplifier unit SA.

[0119] More specifically, one end of the inter-cell module wiring CBL is connected to the bit line BL via plug V1, and the other end is connected to the in-module wiring DBL located in a predetermined area of ​​a plurality of sense amplifier units SA via plug V2, pads PDm, PDc, and plug C5.

[0120] Furthermore, to improve the reliability of the connection between the bit line BL and the inter-cell module wiring CBL, multiple plugs V1 may be interposed between them. For example, by ensuring that the connection portion CP between each inter-cell module wiring CBL and the corresponding bit line BL is made longer in the Y direction, the number of plugs V1 connecting them can be increased, thereby improving the reliability of the electrical connection.

[0121] Furthermore, the inter-cell module wiring CBL is a type of the aforementioned wiring M1. That is, among the wiring M1 that connects the bit line BL and the sense amplifier unit SA, or the aforementioned contact CC and the row decoder RD, the inter-cell module wiring CBL corresponds to the wiring M1 that connects the bit line BL and the sense amplifier unit SA.

[0122] Furthermore, the module-internal wiring DBL is a type of the aforementioned wiring D4. That is, among the wiring D4 that connects the bit line BL and the sense amplifier unit SA, or the aforementioned contact CC and the row decoder RD, the module-internal wiring DBL corresponds to the wiring D4 that connects the bit line BL and the sense amplifier unit SA.

[0123] In the example in Figure 6, four in-module wiring DBLs are located within one group GR containing four sense amplifier units SA. Of these, two in-module wiring DBLs <0> ,DBL <1> These are two sub-regions (DIVs) adjacent to each other in the X direction. <00> , <01> spanning, domain DIV <0> It extends in the Y direction inside. Also, there are two module-internal wiring DBLs. <2> ,DBL <3> These are two sub-regions (DIVs) adjacent to each other in the X direction. <10> , <11> spanning, domain DIV <1> It extends in the Y direction.

[0124] In other words, the multiple regions DIV that divide the sense amplifier unit SA in the Y direction are assigned within a single group GR, according to the extension position and extension distance of each in-module wiring DBL that is arranged side by side in the Y direction.

[0125] Two subregions (DIVs) <00> , <01> Among the intra-module wiring DBLs that are arranged across multiple modules, one intra-module wiring DBL is connected to the corresponding inter-cell module wiring CBL and sub-region DIVs. <00> Connected within, subregions DIVs <00> Wiring D3 located inside <0> It is connected via plug C4. Wiring D3 <0> That is the wiring D3 <0> It is connected to the sense amplifier unit SA directly below via wiring D0-D2 and plugs C1-C3.

[0126] Two subregions (DIVs) <00> , <01> Of the intermodule wiring DBLs that span across the module, another intermodule wiring DBL is the corresponding inter-cell module wiring CBL and sub-region DIVs. <00> Connected within, subregions DIVs <01> Wiring D3 located inside <1> It is connected via plug C4. Wiring D3 <1> It extends in the direction along the X direction, wiring D3 <0> The sense amplifier unit SA to which the sense amplifier unit SA adjacent to the X-direction is connected, and the sub-regions DIVs via wiring D0~D2 and plugs C1~C3. <01> They are connected internally.

[0127] Two subregions (DIVs) <10> , <11> Among the intra-module wiring DBLs that are arranged across multiple modules, one intra-module wiring DBL is connected to the corresponding inter-cell module wiring CBL and sub-region DIVs. <10> Connected within, subregions DIVs <10> Wiring D3 located inside <2> It is connected via plug C4. Wiring D3 <2> This is wiring D3 <1> The sense amplifier unit SA to which the sense amplifier unit SA adjacent to the X-direction is connected, and the sub-regions DIVs via wiring D0~D2 and plugs C1~C3. <10> They are connected internally.

[0128] Two subregions (DIVs) <10> , <11> Of the intermodule wiring DBLs that span across the module, another intermodule wiring DBL is the corresponding inter-cell module wiring CBL and sub-region DIVs. <10> Connected within, subregions DIVs <11> Wiring D3 located inside <3> It connects to wiring D3. <3> It extends in the direction along the X direction, wiring D3 <2> The sense amplifier unit SA to which the sense amplifier unit SA adjacent to the X-direction is connected, and the sub-regions DIVs via wiring D0~D2 and plugs C1~C3. <11> They are connected internally.

[0129] With the above configuration, a predetermined bit line BL and a sense amplifier unit SA, which is shifted to the right relative to the bit line BL on the paper, are electrically connected.

[0130] In the example in Figure 6, bit line BL0 is connected to the sense amplifier unit via inter-cell module wiring CBL. <00> subregions DIVs <00> , <01> Module-internal wiring DBLs arranged across <0> subregions DIVs <00> It is connected internally, and further wiring D3 <0> via the sense amplifier unit SA <00> subregions DIVs <00> They are connected internally.

[0131] Furthermore, bit line BL3 is connected to the inter-cell module wiring CBL, and to the intra-module wiring DBL. <0> And adjacent to the X direction is the sense amplifier unit <00> Module-internal wiring DBL located at <1> subregions DIVs <01> It is connected internally, and further wiring D3 <1> via the sense amplifier unit SA <01> subregions DIVs <01> They are connected internally.

[0132] Furthermore, the bit line BL18 connects to the sense amplifier unit via the inter-cell module wiring CBL. <10> subregions DIVs <10> , <11> Module-internal wiring DBLs arranged across <2> subregions DIVs <10> It is connected internally, and further wiring D3 <2> via the sense amplifier unit SA <12> subregions DIVs <10> They are connected internally.

[0133] Furthermore, bit line BL21 is connected to the inter-cell module wiring CBL and to the intra-module wiring DBL. <2> And adjacent to the X direction is the sense amplifier unit <10> Module-internal wiring DBL located at <3> subregions DIVs <11> It is connected internally, and further wiring D3 <3> via the sense amplifier unit SA <13> subregions DIVs <11> They are connected internally.

[0134] In Figure 6, multiple bit lines BL are highlighted to show the sub-regions DIVs within the sense amplifier unit SA to which they are connected.

[0135] Furthermore, the inter-cell module wiring CBL connected to bit lines BL24 and BL27 respectively are sub-regions DIVs of multiple sense amplifier units SA. <00> The position overlapping vertically extends in the X direction and is connected to the sense amplifier unit SA (not shown in Figure 6).

[0136] Furthermore, the inter-cell module wiring CBLs connected to bit lines BL30 and BL33 respectively are sub-regions DIVs of multiple sense amplifier units SA. <10> The position overlapping vertically extends in the X direction and is connected to a sense amplifier unit SA (not shown in Figure 6).

[0137] Thus, the inter-cell module wiring CBLs, which are connected to multiple bit lines BL0, BL3, BL12, BL15, BL24, BL27, etc., are sub-regions DIVs of multiple sense amplifier units SA. <00> The inter-cell module wiring CBLs, which are arranged in a position that overlaps vertically and are connected to multiple bit lines BL6, BL9, BL18, BL21, BL30, BL33, etc., are sub-regions DIVs of multiple sense amplifier units SA. <10> They are arranged in a concentrated position where they overlap vertically.

[0138] This allows plug V2, pads PDm, PDc, and plug C5 to be positioned in the layers between multiple cell module wiring CBLs and multiple module intra-module wiring DBLs of multiple sense amplifier units SA. <00> and subregions DIVs <10> By consolidating them in a position that overlaps vertically, a unified space is secured in the layer between multiple inter-cell module wirings (CBLs) and multiple intra-module wirings (DBLs).

[0139] In Figure 6, the bit lines BL1, BL2, BL4, BL5...BL10, BO11...BL25, BO26..., etc., which are not connected to the inter-cell module wiring CBL, are connected to the multiple sense amplifier units SA shown in Figure 6 and to multiple sense amplifier units SA (not shown) located at positions separated in the Y direction.

[0140] Furthermore, in this specification, the entirety of the bit line BL, inter-cell module wiring CBL, and intra-module wiring DBL may be referred to as the bit line in a broad sense. In addition to the bit line BL, inter-cell module wiring CBL, and intra-module wiring DBL, plugs V1, V2, C5, etc. that connect them may also be included in the bit line, and furthermore, pads PDm, PDc that connect the inter-cell module wiring CBL and the intra-module wiring DBL may also be included in the bit line.

[0141] Furthermore, within a memory cell array (MR), bit lines (BL) connected to multiple pillars (PL) are an example of intra-cell wiring.

[0142] Here, shield wiring with a predetermined potential is placed near multiple module-internal wiring DBLs. Figures 7 and 8 show examples of the configuration of the shield wiring SH.

[0143] Figure 7 is a schematic diagram showing an example of the configuration of a shielded wiring SH arranged near an in-module wiring DBL according to the embodiment. As shown in Figure 7, shielded wiring SH is arranged between multiple inter-cell module wirings CBL arranged in the same group GR and aligned in the X direction, and on both sides of these in the X direction.

[0144] These shielded wirings SH can be positioned along the entire extension direction of multiple module wirings DBLs aligned in the Y direction. That is, for example, three shielded wirings SH can be positioned for four module wirings DBLs arranged within a single group GR.

[0145] Furthermore, these shielded wires SH are maintained at a predetermined potential as described above. These shielded wires SH may each be maintained at different potentials.

[0146] This isolates individual module wiring DBLs from each other, suppressing the influence of noise and other factors between adjacent module wiring DBLs.

[0147] Figure 8 is a schematic diagram showing another example of the configuration of shielded wiring SH located near the module wiring DBL according to the embodiment. In the example shown in Figure 8, shielded wiring SH is not located between multiple inter-cell module wiring CBLs located within the same group GR and aligned in the X direction.

[0148] Multiple inter-cell module wiring lines (CBLs) aligned in the X direction may have different voltages applied to them during the electrical operation of their respective memory cells (MCs). Furthermore, the highest voltage may be applied during data erasure. However, the voltage applied during data erasure remains constant across these inter-cell module wiring lines (CBLs).

[0149] Therefore, as shown in the example in Figure 8, even when multiple inter-cell module wirings CBLs aligned in the X direction are separated from other wiring by a set of shield wiring SHs that sandwich them from both sides in the X direction, noise in the intra-module wiring DBLs can be sufficiently reduced.

[0150] [Summary] A semiconductor memory device has, for example, multiple sense amplifier units that read data from multiple memory cells. Furthermore, a memory cell array, where multiple memory cells are arranged, and a sense amplifier module containing multiple sense amplifier units are arranged, for example, spaced apart in the vertical direction. However, the width of the sense amplifier module in the X direction is narrower than the width of the memory cell area in the X direction, and memory cells that do not overlap the sense amplifier module in the vertical direction are connected to their corresponding sense amplifier units by wiring extending to the sense amplifier module in the X direction.

[0151] Figure 9 is a layout diagram showing the connection relationship between the pillar and the sense amplifier unit SA in the comparative example. As shown in Figure 9, in the semiconductor memory device of the comparative example, the four module wirings DBLx contained within one group GRx are arranged in a single row in the Y direction. Accordingly, the multiple sense amplifier units SA are divided into four regions DIVx in the Y direction.

[0152] Sense Amplifier Unit SA Domain DIVx <0> Module-internal wiring DBLx located in <0> is region DIVx <0> Internal wiring D3x <0> Wiring D3x <0> The sense amplifier unit SA directly below it has the DIVx domain. <0> They are connected internally.

[0153] Sense Amplifier Unit SA Domain DIVx <1> Module-internal wiring DBLx located in <1> is region DIVx <1> Internal wiring D3x <1> Wiring D3x <0> To the sense amplifier unit SA to which is connected, the sense amplifier unit SA adjacent to the sense amplifier unit SA in the X direction, region DIVx <1> They are connected internally.

[0154] Sense Amplifier Unit SA Domain DIVx <2> Module-internal wiring DBLx located in <2> is region DIVx <2> Internal wiring D3x <2> Wiring D3x <1> To the sense amplifier unit SA to which is connected, the sense amplifier unit SA adjacent to the sense amplifier unit SA in the X direction, region DIVx <2> They are connected internally.

[0155] Sense Amplifier Unit SA Domain DIVx <3> Module-internal wiring DBLx located in <3> is region DIVx <3> Internal wiring D3x <3> Wiring D3x <2> To the sense amplifier unit SA to which is connected, the sense amplifier unit SA adjacent to the sense amplifier unit SA in the X direction, region DIVx <3> They are connected internally.

[0156] As a result, multiple inter-cell module wirings CBLx, each connected to multiple bit lines BL, are located in area DIVx. <0> ~DIVx <3> They will be distributed and arranged in a manner. Therefore, the plug V2, pads PDm, PDc, and plug C5 that connect the multiple inter-cell module wiring CBLx and the corresponding intra-module wiring DBLx will also be located in area DIVx. <0> ~DIVx <3> They are distributed and arranged in a scattered manner.

[0157] Figure 10 shows the connection relationship between the bit line BL and the sense amplifier unit SA in three dimensions. For reference, Figure 10 also shows the three-dimensional structure of the semiconductor memory device 1 of the embodiment shown in Figure 5 above.

[0158] As shown in Figure 10(a), in the comparative semiconductor memory device, the four module-internal wirings DBLx are arranged in four regions DIVx, aligned in the Y direction. As a result, the extension distance of each module-internal wiring DBLx in the Y direction becomes short, and if the required number of cell-module wirings CBLx are placed in positions that overlap with the corresponding module-internal wiring DBLx, the pitch between cell-module wirings CBLx becomes narrow. On the other hand, if the pitch between cell-module wirings CBLx is widened, the width of the sense amplifier unit SA in the Y direction becomes longer.

[0159] Furthermore, in the comparative example semiconductor memory device, as described above, the plug V2, pads PDm, PDc, and plug C5 that connect the multiple inter-cell module wiring CBLx and the inter-module wiring DBLx are located in region DIVx <0> ~DIVx <3> They are distributed and arranged in a dispersed manner. As a result, a unified space is not secured in the layer between multiple inter-cell module wirings (CBLx) and multiple intra-module wirings (DBLx).

[0160] Furthermore, since multiple inter-cell module wirings CBLx are distributed among multiple corresponding intra-module wirings DBLx, the spacing between inter-cell module wirings CBLx connected to different intra-module wirings DBLx is relatively narrow. Therefore, the length of the connection portion CPx between each inter-cell module wiring CBLx and the corresponding bit line BL is constrained in the Y direction.

[0161] Semiconductor memory devices have numerous other wires that belong to the layer between multiple cell module wirings CBLx and multiple module-internal wirings DBLx, and are not involved in the connection between bit lines BL and sense amplifier units SA. If such wires are to be placed in the region between the multiple cell module wirings CBLx and multiple module-internal wirings DBLx, these wires must be placed while avoiding plugs V2, pads PDm, PDc, and plug C5, etc., which connect the cell module wirings CBLx and the module-internal wirings DBLx, resulting in a complex wiring structure.

[0162] According to the semiconductor memory device 1 of the embodiment, there is an inter-cell module wiring CBL that is electrically connected to a predetermined memory cell MC and extends in the direction along the X direction toward the sense amplifier module 530 from a position that overlaps the memory cell MC in the vertical direction, and an internal module wiring DBL that is close to an internal module wiring DBL to which another inter-cell module wiring CBL is connected, and extends in the direction along the Y direction parallel to the other internal module wiring DBL in the X direction, and electrically connects the inter-cell module wiring CBL and the corresponding sense amplifier unit SA.

[0163] As shown in Figure 10(b), with the above configuration, in the semiconductor memory device 1 of the embodiment, a consolidated space S is secured in the layer between the multiple inter-cell module wirings CBL and the multiple intra-module wirings DBL.

[0164] Therefore, other wiring belonging to the layer between multiple cell module wirings CBL and multiple module intra-module wirings DBL, and not involved in the connection between bit lines BL and sense amplifier units SA, can be placed using the space S described above. This increases the flexibility of the placement of other wiring, thereby preventing the wiring structure from becoming overly complex.

[0165] Furthermore, since multiple inter-cell module wiring lines (CBLs) are aggregated and arranged for each corresponding multiple intra-module wiring line (DBL), it is possible to maintain a relatively wide spacing between inter-cell module wiring lines (CBLs) connected to different intra-module wiring lines (DBLs). Therefore, the connection portion CP between each inter-cell module wiring line (CBL) and the corresponding bit line (BL) can be made longer in the Y direction, thereby improving the reliability of the electrical connection between each inter-cell module wiring line (CBL) and the corresponding bit line (BL).

[0166] Therefore, in the semiconductor memory device 1, bit lines BL, inter-cell module wiring CBL, and intra-module wiring DBL can be efficiently routed.

[0167] According to the semiconductor memory device 1 of the embodiment, the number of sense amplifier units SA included in one of the multiple groups GR is greater than the number of multiple regions DIV. In such a configuration, the distance over which the module wiring DBL extends in the Y direction is long for one sense amplifier unit SA. This makes it possible to suppress the narrowing of the pitch of the inter-cell module wiring CBL and the lengthening of the width of the sense amplifier unit SA in the Y direction.

[0168] In the semiconductor memory device 1 of this embodiment, multiple module-internal wiring DBLs are arranged within a predetermined area of ​​the sense amplifier module 530, which is partitioned by one group GR and one of the multiple regions DIV. In this way, multiple module-internal wiring DBLs, which are aligned in the X direction, are arranged in close proximity within a very limited predetermined area of ​​the sense amplifier module 530, so that the associated plugs V2, pads PDm, PDc, and plug C5 are also concentrated in the predetermined area. Therefore, a wider space S can be secured in the layer between the multiple cell module-interconnection CBLs and the multiple module-internal wiring DBLs.

[0169] According to the semiconductor memory device 1 of this embodiment, the number of sense amplifier units SA included in one group GR is equal to the number of in-module wiring DBLs arranged within one group GR. This allows each of the sense amplifier units SA in one group GR to be connected to the corresponding inter-cell module wiring CBL via these in-module wiring DBLs.

[0170] According to the semiconductor memory device 1 of this embodiment, a shield wiring SH having a predetermined potential is arranged on both sides in the X direction of a plurality of module wirings DBLs aligned in the X direction. This makes it possible to suppress noise between the plurality of module wirings DBLs.

[0171] In the above embodiment, the module wiring DBL connecting the inter-cell module wiring CBL and the wiring D3 on the sense amplifier unit SA side is arranged on a single layer. However, since the wiring D4 is configured as a multi-layer wiring arranged on multiple layers, the module wiring DBL may also be multi-layered. That is, one inter-cell module wiring CBL and one corresponding wiring D3 may be connected by multiple module wiring DBLs arranged across multiple layers.

[0172] In this case, at least the shield wiring SH described above can be provided in the module wiring DBL located closest to the memory cell array and connected to the inter-cell module wiring CBL, and in the module wiring DBL located closest to the sense amplifier unit SA and connected to wiring D3. However, each of the individual module wiring DBLs in multiple layers may also have shield wiring SH.

[0173] [Differentiation] Next, semiconductor memory devices of modified embodiments 1 and 2 will be described with reference to Figures 11 and 12. In the following description, components similar to those in the above-described embodiments will be denoted by the same reference numerals, and their descriptions may be omitted.

[0174] (Variation 1) Figure 11 shows an example of a wiring structure for electrically connecting a pillar PL and a sense amplifier unit SA in a semiconductor memory device according to a modified embodiment 1. More specifically, Figure 11(a) is a layout diagram showing the connection relationship between the pillar PL and the sense amplifier unit SA. Figure 11(b) is a schematic diagram showing the connection relationship between the pillar PL and the sense amplifier unit SA in three dimensions.

[0175] The semiconductor memory device of Modification 1 differs from the above-described embodiment in the number of sense amplifier units SA included in one group GRa, and in the regions DIVa included in each of the multiple sense amplifier units SA.

[0176] As shown in Figure 11, in the semiconductor memory device of Modification 1, eight sense amplifier units SA are included in one group GRa. <0> The sense amplifier unit SA is included. <00> ~SA <07> This is shown.

[0177] These sense amplifier units SA have four regions DIVa in the Y direction. <0> ~DIVa <3> It is divided into. In other words, of these sense amplifier units SA, sense amplifier unit SA <00> In this configuration, four DBLa modules are arranged in two rows in the Y direction, and accordingly, each sense amplifier unit SA has four DIVa regions. <0> ~DIVa <3> It is divided into.

[0178] Of the eight module-internal wiring DBLas within one group GRa, two module-internal wiring DBLas <0> ,DBLa <1> This is the SA sense amplifier unit. <00> In the region DIVa <0> They are aligned in the X direction and extend in the Y direction within the interior.

[0179] These modules have internal wiring DBLa <0> ,DBLa <1> Among them, module internal wiring DBLa <0> This includes the inter-cell module wiring CBLa, which is electrically connected to the bit line BL0, and the sense amplifier unit SA <00> DIVa <0> Connected within, region DIVa <0> Wiring D3 located inside <0> via the sense amplifier unit SA <00> and the region DIVa <0> They are connected internally.

[0180] Furthermore, in the semiconductor memory device of Modification 1, in order to ensure a long connection in the Y direction between each cell module wiring CBLa and the corresponding bit line BL, a connection portion CPa extending in the Y direction can be provided.

[0181] Also, module internal wiring DBLa <1> This includes the inter-cell module wiring CBLa connected to the bit line BL3, and the sense amplifier unit SA <00> DIVa <0> Connected within, region DIVa <0> Wiring D3 located inside and extending in the X direction <1> Wiring D3 <0> The sense amplifier unit SA to which it is connected <00> And adjacent sense amplifier unit SA in the X direction <01> And, Domain DIVa <0> They are connected internally.

[0182] Of the eight module-internal wiring DBLas within one group GRa, two module-internal wiring DBLas <2> ,DBLa <3> This is module internal wiring DBLa <0> ,DBLa <1> And aligned in the Y direction, sense amplifier unit SA <00> DIVa <1> They are aligned in the X direction and extend in the Y direction within the interior.

[0183] Of these, module internal wiring DBLa <2> This includes the inter-cell module wiring CBLa connected to the bit line BL6, and the sense amplifier unit SA <00> DIVa <1> Connected within, region DIVa <1> Wiring D3 located inside and extending in the X direction <2> Wiring D3 <1> The sense amplifier unit SA to which it is connected <01> And adjacent sense amplifier unit SA in the X direction <02> And, Domain DIVa <1> It is connected internally. Also, the module internal wiring DBLa <3> This includes the inter-cell module wiring CBLa connected to the bit line BL9, and the sense amplifier unit SA <00> DIVa <1> Connected within, region DIVa <1> Wiring D3 located inside and extending in the X direction <3> Wiring D3 <2> The sense amplifier unit SA to which it is connected <02> And adjacent sense amplifier unit SA in the X direction <03> And, Domain DIVa <1> They are connected internally.

[0184] Of the eight module-internal wiring DBLas within one group GRa, two module-internal wiring DBLas <4> ,DBLa <5> This is module internal wiring DBLa <0> ,DBLa <2> , and module internal wiring DBLa <1> ,DBLa <3> And aligned in the Y direction, sense amplifier unit SA <00> DIVa <2> They are aligned in the X direction and extend in the Y direction within the interior.

[0185] Of these, module internal wiring DBLa <4> This includes the inter-cell module wiring CBLa connected to the bit line BL12, and the sense amplifier unit SA <00> DIVa <2> Connected within, region DIVa <2> Wiring D3 located inside and extending in the X direction <4> Wiring D3 <3> The sense amplifier unit SA to which it is connected <03> And adjacent sense amplifier unit SA in the X direction <04> And, Domain DIVa <2> It is connected internally. Also, the module internal wiring DBLa <5> This includes the inter-cell module wiring CBLa connected to the bit line BL15, and the sense amplifier unit SA <00> DIVa <2> Connected within, region DIVa <2> Wiring D3 located inside and extending in the X direction <5> Wiring D3 <4> The sense amplifier unit SA to which it is connected <04> And adjacent sense amplifier unit SA in the X direction <05> And, Domain DIVa <2> They are connected internally.

[0186] Of the eight module-internal wiring DBLas within one group GRa, two module-internal wiring DBLas <6> ,DBLa <7> This is module internal wiring DBLa <0> ,DBLa <2> DIVa <4> , and module internal wiring DBLa <1> ,DBLa <3> DIVa <5> And aligned in the Y direction, sense amplifier unit SA <00> DIVa <3> They are aligned in the X direction and extend in the Y direction within the interior.

[0187] Of these, module internal wiring DBLa <6> This includes the inter-cell module wiring CBLa connected to the bit line BL18, and the sense amplifier unit SA <00> DIVa <3> Connected within, region DIVa <3> Wiring D3 located inside and extending in the X direction <6> Wiring D3 <5> The sense amplifier unit SA to which it is connected <05> And adjacent sense amplifier unit SA in the X direction <06> And, Domain DIVa <3> It is connected internally. Also, the module internal wiring DBLa <7> This includes the inter-cell module wiring CBLa connected to the bit line BL21, and the sense amplifier unit SA <00> DIVa <3> Connected within, region DIVa <3> Wiring D3 located inside and extending in the X direction <7> Wiring D3 <6> The sense amplifier unit SA to which it is connected <06> And adjacent sense amplifier unit SA in the X direction <07> And, Domain DIVa <3> They are connected internally.

[0188] As a result, in the layer between multiple cell module wiring CBLa and multiple module intra-module wiring DBLa, the sense amplifier unit SA <01> ~SA <07> The entire area that overlaps vertically is reserved as a single, unified space, Sa.

[0189] According to the semiconductor memory device of Modification 1, a larger space Sa is secured by the above configuration.

[0190] The semiconductor memory device of Modified Example 1 also provides the same effects as the embodiments described above.

[0191] (Modification 2) Figure 12 shows an example of a wiring structure for electrically connecting the pillar PL and the sense amplifier unit SA of a semiconductor memory device according to a modified embodiment 2. More specifically, Figure 12(a) is a layout diagram of the sense amplifier unit SA. Figure 12(b) is a schematic diagram mainly showing the connection relationships within the sense amplifier unit SA in three dimensions.

[0192] The semiconductor memory device of Modification 2 differs from the embodiment described above in the location where the module wiring DBLb is arranged.

[0193] As shown in Figure 12, in the semiconductor memory device of Modification 2, the grouping and region division of the multiple sense amplifier units SA is the same as in the embodiment described above. That is, one group GR includes four sense amplifier units SA that are adjacent to each other in the X direction, and these sense amplifier units SA are divided in the Y direction into two regions DIV, each containing two sub-regions DIVs.

[0194] Within one group GR, four module wiring DBLs are arranged, similar to the embodiments described above. However, these four module wiring DBLb are located within the two sense amplifier units SA located in the center of the X-direction, out of four sense amplifier units SA arranged in the X-direction within group GR.

[0195] For more details, see Group GA. <0> Of the four module wiring DBLb located inside, <1> This is the SA sense amplifier unit. <01> subregions DIVs <00> DIVs <01> It extends in the Y direction across the sub-regions DIVs <00> Wiring D3b located inside <1> via the sense amplifier unit SA <01> and subdomains DIVs <00> They are connected internally.

[0196] Also, module internal wiring DBLb <3> This is the SA sense amplifier unit. <02> subregions DIVs <00> DIVs <01> Spanning across, module internal wiring DBLb <1> And aligned in the X direction and extending in the Y direction, sub-regions DIVs <00> Wiring D3b located inside <3> via the sense amplifier unit SA <03> and subdomains DIVs <00> They are connected internally.

[0197] Also, module internal wiring DBLb <0> This is the SA sense amplifier unit. <01> subregions DIVs <10> DIVs <11> Spanning across, module internal wiring DBLb <1> And aligned in the Y direction, extending in the Y direction, sub-regions DIVs <10> Wiring D3b located inside <0> via the sense amplifier unit SA <00> and subdomains DIVs <10> They are connected internally.

[0198] Also, module internal wiring DBLb <2> This is the SA sense amplifier unit. <02> subregions DIVs <10> DIVs <11> Spanning across, module internal wiring DBLb <0> And aligned in the X direction and extending in the Y direction, sub-regions DIVs <10> Wiring D3b located inside <2> via the sense amplifier unit SA <02> and subdomains DIVs <10> They are connected internally.

[0199] Furthermore, Group GR <1> The four modules included in DBLb <0> ~DBLb <3> And the wiring D3b that connects to each of these <0> ~D3b <3> Also, Group GR <0> It is configured similarly to the internal module wiring DBLb and wiring D3b.

[0200] With the above configuration, in the semiconductor memory device of Modification 2, multiple plugs C4 connecting the module wiring DBLb and wiring D3b are concentrated and arranged in the central part in the X direction within group GR. As a result, a consolidated space Sb is secured in the layer between the module wiring DBLb and wiring D3b.

[0201] The semiconductor memory device of Modified Example 2 also provides the same effects as the embodiments described above.

[0202] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0203] 1...Semiconductor memory device, 510(MR)...Memory cell array, 520(RD)...Raw decoder, 530...Sense amplifier module, BL...Bit line, C1~C5,V1,V2...Plug, CBA...Peripheral circuit, CBL,CBLa...Inter-cell module wiring, CC...Contact, CP,CPa...Connection part, D0~D4,M1,MX...Wiring, DBL,DBLa,DBLb...Inter-module wiring, MC...Memory cell, MR...Memory cell array, PDc,PDm...Pad, PL...Pillar, SA...Sense amplifier unit, SB...Semiconductor substrate, WL...Word line.

Claims

1. A memory cell array containing multiple memory cells, A sense amplifier module is provided, which includes a plurality of sense amplifier units arranged in a position overlapping the memory cell array in the vertical direction and aligned in a first direction intersecting the vertical direction, wherein the width in the first direction is narrower than that of the memory cell array. The system comprises a plurality of bit lines connecting a corresponding sense amplifier unit among the plurality of sense amplifier units and the plurality of memory cells, The aforementioned multiple bit lines are A first bit line connects a first memory cell among the plurality of memory cells to a first sense amplifier unit corresponding to the first memory cell, It includes a second bit line connecting a second memory cell among the plurality of memory cells and a second sense amplifier unit corresponding to the second memory cell, The first bit line is, A first cell module wiring is electrically connected to the first memory cell and extends in the first direction toward the sense amplifier module from a position overlapping the first memory cell in the vertical direction, The sense amplifier module has a position that overlaps with the vertical direction, and the first module internal wiring extends in a second direction that intersects the first direction and the vertical direction, and electrically connects the first inter-cell module wiring and the first sense amplifier unit, The second bit line is, A second cell module wiring is electrically connected to the second memory cell and extends in the first direction toward the sense amplifier module from a position overlapping the second memory cell in the vertical direction, The module has a second module wiring located adjacent to the first module wiring, which extends in the second direction parallel to the first direction and electrically connects the second cell module wiring and the second sense amplifier unit. Semiconductor memory device.

2. The first and second sense amplifier units are adjacent to each other in the first direction, The internal wiring of the first and second modules extends in the second direction, aligned in the first direction, at a position that overlaps with the first sense amplifier unit in the vertical direction. The semiconductor memory device according to claim 1.

3. The first bit line is, The first cell further comprises a first intracell wiring that extends in the second direction from a position overlapping the first memory cell in the vertical direction, and electrically connects the first memory cell and the first inter-cell module wiring, The second bit line is, The cell further comprises a second intracellular wiring that extends in the second direction at a position overlapping the second memory cell in the vertical direction, and electrically connects the second memory cell and the second inter-cell module wiring. The semiconductor memory device according to claim 1.

4. The first and second intra-cell wiring, the first and second inter-cell module wiring, and the first and second intra-module wiring are arranged in different layers between the memory cell array and the sense amplifier module, in this order from the memory cell array side to the sense amplifier module side. The semiconductor memory device according to claim 3.

5. The first and second module wirings, which are aligned in the first direction, are further arranged on both sides of the first direction and have shielded wiring having a predetermined potential. The semiconductor memory device according to claim 1.

6. The aforementioned multiple bit lines are A third bit line connects a third memory cell among the plurality of memory cells to a third sense amplifier unit corresponding to the third memory cell, It includes a fourth bit line connecting a fourth memory cell among the plurality of memory cells and a fourth sense amplifier unit corresponding to the fourth memory cell, The third bit line mentioned above is, A third cell module wiring is electrically connected to the third memory cell and extends in the first direction toward the sense amplifier module from a position overlapping the third memory cell in the vertical direction, The sense amplifier module and the third module internal wiring extend in the second direction at a position overlapping in the vertical direction, electrically connecting the third inter-cell module wiring and the third sense amplifier unit, The fourth bit line is, A fourth cell module wiring is electrically connected to the fourth memory cell and extends in the first direction toward the sense amplifier module from a position overlapping the fourth memory cell in the vertical direction, The module has a fourth module wiring located adjacent to the third module wiring, which extends in the second direction parallel to the first direction and electrically connects the fourth inter-cell module wiring and the fourth sense amplifier unit. The semiconductor memory device according to claim 1.

7. The first to fourth sense amplifier units are adjacent to each other in the first direction in this order, The wiring within the first and second modules extends in the second direction, aligned in the first direction, at a position that overlaps with the first sense amplifier unit in the vertical direction. The third and fourth module wirings are arranged in the second direction alongside the first and second module wirings, and extend in the second direction alongside each other in the first direction. The semiconductor memory device according to claim 6.

8. The first bit line is, The first cell further comprises a first intracell wiring that extends in the second direction from a position overlapping the first memory cell in the vertical direction, and electrically connects the first memory cell and the first inter-cell module wiring, The second bit line is, The cell further comprises a second intracellular wiring that extends in the second direction at a position overlapping the second memory cell in the vertical direction, and electrically connects the second memory cell and the second inter-cell module wiring, The third bit line mentioned above is, The third cell further comprises a third intracell wiring that extends in the second direction to a position overlapping the third memory cell in the vertical direction, and electrically connects the third memory cell and the third inter-cell module wiring, The fourth bit line is, The fourth cell further comprises a fourth intracell wiring that extends in the second direction to a position overlapping the fourth memory cell in the vertical direction, and electrically connects the fourth memory cell and the fourth inter-cell module wiring, The first to fourth cell internal wirings are, In the first direction, arranged in this order, The semiconductor memory device according to claim 7.

9. The first to fourth sense amplifier units are adjacent to each other in the first direction in this order, The first and third module internal wirings extend in the second direction, aligned with each other in the second direction, at positions that overlap with the second sense amplifier unit in the vertical direction. The second and fourth module internal wirings extend in the second direction, aligned with each other in the second direction, at positions that overlap vertically with the third sense amplifier unit. The semiconductor memory device according to claim 6.

10. The first bit line is, The first cell further comprises a first intracell wiring that extends in the second direction from a position overlapping the first memory cell in the vertical direction, and electrically connects the first memory cell and the first inter-cell module wiring, The second bit line is, The cell further comprises a second intracellular wiring that extends in the second direction at a position overlapping the second memory cell in the vertical direction, and electrically connects the second memory cell and the second inter-cell module wiring, The third bit line mentioned above is, The third cell further comprises a third intracell wiring that extends in the second direction to a position overlapping the third memory cell in the vertical direction, and electrically connects the third memory cell and the third inter-cell module wiring, The fourth bit line is, The fourth cell further comprises a fourth intracell wiring that extends in the second direction to a position overlapping the fourth memory cell in the vertical direction, and electrically connects the fourth memory cell and the fourth inter-cell module wiring, The first to fourth cell internal wirings are, In the first direction, arranged in this order, The semiconductor memory device according to claim 9.

11. A memory cell array containing multiple memory cells, A sense amplifier module is provided, which includes a plurality of sense amplifier units arranged in a position overlapping the memory cell array in the vertical direction and aligned in a first direction intersecting the vertical direction, wherein the width in the first direction is narrower than that of the memory cell array. The system comprises a plurality of bit lines connecting a corresponding sense amplifier unit among the plurality of sense amplifier units and the plurality of memory cells, Each of the aforementioned plurality of bit lines is A cell module wiring is electrically connected to one of the plurality of memory cells and extends in the first direction toward the sense amplifier module from a position overlapping the one memory cell in the vertical direction, The sense amplifier module and the position overlapping in the vertical direction have internal module wiring that extends in a second direction intersecting the first direction and the vertical direction, and electrically connects the inter-cell module wiring and the sense amplifier unit corresponding to one memory cell, The aforementioned sense amplifier module is In the first direction, it is divided into multiple groups, each containing two or more adjacent sense amplifier units. In the second direction, the plurality of bit lines are each divided into a plurality of regions assigned to each module wiring that is aligned in the second direction, The number of sense amplifier units included in one of the aforementioned multiple groups is greater than the number of the aforementioned multiple regions. Semiconductor memory device.

12. The aforementioned group includes N sense amplifier units (where N is an integer greater than or equal to 2), The number of regions that each of the N sense amplifier units has is N / 2. The semiconductor memory device according to claim 11.

13. Within a predetermined area of ​​the sense amplifier module, which is demarcated by the aforementioned group and one of the plurality of regions, a plurality of module wirings are arranged among the module wirings that each of the plurality of bit lines has. The semiconductor memory device according to claim 11.

14. The multiple modules' internal wiring are arranged in a line in the first direction. The semiconductor memory device according to claim 13.

15. The number of sense amplifier units included in the group is equal to the number of module wirings among the plurality of bit lines that are arranged within the group. The semiconductor memory device according to claim 13.

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