Semiconductor device and method for manufacturing a semiconductor device

Abstract

To reduce the contact resistance between the channel layer and the lower electrode. [Solution] The semiconductor device of the embodiment includes a first electrode, a first insulating layer provided on the first electrode, a gate electrode provided on the first insulating layer, a second insulating layer provided on the gate electrode, a second electrode provided on the second insulating layer, a channel layer having one end connected to the first electrode and the other end connected to the second electrode, and a gate insulating layer provided between the channel layer and the gate electrode. In the channel layer, at a first height position between the two ends in the thickness direction of the first insulating layer, the length in a first direction intersecting the thickness direction increases discontinuously from the gate electrode side toward the first electrode side.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device.

Background Art

[0002] A semiconductor device configured as a vertical transistor having a composite oxide semiconductor as a channel layer is known. Such a semiconductor device has a channel layer connected at both ends to upper and lower electrodes and connected on the side to a gate electrode provided between these electrodes.

[0003] The channel layer is provided, for example, penetrating an interlayer insulating layer separating the upper and lower electrodes and the gate electrode. At this time, if the diameter of the lower end portion of the channel layer connected to the lower electrode varies, the contact resistance between the channel layer and the lower electrode may increase.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment aims to provide a semiconductor device and a method of manufacturing a semiconductor device capable of reducing the contact resistance between a channel layer and a lower electrode.

Means for Solving the Problems

[0006] The semiconductor device of the embodiment includes a first electrode, a first insulating layer provided on the first electrode, a gate electrode provided on the first insulating layer, a second insulating layer provided on the gate electrode, a second electrode provided on the second insulating layer, a channel layer with one end connected to the first electrode and the other end connected to the second electrode, and a gate insulating layer provided between the channel layer and the gate electrode, wherein in the channel layer, at a first height position between the two ends in the thickness direction of the first insulating layer, the length in a first direction intersecting the thickness direction increases discontinuously from the gate electrode side toward the first electrode side. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic diagram showing an example of the configuration of a semiconductor device according to Embodiment 1. [Figure 2] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 3] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 4] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 5] A schematic diagram showing an example of the configuration of a semiconductor device according to Embodiment 2. [Figure 6] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to Embodiment 2. [Figure 7] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to Embodiment 2. [Figure 8] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 1 of Embodiment 2. [Figure 9] A schematic diagram showing an example of the configuration of a semiconductor device according to a modified example 2 of Embodiment 2. [Figure 10] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 2 of Embodiment 2. [Figure 11]A schematic diagram illustrating the definition of the taper angle when the channel layer in Embodiment 2 and Modifications 1 and 2 is considered to have a tapered shape. [Modes for carrying out the invention]

[0008] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0009] [Embodiment 1] Embodiment 1 will be described in detail below with reference to the drawings.

[0010] (Example of semiconductor device configuration) Figure 1 is a schematic diagram showing an example of the configuration of a semiconductor device 1 according to Embodiment 1. Figure 1(a) is an XY cross-sectional view of the semiconductor device 1 at the height of the gate electrode 30, which will be described later. Figure 1(b) is a cross-sectional view of the semiconductor device 1 along the X direction. Figure 1(c) is a cross-sectional view of the semiconductor device 1 along the Y direction.

[0011] In this specification, both the X and Y directions are directions along the plane of the gate electrode 30, which will be described later, and the X and Y directions are orthogonal to each other. The Z direction is the stacking direction of each layer of the semiconductor device 1, and is a direction orthogonal to the X and Y directions.

[0012] Furthermore, the direction in which the gate electrode 30 extends is sometimes referred to as the first direction, and this first direction is the direction along the X direction. Also, the direction in which the bit line 70 extends, which will be described later, and which intersects with the first direction is sometimes referred to as the second direction, and this second direction is the direction along the Y direction. However, since the semiconductor device 1 may contain manufacturing tolerances, the first direction and the second direction are not necessarily orthogonal.

[0013] As shown in Fig. 1, the semiconductor device 1 includes a lower electrode 11 as a first electrode, a gate electrode 30, an upper electrode 51 as a second electrode, and a pillar 60. The lower electrode 11, the gate electrode 30, the upper electrode 51, and the pillar 60 are provided above a substrate (not shown) such as a silicon substrate.

[0014] More specifically, above the substrate, an insulating layer 10, 20, the gate electrode 30, and insulating layers 40, 50 are provided in this order. The layer thicknesses of the gate electrode 30 and the insulating layers 20, 40 are, for example, both on the order of several tens of nm.

[0015] The insulating layer 10 is, for example, a SiN layer or the like. In the insulating layer 10, contacts 13 extending through the insulating layer 10 are provided at predetermined intervals in the X direction and the Y direction. The contacts 13 are, for example, SiGe layers or the like and are connected to the substrate via a source line (not shown) or directly.

[0016] On the upper end portion of the contact 13, a lower electrode 11, which is, for example, an indium tin oxide (ITO) layer or the like, is provided. As a result, the lower electrode 11 is at the substrate potential. Note that the upper surfaces of the insulating layer 10 and the lower electrode 11 are located on substantially the same plane, and the upper surface of the lower electrode 11 is not covered by the insulating layer 10.

[0017] The side surfaces of the contacts 13 and the lower electrode 11 are covered by a liner layer 12. The liner layer 12 has a multilayer structure in which, for example, a TiN layer, a ZrO layer, and a ZrAlO layer (all not shown) are laminated in this order from the sides of the contacts 13 and the lower electrode 11 toward the outside.

[0018] On the insulating layer 10, an insulating layer 20 covering the upper surfaces of the insulating layer 10, the contacts 13, and the lower electrode 11 is provided. The insulating layer 20 as the first insulating layer is, for example, a SiO layer or the like. The insulating layer 20 may be a Low-k layer such as a SiOC layer.

[0019] Multiple gate electrodes 30 are provided on the insulating layer 20, extending in the direction along the X direction and arranged at predetermined intervals in the Y direction. The multiple gate electrodes 30 are made of tungsten or the like, and are provided in positions that overlap with the lower electrodes 11, which are arranged in a grid in the X and Y directions, in the Z direction. The insulating layer 20 is also provided between adjacent gate electrodes 30 in the Y direction.

[0020] However, an insulating layer 40, which is the upper layer of the gate electrode 30, may be filled between adjacent gate electrodes 30 in the Y direction. Such differences may arise, for example, from differences in the timing of patterning the gate electrodes 30 in the manufacturing method of the semiconductor device 1 described later.

[0021] Multiple gate electrodes 30 are provided with an insulating layer 40 covering them. The insulating layer 40, as a second insulating layer, may be made of the same material as the insulating layer 20, for example, an SiO layer or a low-k layer such as an SiOC layer.

[0022] An insulating layer 50, such as an SiO layer, is provided on the insulating layer 40. On the lower surface of the insulating layer 50, a plurality of upper electrodes 51 are provided in positions that overlap with the plurality of lower electrodes 11 in the Z direction. These upper electrodes 51, like the lower electrodes 11, are made of, for example, an ITO layer, and are connected to bit lines 70 further above the insulating layer 50 via plugs 52 that penetrate the insulating layer 50. The plurality of bit lines 70 each extend in the direction along the Y direction and are arranged at predetermined intervals in the X direction.

[0023] An insulating layer 40, a gate electrode 30 corresponding to that position, and a plurality of pillars 60 penetrating the insulating layer 20 are provided at the position sandwiched between the lower electrode 11 and the upper electrode 51. Each of the plurality of pillars 60 has a channel layer 61 and a gate insulating layer 62.

[0024] The channel layer 61 includes a lower channel layer 61b and an upper channel layer 61a, and is connected to the lower electrode 11 and the upper electrode 51 by penetrating the insulating layer 40, the gate electrode 30, and the insulating layer 20. The channel layer 61 is a composite oxide semiconductor layer such as an IGZO layer, which is an oxide layer of indium (In), gallium (Ga), and zinc (Zn).

[0025] The lower channel layer 61b, as the second part, is provided within the insulating layer 20 and is connected to the lower electrode 11 at its lower end. The upper end of the lower channel layer 61b is positioned at a height between the two sides of the insulating layer 20 in the Z direction. This height position of the upper end of the lower channel layer 61b is also referred to as the first height position.

[0026] The upper channel layer 61a, as the first part, is connected to the upper electrode 51 at its upper end, penetrates the insulating layer 40 and the gate electrode 30, extends further through the insulating layer 20, and is connected to the upper end of the lower channel layer 61b at its lower end. At this time, the lower end of the upper channel layer 61a may extend into the lower channel layer 61b at its lower end.

[0027] Both the lower channel layer 61b and the upper channel layer 61a have a circular shape when viewed from, for example, the Z direction, and the diameter of the lower channel layer 61b is larger than the diameter of the upper channel layer 61a. However, the lower channel layer 61b and the upper channel layer 61a may have shapes other than circular, such as elliptical or oval shapes. Even in that case, when viewed from the Z direction, the cross-sectional area of ​​the lower channel layer 61b is larger than the cross-sectional area of ​​the upper channel layer 61a.

[0028] In other words, the length of the lower channel layer 61b in the X direction and the length in the Y direction are both greater than the length of the upper channel layer 61a in the X direction and the length in the Y direction.

[0029] In this case, the upper channel layer 61a may have a shape in which the diameter at the lower end, that is, the length in the X and Y directions, is smaller than the diameter at the upper end, that is, the length in the X and Y directions. In other words, the upper channel layer 61a may have a tapered shape in which the diameter decreases from the upper end to the lower end.

[0030] However, since the upper channel layer 61a has substantially vertical side walls, the diameter at the lower end and the diameter at the upper end may be substantially equal.

[0031] Furthermore, the lower channel layer 61b may have a shape in which the diameter at its lower end, that is, the length in the X and Y directions, is smaller than the diameter at its upper end, that is, the length in the X and Y directions. In other words, the lower channel layer 61b may have a tapered shape in which the diameter decreases from the upper side to the lower side of the insulating layer 20. Even in this case, the diameter of the lower channel layer 61b is generally larger than the diameter of the upper channel layer 61a.

[0032] Furthermore, since the lower channel layer 61b has substantially vertical side walls, the diameter at the lower end and the diameter at the upper end may be substantially equal.

[0033] Furthermore, as described above, both the lower channel layer 61b and the upper channel layer 61a are composite oxide semiconductor layers such as IGZO layers. The composite oxide semiconductor layers contained in the lower channel layer 61b and the upper channel layer 61a may have the same or different composition ratios of the various metals in the composite oxide semiconductor layer.

[0034] For example, if the composite oxide semiconductor layer is, for instance, an IGZO layer and the composition ratios of the various metals are equal, the lower channel layer 61b and the upper channel layer 61a may have a composition ratio of In:Ga:Zn = 1:1:1.

[0035] When the composition ratios of various metals are varied, it is preferable that the lower channel layer 61b contains a higher content of metals with lower oxygen bonding strength than other metals than the upper channel layer 61a. Furthermore, it is preferable that the upper channel layer 61a contains a higher content of metals with higher oxygen bonding strength than other metals than the lower channel layer 61b.

[0036] For example, if the composite oxide semiconductor layer is, for instance, an IGZO layer, then among the In, Ga, and Zn contained in the IGZO layer, In has the characteristic of having a lower bonding strength with oxygen than the other metals. Therefore, when the composition ratios of the various metals are different, the lower channel layer 61b may have a composition ratio of, for example, In:Ga:Zn = 2:1:1.

[0037] On the other hand, in the IGZO layer, Ga has the characteristic of having a higher bonding strength with oxygen than other metals. Therefore, when the composition ratios of the various metals are different, the upper channel layer 61a may have a composition ratio of In:Ga:Zn=1:2:1 instead of or in addition to the lower channel layer 61b with the above composition ratio.

[0038] The composite oxide semiconductor layer included in the lower channel layer 61b is sometimes referred to as the second semiconductor layer, and the composite oxide semiconductor layer included in the upper channel layer 61a is sometimes referred to as the first semiconductor layer.

[0039] As described above, the semiconductor device 1 is configured as, for example, a vertical transistor. In other words, the vertical transistor can be turned on by applying a predetermined voltage from the gate electrode 30 to the channel layer 61 of the pillar 60 that penetrates the gate electrode 30.

[0040] Therefore, the semiconductor device 1 may be considered as containing multiple vertical transistors, with each pillar 60 and the lower electrode 11, gate electrode 30, and upper electrode 51 connected to each of those pillars 60 being considered as a single vertical transistor. In the vertical transistor, the gate electrode 30 that applies voltage to the channel layer 61 functions as a word line.

[0041] As described above, in the IGZO layer, In has a lower bond strength with oxygen than other metals. Therefore, oxygen easily dissociates from the In-O bond, and vacancies that act as donors are generated in the places where oxygen dissociates. In the lower channel layer 61b, which is directly connected to the lower electrode 11, by increasing the content of a metal that has a lower bond strength with oxygen than other metals such as In and that easily generates donors, as described above, the number of donors in the composite semiconductor layer can be increased, thereby increasing the on-current of the semiconductor device 1, which is configured as a vertical transistor, and enabling the semiconductor device 1 to operate at high speed.

[0042] Furthermore, as mentioned above, Ga has a higher bonding strength with oxygen than other metals in the IGZO layer. Therefore, oxygen is less likely to dissociate from the Ga-O bond, and it is less likely to generate vacancies that can serve as donors. In the upper channel layer 61a, which is directly affected by the field effect from the gate electrode 30, by increasing the content of a metal that has a higher bonding strength with oxygen than other metals such as Ga and is less likely to generate donors, as mentioned above, it is possible to reduce donors in the composite semiconductor layer, thereby increasing the threshold voltage of the semiconductor device 1 configured as a vertical transistor and reducing leakage current.

[0043] Therefore, by increasing the metal content of In and other metals in the lower channel layer 61b, and further increasing the metal content of Ga and other metals in the upper channel layer 61a, it is possible to achieve both high on-current and high threshold voltage in a vertical transistor.

[0044] The gate insulating layer 62 extends through the insulating layer 40, the gate electrode 30, and the insulating layer 20, similar to the upper channel layer 61a described above, and covers the side wall portion of the upper channel layer 61a. As described above, if the lower end of the upper channel layer 61a extends into the lower channel layer 61b, the lower end of the gate insulating layer 62 may also extend into the lower channel layer 61b.

[0045] The gate insulating layer 62 has a multilayer structure in which, for example, gate insulating layers 62x and gate insulating layers 62n are stacked in this order from the channel layer 61 side. The gate insulating layer 62x is, for example, an SiO layer, and the gate insulating layer 62n is, for example, a SiN layer. The gate insulating layer 62n that covers the gate insulating layer 62x from the outside may also cover the lower end of the gate insulating layer 62x.

[0046] (Method of manufacturing semiconductor devices) Next, an example of a manufacturing method for the semiconductor device 1 of Embodiment 1 will be described using Figures 2 to 4.

[0047] Figures 2 to 4 are cross-sectional views illustrating, in order, a part of the procedure for manufacturing the semiconductor device 1 according to Embodiment 1. More specifically, the drawings labeled (A) in Figures 2 to 4 are cross-sectional views along the X direction of the semiconductor device 1 during manufacturing, and the drawings labeled (B) in Figures 2 to 4 are cross-sectional views along the Y direction of the semiconductor device 1 during manufacturing.

[0048] As shown in Figures 2(Aa) and 2(Ba), an insulating layer 10, such as a SiN layer, is formed on top of the substrate. Multiple contacts 13 are formed penetrating the insulating layer 10, and multiple lower electrodes 11 are formed at the upper ends of these contacts 13. A liner layer 12 is also formed to cover the side walls of these contacts 13 and the lower electrodes 11.

[0049] When forming the lower electrode 11 on the upper end of the contact 13, the ITO layer that will become the lower electrode 11 is formed to cover the entire upper surface of the insulating layer 10, including the upper end of the contact 13. Subsequently, the ITO layer is processed by CMP (Chemical Mechanical Polishing) or the like to form the shape of the lower electrode 11 so that the upper surface of the ITO layer lies substantially flush with the upper surface of the insulating layer 10. At this time, the upper surface of the lower electrode 11 may have a depression called a dishing.

[0050] Furthermore, an insulating layer 20, such as an SiO layer or a Low-k layer, is formed to cover the upper surface of the insulating layer 10 and the lower electrode 11. At this time, the insulating layer 20 is formed to be thinner than the final thickness of the insulating layer 20 of the semiconductor device 1, for example, to the thickness of the lower channel layer 61b described above.

[0051] As shown in Figures 2(Ab) and 2(Bb), a plurality of recessed patterns 61p are formed in the insulating layer 20 at the location where the channel layer 61 will later be formed. In this case, the recessed patterns 61p may have a tapered shape, with the diameter decreasing from the upper side to the lower side of the insulating layer 20.

[0052] As shown in Figures 2(Ac) and 2(Bc), a semiconductor layer 61d, such as an IGZO layer, is formed to cover the entire upper surface of the insulating layer 20, including a plurality of recessed patterns 61p. The semiconductor layer 61d is also filled into the plurality of recessed patterns 61p, so the upper surface of the semiconductor layer 61d may be slightly recessed at the locations where the plurality of recessed patterns 61p are arranged.

[0053] As shown in Figures 2(Ad)(Bd), the semiconductor layer 61d is processed by CMP or the like to form the shape of the lower channel layer 61b such that the upper surface of the semiconductor layer 61d lies substantially on the same plane as the upper surface of the insulating layer 20.

[0054] As shown in Figures 2(Ae) and 2(Be), the insulating layer 20 is stacked to cover the lower channel layer 61b. At this time, the insulating layer 20 is formed to be thicker than the final thickness of the insulating layer 20 of the semiconductor device 1 by, for example, the thickness of the gate electrode 30 mentioned above.

[0055] As shown in Figures 2(Af) and 2(Bf), multiple groove patterns 30p are formed in the insulating layer 20 at predetermined intervals in the Y direction and extending in the direction along the X direction. These groove patterns 30p are formed in positions that overlap with the multiple lower electrodes 11 in the Z direction.

[0056] As shown in Figures 3(Aa) and 3(Ba), a tungsten layer or the like is filled into multiple grooves 30t. This forms multiple gate electrodes 30 with insulating layers 20 between the wiring.

[0057] As shown in Figures 3(Ab) and 3(Bb), an insulating layer 40, such as an SiO layer or a Low-k layer, is formed to cover the upper surfaces of the insulating layer 20 and the multiple gate electrodes 30.

[0058] The method for forming the gate electrodes 30 shown in Figures 2(Ae)(Be) to 3(Aa)(Ba) is also called the damascene method. However, multiple gate electrodes 30 may be formed by methods other than the damascene method.

[0059] As an example, an insulating layer 20 is initially formed with the thickness that the insulating layer 20 of the semiconductor device 1 will ultimately have, and a tungsten layer or the like is formed to cover the insulating layer 20. Furthermore, a resist layer or the like having a pattern of multiple gate electrodes 30 is formed on the tungsten layer, and the tungsten layer is etched to form multiple gate electrodes 30.

[0060] After removing the resist layer, an insulating layer 40 is formed to cover the multiple gate electrodes 30, similar to Figures 3(Ab) and 3(Bb). In this case, the insulating layer 40 fills the spaces between the multiple gate electrodes 30 aligned in the Y direction.

[0061] As shown in Figures 3(Ac)(Bc), multiple through-holes TH are formed at positions overlapping with the multiple lower electrodes 11 in the Z direction. These holes penetrate the insulating layer 40 and the gate electrode 30, and further extend through the insulating layer 20 to reach the lower channel layer 61b. In this case, the lower end of the through-hole TH may extend slightly into the lower channel layer 61b.

[0062] As shown in Figures 3(Ad) and 3(Bd), a gate insulating layer 62bx, such as an SiO layer, and a gate insulating layer 62bn, such as a SiN layer, are formed in this order to cover the side walls and bottom surfaces of each of the multiple through holes TH. At this time, the gate insulating layers 62bx and 62bn also cover the upper surface of the insulating layer 40.

[0063] As shown in Figures 4(Aa) and 4(Ba), the gate insulating layers 62bx and 62bn are removed from the bottom surface of each of the multiple through holes TH. At this time, some gate insulating layer 62bx may remain at the lower end of the gate insulating layer 62bn that remains on the side wall of the through hole TH. Also at this time, the gate insulating layers 62bx and 62bn on the upper surface of the insulating layer 40 are removed.

[0064] This forms a gate insulating layer 62 that covers the side walls within each through-hole TH. In addition, the upper end of the lower channel layer 61b is exposed from the bottom surface of the through-hole TH.

[0065] As shown in Figures 4(Ab) and 4(Bb), a semiconductor layer 61f, such as an IGZO layer, is formed in multiple through-holes TH using, for example, an atomic layer deposition (ALD) method. In this case, the semiconductor layer 61f also covers the upper surface of the insulating layer 40.

[0066] As shown in Figures 4(Ac) and 4(Bc), the semiconductor layer 61f on the upper surface of the insulating layer 40 is removed by CMP or the like. As a result, the semiconductor layer 61f is separated individually, and multiple upper channel layers 61a are formed, each connected to a multiple lower channel layer 61b. In addition, a channel layer 61 including the lower channel layer 61b and the upper channel layer 61a is formed, and multiple pillars 60 comprising the channel layer 61 and the gate insulating layer 62 are formed.

[0067] As shown in Figures 4(Ad) and 4(Bd), an insulating layer 50, such as an SiO layer, is formed to cover the insulating layer 40 and the upper surfaces of the multiple pillars 60. In addition, multiple upper electrodes 51 are formed in the insulating layer 50, and further, multiple plugs 52 are formed that penetrate the insulating layer 50 and are connected to these upper electrodes 51.

[0068] As described above, the semiconductor device 1 of Embodiment 1 is manufactured.

[0069] (Overview) Miniaturization is being pursued in semiconductor devices configured as vertical transistors. Along with this, the pillar diameter, including the channel layer, is also being reduced. Such pillars are formed by penetrating, for example, the interlayer insulating layer separating the upper and lower electrodes, and the gate electrode located between the upper and lower electrodes. However, the reduction in pillar diameter can lead to variations in the diameter of the lower end of the through-hole, potentially increasing the contact resistance between the pillar's channel layer and the lower electrode.

[0070] Furthermore, the gate insulating layer covering the sidewalls of the channel layer may have a multilayer structure consisting of, for example, an SiO layer and a SiN layer. When forming the gate insulating layer, the SiN layer and the SiO layer are formed in that order on the sidewalls and bottom surface of the through-holes described above. However, when forming the SiN layer on a lower electrode layer such as an ITO layer, the ITO layer may sublimate due to the reducing action of the raw material gas of the SiN layer, causing the lower electrode to disappear.

[0071] According to the semiconductor device 1 of Embodiment 1, in the channel layer 61, at a predetermined height position between both ends in the thickness direction of the insulating layer 20, the length in the X direction increases discontinuously from the gate electrode 30 side toward the lower electrode 11 side. This makes it possible to reduce the contact resistance between the channel layer 61 and the lower electrode 11.

[0072] According to the semiconductor device 1 of Embodiment 1, the composite oxide semiconductor layer contained in the lower channel layer 61b has a higher content of a metal with a lower bond strength with oxygen than other metals among the multiple metals compared to the composite oxide semiconductor layer contained in the upper channel layer 61a. This increases the on-current of the semiconductor device 1, enabling high-speed operation of the semiconductor device 1.

[0073] According to the semiconductor device 1 of Embodiment 1, the composite oxide semiconductor layer contained in the upper channel layer 61a has a higher content of a metal with a stronger bond strength with oxygen than other metals among the multiple metals compared to the composite oxide semiconductor layer contained in the lower channel layer 61b. This makes it possible to increase the threshold voltage of the semiconductor device 1 and reduce the leakage current.

[0074] According to the manufacturing method of the semiconductor device 1 of Embodiment 1, the formation of the channel layer 61 includes forming a lower channel layer 61b having a predetermined length in the X direction in the insulating layer 20 on the lower electrode 11, and forming an upper channel layer 61a that extends from the insulating layer 40 to the insulating layer 10, is connected to the lower channel layer 61b in the insulating layer 10, and has a length in the X direction that is shorter than the length of the lower channel layer 61b.

[0075] This reduces the contact resistance between the channel layer 61 and the lower electrode 11. Furthermore, since the lower channel layer 61b and the upper channel layer 61a are formed in two stages, the embedding of the composite oxide semiconductor layer in the channel layer 61 can be improved, further reducing the contact resistance between the channel layer 61 and the lower electrode 11.

[0076] Furthermore, since the through-hole TH, which forms the upper channel layer 61a, reaches the upper surface of the lower channel layer 61b without reaching the lower electrode 11, the lower channel layer 61b can function as a stopper layer, thereby suppressing damage to the lower electrode 11 during the formation of the through-hole TH.

[0077] According to the manufacturing method of the semiconductor device 1 of Embodiment 1, the formation of the gate insulating layer 62 includes forming a gate insulating layer 62bn on the side walls and bottom surface of a through hole TH that extends from the insulating layer 40 to the insulating layer 20 and is connected to the lower channel layer 61b in the insulating layer 20.

[0078] Thus, when forming the gate insulating layer 62, the gate insulating layer 62bn, which is a SiN layer or the like, is not formed directly on the lower electrode 11, but is formed on the lower channel layer 61b. This prevents the ITO layer or the like that constituting the lower electrode 11 from sublimating due to the reduction action of the raw material gas in the gate insulating layer 62bn, and thus prevents the lower electrode 11 from disappearing.

[0079] [Embodiment 2] Embodiment 2 will now be described in detail with reference to the drawings. In Embodiment 2, the shape and formation method of the channel layer 161 differ from those of Embodiment 1 described above.

[0080] In the following drawings, components similar to those in Embodiment 1 described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0081] (Example of semiconductor device configuration) Figure 5 is a schematic diagram showing an example of the configuration of the semiconductor device 2 according to Embodiment 2. Figure 5(a) is a cross-sectional view of the semiconductor device 2 along the X direction. Figure 5(b) is a cross-sectional view of the semiconductor device 2 along the Y direction.

[0082] As shown in Figure 5, the lower electrode 110 of the semiconductor device 2 is configured to include a base electrode 112 and a protruding electrode 111, in place of the lower electrode 11 of the embodiment 1 described above.

[0083] The base electrode 112 is, for example, a TiN layer, and is provided at the upper end of the contact 13 such that the height of its upper surface is approximately the same as the upper surface of the insulating layer 10. The protruding electrode 111 is, for example, an ITO layer, and is provided protruding upward from the upper surface of the base electrode 112.

[0084] Furthermore, the pillar 160 of the semiconductor device 2 is equipped with a channel layer 161 instead of the channel layer 61 of the embodiment 1 described above.

[0085] The channel layer 161 is a composite oxide semiconductor layer such as an IGZO layer, and includes an upper channel layer 161a and a lower channel layer 161b, penetrating the upper electrode 51, insulating layer 40, gate electrode 30, and insulating layer 20, thereby connecting the lower electrode 110 and the upper electrode 51. The channel layer 161 may also have a gap 161s extending in the Z direction across the upper channel layer 161a and the lower channel layer 161b.

[0086] The upper channel layer 161a and the lower channel layer 161b may both have a circular shape when viewed from the Z direction, or they may have other shapes such as a circular or oval shape.

[0087] The upper channel layer 161a penetrates the upper electrode 51, the insulating layer 40, and the gate electrode 30 to reach the upper surface of the insulating layer 20. The upper channel layer 161a has substantially vertical side walls, so that the diameter at the lower end of the upper channel layer 161a, i.e., the length in the X and Y directions, is approximately equal to the diameter at the upper end, i.e., the length in the X and Y directions.

[0088] However, the upper channel layer 161a may have a tapered shape in which the diameter decreases from the upper side to the lower side of the insulating layer 20.

[0089] The lower channel layer 161b is connected at its upper end to the lower end of the upper channel layer 161a, and at its lower end, it is connected to the protruding electrode 111 that protrudes from the upper surface of the base electrode 112, penetrating the insulating layer 20. In other words, the protruding electrode 111 penetrates the gate insulating layer 62 at the lower end of the lower channel layer 161b and protrudes into the lower channel layer 161b, thereby connecting the lower channel layer 161b and the lower electrode 110.

[0090] The lower channel layer 161b has a shape in which the diameter at the lower end, i.e., the length in the X and Y directions, is larger than the diameter at the upper end, i.e., the length in the X and Y directions. In this case, the diameter of the lower channel layer 161b changes continuously from the upper end to the lower end.

[0091] In other words, the lower channel layer 161b has a tapered shape in which the diameter increases from the upper side to the lower side of the insulating layer 20. However, the lower channel layer 161b may have a bowing shape in which the side wall portion bulges slightly outward.

[0092] As a result, the lower channel layer 161b has a diameter at its upper end that is approximately equal to the diameter at the lower end of the upper channel layer 161a. Furthermore, the lower channel layer 161b has a diameter at its lower end that is larger than the maximum diameter of the upper channel layer 161a. In other words, the lower channel layer 161b has a length at its lower end that is larger than the maximum length of the upper channel layer 161a in both the X and Y directions.

[0093] As described above, the channel layer 161 of Embodiment 2 generally has a tapered shape in which the diameter increases from the upper end to the lower end.

[0094] The gate insulating layer 62 of the semiconductor device 2 covers the sidewall of the channel layer 161 and the bottom surface of the channel layer 161, excluding the portion through which the protruding electrode 111 penetrates, at the height of the insulating layer 40, the gate electrode 30, and the insulating layer 20. The gate insulating layer 62 does not cover the sidewall of the channel layer 161 in the portion that penetrates the upper electrode 51. As a result, the channel layer 161 can be connected to the upper electrode 51 on its side.

[0095] (Method of manufacturing semiconductor devices) Next, an example of a manufacturing method for the semiconductor device 2 of Embodiment 2 will be described using Figures 6 and 7.

[0096] Figures 6 and 7 are cross-sectional views illustrating a part of the procedure for manufacturing the semiconductor device 2 according to Embodiment 2. More specifically, the drawings labeled (A) in Figures 6 and 7 are cross-sectional views along the X direction of the semiconductor device 2 during manufacturing, and the drawings labeled (B) in Figures 6 and 7 are cross-sectional views along the Y direction of the semiconductor device 2 during manufacturing.

[0097] As shown in Figures 6(Aa) and 6(Ba), an insulating layer 10 such as a SiN layer is formed on top of the substrate, and a plurality of contacts 13, a plurality of base electrodes 112, and a liner layer 12 are formed on the insulating layer 10. Furthermore, an insulating layer 20 such as an SiO layer or a Low-k layer, a gate electrode 30, and an insulating layer 40 such as an SiO layer or a Low-k layer are formed on the insulating layer 10 in this order.

[0098] In other words, with the exception of the process of forming the lower channel layer 61b in the insulating layer 20, the above processes are carried out in the same manner as, for example, the processes up to Figure 3(Aa)(Ba) of Embodiment 1 described above.

[0099] As shown in Figures 6(Ab) and 6(Bb), multiple through-holes THs are formed at positions overlapping with the multiple base electrodes 112 in the Z direction, penetrating the insulating layer 40 and the gate electrode 30 and reaching the upper surface of the insulating layer 20.

[0100] Multiple through-holes (THs) can be formed under highly anisotropic conditions, for example, by using reactive ion etching (RIE). This results in the formation of through-holes (THs) with nearly vertical side walls.

[0101] As shown in Figures 6(Ac) and 6(Bc), a sidewall protective layer CB is formed on the sidewalls of multiple through holes THs.

[0102] The sidewall protective layer CB can be obtained by forming, for example, a CVD (Chemical Vapor Deposition)-carbon layer under conditions that reduce coverage, so as to cover the upper surface of the insulating layer 40 in which multiple through-holes THs are formed. Alternatively, in the process shown in Figures 6(Ab) and 6(Bb) above, by using a CF-based etching gas and conditions that facilitate deposition generation, a CF-based deposition can be formed on the sidewall protective layer CB of the through-holes THs in parallel with the formation of the through-holes THs.

[0103] As shown in Figures 6(Ad) and 6(Bd), with the side walls of the through-holes THs protected by the side wall protective layer CB, further etching is performed on the bottom surface of the through-holes THs to form a through-hole THt that penetrates the insulating layer 40, the gate electrode 30, and the insulating layer 20.

[0104] In this case, by performing additional etching of the through-holes THs under conditions that weaken anisotropy and facilitate side etching, the diameter of the bottom surface of the through-holes THt can be expanded. As a result, through-holes THt are obtained that have a nearly vertical shape at the height of the insulating layer 40 and the gate electrode 30, and have a larger diameter at the height of the lower surface of the insulating layer 20 than the upper vertical portion.

[0105] After this, the sidewall protective layer CB is removed by ashing treatment, for example, using oxygen plasma.

[0106] As shown in Figures 7(Aa) and 7(Ba), a gate insulating layer 62bx, such as an SiO layer, and a gate insulating layer 62bn, such as a SiN layer, are formed in this order to cover the side walls and bottom surfaces of each of the multiple through holes THt. At this time, the gate insulating layers 62bx and 62bn also cover the upper surface of the insulating layer 40.

[0107] Furthermore, the base electrode 112, which is a TiN layer or the like, is exposed at the bottom of the through hole THt. In this way, since the gate insulating layer 62bn, such as a SiN layer, is formed without directly contacting the protruding electrode 111, such as an ITO layer, which is formed later, the disappearance of the protruding electrode 111 can also be suppressed by the method of Embodiment 2.

[0108] As shown in Figures 7(Ab) and 7(Bb), the gate insulating layers 62bx and 62bn are removed from the bottom surface of each of the multiple through holes THt. At this time, the gate insulating layers 62bx and 62bn on the upper surface of the insulating layer 40 are also removed.

[0109] Furthermore, at this time, the processing is carried out through an opening at the upper end of the through-hole THt, which has a diameter smaller than the diameter of the bottom surface of the through-hole THt. Therefore, it is not necessary for the gate insulating layers 62bx and 62bn on the bottom surface of the through-hole THt to be completely removed. That is, it is sufficient for the gate insulating layers 62bx and 62bn to be removed from a portion of the bottom surface of the through-hole THt that overlaps with the opening of the through-hole THt in the Z direction.

[0110] This creates a gate insulating layer 62 that covers the side walls and a portion of the bottom surface within each through-hole THt. Additionally, the upper surface of the base electrode 112 is exposed from the bottom surface of the through-hole THt where the gate insulating layers 62bx and 62bn have been partially removed.

[0111] As shown in Figures 7(Ac) and 7(Bc), an ITO layer 51b is formed on the upper surface of the insulating layer 40 through which multiple through-holes THt are opened, using a method such as Physical Vapor Deposition (PVD). The ITO layer 51b is also formed on the bottom surface of the through-holes THt where the base electrode 112 is exposed through the openings of the through-holes THt. As a result, a protruding electrode 111 is formed on the bottom surface of the through-holes THt, protruding into the through-holes THt and connected to the base electrode 112 at its lower end.

[0112] As shown in Figures 7(Ad) and 7(Bd), a semiconductor layer 161f, such as an IGZO layer, is formed in multiple through-holes THt using methods such as ALD. At this time, the semiconductor layer 161f also covers the upper surface of the insulating layer 40.

[0113] Furthermore, at this time, the processing is carried out through an opening at the upper end of the through-hole THt, which has a diameter smaller than the diameter of the bottom surface of the through-hole THt. Therefore, the through-hole THt does not need to be completely filled with the IGZO layer or the like. In this case, a void 161s extending in the Z direction may be created in the semiconductor layer 161f filled in the through-hole THt.

[0114] Subsequently, the semiconductor layer 161f is removed from the upper surface of the insulating layer 40 by CMP or the like. This forms channel layers 161 that extend through the ITO layer 51b, the insulating layer 40, the gate electrode 30, and the insulating layer 20, and are individually independent. In addition, a pillar 160 having the channel layer 161 and the gate insulating layer 62 is formed.

[0115] Furthermore, the ITO layer 51b is processed into a pattern for the upper electrodes 51 to form multiple upper electrodes 51 connected to individual channel layers 161. In addition, an insulating layer 50 is formed to fill the spaces between the multiple upper electrodes 51.

[0116] As described above, the semiconductor device 2 of Embodiment 2 is manufactured.

[0117] (Overview) According to the semiconductor device 2 of Embodiment 2, in the channel layer 161, the length in the X direction changes continuously between both ends in the thickness direction of the insulating layer 20, and the length in the X direction is greater at the height position of the lower surface of the insulating layer 20 than at the height position of the upper surface of the insulating layer 20. This makes it possible to reduce the contact resistance between the channel layer 161 and the lower electrode 110.

[0118] According to the semiconductor device 2 of Embodiment 2, the lower electrode 110 has a protruding electrode 111 that protrudes into the channel layer 161. This further increases the contact area between the channel layer 161 and the lower electrode 110, and further reduces the contact resistance between them.

[0119] The semiconductor device 2 of Embodiment 2 also provides the same effects as the semiconductor device 1 of Embodiment 1 described above.

[0120] (Variation 1) Next, the semiconductor device 2a of the modified example 1 of Embodiment 2 will be described with reference to Figure 8. The semiconductor device 2a of the modified example 1 differs from the semiconductor device 2 of Embodiment 2 described above in that the lower end of the protruding electrode 111a is embedded in the base electrode 112.

[0121] Figure 8 is a cross-sectional view illustrating part of the procedure for manufacturing a semiconductor device 2a according to Modification 1 of Embodiment 2. More specifically, Figures 8(Aa) to 8(Ad) are cross-sectional views of the semiconductor device 2a in the manufacturing process along the X direction, and Figures 8(Ba) to 8(Bd) are cross-sectional views of the semiconductor device 2a in the manufacturing process along the Y direction.

[0122] In the following drawings, components similar to those in Embodiment 2 described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0123] In the manufacturing process of the semiconductor device 2a of the modified example 1, the same process as in Figures 6(Aa)(Ba) to 7(Aa)(Ba) of the above-described embodiment 2 is performed. As a result, a plurality of through-holes THt are formed that penetrate the insulating layer 40, the gate electrode 30, and the insulating layer 20, and have gate insulating layers 62bx and 62bn on their side walls and bottom surfaces.

[0124] As shown in Figures 8(Aa)(Ba), the gate insulating layers 62bx and 62bn are removed from the bottom surface of each of the multiple through holes THt. At this time, the gate insulating layers 62bx and 62bn on the upper surface of the insulating layer 40 are also removed.

[0125] At this time, the amount of over-etching of the gate insulating layers 62bx and 62bn is increased to remove a portion of the base electrode 112 that is exposed from the bottom surface of the through hole THt after the gate insulating layers 62bx and 62bn have been removed. As a result, a recess 112r is formed at the upper end of the base electrode 112.

[0126] As shown in Figures 8(Ab) and 8(Bb), an ITO layer 51b is formed to cover the upper surface of the insulating layer 40 by PVD or the like. The ITO layer 51b is also formed on the bottom surface of the through hole THt in which the base electrode 112 is exposed.

[0127] Furthermore, this fills the recess 112r of the base electrode 112 with the ITO layer 51b, forming a protruding electrode 111a whose lower end extends into the base electrode 112 and whose upper end protrudes into the through hole THt. In addition, a lower electrode 110a is formed comprising the protruding electrode 111a and the base electrode 112.

[0128] The subsequent processing is carried out in the same manner as in Embodiment 2 described above.

[0129] Specifically, as shown in Figures 8(Ac) and 8(Bc), a semiconductor layer 161f, such as an IGZO layer, is filled into the through-hole THt. As shown in Figures 8(Ad) and 8(Bd), the semiconductor layers 161f are individually separated to form a pillar 160 having a channel layer 161 and a gate insulating layer 62. In addition, the ITO layer 51b is patterned to form the upper electrode 51.

[0130] Based on the above, the semiconductor device 2a of Modification 1 is manufactured.

[0131] In the semiconductor device 2a of the modified example 1, the lower end of the protruding electrode 111a extends into the base electrode 112. This increases the contact area between the protruding electrode 111a and the base electrode 112, thereby reducing their contact resistance.

[0132] The semiconductor device 2a of the modified example 1 also provides the same effects as the semiconductor device 2 of the embodiment 2 described above.

[0133] (Modification 2) Next, the semiconductor device 3 of the modified embodiment 2 will be described using Figures 9 and 10. The semiconductor device 3 of the modified embodiment 2 has a different shape for the channel layer 261 compared to the embodiment 2 described above.

[0134] In the following drawings, components similar to those in Embodiment 1 described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0135] Figure 9 is a schematic diagram showing an example of the configuration of a semiconductor device 3 according to a modified example 2 of Embodiment 2. Figure 9(a) is a cross-sectional view of the semiconductor device 3 along the X direction. Figure 9(b) is a cross-sectional view of the semiconductor device 3 along the Y direction.

[0136] As shown in Figure 9, the semiconductor device 3 has insulating layers 220 and 240 instead of the insulating layers 20 and 40 of Embodiment 2 described above. The insulating layers 220 and 240 may both be SiO layers or Low-lk layers, etc., as in Embodiment 2 described above. However, insulating layer 220 has a lower density than insulating layer 240.

[0137] Furthermore, the pillar 260 of the semiconductor device 3 is equipped with a channel layer 261e instead of the channel layer 161 of the embodiment 2 described above.

[0138] The channel layer 261e is a composite oxide semiconductor layer such as an IGZO layer, and includes an upper channel layer 261a, a middle channel layer 161c, and a lower channel layer 261b, penetrating the upper electrode 51, the insulating layer 240, the gate electrode 30, and the insulating layer 220, thereby connecting the lower electrode 110 and the upper electrode 51. The channel layer 261e may also have a void 261s extending in the Z direction from the upper channel layer 261a through the middle channel layer 261c to the lower channel layer 261b.

[0139] The upper channel layer 261a, the middle channel layer 261c, and the lower channel layer 261b may all have a circular shape when viewed from the Z direction, for example, or they may have other shapes such as circular or oval.

[0140] The upper channel layer 261a penetrates the upper electrode 51 and the insulating layer 240, reaching the upper surface of the gate electrode 30.

[0141] The upper channel layer 261a in the portion that penetrates the upper electrode 51 and connects to the upper electrode 51 has substantially vertical side walls. As a result, the diameter of the upper channel layer 161a at the height of the upper surface of the upper electrode 51, i.e., its length in the X and Y directions, is approximately equal to the diameter of the upper channel layer 161a at the height of the lower surface of the upper electrode 51, i.e., its length in the X and Y directions.

[0142] However, the upper channel layer 261a may have a tapered shape in which the diameter decreases from the upper side to the lower side of the upper electrode 51.

[0143] In the portion penetrating the insulating layer 240, the diameter of the upper channel layer 261a at the height of the lower surface of the insulating layer 240, i.e., its length in the X and Y directions, is greater than the diameter of the upper channel layer 261a at the height of the upper surface of the insulating layer 240, i.e., its length in the X and Y directions. At this time, the diameter of the upper channel layer 261a changes continuously from the height of the upper surface to the height of the lower surface of the insulating layer 240.

[0144] In other words, in the portion that penetrates the insulating layer 240, the upper channel layer 261a has a tapered shape in which the diameter increases from the upper side to the lower side of the insulating layer 240. However, the upper channel layer 261a may have a bowing shape in which the side wall portion bulges slightly outward.

[0145] The middle channel layer 261c is connected at its upper end to the lower end of the upper channel layer 261a and penetrates the gate electrode 30 to reach the upper surface of the insulating layer 220. The middle channel layer 261c has substantially vertical side walls, so that the diameter at the lower end of the middle channel layer 261c, i.e., the length in the X and Y directions, is approximately equal to the diameter at the upper end, i.e., the length in the X and Y directions.

[0146] However, the central channel layer 261c may have a tapered shape in which the diameter decreases from the upper side to the lower side of the gate electrode 30.

[0147] The lower channel layer 261b is connected at its upper end to the lower end of the middle channel layer 261c, and at its lower end, it penetrates the insulating layer 220 and is connected to a protruding electrode 111 that protrudes from the upper surface of the base electrode 112.

[0148] Furthermore, the lower channel layer 261b, like the lower channel layer 161b in Embodiment 2 described above, has a shape in which the diameter at the lower end, that is, the length in the X and Y directions, is larger than the diameter at the upper end, that is, the length in the X and Y directions. In this case, the diameter of the lower channel layer 261b changes continuously from the upper end to the lower end.

[0149] In other words, the lower channel layer 261b has a tapered shape in which the diameter increases from the upper side to the lower side of the insulating layer 220. However, the lower channel layer 261b may have a bowing shape in which the side wall portion bulges slightly outward.

[0150] Thus, the upper channel layer 261a and the middle channel layer 261c correspond to the upper channel layer 161a in the channel layer 161 of Embodiment 2 described above, and the lower channel layer 262b corresponds to the lower channel layer 161b in the channel layer 161 of Embodiment 2 described above. Of these, the channel layer 261 of Modified Example 2 has a different shape in the upper channel layer 261a compared to the channel layer 161 of Embodiment 2 described above.

[0151] With the above configuration, the maximum diameter of the upper channel layer 261a, the maximum diameter of the middle channel layer 261c, and the maximum diameter of the lower channel layer 261b increase in the order of middle channel layer 261c, upper channel layer 261a, and lower channel layer 261b (maximum diameter of middle channel layer 261c < maximum diameter of upper channel layer 261a < maximum diameter of lower channel layer 261b).

[0152] Having this shape, the channel layer 261 of modified example 2 is even closer to a tapered shape in which the diameter increases from the upper end to the lower end.

[0153] Figure 10 is a cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device 3 according to a modified example 2 of Embodiment 2.

[0154] More specifically, Figures 10(Aa) to 10(Ad) are cross-sectional views of the semiconductor device 3 in the manufacturing process along the X direction, and Figures 10(Ba) to 10(Bd) are cross-sectional views of the semiconductor device 3 in the manufacturing process along the Y direction.

[0155] As shown in Figures 10(Aa)(Ba), an insulating layer 10 having a contact 13, a base electrode 112, and a liner layer 12 is formed on the substrate, and an insulating layer 220 and a gate electrode 30 are formed on the insulating layer 10 in that order.

[0156] As shown in Figures 10(Ab) and 10(Bb), an insulating layer 240 is formed on the gate electrode 30.

[0157] Here, the insulating layers 220 and 240 are SiO layers or Low-k layers, etc., and are formed by chemical vapor deposition (CVD) or ALD (Advanced Laser Development) using, for example, a Si source gas and an oxidizing gas such as O2 gas to oxidize the Si. At this time, the film deposition conditions are adjusted so that the density of insulating layer 220 is lower than that of insulating layer 240.

[0158] For example, the density of insulating layers 220 and 240 can be adjusted by changing the flow rate of the Si raw material gas relative to the oxidizing gas. More specifically, when forming insulating layer 220, the density of insulating layer 220 can be decreased by increasing the flow rate of the Si raw material gas relative to the oxidizing gas. On the other hand, when forming insulating layer 240, the density of insulating layer 240 can be increased by decreasing the flow rate of the Si raw material gas relative to the oxidizing gas.

[0159] As shown in Figure 10(Ac)(Bc), multiple through-holes THv are formed that penetrate the insulating layer 240, the gate electrode 30, and the insulating layer 220, reaching each of the multiple base electrodes 112. The multiple through-holes THv can be formed under highly anisotropic conditions, for example, using RIE. This results in the formation of through-holes THv with substantially vertical side walls.

[0160] As shown in Figure 10(Ad)(Bd), the sidewall portions of multiple through-holes THv are treated by wet etching using a dissolving solution for the insulating layers 220 and 240, which are SiO layers or Low-k layers. This creates through-holes THw in which the sidewalls of the portions penetrating the insulating layers 220 and 240 are recessed.

[0161] In the RIE process described above, etching proceeds primarily in the Z direction, and there is almost no difference in the sidewall shape of the through-hole THv due to the density difference between the insulating layers 220 and 240. However, in wet etching, etching proceeds isotropically, and depending on the density difference between the insulating layers 220 and 240, it is possible to create an etch rate difference of, for example, about twice as much.

[0162] Therefore, in the through-hole THw, the recession rate of the sidewall due to wet etching is low in the portion that penetrates the high-density insulating layer 240, and high in the portion that penetrates the low-density insulating layer 220. Furthermore, in the through-hole THw, the sidewall of the portion that penetrates the gate electrode 30, which is a tungsten layer or the like, hardly recedes at all.

[0163] As a result, in the through-hole THw, the diameter of the portion that penetrates the gate electrode 30, i.e., the length in the X and Y directions, is smallest. Also, the diameter of the portion that penetrates the insulating layer 240, i.e., the length in the X and Y directions, is larger than the portion that penetrates the gate electrode 30. Furthermore, the diameter of the portion that penetrates the insulating layer 220, i.e., the length in the X and Y directions, is even larger than the portion that penetrates the insulating layer 240.

[0164] The subsequent processing is carried out in the same manner as shown in Figures 7(Aa)(Ba) and later of Embodiment 2 described above. However, when removing the gate insulating layers 62bx and 62bn from the bottom surface of the through hole THw, the processing of Modification 1 described above may be applied to form a protruding electrode 111a whose lower end extends into the base electrode 112.

[0165] Based on the above, the semiconductor device 2a of Modification 1 is manufactured.

[0166] According to the semiconductor device 3 of the modified example 2, the shape of the channel layer 261 can be made closer to a tapered shape. This further improves the embedding of semiconductor layers such as the IGZO layer, and further reduces the contact resistance between the channel layer 261 and the lower electrode 110.

[0167] The semiconductor device 3 of the modified example 2 also provides the same effects as the semiconductor device 2 of the embodiment 2 described above.

[0168] In the modified example 2 described above, the semiconductor device 3 has a low-density insulating layer 220 and a high-density insulating layer 240. However, the density may vary within each of the insulating layers 220 and 240. That is, the insulating layers 220 and 240 may be configured such that the density gradually increases from the bottom surface to the top surface of the insulating layer 220, and the density further increases from the bottom surface to the top surface of the insulating layer 240.

[0169] In this case, by gradually reducing the flow rate of the Si raw material gas during the formation of the insulating layers 220 and 240, insulating layers 220 and 2240 can be formed in which the density within the layer changes continuously.

[0170] By treating these insulating layers 220 and 240 with wet etching, it becomes possible to bring the shape of the channel layer even closer to a tapered shape in which the diameter increases from the top to the bottom.

[0171] Furthermore, in the above-described embodiment 2 and modified examples 1 and 2, it was explained that the channel layers 161 and 261 can generally be considered to have a tapered shape in which the diameter increases from the upper end to the lower end. In Figure 11, which schematically shows the channel layers 161 and 261 of embodiment 2 and modified examples 1 and 2, an example of the definition of the taper angle of such a channel layer will be explained.

[0172] Figure 11 is a schematic diagram illustrating the definition of the taper angle when the channel layers 161 and 261 in Embodiment 2 and Modifications 1 and 2 are considered to have a tapered shape.

[0173] As shown in Figure 11, when the channel layer is considered to have a tapered shape, the taper angle θ of the channel layer can be defined as, for example, the angle between the inner surface of the side wall of the channel layer and the lower surface of the upper electrode. In this case, in Embodiment 2 and Modifications 1 and 2, the taper angle θ of the channel layer is greater than 90°.

[0174] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0175] 1,2,2a,3...Semiconductor device, 11,110,110a...Lower electrode, 20,40,220,240...Insulating layer, 30...Gate electrode, 51...Upper electrode, 60,160,260...Pillar, 61,161,261,261e...Channel layer, 61a,161a,261a...Upper channel layer, 61b,161b,261b...Lower channel layer, 111,111a...Protruding electrode, 112...Base electrode, 261c...Middle channel layer, 62,62n,62x...Gate insulating layer.

Claims

1. The first electrode and A first insulating layer provided on the first electrode, A gate electrode provided on the first insulating layer, A second insulating layer provided on the gate electrode, A second electrode provided on the second insulating layer, A channel layer having one end connected to the first electrode and the other end connected to the second electrode, A gate insulating layer is provided between the channel layer and the gate electrode, In the channel layer, At a first height position between the two ends in the thickness direction of the first insulating layer, the length of the first direction intersecting the thickness direction increases discontinuously from the gate electrode side toward the first electrode side. Semiconductor equipment.

2. The aforementioned channel layer is A first portion extending from the other end to the first height position and having a first length in the first direction, A second portion extending from the first height position to the one end and having a second length greater than the first length in the first direction, The semiconductor device according to claim 1.

3. The first part is, The first semiconductor layer is mainly composed of a composite oxide semiconductor containing multiple metals, The second part mentioned above is, The second semiconductor layer is mainly composed of a composite oxide semiconductor containing multiple metals of the same type as the first semiconductor layer. The semiconductor device according to claim 2.

4. In the second semiconductor layer, The content of the metal among the aforementioned multiple metals that has a lower bond strength with oxygen than the other metals is higher than that of the first semiconductor layer. The semiconductor device according to claim 3.

5. In the first semiconductor layer, The content of the metal among the aforementioned multiple metals that has a higher bond strength with oxygen than the other metals is higher than that of the second semiconductor layer. The semiconductor device according to claim 3.

6. The gate insulating layer is Extending from the height position of the upper surface of the second insulating layer, through the gate electrode, to the first height position, The semiconductor device according to claim 2.

7. The first electrode and A first insulating layer provided on the first electrode, A gate electrode provided on the first insulating layer, A second insulating layer provided on the gate electrode, A second electrode provided on the second insulating layer, A channel layer having one end connected to the first electrode and the other end connected to the second electrode, A gate insulating layer is provided between the channel layer and the gate electrode, In the channel layer, Between the two ends in the thickness direction of the first insulating layer, the length of the first direction intersecting the thickness direction changes continuously. The length in the first direction is greater at the height of the lower surface of the first insulating layer than at the height of the upper surface of the first insulating layer. Semiconductor equipment.

8. The first electrode is, It has a protrusion that protrudes into the channel layer, The semiconductor device according to claim 7.

9. The first electrode is, It has a base portion that supports the protruding portion, The semiconductor device according to claim 8.

10. The lower end of the protruding portion extends into the base portion. The semiconductor device according to claim 9.

11. Form the first electrode, A first insulating layer is formed on the first electrode, A gate electrode is formed on the first insulating layer, A second insulating layer is formed on the gate electrode, A channel layer is formed by penetrating the second insulating layer, the gate electrode, and the first insulating layer and connecting to the first electrode, and including the first and second portions. The formation of the channel layer is A second portion having a first length in a first direction intersecting the thickness direction of the first insulating layer is formed in the first insulating layer on the first electrode, This includes extending from the second insulating layer to the first insulating layer, connecting with the second portion in the first insulating layer, and forming the first portion having a second length smaller than the first length in the first direction, A method for manufacturing a semiconductor device.

12. The formation of the first part is To form a through hole that extends from the second insulating layer to the first insulating layer and reaches the second portion in the first insulating layer, A gate insulating layer is formed on the side wall of the through hole. This includes filling the through-hole in which the gate insulating layer is formed with a first semiconductor layer mainly composed of a composite oxide semiconductor containing multiple metals. A method for manufacturing a semiconductor device according to claim 11.

13. The formation of the gate insulating layer is A first gate insulating layer is formed on the side wall and bottom surface of the through hole, A second gate insulating layer is formed on the side wall and bottom surface of the through hole via the first gate insulating layer, This includes removing the first and second gate insulating layers formed on the bottom surface of the through hole, The method for manufacturing a semiconductor device according to claim 12.

14. The first gate insulating layer is a SiN layer, The second gate insulating layer is an SiO layer. The method for manufacturing a semiconductor device according to claim 13.

15. The formation of the second part described above is The first insulating layer is processed into the pattern of the second portion to expose the first electrode, This includes filling the pattern with a second semiconductor layer, which is mainly composed of a composite oxide semiconductor containing multiple metals of the same type as the first semiconductor layer. The method for manufacturing a semiconductor device according to claim 12.

16. The formation of the second part described above is The further step includes forming the first insulating layer so as to cover the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 15.

17. The formation of the second part described above is This includes filling the pattern with a second semiconductor layer in which the content of a metal among the plurality of metals that has a lower bond strength with oxygen than the other metals is higher than that of the first semiconductor layer. The method for manufacturing a semiconductor device according to claim 15.

18. The formation of the first part is This includes filling the through-hole with a first semiconductor layer in which the content of a metal among the plurality of metals that has a higher bond strength with oxygen than the other metals is higher than that of the second semiconductor layer. The method for manufacturing a semiconductor device according to claim 15.

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