Semiconductor device and method for manufacturing a semiconductor device

Abstract

Stacking multiple transistors while suppressing the increase in parasitic capacitance. [Solution] The semiconductor device of the embodiment comprises a semiconductor substrate, a first transistor provided on the semiconductor substrate, a semiconductor layer provided above the semiconductor substrate and having a smaller area than the semiconductor substrate, a second transistor provided on the side of the semiconductor layer facing the semiconductor substrate, an insulating layer provided on the semiconductor layer and having a larger area than the semiconductor layer, and a contact extending upward from the first transistor through the insulating layer at a position that does not overlap the semiconductor layer in the vertical direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device in which a plurality of transistors are provided on a semiconductor substrate is known. In order to miniaturize the semiconductor device, for example, attempts have been made to stack a plurality of semiconductor substrates on which transistors are provided. However, in order to draw out the transistors on the lower layer side to the upper layer side, it is necessary to penetrate the semiconductor substrate on which the transistors on the upper layer side are provided and provide contacts or the like, which leads to an increase in parasitic capacitance.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device and a method for manufacturing the semiconductor device capable of stacking a plurality of transistors while suppressing an increase in parasitic capacitance.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a semiconductor substrate, a first transistor provided on the semiconductor substrate, a semiconductor layer provided above the semiconductor substrate and having an area smaller than that of the semiconductor substrate, a second transistor provided on a side of the semiconductor layer facing the semiconductor substrate, an insulating layer provided on the semiconductor layer and having an area larger than that of the semiconductor layer, and a contact that extends upward through the insulating layer from the first transistor at a position not overlapping the semiconductor layer in the vertical direction. [Brief explanation of the drawing]

[0006] [Figure 1] Block diagram of a semiconductor device according to an embodiment. [Figure 2] An equivalent circuit diagram showing an example of the configuration of a memory cell array in a semiconductor device according to an embodiment. [Figure 3] A circuit diagram showing an example of the configuration of a sense amplifier circuit and a latch circuit in a semiconductor device according to an embodiment. [Figure 4] A circuit diagram showing an example of the configuration of a low decoder in a semiconductor device according to an embodiment. [Figure 5] A cross-sectional view showing an example configuration of a semiconductor device according to an embodiment. [Figure 6] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 7] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 8] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 9] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 10] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 11] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 12] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 13] A cross-sectional view illustrating, in sequence, some of the steps in the method for manufacturing a semiconductor device according to an embodiment. [Figure 14] A cross-sectional view showing an example of the configuration of a semiconductor device according to a modified embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0008] [Circuit configuration of semiconductor device] First, an example of the circuit configuration of the semiconductor device 1 of the embodiment will be explained using Figures 1 to 4.

[0009] (Overall configuration of semiconductor device) Figure 1 is a block diagram of a semiconductor device 1 according to an embodiment. As shown in Figure 1, the semiconductor device 1 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0010] The input / output circuit 310 controls the input and output of signal DQ to an external device, such as a memory controller (not shown), which controls the semiconductor device 1. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0011] The input circuit sends data DAT, such as the write data WDT, received from an external device to the data register 540, sends address ADD to the address register 340, and sends command CMD to the command register 350.

[0012] The output circuit transmits status information STS received from status register 330, data DAT such as read data RDT received from data register 540, and address ADD received from address register 340 to an external device.

[0013] The logic control circuit 320 receives signals from an external device, such as the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn. The logic control circuit 320 also controls the input / output circuit 310 and the sequencer 360 according to the received signals.

[0014] The status register 330 temporarily holds status information STS for, for example, data write, read, and erase operations, and notifies an external device whether the operation has been completed successfully.

[0015] The address register 340 temporarily holds the address ADD received from an external device via the input / output circuit 310. The address register 340 also transfers the row address RA to the row decoder 520 and the column address CA to the column decoder 550.

[0016] The command register 350 temporarily stores the command CMD received from an external device via the input / output circuit 310 and transfers it to the sequencer 360.

[0017] The sequencer 360 controls the operation of the entire semiconductor device 1. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550, etc., in response to the command CMD held in the command register 350, and performs write operations, read operations, erase operations, etc.

[0018] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device depending on the operating status of the sequencer 360.

[0019] The voltage generation circuit 380 generates the voltages necessary for write, read, and erase operations in response to the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltage supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0020] The memory cell array 510 includes multiple blocks BLK (BLK0 to BLKn), where n is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cells associated with bit lines and word lines, and serves, for example, as a data erasure unit. The memory cells are configured, for example, as transistors, and hold non-volatile data.

[0021] By providing such memory cells, the semiconductor device 1 is configured as, for example, a NAND-type non-volatile memory.

[0022] The row decoder 520 decodes the row address RA. Based on the decoding result, the row decoder 520 selects one of the blocks BLK. The row decoder 520 also applies the required voltage to the block BLK.

[0023] During a read operation, the sense amplifier module 530 senses the data read from the memory cell array 510. The sense amplifier module 530 also transmits the read data RDT to the data register 540. During a write operation, the sense amplifier module 530 transmits the write data WDT to the memory cell array 510.

[0024] The data register 540 includes multiple latch circuits. The latch circuits hold the write data WDT and the read data RDT. For example, during a write operation, the data register 540 temporarily holds the write data WDT received from the input / output circuit 310 and transmits it to the sense amplifier module 530. Similarly, during a read operation, the data register 540 temporarily holds the read data RDT received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0025] The column decoder 550 decodes the column address CA during operations such as write, read, and erase, and selects a latch circuit in the data register 540 according to the decoding result.

[0026] The group of circuits arranged around the memory cell array 510 is also called the peripheral circuit. The peripheral circuit includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. The peripheral circuit may also include a status register 330, an address register 340, a command register 350, and a sequencer 360, and may further include an input / output circuit 310, a logic control circuit 320, a ready / busy circuit 370, and a voltage generation circuit 380.

[0027] Thus, the semiconductor device 1 comprises a memory cell array 510 containing multiple memory cells and peripheral circuits for operating the multiple memory cells.

[0028] (Circuit configuration of a memory cell array) Figure 2 is an equivalent circuit diagram showing an example of the configuration of a memory cell array 510 provided in the semiconductor device 1 according to the embodiment.

[0029] The memory cell array 510 comprises multiple block BLKs as described above. Each of the multiple block BLKs comprises multiple string units SUs. Each of the multiple string units SUs comprises multiple memory strings MSs. One end of each of the multiple memory strings MSs is connected to peripheral circuits such as the sense amplifier module 530 via a bit line BL. The other end of each of the multiple memory strings MSs is connected to peripheral circuits via a common source line SL.

[0030] A memory string MS comprises a drain selection transistor STD connected in series between the bit line BL and the source line SL, a plurality of memory cells MC, and a source selection transistor STS. Hereinafter, the drain selection transistor STD and the source selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0031] A memory cell MC is, for example, a field-effect transistor (FET) that includes a charge storage layer in its gate insulating layer. The threshold voltage of the memory cell MC changes depending on the amount of charge in the charge storage layer. By providing one or more threshold voltages, the memory cell MC may be able to store one bit or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to a single memory string MS. These word lines WL are each connected in common to all memory string MS in a single block BLK.

[0032] The selection transistors (STD, STS) are, for example, field-effect transistors. A selection gate line (SGD, SGS) is connected to the gate electrode of each selection transistor (STD, STS). The drain selection line SGD, connected to the drain selection transistor STD, is provided corresponding to a string unit SU and is commonly connected to all memory strings MS within a single string unit SU. The source selection line SGS, connected to the source selection transistor STS, is commonly connected to all memory strings MS within a single block BLK.

[0033] One end of the word line WL and the selection gate lines (SGD, SGS) are connected to peripheral circuits such as the low decoder 520.

[0034] (Circuit configuration of the sense amplifier module) Figure 3 is a circuit diagram showing an example of the configuration of the sense amplifier circuit SA and latch circuits DL and XDL included in the semiconductor device 1 according to the embodiment.

[0035] The sense amplifier module 530 described above consists of multiple sense amplifier circuits SA provided for each bit line BL. Each sense amplifier circuit SA senses the data read to the corresponding bit line BL, for example, during a read operation, and determines whether the read data is "0" or "1".

[0036] Furthermore, the aforementioned data register 540 includes multiple latch circuits DL and XDL, each corresponding to a multiple sense amplifier circuit SA. A latch circuit XDL is also provided for each bit line BL. On the other hand, multiple latch circuits DL are provided for each corresponding sense amplifier circuit SA. In this case, the number of latch circuits DL is designed based, for example, on the number of data bits that one memory cell MC can hold. The latch circuits DL and XDL temporarily hold the data associated with the corresponding bit line BL.

[0037] Figure 3 shows one sense amplifier circuit SA within the sense amplifier module 530 and one latch circuit DL,XDL within the data register 540. The multiple control signals supplied to the sense amplifier circuit SA and other components are controlled by the sequencer 360.

[0038] As shown in Figure 3, the sense amplifier circuit SA is composed of a transistor TR 31 ~TR 38 , and capacitor CAP are included. In the figure, transistor TR 31is a low-breakdown-voltage P-channel MOS (Metal-Oxide-Semiconductor) transistor. Also, transistor TR 32 ~TR 38 is a low-breakdown-voltage N-channel MOS transistor.

[0039] Low-breakdown-voltage CMOS transistors including low-breakdown-voltage P-channel MOS transistors and low-breakdown-voltage N-channel MOS transistors are transistors to which a relatively low voltage is applied, and are also called low-voltage (LV: Low Voltage, VLV: Very Low Voltage) MOS transistors.

[0040] One end of transistor TR 31 is connected to a power supply line to which a power supply voltage Vdd is supplied. The gate electrode of transistor TR 31 is connected to node INV. One end of transistor TR 32 is connected to the other end of transistor TR 31 The other end of transistor TR 32 is connected to node COM. A control signal BLX is input to the gate electrode of transistor TR 32 One end of transistor TR 33 is connected to node COM. The other end of transistor TR 33 is connected to the corresponding bit line BL. A control signal BLC is input to the gate electrode of transistor TR 33 One end of transistor TR

[0041] One end of transistor TR 34 is connected to node COM. The other end of transistor TR 34 is connected to node SRC. The gate electrode of transistor TR 34 is connected to node INV.

[0042] One end of transistor TR 35 is connected to the other end of transistor TR 31 The other end of transistor TR 35 is connected to node SEN. The other end of transistor TR 35The gate electrode of the transistor TR receives the control signal HLL. 36 One end is connected to node SEN, and transistor TR 36 The other end is connected to node COM, and transistor TR 36 The control signal XXL is input to the gate electrode.

[0043] Transistor (TR) 37 A clock signal CLK is input to one end of the transistor TR 37 The gate electrode of the transistor TR is connected to node SEN. 38 One end is a transistor TR 37 It is connected to the other end of the transistor TR 38 The other end is connected to the bus LBUS, and the transistor TR 38 The gate electrode of the capacitor receives the control signal STB. One end of capacitor CAP is connected to node SEN, and the other end of capacitor CAP receives the clock signal CLK.

[0044] The latch circuit DL consists of inverters IVa and IVb, and transistor TR. 41 ,TR 42 It is equipped with a transistor TR. 41 ,TR 42 This is a low-voltage N-channel MOS transistor. The following describes the transistor TR included in data register 540. 41 ,TR 42 These are sometimes simply called transistors (TR).

[0045] Although Figure 3 shows one latch circuit DL, other latch circuits DL have a similar configuration.

[0046] Inverter IVa has its input terminal connected to node LAT and its output terminal connected to node INV. Inverter IVb has its input terminal connected to node INV and its output terminal connected to node LAT.

[0047] Transistor (TR) 41One end is connected to node INV, the other end is connected to bus LBUS, and the control signal STI is input to the gate electrode. Transistor TR 42 One end is connected to node LAT, the other end is connected to bus LBUS, and the control signal STL is input to the gate electrode.

[0048] The latch circuit XDL has a configuration substantially similar to, for example, the latch circuit DL, and is connected to the bus LBUS so that it can transmit and receive data with the sense amplifier circuit SA and the latch circuit DL. The latch circuit XDL is also connected to the input / output circuit 310 described above and is used for data input and output between the sense amplifier circuit SA and the input / output circuit 310.

[0049] Furthermore, the latch circuit XDL is also used for the cache operation of the semiconductor device 1. In other words, even if all the latch circuits DL corresponding to the sense amplifier circuit SA are in use, the semiconductor device 1 can still receive data from the outside as long as the latch circuit XDL is available.

[0050] Thus, the sense amplifier circuit SA and latch circuits DL and XDL, which belong to the peripheral circuitry, are equipped with multiple transistors TR.

[0051] Next, we will briefly explain the operation of the sense amplifier circuit SA with the above configuration.

[0052] As an example of writing data to a memory cell MC, when charge is injected into the memory cell MC to raise the threshold, the node INV of the latch circuit DL stores an "H" level ("1" data). This causes the transistor TR 34 When the switch is turned on, the bit line BL is set to 0V.

[0053] Another example of writing data to a memory cell MC is when no charge is injected into the memory cell MC and the threshold is not changed; in this case, the node INV of the latch circuit DL stores an "L" level ("0" data). This causes the transistor TR 31 The switch is turned on, and a predetermined positive voltage is applied to the bit line BL.

[0054] During readout, node INV is set to the "L" level, and transistor TR 31 The transistor TR is turned on. 41 ,TR 42 Through the bit line BL, the transistor TR 31 It is precharged by the transistor TR. 35 The device is also turned on, and node SEN is charged to the predetermined potential.

[0055] Subsequently, the transistor TR 35 When the transistor TR is turned off, the signal XXL is set to "H" level. 36 This is turned on. As a result, if the corresponding memory cell MC is turned on, the potential of node SEN decreases, and transistor TR 37 The transistor TR is turned off. On the other hand, if the corresponding memory cell MC is turned off, the potential of node SEN remains at the "H" level, and the transistor TR 37 It will be turned on.

[0056] Furthermore, the signal STB controls the transistor TR 38 When it is turned on, the transistor TR 37 The potential corresponding to the on / off state is read to the bus LBUS and held in the latch circuit DL.

[0057] Note that the circuit configurations of the sense amplifier circuit SA and latch circuits DL and XDL shown in Figure 3 are just examples, and the sense amplifier circuit SA and latch circuits DL and XDL can take various other configurations. Therefore, the number and types of transistors TR included in the sense amplifier circuit SA and latch circuits DL and XDL can also vary. For example, the sense amplifier circuit SA and latch circuits DL and XDL may be configured to include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors.

[0058] (Raw Decoder Circuit Configuration) Figure 4 is a circuit diagram showing an example of the configuration of a low decoder 520 provided in the semiconductor device 1 according to the embodiment.

[0059] As shown in Figure 4, the row decoder 520 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23.

[0060] The address decoder 21 includes multiple block selection lines BLKSEL and multiple voltage selection lines VOLSEL.

[0061] The address decoder 21, for example, refers to the address data of the address register 340 included in the peripheral circuit described above, according to a control signal from the sequencer 360.

[0062] Furthermore, the address decoder 21 decodes the referenced address data and determines the transistor TR corresponding to the address data. 22 and transistor TR 23 Turn on the other transistors TR 22 and transistor TR 23 Turn it off. Note that the transistor TR 22 and transistor TR 23 These are transistors included in the block selection circuit 22 and the voltage selection circuit 23, respectively, which will be described later.

[0063] Furthermore, the address decoder 21 sets the voltage of the block selection line BLKSEL and voltage selection line VOLSEL corresponding to the address data to a "H" state, for example, and sets all other voltages to a "L" state. Note that the voltages applied to these wires will be reversed depending on whether N-channel or P-channel transistors are used in the block selection circuit 22 and voltage selection circuit 23. The voltages described above are examples for the case where the transistor is an N-channel type.

[0064] In the example shown in Figure 4, the address decoder 21 is provided with one block selection line BLKSEL for each block BLK in the memory cell array 510. However, this configuration can be changed as appropriate. For example, it may be provided with one block selection line BLKSEL for each of two or more block BLKs.

[0065] The block selection circuit 22 comprises a plurality of block selection units 220, each corresponding to a block BLK of the memory cell array 510. Each of these plurality of block selection units 220 comprises a plurality of transistors TR, each corresponding to a word line WL and a selection gate line (SGD, SGS). 22 It is equipped with.

[0066] Transistor (TR) 22 This is a high-voltage N-channel MOS transistor that functions as a block drive transistor. 22 The drain electrodes of each transistor are electrically connected to the corresponding word line WL or select gate line (SGD, SGS). 22 The source electrodes are electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23, respectively. Transistor TR 22 The gate electrode is commonly connected to the corresponding block selection line BLKSEL.

[0067] Furthermore, the block selection circuit 22 further comprises several transistors (not shown). These transistors are high-voltage CMOS transistors connected between the selection gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors connect the selection gate lines (SGD, SGS) included in the unselected block BLK in the memory cell array 510 to the ground voltage supply terminal. Note that the multiple word lines WL included in the unselected block BLK are in a floating state.

[0068] The voltage selection circuit 23 includes a plurality of voltage selection units 230 corresponding to the word line WL and the selection gate lines (SGD, SGS). Each of these plurality of voltage selection units 230 is comprised of a plurality of transistors TR 23 It is equipped with.

[0069] Transistor (TR) 23 This is a high-voltage N-channel MOS transistor that functions as a voltage-selective transistor. 23The drain terminals are electrically connected to the corresponding word line WL or selection gate line (SGD, SGS) via wiring WR and block selection circuit 22, respectively. The source terminals are electrically connected to the corresponding voltage output terminal OTM, respectively. The gate electrodes are connected to the corresponding voltage selection line VOLSEL, respectively.

[0070] High-voltage CMOS transistors, including the high-voltage P-channel MOS transistors and high-voltage N-channel MOS transistors mentioned above, are transistors to which relatively high voltages are applied, and are also called high-voltage (HV) MOS transistors.

[0071] Thus, the low decoder 520, which belongs to the peripheral circuitry, consists of multiple transistors TR 22 ,TR 23 It includes the following. However, the circuit configuration of the low decoder 520 shown in Figure 4 is just one example, and the transistor TR included in the low decoder 520 22 ,TR 23 The number and types of these items can also vary considerably.

[0072] [Physical configuration of semiconductor equipment] Next, an example of the physical configuration of the semiconductor device 1 of the embodiment will be described using Figure 5.

[0073] Figure 5 is a cross-sectional view showing an example configuration of the semiconductor device 1 according to the embodiment. However, in Figure 5, hatching of some components is omitted for the sake of readability.

[0074] Note that the X and Y directions shown in Figure 5 are mutually orthogonal. Furthermore, in Figure 5, the X direction is the direction perpendicular to the extension direction of the gate electrodes GEv and GEh, which will be described later, that is, the direction along the gate length of the gate electrodes GEv and GEh. The Y direction is the direction along the gate width of the gate electrodes GEv and GEh.

[0075] As shown in Figure 5, the semiconductor device 1 comprises, in this order, a peripheral circuit CBA, a laminate LM including multiple word lines WL with pillars PL formed on it, a source line SL, and an electrode layer EL above the semiconductor substrate SB. In the following description, the side on which the semiconductor substrate SB is located will be referred to as the lower side of the semiconductor device 1.

[0076] The semiconductor substrate SB is, for example, a flaked silicon substrate. Above the semiconductor substrate SB, multiple semiconductor layers DB are arranged, each having a smaller area than the top surface of the semiconductor substrate SB. These semiconductor layers DB are, for example, polysilicon layers.

[0077] Between the semiconductor substrate SB and multiple semiconductor layers DB, a peripheral circuit CBA is arranged, in which multiple transistors TRv and TRh are stacked in multiple stages. Of these transistors TRv and TRh, transistor TRv is located on the semiconductor substrate SB, and transistor TRh is located on the surface of semiconductor layer DB facing the semiconductor substrate SB.

[0078] In other words, these transistors TRh are positioned above the transistors TRv on the semiconductor substrate SB, in an inverted state relative to the transistors TRv. However, these transistors TRh and TRv may be positioned so that they overlap vertically, as shown in Figure 5, or some or all of them may be positioned so that they do not overlap vertically.

[0079] The semiconductor substrate SB is provided with an insulating layer 31 covering the transistor TRv on the semiconductor substrate SB. The semiconductor layer DB is provided with an insulating layer 32 covering the transistor TRh on the semiconductor layer DB. The semiconductor substrate SB and the semiconductor layer DB are bonded together via these insulating layers 31 and 32, so that multiple transistors TRv and TRh are stacked in multiple layers.

[0080] A transistor TRv on a semiconductor substrate SB comprises a source / drain region SDv, a gate insulating layer GXv, a gate electrode GEv, and a liner layer LLv.

[0081] The source / drain regions SDv are spaced apart on the semiconductor substrate SB and are regions where impurities of a predetermined conductivity type are diffused. The gate electrode GEv is positioned on the semiconductor substrate SB, spanning the spaced-apart source / drain regions SDv, via a gate insulating layer GXv. The gate electrode GEv and the gate insulating layer GXv are entirely covered by a liner layer LLv. The liner layer LLv is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or has a multilayer structure combining several of these layers.

[0082] These transistors TRv are configured as low-voltage (LV,VLV) MOS transistors to which a relatively low voltage is applied, and are included in the peripheral circuit CBA, for example, the sense amplifier module 530 (see Figure 3), as well as the input / output circuit 310, the logic control circuit 320, and the ready / busy circuit 370 (see Figure 1), which serve as interfaces with external devices.

[0083] The transistors TRv used in these interface circuits are required to operate at high speeds, and it is preferable that they be configured to have a relatively short gate length. For this reason, the gate electrode GEv of the transistor TRv is made of, for example, a tungsten layer or a nickel-platinum silicide layer. These tungsten layers or nickel-platinum silicide layers are suitable gate electrode materials for low-voltage MOS transistors that require high-speed operation and have a relatively short gate length.

[0084] As described above, in Figure 5, the distance along the X direction of the gate electrodes GEv and GEh of individual transistors TRv and TRh corresponds to the gate length of the gate electrodes GEv and GEh in these transistors TRv and TRh, and the distance along the Y direction of the gate electrodes GEv and GEh corresponds to the gate width of the gate electrodes GEv and GEh in these transistors TRv and TRh.

[0085] The source / drain region SDv and gate electrode GEv of these transistors TRv are connected to contacts CSv and CGv, respectively, which extend through the insulating layer 31 covering the transistors TRv. Each of these contacts CSv and CGv is connected, in order from the transistor TRv side, to the wiring layer D0v, via C1v, wiring layer D1v, etc., located within the insulating layer 31. As a result, some of the multiple transistors TRv are connected to transistors TRh located opposite them, while others are connected to the electrode layer EL via contacts C3, which extend vertically at the same layer as the laminate LM.

[0086] A transistor TRh on a semiconductor layer DB comprises a source / drain region SDh, a gate insulating layer GXh, a gate electrode GEh, and a liner layer LLh.

[0087] The source / drain regions SDh are spaced apart in the semiconductor layer DB and are regions where impurities of a predetermined conductivity type are diffused. The gate electrode GEh is positioned on the semiconductor layer DB, spanning the spaced-apart source / drain regions SDh, via a gate insulating layer GXh. The gate electrode GEh and the gate insulating layer GXh are entirely covered by a liner layer LLh. The liner layer LLh is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or has a multilayer structure combining several of these layers.

[0088] These transistors TRh are configured, for example, as high-voltage (HV) MOS transistors to which a relatively high voltage is applied. However, some of these transistors TRh may be configured as low-voltage (VLV) MOS transistors. These transistors TRh on the semiconductor layer DB are included in the peripheral circuit CBA, for example, the low decoder 520 (see Figure 4).

[0089] Furthermore, high-voltage transistors (TRh) do not require the same high-speed operation as low-voltage MOS transistors. For this reason, the gate electrode material (GEh) of transistor TRh can be made from a gate electrode material that is relatively easy to process, such as a tungsten silicide layer or a tungsten nitride layer, rather than the tungsten layer or nickel-platinum silicide layer used as the gate electrode material for low-voltage MOS transistors.

[0090] Furthermore, the transistor TRh to which high voltage is applied is configured to have a higher voltage rating than, for example, the low-voltage transistor TRv mentioned above.

[0091] Specifically, the gate insulating layer GXh of these transistors TRh is formed to be thicker than, for example, the gate insulating layer GXv of the transistor TRv described above. Also, the gate electrode GEh of these transistors TRh has a longer gate length than, for example, the gate electrode GEv of the transistor TRv described above.

[0092] Furthermore, a single-crystal semiconductor substrate SB exhibits higher carrier mobility than a semiconductor layer DB, such as a polysilicon layer. Therefore, by placing the low-voltage transistor TRv, which requires high-speed operation in certain applications, on the semiconductor substrate SB, the operating performance of transistor TRv can be improved.

[0093] Contacts CSh and CGh, extending through the insulating layer 32 covering the transistor TRh, are connected to the source / drain region SDh and gate electrode GEh of the transistor TRh. Each of these contacts, CSh and CGh, is connected, in order from the transistor TRh side, to the wiring layer D0h, via C1h, wiring layer D1h, etc., located within the insulating layer 32. As a result, some of the multiple transistors TRh are connected to transistor TRv located opposite them, while others are connected to contact CC, described later, which supplies power to the word line WL, via contact C4 extending toward the laminate LM side.

[0094] Furthermore, the peripheral circuit CBA described above may include, in addition to transistors TRv and TRh, contacts CSv and CGv, wiring layer D0v, via C1v, and wiring layer D1v... connected to these transistors TRv and TRh, respectively, as well as contacts CSh and CGh, wiring layer D0h, via C1h, and wiring layer D1h...

[0095] Above the peripheral circuit CBA, an insulating layer 40 is positioned to cover the upper surface of an insulating layer 32 which includes multiple semiconductor layers DB. The insulating layer 40 has an area at least larger than the semiconductor layers DB mentioned above and covers the entire semiconductor substrate SB on which the peripheral circuit CBA is provided.

[0096] Furthermore, the insulating layer 40 is preferably a silicon oxide layer such as an NSG (Nondoped Silicate Glass) layer, and the carbon concentration is lower than that of other parts of the insulating layer 40, at least from the side in contact with the semiconductor layer DB up to a predetermined thickness. The carbon concentration of the insulating layer 40 in the low carbon concentration portion is, for example, 1 × 10⁻⁶. 18 pieces / cm 3 The following is preferable. However, the entire insulating layer 40 may have a low carbon concentration. This makes it possible to suppress leakage current from the semiconductor layer DB on which the transistor TRh is provided.

[0097] Above the peripheral circuit CBA, a laminate LM is arranged with multiple word lines WL stacked spaced apart from each other, separated by an insulating layer 40. One or more selection gate lines SGS (see Figure 2) may be stacked on the lower side of the multiple word lines WL, i.e., on the peripheral circuit CBA side. Also, one or more selection gate lines SGD (see Figure 2) may be stacked on the upper side of the multiple word lines WL, i.e., on the opposite side of the peripheral circuit CBA. The laminate LM containing the multiple word lines WL is covered with an insulating layer 50, and the peripheral circuit CBA is joined to this insulating layer 50 and the insulating layer 40 mentioned above.

[0098] The insulating layer 50 extends around the laminate LM. Contacts C3 are arranged in the surrounding insulating layer 50, extending through the insulating layer 50 in the stacking direction of multiple word lines WL. Contacts C3 are electrically connected to some of the transistors TRv provided on the semiconductor substrate SB. This electrically connects the peripheral circuit CBA and the source line SL.

[0099] A memory region MR is located in the center of the stacked structure LM in the X direction, and stepped regions SR are located at both ends of the stacked structure LM in the X direction.

[0100] Multiple pillars PL are arranged in the memory region MR, penetrating the word lines WL in the stacking direction. Memory cells MC (see Figure 2) are formed at the intersections of the pillars PL and the word lines WL. Selective gate lines STD and STS (see Figure 2) are formed at the intersections of the pillars PL and the selective gate lines SGD and SGS, respectively. Thus, the semiconductor device 1 is configured as a three-dimensional non-volatile memory, for example, in which memory cells MC are arranged three-dimensionally in the memory region MR.

[0101] Thus, the memory region MR is an example of a physical configuration corresponding to the memory cell array 510 (see Figure 2) described above. Furthermore, the pillar PL is an example of a physical configuration corresponding to the memory string MS (see Figure 2) described above, in which memory cells MC and the like are connected in series.

[0102] In the physical configuration of semiconductor device 1, the pillar PL is electrically connected to the sense amplifier module 530 of the peripheral circuit CBA via a bit line BL or the like located below the pillar PL.

[0103] In the staircase region SR, staircase sections SP are arranged, each with multiple word lines WL and other elements processed in a staircase shape at both ends. As a result, the width of each end of the multiple word lines WL and other elements widens as it moves towards the source line SL above. Each layer of multiple word lines WL and other elements in the staircase section SP is connected to a contact CC.

[0104] These contact CCs allow the stacked word lines WLs to be individually drawn out. In other words, from these contact CCs, write voltages and read voltages are applied to memory cells MCs located in the central memory region MR in the direction of extension of multiple word lines WLs, via the word lines WLs at the same height as the memory cells MCs.

[0105] The various voltages applied from the contact CC to the memory cell MC are controlled by the low decoder 520 of the peripheral circuit CBA, which is electrically connected to these contact CCs.

[0106] A source wire SL is positioned above a laminate LM containing multiple word wires WL, etc. An electrode layer EL is positioned on the source wire SL via an insulating layer 60 such as a silicon oxide layer. Multiple plugs PG are positioned within the insulating layer 60, electrically connecting the electrode layer EL and the source wire SL. In addition, the electrode layer EL has a pad region PD that penetrates the insulating layer 60 and the source wire SL in some areas and has electrical conductivity with contact C3.

[0107] With this configuration, a source potential can be applied to the source line SL via the electrode layer EL from outside the semiconductor device 1.

[0108] Incidentally, some of the transistors TRv mentioned above are connected to contact C3, which is on the same layer as the laminate LM, via contact CSv, wiring layer D0v, via C1v, and wiring layer D1v.... Also, some of the transistors TRh mentioned above are connected to contact C4, which leads to contact CC of the laminate LM, via contact CSh, wiring layer D0h, via C1h, and wiring layer D1h....

[0109] In this configuration, contacts CSv, wiring layer D0v, via C1v, wiring layer D1v..., and contact C3, as well as contact CSh, wiring layer D0h, via C1h, wiring layer D1h..., and contact C4, extend through insulating layers 31, 32, and 40. This maintains insulation from the surrounding components and suppresses the occurrence of parasitic capacitance and other issues.

[0110] [Manufacturing method for semiconductor devices] Next, the method for manufacturing the semiconductor device 1 according to the embodiment will be described using Figures 6 to 13. Figures 6 to 13 are cross-sectional views illustrating, in order, a part of the procedure for manufacturing the semiconductor device 1 according to the embodiment.

[0111] As shown in Figure 6(a), an insulating layer 40 and a semiconductor layer DBb are formed on a support substrate HN in this order. The support substrate HN is a semiconductor substrate such as a silicon substrate, the insulating layer 40 is a silicon oxide layer, and the semiconductor layer DBb is a polysilicon layer. However, the semiconductor substrate HN may be an insulating substrate such as a ceramic substrate, or a conductive substrate. Furthermore, the semiconductor layer DBb is a layer that will be patterned afterward to become a semiconductor layer DB on which the transistor TRh will be formed.

[0112] Furthermore, it is preferable that the insulating layer 40 be formed as a silicon oxide layer such as a high-quality NSG layer with a low carbon concentration, for example, by using a thermal chemical vapor deposition (CVD) method. By using thermal CVD, the carbon concentration can be reduced to, for example, 1 × 10⁻⁶. 18 pieces / cm 3 The following high-quality NSG layers can be formed.

[0113] As shown in Figure 6(b), an insulating layer GXb and a conductive layer GEb are formed on the semiconductor layer DBb in this order. The insulating layer GXb is, for example, a silicon oxide layer, or a high-k insulating layer such as a hafnium oxide layer or a zirconia layer, and is later patterned to become the gate insulating layer GXh of the transistor TRh. The conductive layer GEb is, for example, a tungsten silicide layer or a tungsten nitride layer, and is later patterned to become the gate electrode GEh of the transistor TRh.

[0114] As shown in Figure 6(c), the insulating layer GXb and the conductive layer GEb are patterned to form the gate insulating layer GXh and the gate electrode GEh, respectively.

[0115] Furthermore, using the gate insulating layer GXh and the gate electrode GEh as masks, impurities of a predetermined conductivity type are injected into the semiconductor layer DBb to form source / drain regions SDh at the lower ends on both sides in the X direction of the gate insulating layer GXh and the gate electrode GEh.

[0116] Furthermore, an insulating layer LLb is formed on the semiconductor layer DBb, covering the gate insulating layer GXh and the gate electrode GEh. The insulating layer LLb is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or it has a multilayer structure combining several of these layers, and is later patterned to become the liner layer LLh of the transistor TRh.

[0117] As shown in Figure 7(a), the insulating layer LLb is patterned to form a liner layer LLh that covers the gate insulating layer GXh and the gate electrode GEh. In addition, the semiconductor layer DBb is patterned to form a semiconductor layer DB in which transistors TRh are individually arranged.

[0118] As shown in Figure 7(b), an insulating layer 32 covering the semiconductor layer DB and transistor TRh is formed on the insulating layer 40 of the support substrate HN as appropriate, and contacts CSh, CGh, wiring layer D0h, via C1h, wiring layer D1h, via C2h, and wiring layer D2h are sequentially formed in the insulating layer 32. At this time, wiring layers and the like that interpose the connection between transistor TRv on the semiconductor substrate SB and contact C3 formed at the same layer as the laminate LM may also be formed in the insulating layer 32.

[0119] As shown in Figure 8, a semiconductor substrate SB on which transistor TRv is formed and a support substrate HN on which transistor TRh is formed are arranged so that transistors TRv and TRh face each other, and these semiconductor substrates SB and support substrate HN are bonded together. Note that the transistor TRv on the semiconductor substrate SB can be formed using the same method as the transistor TRv on the semiconductor layer DB.

[0120] Specifically, a gate insulating layer GXv and a gate electrode GEv are formed on a semiconductor substrate SB in this order, a source / drain region SDv is formed on the semiconductor substrate SB using the gate insulating layer GXv and gate electrode GEv as a mask, and a liner layer LLv is formed to cover the gate insulating layer GXv and gate electrode GEv to form a transistor TRv.

[0121] Furthermore, while appropriately forming an insulating layer 31 covering the transistor TRv, contacts CSv, CGv, wiring layer D0v, via C1v, wiring layer D1v, via C2v, and wiring layer D2v are sequentially formed within the insulating layer 31.

[0122] As shown in Figure 9, when bonding the semiconductor substrate SB and the support substrate HN, the insulating layers 31 and 32 formed on the semiconductor substrate SB and the support substrate HN, respectively, are joined together. These insulating layers 31 and 32 can be joined by, for example, activating their surfaces in advance by plasma treatment or the like.

[0123] Furthermore, when joining the insulating layers 31 and 32, the semiconductor substrate SB and the support substrate HN are aligned so that the wiring layers D2v and D2h, which are connected to transistors TRv and TRh and brought out onto the surfaces of the insulating layers 31 and 32 respectively, overlap in the vertical direction.

[0124] After bonding the insulating layers 31 and 32, an annealing process is performed to bond these wiring layers D2v and D2h, for example, by a Cu-Cu bond. This bonds the support substrate HN and the semiconductor substrate SB. The bonded product of the support substrate HN and the semiconductor substrate SB is also called a bonded substrate.

[0125] As shown in Figure 10(a), the support substrate HN is removed from the bonded substrate of the support substrate HN and the semiconductor substrate SB to expose the insulating layer 40. After the removal of the support substrate HN, the semiconductor substrate SB also functions as a support substrate that supports the overall structure of transistors TRv, TRh, etc.

[0126] As shown in Figure 10(b), a contact C3c is formed from the side of the insulating layer 40, which is exposed by removing the support substrate HN, penetrating the insulating layers 40 and 32, and extending further through the insulating layer 31 to reach the wiring layer D2v which is electrically connected to the transistor TRv. Also, a contact C4 is formed from the side of the insulating layer 40, penetrating the insulating layer 40, and extending further through the insulating layer 32 to reach the wiring layer D2h which is electrically connected to the transistor TRh. Electrode pads or the like may be provided at the upper ends of each contact C3c and C4.

[0127] As shown in Figure 11, a support substrate SS on which a laminate LM having pillars PL and contacts CC is formed, and a semiconductor substrate SB on which transistors TRv and TRh are stacked in multiple layers are arranged so that the laminate LM and the transistors TRv and TRh face each other, and these support substrate SS and semiconductor substrate SB are bonded together. Here, the laminate LM having pillars PL and contacts CC can be formed as follows.

[0128] Specifically, a support substrate SS is prepared, which is a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate. An insulating layer 60 and a source wire SL are formed on the support substrate SS in that order, and then multiple sacrificial layers (not shown) are laminated on the source wire SL, spaced apart from each other. The multiple sacrificial layers are silicon nitride layers, etc., which will later be replaced by conductive layers such as a tungsten layer to become a word wire WL, etc.

[0129] Multiple sacrificial layers are processed into a stepped shape at both ends in the X direction to form a stepped section SP, and the entire structure is covered with an insulating layer 50. Multiple pillars PL are formed that penetrate the multiple sacrificial layers and reach the source wire SL, and bit wires BL are formed in the insulating layer 50 above the pillars PL and connected to the pillars PL. Multiple sacrificial layers are replaced with conductive layers such as tungsten layers to form a laminate LM having multiple word wires WL, etc. Contacts CC are formed in the stepped section SP of the laminate LM, penetrating the insulating layer 50 covering the laminate LM and connected to the individual word wires WL, etc. Contacts C3 are formed on the outside of the laminate LM in the X direction, penetrating the insulating layer 50 and reaching the source wire SL.

[0130] As shown in Figure 12, the semiconductor substrate SB and the support substrate SS can be bonded together using the same method as described above for bonding the semiconductor substrate SB and the support substrate HN.

[0131] In other words, insulating layers 40 and 50 formed on the semiconductor substrate SB and the support substrate SS are joined together. These insulating layers 40 and 50 can be joined by, for example, activating their surfaces in advance through plasma treatment or the like.

[0132] Furthermore, when joining the insulating layers 40 and 50, the semiconductor substrate SB and the support substrate SS are aligned so that the contacts C3c and C4, which are connected to the transistors TRv and TRh and brought out onto the surface of the insulating layer 40, respectively, and the contacts C3 and CC, which are formed on the laminate LM side, overlap in the vertical direction.

[0133] After bonding the insulating layers 40 and 50, an annealing process is performed to bond these contacts C3c, C3, and C4, CC, for example, by Cu-Cu bonding. This bonds the support substrate SS and the semiconductor substrate SB.

[0134] As shown in Figure 13(a), the support substrate SS is removed to expose the insulating layer 60. Note that from this point onward in Figure 13, the diagrams of the components below the insulating layer 40 are omitted.

[0135] As shown in Figure 13(b), multiple plugs PG are formed that penetrate the exposed insulating layer 60 and reach the source wire SL. In addition, a portion of the insulating layer 60 and the source wire SL are removed to form a recess RS, and the contact C3 is exposed from the bottom surface of the recess RS.

[0136] As shown in Figure 13(c), a conductive layer is formed and patterned over the insulating layer 60 to form the electrode layer EL. The electrode layer EL is also formed within the recess RS described above, thereby forming the pad region PD that connects to the contact C3.

[0137] As described above, the semiconductor device 1 of the embodiment is manufactured.

[0138] [Summary] Semiconductor devices such as three-dimensional non-volatile memory include peripheral circuits that control the electrical operation of memory cells, for example. These peripheral circuits include multiple transistors formed on a semiconductor substrate. With the increasing demand for increased memory capacity and miniaturization of semiconductor devices, the number of transistors included in peripheral circuits is increasing. Therefore, attempts have been made to construct peripheral circuits in which multiple transistors are stacked in multiple layers by forming transistors individually on multiple semiconductor substrates and bonding these semiconductor substrates together.

[0139] However, when electrically connecting a transistor formed on the lower semiconductor substrate, that is, the semiconductor substrate furthest from the laminate where pillars etc. are formed, to an electrode layer above the laminate, it becomes necessary to form a contact that penetrates the upper semiconductor substrate. In this case, parasitic capacitance occurs between the contact and the semiconductor substrate, which may lead to a decrease in the quality and transmission speed of signal transmission between the transistor and the contact.

[0140] Furthermore, when bonding multiple semiconductor substrates, each individually formed with a transistor, it is preferable that the semiconductor substrates be bonded so that the transistors in the upper and lower layers face each other in order to electrically connect the multilayered transistors. In this case, when electrically connecting the transistors formed on the upper semiconductor substrate to the configuration of the laminate, it is necessary to form contacts that penetrate the upper semiconductor substrate, which can similarly lead to a decrease in signal transmission quality and transmission speed.

[0141] According to the embodiment of the semiconductor device 1, it comprises a transistor TRv provided on a semiconductor substrate SB and a transistor TRh provided on the side of the semiconductor layer DB facing the semiconductor substrate SB. As a result, by stacking transistors TRv and TRh in multiple layers, a peripheral circuit CBA can be configured that has a number of transistors TRv and TRh corresponding to the semiconductor device 1, which has increased memory capacity and miniaturization.

[0142] According to the semiconductor device 1 of the embodiment, it comprises a semiconductor layer DB provided above the semiconductor substrate SB and having a smaller area than the semiconductor substrate SB, and a contact C3c extending upward from the transistor TRv through the insulating layer 40 at a position that does not overlap the semiconductor layer DB in the vertical direction.

[0143] Thus, since the upper transistor TRh is formed on the small-area semiconductor layer DB, the transistor TRv formed on the lower semiconductor substrate SB of semiconductor layer DB can be connected to the laminate LM configuration without penetrating, for example, the upper semiconductor substrate, by contact C3c or the like. Therefore, multiple transistors TRv and TRh can be stacked while suppressing an increase in parasitic capacitance.

[0144] According to the semiconductor device 1 of the embodiment, the insulating layer 40 has a carbon concentration of 1 × 10⁻¹⁶ on at least the side in contact with the semiconductor layer DB. 18 pieces / cm 3 The following is the result. This makes it possible to suppress leakage current from the semiconductor layer DB on which the transistor TRh is provided.

[0145] According to the semiconductor device 1 of this embodiment, transistor TRv is a low-voltage MOS transistor, and transistor TRh is a high-voltage MOS transistor. By providing the low-voltage transistor TRv, which is required to operate at high speed in some applications, on a semiconductor substrate SB with higher carrier mobility, the operating performance of transistor TRv can be improved.

[0146] In the above embodiment, the insulating layer 40 and the semiconductor layer DBb were formed in this order on the support substrate HN to form the transistor TRh. However, it is also possible to form the transistor TRh using an SOI (Silicon on Insulator) substrate. An SOI substrate is a substrate in which a single-crystal silicon layer is formed on a silicon substrate called a handle substrate, via a silicon oxide layer called a BOX (Buried Oxide) layer.

[0147] When using an SOI substrate, a transistor TRh can be formed on a single-crystal silicon layer. In this case, the handle substrate, BOX layer, and single-crystal silicon layer of the SOI substrate correspond to the support substrate HN, insulating layer 40, and semiconductor layer DBb described above, respectively.

[0148] [Differentiation] Next, a modified semiconductor device 2 of the embodiment will be described using Figure 14. In the modified semiconductor device 2, the orientation of transistors TRv and TRh relative to each other differs from that of the embodiment described above.

[0149] Figure 14 is a cross-sectional view showing an example of the configuration of a semiconductor device 2 according to a modified embodiment. However, in Figure 14, hatching of some components is omitted for the sake of readability. Also, in Figure 14, components similar to those in the above-described embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0150] As shown in Figure 14, the modified semiconductor device 2 also includes a peripheral circuit CBAa containing multilayer stacked transistors TRv and TRh. However, an insulating layer 40 is interposed between transistors TRv and TRh, and transistors TRv and TRh do not face each other in the vertical direction.

[0151] In other words, the bonding surface between the semiconductor substrate SB on which transistor TRv is formed and the semiconductor layer DB on which transistor TRh is formed is the interface between the insulating layer 31 covering the semiconductor substrate SB and the insulating layer 40 provided on the lower surface of the semiconductor layer DB.

[0152] Furthermore, the vertical orientation of these transistors TRv and TRh is the same, and when electrically connecting transistors TRv and TRh to each other, contacts that penetrate the insulating layer 40 can be provided. Even in this case, since there is no semiconductor substrate or the like interposed between these transistors TRv and TRh, the occurrence of parasitic capacitance can be suppressed.

[0153] A modified semiconductor device 2 can be obtained, for example, by the following manufacturing method.

[0154] In other words, an insulating layer 40 and a semiconductor layer DB are formed in this order, and a support substrate HN on which a transistor TRh is further formed on the semiconductor layer DB and a support substrate SS on which a laminate LM including pillars PL and contacts CC is formed are bonded together by joining an insulating layer 32 covering the transistor TRh and an insulating layer 50 covering the laminate LM.

[0155] Furthermore, the support substrate HN bonded to the support substrate SS is removed to expose the insulating layer 40. In addition, the semiconductor substrate SB on which the transistor TRv is formed and the support substrate SS having the laminate LM and the transistor TRh are bonded together by joining the insulating layer 31 covering the transistor TRv and the insulating layer 40 on the support substrate HN side.

[0156] Subsequently, the modified semiconductor device 2 is manufactured by performing the process shown in Figure 13 of the above embodiment.

[0157] Thus, by stacking multiple transistors TRv and TRh in multiple stages so that their orientations in the vertical direction are equal, it is possible to stack these transistors TRv and TRh in three or more stages.

[0158] The modified semiconductor device 2 also provides the same effects as the embodiment described above.

[0159] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0160] 1,2... Semiconductor equipment, 31,32,40,50,60... Insulating layers, C1h,C1v,C2h,C2v... Vias, C3,C4,CC,CGh,CGv,CSh,CSv... Contacts, CBA,CBAa... Peripheral circuits, D0h~D2h,D0v~D2v... Wiring layers, DB... Semiconductor layer, HN,SS... Support substrate, MC... Memory cell, PL... Pillar, SB... Semiconductor substrate, WL... Word line.

Claims

1. Semiconductor substrate and A first transistor provided on the semiconductor substrate, A semiconductor layer provided above the semiconductor substrate and having a smaller area than the semiconductor substrate, A second transistor is provided on the side of the semiconductor layer facing the semiconductor substrate, An insulating layer provided on the semiconductor layer and having a larger area than the semiconductor layer, The device comprises a contact extending upward from the first transistor, penetrating the insulating layer, at a position that does not overlap the semiconductor layer in the vertical direction, Semiconductor equipment.

2. The insulating layer is At least on the side in contact with the semiconductor layer, the carbon concentration is 1 × 10 １８ pieces / cm ３ The following applies: The semiconductor device according to claim 1.

3. The first transistor described above is The first gate electrode and It has a first gate insulating layer, The second transistor described above is A second gate electrode having a longer gate length than the first gate electrode, The invention has a second gate insulating layer that is thicker than the first gate insulating layer, The semiconductor device according to claim 1.

4. The first transistor is a low-voltage MOS transistor, The second transistor is a high-voltage MOS transistor. The semiconductor device according to claim 1.

5. A laminate is provided above the insulating layer, and a plurality of conductive layers are stacked spaced apart from each other, The laminate further comprises pillars extending within the laminate in the stacking direction of the laminate, The semiconductor device according to claim 1.

6. Semiconductor substrate and A first transistor provided on the semiconductor substrate, An insulating layer provided on the semiconductor substrate and covering the first transistor, A semiconductor layer is provided in the insulating layer, facing the semiconductor substrate, and having a smaller area than the semiconductor substrate. A second transistor is provided on the side of the semiconductor layer facing the semiconductor substrate, The device comprises a contact extending upward from the first transistor, penetrating the insulating layer, at a position that does not overlap the semiconductor layer in the vertical direction, The insulating layer is It has a first portion having a predetermined layer thickness, including a surface that is in contact with the upper surface of the semiconductor layer, The first part is, The insulating layer has a lower carbon concentration than other parts of it. Semiconductor equipment.

7. The first part is, The carbon concentration is 1 × 10 １８ pieces / cm ３ The following is: The semiconductor device according to claim 6.

8. The first transistor described above is The first gate electrode and It has a first gate insulating layer, The second transistor described above is A second gate electrode having a longer gate length than the first gate electrode, The invention has a second gate insulating layer that is thicker than the first gate insulating layer, The semiconductor device according to claim 6.

9. The first transistor is a low-voltage MOS transistor, The second transistor is a high-voltage MOS transistor. The semiconductor device according to claim 6.

10. A laminate is provided above the insulating layer, and a plurality of conductive layers are stacked spaced apart from each other, The laminate further comprises pillars extending within the laminate in the stacking direction of the laminate, The semiconductor device according to claim 6.

11. A first transistor is formed on a first semiconductor substrate. A first insulating layer covering the first transistor is formed on the first semiconductor substrate. A second semiconductor substrate is prepared in which a semiconductor layer is formed via a second insulating layer. A second transistor is formed on the semiconductor layer of the second semiconductor substrate, and the semiconductor layer is patterned to have a smaller area than the first semiconductor substrate. A third insulating layer is formed on the second semiconductor substrate, covering the second transistor and the patterned semiconductor layer. The first and second semiconductor substrates are bonded together with the first and third insulating layers to form a bonded substrate. The second semiconductor substrate is removed from the laminated substrate. A contact is formed at a position that does not overlap the semiconductor layer in the vertical direction, extending upward from the first transistor through the first to third insulating layers. A method for manufacturing a semiconductor device.

12. The second insulating layer is At least on the side in contact with the semiconductor layer, the carbon concentration is 1 × 10 １８ pieces / cm ３ The following applies: The method for manufacturing a semiconductor device according to claim 11.

13. The formation of the first transistor is To form a first gate insulating layer, This includes forming a first gate electrode, The formation of the second transistor described above is Forming a second gate insulating layer that is thicker than the first gate insulating layer, This includes forming a second gate electrode having a gate length longer than that of the first gate electrode. The method for manufacturing a semiconductor device according to claim 11.

14. A laminate is formed above the support substrate, in which multiple conductive layers are stacked spaced apart from each other. A pillar is formed in the laminate that extends within the laminate in the stacking direction of the laminate. The method further includes bonding the second insulating layer side of the first semiconductor substrate having the first and second transistors to the laminate side of the support substrate on which the laminate and the pillars are formed, and then removing the support substrate. The method for manufacturing a semiconductor device according to claim 11.

15. The second semiconductor substrate on which the semiconductor layer is formed via the second insulating layer is an SOI substrate. The method for manufacturing a semiconductor device according to claim 11.

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