Semiconductor device and method for manufacturing a semiconductor device

Abstract

To easily form high aspect ratio patterns. [Solution] The semiconductor device 1 of the embodiment comprises a first structure, a first columnar body extending in a first direction within the first structure, a second structure, a second columnar body extending in a first direction within the second structure, and a bonding surface interposed between the first structure and the second structure, wherein the first columnar body and the second columnar body are connected in the first direction at the bonding surface.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] As the aspect ratio increases, pattern formation tends to become difficult. As a result, the yield of the semiconductor device may decrease.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can easily form a high aspect ratio pattern.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a first structure, a first columnar body extending in a first direction within the first structure, a second structure, a second columnar body extending in the first direction within the second structure, and a bonding surface interposed between the first structure and the second structure, wherein the first columnar body and the second columnar body are connected in the first direction on the bonding surface.

Brief Description of the Drawings

[0006] [Figure 1]A diagram showing a schematic example of the configuration of a semiconductor device according to an embodiment. [Figure 2] A cross-sectional view showing a detailed configuration example of the memory area according to the embodiment. [Figure 3] A diagram showing a detailed configuration example of the staircase area according to the embodiment. [Figure 4] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 5] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 6] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 7] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 8] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 9] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 10] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 11] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 12] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 13] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 14] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 15] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to an embodiment. [Figure 16] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to Modification Example 1. [Figure 17] A diagram illustrating a part of the procedure for manufacturing a semiconductor device according to Modification Example 1. [Figure 18] A diagram showing a detailed configuration example of the staircase area in Modification 2.

Best Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited by the following embodiments. Also, the components in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

[0008] (Configuration Example of Semiconductor Device) FIG. 1 is a diagram showing a schematic configuration example of a semiconductor device 1 according to an embodiment. FIG. 1 shows a cross section along the X direction of the semiconductor device 1. However, in FIG. 1, hatching is omitted for the sake of clarity of the drawing.

[0009] Also, in this specification, the directions along the plane directions of a plurality of word lines WL are defined as the X direction and the Y direction, and the X direction and the Y direction are orthogonal to each other. Also, the electrical extraction direction of the word line WL may be referred to as the second direction, and this second direction is a direction along the X direction. Also, the direction intersecting the X direction and the Y direction, that is, the direction intersecting the plane direction of a plurality of word lines WL is defined as the Z direction. The Z direction is an example of the first direction. Also, in the extending direction of the contact CC, the connection end side of the contact CC with the word line WL is defined as the lower side of the semiconductor device 1, and the opposite side is defined as the upper side.

[0010] As shown in FIG. 1, the semiconductor device 1 includes, in order from the lower side of the paper surface, an electrode film EL, a source line SL, and a laminate LM in which a plurality of word lines WL are laminated. Also, the semiconductor device 1 includes a peripheral circuit CBA provided on the semiconductor substrate SB above the laminate LM.

[0011] The source line SL is disposed on the electrode film EL via an insulating layer 60. The source line SL is, for example, a polysilicon layer or the like.

[0012] A plurality of plugs PG are arranged in the insulating layer 60, and the source line SL and the electrode film EL maintain electrical conduction through the plugs PG. Thus, a source potential can be applied to the source line SL from the outside of the semiconductor device 1 through the electrode film EL and the plugs PG.

[0013] As shown in FIGS. 1(a) and (b), a laminate LM in which a plurality of word lines WL are stacked is arranged on the source line SL. A memory region MR is arranged at the central portion of the laminate LM, and stepped regions ER are arranged at both end portions of the laminate LM. These memory regions MR and stepped regions ER are divided into a plurality of regions by a plurality of plate-like contacts LI extending in a direction along the X direction through the laminate LM.

[0014] A plurality of pillars PL penetrating the word lines WL in the stacking direction are arranged in the memory region MR. The lower ends of the pillars PL reach the source line SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. Thus, the semiconductor device 1 is configured as, for example, a three-dimensional non-volatile memory in which memory cells are three-dimensionally arranged in the memory region MR.

[0015] A plurality of contacts CC connected to respective ones of the plurality of word lines WL are arranged in the stepped region ER.

[0016] Writing voltages, reading voltages, etc. are applied from the contacts CC to the memory cells included in the memory region MR at the central portion of the laminate LM through the word lines WL at the same height position as the memory cells. Thus, by these contacts CC, the word lines WL stacked in multiple layers are individually drawn out.

[0017] The plurality of word lines WL, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around the plurality of word lines WL.

[0018] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuits CBA, including transistors TR and wiring, are arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from contacts CC are controlled by the peripheral circuits CBA that are electrically connected to these contacts CC. In this way, the peripheral circuits CBA control the electrical operation of the memory cell.

[0019] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with the insulating layer 50 covering the laminate LM, a semiconductor device 1 is formed that includes multiple word lines WL, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0020] Next, a detailed configuration example of the semiconductor device 1 will be described using Figures 2 and 3. Figure 2 is a cross-sectional view showing a detailed configuration example of the memory area MR according to the embodiment.

[0021] Figure 2(a) is a cross-sectional view of the memory region MR of the semiconductor device 1 along the Y direction. In Figure 2(a), the structures above the insulating layer 52 and below the insulating layer 60 are omitted. Figure 2(b) is an enlarged cross-sectional view of the pillar PL at the height position of the bonding surface SP1.

[0022] As shown in Figure 2(a), the laminate LM has a structure in which laminates LM1, LM2, and LM3 are bonded together in this order from bottom to top. Therefore, the laminate LM has a bonding surface SP1 between laminates LM1 and LM2, and a bonding surface SP2 between laminates LM2 and LM3. The top of laminate LM3 is covered in this order by insulating layers 51 and 52. Insulating layers 51 and 52 constitute a part of the insulating layer 50 in Figure 1.

[0023] The laminate LM1 has a structure in which multiple word lines WL1 and multiple insulating layers OL1 are alternately stacked one layer at a time. The uppermost layer of the laminate LM1 is, for example, the insulating layer OL1. The laminate LM1 is an example of the first structure and the first laminate. Furthermore, the word lines WL1 are an example of the first conductive layer, and the insulating layer OL1 is an example of the first insulating layer.

[0024] The laminate LM1 has multiple pillars PL1 and plate-like portions LI1 formed on it.

[0025] Multiple pillars PL1 have a substantially cylindrical shape that extends in the Z direction within the laminate LM1. In this case, these pillars PL1 have a tapered shape, for example, with the diameter decreasing from the upper end to the lower end. The lower ends of the multiple pillars PL1 reach the source line SL, and the upper ends reach the bonding surface SP1. Each of the multiple pillars PL1 has, in order from the center outward, a core layer CR1, a channel layer CN1 as the first semiconductor layer, and a memory film ME1. Pillar PL1 is an example of the first columnar body and the first pillar.

[0026] The plate-like portion LI1 is formed as a plate extending in the XZ direction within the laminate LM1. The lower end of the plate-like portion LI1 reaches the source line SL, and the upper end reaches the bonding surface SP1. The plate-like portion LI1 has a conductive portion EC1 and a liner layer LL1 arranged in order from the inside. The plate-like portion LI1 is an example of a first plate-like portion.

[0027] Laminate LM2 is bonded to laminate LM1 via bonding surface SP1. Laminate LM2 has a structure in which multiple word wires WL2 and multiple insulating layers OL2 are alternately laminated one layer at a time. The bottom layer of laminate LM2 is the insulating layer OL2. Therefore, the bottom insulating layer OL2 of laminate LM2 and the top insulating layer OL1 of laminate LM1 are directly joined via bonding surface SP1. The top layer of laminate LM2 is also the insulating layer OL2. Laminate LM2 is an example of the second structure and the second laminate. Furthermore, word wires WL2 are an example of the second conductive layer, and insulating layer OL2 is an example of the second insulating layer.

[0028] The laminate LM2 has multiple pillars PL2 and plate-like portions LI2 formed on it.

[0029] Multiple pillars PL2 extend in the Z direction within the laminate LM2. The lower ends of multiple pillars PL2 connect in the Z direction to the upper ends of each of the multiple pillars PL1 at the bonding surface SP1, and the upper ends of multiple pillars PL2 reach the bonding surface SP2.

[0030] More specifically, as shown in Figure 2(b), each pillar PL2 has an extended portion PE1 extending in the Z direction from the bonding surface SP2 to a predetermined depth in the laminate LM2, and a joint portion PJ1 extending from the predetermined depth to the bonding surface SP1. The joint portion PJ1 is connected to the lower end of the extended portion PE1 by a surface SE1 as a first surface, and to the upper end of the pillar PL1 by a surface SE2 as a second surface.

[0031] The joint PJ1 is formed in a substantially cylindrical shape with a diameter D2. The extension PE1 is also substantially cylindrical and tapered, with its diameter decreasing from the upper end to the lower end. That is, the diameter D1 at the lower end of the extension PE1 is smaller than the diameter D3 at the upper end of the extension PE1. Furthermore, the diameter D2 of the joint PJ1 is greater than or equal to the diameter D1 at the lower end of the extension PE2, and less than or equal to the diameter D3 at the upper end of the extension PE2. The upper end of the extension PE2 is an example of the other end.

[0032] Each pillar PL2 has, from the center outwards, a core layer CR2, a channel layer CN2 as a second semiconductor layer, and a memory film ME2. The core layer CR2, channel layer CN2, and memory film ME2 are connected to the core layer CR1, channel layer CN1, and memory film ME1 of pillar PL1, respectively, at the bonding surface SP1. Pillar PL2 is an example of a second columnar body and a second pillar.

[0033] The plate-like portion LI2 is formed in a plate shape extending in the XZ direction from the laminate LM2. The lower end of the plate-like portion LI2 is connected to the plate-like portion LI1 in the Z direction at the bonding surface SP1, and the upper end reaches the bonding surface SP2. The plate-like portion LI2 has a conductive portion EC2 and a liner layer LL2 arranged on the inside. The lower end of the conductive portion EC2 is connected to the conductive portion EC1 of the pillar PL1 at the bonding surface SP1. The plate-like portion LI2 is an example of a second plate-like portion.

[0034] Laminate LM3 is bonded to the upper surface of laminate LM2 via bonding surface SP2. Laminate LM3 has a structure in which multiple word lines WL3 and multiple insulating layers OL3 are alternately laminated one layer at a time. The bottom layer of laminate LM3 is the insulating layer OL3. Therefore, the top insulating layer OL2 of laminate LM2 and the bottom insulating layer OL3 of laminate LM3 are directly joined via bonding surface SP2.

[0035] The word lines WL1 to WL3 mentioned above are, for example, a tungsten layer or a molybdenum layer, and the insulating layers OL1 to OL3 are, for example, a silicon oxide layer.

[0036] The laminate LM3 has multiple pillars PL3 and plate-like portions LI3 formed on it.

[0037] Multiple pillars PL3 extend in the Z direction within the laminate LM3. The lower end of each of the multiple pillars PL3 connects in the Z direction to each of the multiple pillars PL2 at the bonding surface SP2, and the upper end of each of the multiple pillars PL3 penetrates the uppermost insulating layer OL3 of the laminate LM3 and reaches the insulating layer 51.

[0038] Each of the multiple pillars PL3 also has an extended portion PE2 that extends in the Z direction from the insulating layer 52 to a predetermined depth in the laminate LM3, and a joint portion PJ2 that extends from a predetermined depth in the laminate LM3 to the bonding surface SP2. The joint portion PJ2 and the extended portion PE2 have configurations corresponding to the joint portion PJ1 and the extended portion PE2, so their description is omitted here.

[0039] Each of the multiple pillars PL3 has a core layer CR3, a channel layer CN3, a memory film ME3 from the center outwards, and a cap layer CP above the core layer CR3. Each of the core layer CR3, channel layer CN3, and memory film ME3 is connected to the core layer CR2, channel layer CN2, and memory film ME2 of pillar PL2, respectively, at the bonding surface SP2.

[0040] The cap layer CP is connected to the bit line BL located in the insulating layer 52 via plug CH located in the insulating layers 51 and 52. The bit line BL is connected to the transistor TR (Figure 1) via upper wiring (not shown) and vias.

[0041] The core layers CR1 to CR3 mentioned above are, for example, silicon oxide, and the channel layers CN1 to CN3 and cap layer CP are semiconductor layers such as polysilicon layers or amorphous silicon layers. The memory films ME1 to ME3 have tunnel insulating layers, charge storage layers, and block insulating layers (not shown) arranged sequentially from the center outward of each of the pillars PL1 to PL3. The tunnel insulating layers and block insulating layers are, for example, silicon oxide layers, and the charge storage layer is, for example, a silicon nitride layer.

[0042] The plate-like portion LI3 is formed in a plate shape extending in the XZ direction from the laminate LM3. The lower end of the plate-like portion LI3 is connected to the plate-like portion LI2 in the Z direction at the bonding surface SP2, and the upper end reaches the insulating layer 52. The plate-like portion LI3 also has a conductive portion EC3 and a liner layer LL3 arranged from the inside. The lower end of the conductive portion EC3 is connected to the conductive portion EC2 of the plate-like portion LI2 at the bonding surface SP2.

[0043] The liner layers LL1 to LL3 mentioned above are, for example, silicon oxide layers. The conductive parts EC1 to EC3, which are conductive materials, are, for example, tungsten layers, tungsten nitride layers, titanium layers, titanium nitride layers, molybdenum layers, or molybdenum nitride layers.

[0044] Pillar PL is formed when pillars PL1 to PL3, as described above, are connected to each other, and plate-shaped contacts LI are formed when plate-shaped parts LI1 to LI3 are connected to each other.

[0045] Figure 3 shows a detailed example of the configuration of the staircase area ER according to the embodiment.

[0046] Figure 3(a) is a cross-sectional view of the stepped region ER of the semiconductor device 1 along the X direction. In Figure 3(a), the structures above the insulating layer 52 and below the insulating layer 60 are omitted. Figure 3(b) is an enlarged cross-sectional view of the contact CC at the height position of the bonding surface SP1.

[0047] As shown in Figure 3(a), a stepped section SR1 and a contact CC1 are formed at the X-direction end of the laminate LM1.

[0048] The stepped section SR1 is formed by processing multiple word lines WL1 of the laminate LM1 into a stepped shape extending in the X direction. The stepped section SR1 is covered by the insulating layer 53 up to the height of the uppermost insulating layer OL1, i.e., the height of the bonding surface SP1. The insulating layer 53 is, for example, a silicon oxide layer and, together with insulating layers 51 and 52, constitutes a part of the insulating layer 50 in Figure 1. The insulating layer 53 is an example of a third insulating layer. The stepped section SR1 is an example of a first stepped section.

[0049] Contact CC1 extends in the Z direction within the insulating layer 53. The lower end of contact CC1 is connected to the word lines WL1 that constitute each step of the staircase section SR1, and the upper end reaches the bonding surface SP1. Contact CC1 has a conductive layer EL1 and an insulating layer LE1 extending from the inside to the outside. Contact CC1 is an example of the first columnar body and the first contact.

[0050] More specifically, as shown in Figure 3(b), contact CC1 has a joint CJ1 extending in the Z direction from the bonding surface SP1 to a predetermined depth of the insulating layer 53, and an extended portion CE1 extending from the predetermined depth to each word line WL1. The joint CJ1 is connected to the upper end of the extended portion CE1 by a surface SJ1 as a third surface, and is connected to the lower end of contact CC2, which will be described later, by a surface SJ2 as a fourth surface. The diameter D4 of the conductive layer EL1 formed on the joint CJ1 is greater than or equal to the diameter D5 at the lower end of the conductive layer EL2 of contact CC2, which will be described later.

[0051] A stepped section SR2 and a contact CC2 are formed at the X-direction end of the laminate LM2.

[0052] The staircase section SR2 is formed by processing multiple word lines WL2 of the laminated body LM2 into a staircase shape extending in the X direction. Of the terrace surfaces of each step in the staircase section SR2, the lowest terrace surface TRb is located on the ascending side of the terrace surface TRa of the uppermost step in the staircase section SR1. That is, the staircase sections SR1 and SR2 are continuous staircases in the X direction. The staircase section SR2 is an example of a second staircase section.

[0053] The stepped section SR2 and the area above the bonding surface SP1 are covered by an insulating layer 54 up to the height of the uppermost insulating layer OL2, i.e., the height of the bonding surface SP2. The insulating layer 54 is, for example, a silicon oxide layer and, like the insulating layer 53 described above, constitutes a part of the insulating layer 50 in Figure 1. The insulating layer 54 is an example of a fourth insulating layer.

[0054] Contact CC2 extends in the Z direction within the insulating layer 54. A portion of the lower end of contact CC2 connects to the word lines WL2 that constitute each step of the staircase section SR2, and its upper end reaches the bonding surface SP2. The remaining portion of the lower end of contact CC2 connects to contact CC1 in the Z direction at the bonding surface SP1, and its upper end reaches the bonding surface SP2. Contact CC2 is an example of a second columnar body and a second contact.

[0055] Contact CC2 has a conductive layer EL2 and an insulating layer LE2 from the inside. The conductive layer EL2 is connected to the conductive layer EL1 at the bonding surface SP1.

[0056] Contact CC2 also has a joint portion CJ2 extending in the Z direction from the bonding surface SP2 to a predetermined depth in the insulating layer 54, and an extended portion CE2 extending from a predetermined depth in the insulating layer 54 to the bonding surface SP1. Since the joint portion CJ2 and the extended portion CE2 have configurations corresponding to the joint portion CJ1 and the extended portion CE1, their description is omitted here.

[0057] A stepped section SR3 and a contact CC3 are formed at the X-direction end of the laminate LM3.

[0058] The staircase section SR3 is formed by processing multiple word lines WL3 of the laminated body LM3 into a staircase shape extending in the X direction. Of the terrace surfaces of the staircase section SR3, the lowest terrace surface TRd is located on the ascending side of the terrace surface TRc of the uppermost terrace surface TR2. In other words, the staircase sections SR2 and SR3 are continuous staircases in the X direction.

[0059] The stepped section SR3 and the area above the bonding surface SP2 are covered by an insulating layer 55 up to the height of the uppermost insulating layer OL3. The insulating layer 55 is, for example, a silicon oxide layer and, like the insulating layers 53 and 54 described above, constitutes a part of the insulating layer 50 in Figure 1. Thus, since the insulating layers 53 to 55 are made of, for example, the same material, these insulating layers 53 to 55 are substantially integrated.

[0060] Contact CC3 extends in the Z direction within the insulating layer 55. A portion of the lower end of contact CC3 connects to the word wires WL3 that constitute each step of the stair section SR3, and its upper end penetrates the insulating layer 51 to reach the insulating layer 52. The remaining portion of the lower end of contact CC3 connects to contact CC2 at the bonding surface SP2, and its upper end penetrates the insulating layer 51 to reach the insulating layer 52.

[0061] Contact CC3 has a conductive layer EL3 and an insulating layer LE3 from the inside. The conductive layer EL3 is connected to the conductive layer EL2 of contact CC2 at the bonding surface SP2.

[0062] The conductive layer EL3 is connected to the upper layer wiring MX via plug CH located in the insulating layer 52. This electrically leads to the word wires WL1 to WL3 of each layer being drawn out via contacts CC1 to CC3.

[0063] As explained above, contact CC is formed by the connection of contacts CC1 to CC3 to each other.

[0064] In Figures 2 and 3, the number of layers in the laminates LM1 to LM3 is shown to be appropriate for explanation, but the number of layers in the laminates LM1 to LM3 is not limited to the examples shown. In each of the laminates LM1 to LM3, there may be, for example, 100 or more layers of multiple word lines and multiple insulating layers.

[0065] Furthermore, if the aspect ratio is obtained by dividing the height of the pillar PL and contact CC in the Z direction by the diameter of the largest diameter portion, such as the upper end of each, then the aspect ratio of the pillar PL and contact CC in this embodiment is, for example, 25 to 100, more preferably 50 to 100.

[0066] (Method of manufacturing semiconductor devices) Figures 4 to 15 illustrate a part of the procedure for manufacturing the semiconductor device 1 according to an embodiment.

[0067] The manufacturing process for the semiconductor device 1 includes at least a first step of forming a laminate LM1 on a substrate SB1, a second step of forming a laminate LM2 on a substrate SB2, a third step of forming a laminate LM3 on a substrate SB3, and a bonding step of bonding substrates SB1 to SB3 together.

[0068] Furthermore, the first step includes at least the process of forming the pillar PL1, contact CC1, and plate-like portion LI1 described above; the second step includes at least the process of forming the pillar PL2, contact CC2, and plate-like portion LI2; and the third step includes at least the process of forming the pillar PL3, contact CC3, and plate-like portion LI3. In addition, each of the first to third steps includes an inspection step for inspecting the shape of the formed pattern.

[0069] The flow of the first process will be explained using Figures 4 to 9.

[0070] First, Figure 4 shows how the portions that will later become the staircase portion SR1 and the pillar portion PL1 are formed on the substrate SB1. Figure 4(a) shows a cross-section along the X direction of the portion of the substrate SB1 that will later become the staircase region ER, and Figure 4(b) shows a cross-section along the Y direction of the portion of the substrate SB1 that will later become the memory region MR.

[0071] As shown in Figure 4(a), an insulating layer 60 and a source wire SL are formed on a substrate SB1 such as a silicon substrate. A laminate LMs1 is formed on the source wire SL by alternately stacking multiple insulating layers OL1 and multiple sacrificial layers NL1 one layer at a time. Substrate SB1 is an example of a first substrate.

[0072] Sacrificial layer NL1 is, for example, a silicon nitride layer. Sacrificial layer NL1 functions as a sacrificial layer that will later be replaced by the word line WL1. Sacrificial layer NL1 is an example of a second insulating layer.

[0073] Next, a series of steps—forming a mask with photoresist, etching using this mask, slimming the mask, and etching using the slimmed mask—are used to create a staircase section SR1 on a part of the laminate LMs1. At this time, the staircase section SR1 is formed such that each terrace surface of the staircase section SR1 is positioned between a position P1, which is a distance L1 in the X direction from a predetermined reference point P0 of the laminate LMs1, and a position P2, which is a distance L2 in the X direction. Position P2 is closer to the reference point P0 than position P1. Therefore, each step of the staircase section SR1 ascends from position P1 to position P2.

[0074] Next, an insulating layer 53 is formed that covers the staircase section SR1 and reaches the height of the uppermost insulating layer OL1.

[0075] As shown in Figure 4(b), an insulating layer 60, a source line SL, and a laminate LMs1 are also formed on the substrate SB1 in the region that will later become the memory region MR. Multiple memory holes MHA1 are formed that penetrate the laminate LMs1 in the Z direction and reach the source line SL. The memory holes MHA1 are provided to form pillars PL1.

[0076] Here, we will describe the multiple shots SH present on substrate SB1. Figure 5(a) is a plan view showing the state of the shots formed on substrate SB1. Figure 5(b) is a diagram showing an example of the inspection results of the memory holes MHA1 formed in each shot.

[0077] As shown in Figure 5(a), the area of ​​the substrate SB1 excluding the outermost periphery is the element region DA where the semiconductor device 1 described above will be placed. The element region DA is divided into multiple shots SH1 to SHn (where n is an integer of 1 or more) by multiple intersecting division lines DL. Each of these individual shots SH is an element that forms the unit of individual processing in the manufacturing process of the semiconductor device 1.

[0078] In the processes shown in Figures 4(a) and 4(b) above, at least one laminated LMs1 is formed on each of the shots SH1 to SHn. That is, at least n laminated LMs1 are formed on the substrate SB1, and multiple memory holes MHA1 are formed on each of the n laminated LMs1. In the final stage of the semiconductor device 1 manufacturing process, each of these n laminated LMs1 is fragmented along multiple division lines DL, and cut out into chips on which the semiconductor device 1 is individually mounted. Therefore, the example in Figure 5 shows a case where the area of ​​shot SH and the chip to be fragmented are approximately equal. However, there may be multiple laminated LM1 etc. included in a single semiconductor device 1 chip.

[0079] In the inspection process for memory hole MHA1, the substrate SB1 is first brought into the inspection equipment. For example, a critical dimension scanning electron microscope (CD-SEM) is used as the inspection equipment.

[0080] The length-measuring SEM acquires imaging data of multiple memory holes MHA1 formed on the substrate SB1 and measures the dimensions of each memory hole MHA1 by analyzing the acquired imaging data. For example, the length-measuring SEM determines whether the memory holes MHA1 are formed correctly or not based on the dimensional deviation of the multiple memory holes MHA1 for each shot.

[0081] For example, if the dimensional deviation of multiple memory holes MHA1 exceeds a predetermined threshold, the memory holes MHA1 are determined to be not properly formed (fail) in that shot, such as not penetrating the stacked LMs1. If the memory holes MHA1 are not properly formed, the pillars PL1 may not be properly formed in a later process. As a result, the memory cells may not function properly. On the other hand, if the dimensional deviation of multiple memory holes MHA1 is below a predetermined threshold, the memory holes MHA1 are determined to be properly formed (pass) in that shot.

[0082] As shown in Figure 5(b), the length measuring SEM outputs inspection results that associate the judgment result with the shot number. The substrate SB1 is removed from the inspection device, and the inspection process is completed.

[0083] Furthermore, the above-mentioned determination process based on the measurement results of the dimensions of the memory hole MHA1 may be performed by an information processing device different from the measuring SEM. These devices may also be operated by an operator or other personnel.

[0084] Next, Figure 6 shows how multiple pillars PL1 and plate-like portions LI1 are formed on the substrate SB1 after the inspection process. Figures 6(a) and (b) show cross-sections of the portion of the substrate SB1 that will later become the memory area MR, along the Y direction.

[0085] As shown in Figure 6(a), the memory film ME1 and the channel layer CN1 are formed in this order inside the memory hole MHA1. Before forming the channel layer CN1, the memory film ME1 on the bottom surface of the memory hole MHA1 is removed. This connects the channel layer CN1 to the source line SL at the bottom surface. The core layer CR1 is then filled into the remaining void inside the channel layer CN1. As a result, multiple pillars PL1 are formed.

[0086] Next, a slit STA1 is formed that penetrates the laminate LMs1 and reaches the source line SL. The slit STA1 also extends in the direction along the X direction of the laminate LMs1. The slit STA1 is the portion that becomes the plate-like part LI1.

[0087] Next, in Figure 6(b), a word line WL1 is formed in the area where the sacrificial layer NL1 was located in the laminate LMs1, thereby forming the laminate LM1.

[0088] Specifically, first, the sacrificial layer NL1 is removed by wet etching through slit STA1. This removes the sacrificial layer NL1 exposed on the side of slit STA1 in the X and Y directions, creating a space (not shown) between the insulating layers OL1 that extends in the XY plane and is arranged in layers in the Z direction. Next, a conductive material raw material gas such as tungsten or molybdenum is injected into the space between the insulating layers OL1 through slit STA1. This replaces the sacrificial layer NL1 with word lines WL1, forming the laminate LM1. From this point onward, the process of forming word lines in the location where the sacrificial layer was is sometimes referred to as the replacement process.

[0089] Next, a liner layer LL1 is formed on the side wall of the slit STA1, and a conductive portion EC1 is filled into the liner layer LL1 to form a plate-like portion LI1.

[0090] Next, Figures 7 and 8 show how the contact CC is formed. Figures 7(a), (b), and 8 show a cross-section along the X direction of the portion of the substrate SB1 that will later become the stepped region ER.

[0091] As shown in Figure 7(a), multiple word lines WL1 are formed in the staircase section SR1 by the replacement process described in Figure 6(b).

[0092] Multiple contact holes HLc are formed that penetrate the insulating layer 53 and reach individual word lines WL1. These contact holes HLc are the portions that will later become contacts CC1.

[0093] Next, a photoresist film RF is applied to the laminate LM1 and the insulating layer 53, and the photoresist film RF is opened by exposure and development so that the area above the contact hole HLc is exposed. At this time, the diameter of the opening OP is made wider than the diameter of the contact hole HLc. Then, using the photoresist film RF as a mask, dry etching is performed to a depth that does not penetrate the insulating layer 53. This forms an opening OP at the upper end of the contact CC1. The opening OP is the part that will later become the joint CJ1.

[0094] This allows for a wider tolerance range for misalignment of contact CC2 relative to the upper end of contact CC1 when the joint SJ1 of contact CC1 and the lower end of contact CC2 are connected in the subsequent bonding process. As a result, contact CC1 and contact CC2 can be connected more reliably.

[0095] After removing the photoresist film RF, as shown in Figure 8, an insulating layer LE1 covers the side walls of multiple contact holes HLc, and a conductive layer EL1 fills the gaps in the contact holes HLc remaining inside the insulating layer LE1. This forms the contact CC1.

[0096] Next, Figure 9 shows how the substrate SB1 is separated into multiple chips for each stack LM1, and how acceptable chips are selected from these multiple chips.

[0097] As shown in Figure 9, the substrate SB1 is cut in the Z direction along the division line DL. This forms chips CPL1 to CPLn. As described above, in this embodiment, each of the chips CPL1 to CPLn corresponds to each of the shots SH1 to SHn.

[0098] Based on the inspection results of the memory hole MHA1 output in the inspection process described using Figures 5(a) and (b), chips containing "pass" shots are selected from chips CPL1 to CPLn. For example, in the example in Figure 9, all chips except chip CPL3 are pass chips. The selected pass chips are bonded with the other chips in the bonding process described later. This completes the first process.

[0099] Next, we will explain the flow of the second process using Figures 10 to 12.

[0100] First, Figures 10 and 11 show how the portion that will later become the pillar PL2 is formed on the substrate SB2. Figures 10(a) to (d) and 11(a) and (b) show a cross-section of the portion of the substrate SB2 that will later become the step region ER, along the X direction.

[0101] As shown in Figure 10(a), a laminate LMs21 is formed by alternately stacking a predetermined number of insulating layers OL2 and sacrificial layers NL2 one at a time on a substrate SB2 such as a silicon substrate. The sacrificial layer NL2 is, for example, a silicon nitride layer. The sacrificial layer NL2 functions as a sacrificial layer that will later be replaced by a word line WL2. The sacrificial layer NL2 is an example of a third insulating layer. The substrate SB2 is an example of a second substrate.

[0102] As shown in Figure 10(b), multiple holes MHA21 are formed that penetrate the laminate LMs21 in the Z direction and reach the substrate SB2. The holes MHA21 are the parts that will later become the joint PJ1. The multiple holes MHA21 have a diameter D2.

[0103] As shown in Figure 10(c), a CVD carbon layer, for example, is embedded in the hole MHA21, and an insulating layer OL2 and a sacrificial layer NL2 are further laminated on top of the laminate LMs21 and the CVD carbon layer. This forms the laminate LMs2.

[0104] Next, as shown in Figure 10(d), a hole MHA22 is formed above the hole MHA21, penetrating the insulating layer OL2 and the sacrificial layer NL2 in the Z direction and reaching the CVD carbon layer embedded in the hole MHA21. The hole MHA22 is the portion that will later become the stretched portion PE2. The upper end of the hole MHA22 has a diameter D3, and the lower end has a diameter D1 which is smaller than the diameter D3. That is, the hole MHA22 has a tapered shape in which the diameter decreases from the upper end to the lower end.

[0105] Here, the diameter D2 of hole MHA21 is larger than the diameter D1 of the lower end of hole MHA22. This allows for a wider tolerance range for misalignment of pillar PL2 relative to the upper end of pillar PL1 when the joint PJ1 of pillar PL2 is connected to the upper end of pillar PL1 during the subsequent bonding process. As a result, pillar PL1 and pillar PL2 can be connected more reliably.

[0106] Furthermore, the diameter D2 of hole MHA21 is less than or equal to the diameter D3 of the upper end of hole MHA22. That is, the cross-sectional area of ​​joint PJ1 when viewed from the Z direction does not exceed the cross-sectional area of ​​the upper end of pillar PL2. Therefore, it is possible to avoid a decrease in the arrangement density of pillar PL2 due to the formation of joint PJ1. In addition, interference between adjacent pillar PL2 at joint PJ1 can be suppressed.

[0107] As shown in Figure 11(a), the CVD carbon layer embedded in hole MHA21 is removed by ashing or the like. This forms memory hole MHA2.

[0108] Next, the substrate SB2 is brought into the inspection device, and the shape of the multiple memory holes MHA2 formed on the substrate SB2 is inspected.

[0109] Although not shown in the diagram, the element regions of the substrate SB2, which are not shown, are also divided into n shots corresponding to shots SH1 to SHn. In each of the multiple shots, a stacked LMs2 and multiple memory holes MHA2 are formed by the process described in Figures 10(a) to 11(a) above.

[0110] As described in Figures 5(a) and 5(b), it is determined for each shot whether or not the memory holes MHA2 are formed correctly. An inspection result is output, corresponding to the determination result and the shot number, and the inspection process is completed when the substrate SB2 is removed from the inspection device.

[0111] Next, as shown in Figure 11(b), the memory film ME2, channel layer CN2, and core layer CR2 are formed in this order inside the memory hole MHA2 of the substrate SB2 that has undergone the inspection process. At this time, before forming the channel layer CN2, the memory film ME2 on the bottom surface of the memory hole MHA2 is removed so that the channel layer CN2 is in contact with the substrate SB2. This allows the channel layer CN2 to be connected to the channel layer CN1 of the pillar PL1 when it is later connected to the pillar PL1 of the laminate LM1. As a result, multiple pillars PL2, each including a joint PJ1 and an extended portion PE1, are formed.

[0112] Next, a slit (not shown) is formed through the laminate LMs2 and reaches the substrate SB2. A word line WL2 is formed in the area where the sacrificial layer NL2 of the laminate LMs2 was located by a replacement process, thereby forming the laminate LM2. A liner layer LL2 and a conductive part EC2 are formed in the slit. As a result, the plate-like part LI2 is formed.

[0113] Next, Figure 12 shows how contact CC2 is formed. Figures 12(a) and (b) show a cross-section along the X direction of the portion of the substrate SB2 that will later become the stepped region ER.

[0114] In the region of the substrate SB2 that will later become the staircase region ER, a laminate LMs2 is formed by the process shown in Figures 10(a) to (c), and, although a detailed explanation is omitted, a staircase portion SR2 is formed by the process corresponding to the staircase portion SR1. Next, an insulating layer 54 is formed on the substrate SB2 and the staircase portion SR2, reaching the height of the uppermost insulating layer OL2. Then, a replacement process as shown in Figure 11(b) forms multiple word lines WL2 as shown in Figure 12(a).

[0115] When the staircase section SR2 is formed, the terrace surface of the staircase section SR2 is formed to be located between a position P2, which is a distance L2 in the X direction from a predetermined reference point P0 of the laminate LMs2, and a position P3, which is a distance L3 in the X direction. The reference point P0 is defined so that the position on each substrate SB1 and SB2 coincides with the reference point P0 set for the laminate LMs1 in the process shown in Figure 4(a) above. Position P2 is such that the distance L2 from the reference point P0 coincides with the position P2 set for the laminate LMs1. Position P3 is closer to the reference point P0 than position P2. Therefore, each step of the staircase section SR2 ascends from position P2 to position P3. As a result, when the laminate LM1 and laminate LM2 are later bonded together so that their respective reference points P0 overlap vertically, the staircase section SR1 and the staircase section SR2 will form a continuous staircase in the X direction.

[0116] Next, through the processes shown in Figures 7(a), (b), and 8, and the corresponding processes, the contact CC2 shown in Figure 12(b) is formed.

[0117] Next, the substrate SB2 is polished from the bottom until the bottom insulating layer OL2 is exposed, and then cut in the Z direction along the division line. This forms n chips.

[0118] Next, based on the inspection results of the memory hole MHA2 output in the inspection process shown in Figure 11(a), chips containing "pass" shots are selected from the n chips. The selected pass chips are bonded with the other chips in the bonding process described later. This completes the second process.

[0119] Next, we will explain the flow of the third process using Figures 13 and 14.

[0120] First, Figure 13(a) shows how the portion that will later become the pillar PL3 is formed on the substrate SB3. Figure 13(a) shows a cross-section of the portion of the substrate SB3 that will later become the memory area MR, along the X direction.

[0121] Specifically, a laminate LMs3 is formed by alternately stacking insulating layers OL3 and sacrificial layers NL3 one layer at a time on a substrate SB3 such as a silicon substrate. The sacrificial layer NL3 is, for example, a silicon nitride layer. The sacrificial layer NL3 functions as a sacrificial layer that will later be replaced by word lines WL3.

[0122] By the processes shown in Figures 10(a) to 11(a), multiple memory holes MHA3 are formed that penetrate the laminate LMs3 in the Z direction and reach the substrate SB3.

[0123] Note that each of the multiple memory holes MHA3 includes holes MHA31, which will later become the joint PJ2, and holes MHA32, which will later become the extension PE2. The method for forming holes MHA31 and MHA32 has been explained using Figures 10(a) to (d), so that explanation is omitted here.

[0124] Next, the substrate SB3 is brought into the inspection device, and the shape of the multiple memory holes MHA3 formed on the substrate SB3 is inspected.

[0125] Although not shown in the diagram, the element regions of substrate SB3, which are not shown, are also partitioned into n shots corresponding to shots SH1 to SHn of substrate SB1. Each of the multiple shots has a laminate LMs3 and multiple memory holes MHA3 formed within it.

[0126] The method described in Figures 5(a) and 5(b) determines whether the memory holes MHA3 are formed correctly for each shot. An inspection result is output, corresponding to the determination result and the shot number, and the inspection process is completed when the substrate SB3 is removed from the inspection device.

[0127] Next, as shown in Figure 13(b), the memory film ME3, channel layer CN3, and core layer CR3 are formed in this order inside the memory hole MHA3 of the substrate SB3 that has undergone the inspection process. A cap layer CP is formed above the core layer CR3. As a result, multiple pillars PL3 are formed.

[0128] Next, an insulating layer 51 is formed on the laminate LMs3, and a slit (not shown) is formed that penetrates the laminate LMs3 and the insulating layer 51 in the Z direction to reach the substrate SB3, and the laminate LM3 is formed by a replacement process. A liner layer LL3 and a conductive part EC3 are formed in the slit. As a result, the plate-like part LI3 is formed.

[0129] An insulating layer 52 is formed on the insulating layer 51, and a plug CH is formed that extends in the Z direction of the insulating layer 52 and connects to the cap layer CP and the conductive part EC3. A bit wire BL is formed that connects to the pillar PL3 via the plug CH, and an upper layer wiring MX is formed that connects to the conductive part EC3 via the plug CH.

[0130] Next, Figure 14 shows how contact CC3 is formed. Figures 14(a) and (b) show a cross-section along the X direction of the portion of the substrate SB3 that will later become the stepped region ER.

[0131] In the region that becomes the staircase region ER after the substrate SB3, a laminate LMs3 is formed, and the staircase region SR3 is formed by a process corresponding to the staircase regions SR1 and SR2. Next, an insulating layer 55 is formed on the substrate SB3 and the staircase region SR3, reaching the height of the uppermost insulating layer OL3, and multiple word lines WL3 as shown in Figure 14(a) are formed by a replacement process.

[0132] Figure 14(a) shows the state before the insulating layer 52, plug CH, bit wire BL, and upper layer wiring MX are formed in the process described in Figure 13(b) above.

[0133] When the staircase section SR3 is formed, the terrace surface of the staircase section SR3 is formed to be located between a position P3, which is a distance L3 in the X direction from a predetermined reference point P0 of the laminated body LMs3, and the reference point P0. The reference point P0 is set to the same position as the reference point P0 set for the laminated bodies LMs1 and LMs2 described above, and position P3 is set to the same position as the position P3 set for the laminated body LMs2 described above. In addition, each step of the staircase section SR3 ascends from position P3 toward the reference point P0. As a result, when the laminated bodies LM2 and LM3 are later bonded together so that their respective reference points P0 overlap vertically, the staircase sections SR2 and SR3 will form a continuous staircase in the X direction.

[0134] Next, multiple contact holes are formed that penetrate the insulating layer 55 and reach individual word lines WL1 and substrate SB3. An insulating layer LE3 and a conductive layer EL3 are formed in the multiple contact holes. As a result, contact CC3 is formed as shown in Figure 14(b).

[0135] Furthermore, in parallel with the process shown in Figure 13(b) above, an insulating layer 52 is formed on the insulating layer 51 in the stepped section SR3, and a plug CH is formed that extends in the Z direction and connects to the conductive layer EL3 of the contact CC3. An upper wiring MX is formed that connects to the contact CC3 via the plug CH.

[0136] Next, the substrate SB3 is polished from the bottom until the bottom insulating layer OL3 is exposed, and then cut in the Z direction along the division line. This forms n chips.

[0137] Next, based on the inspection results of the memory hole MHA3 output in the inspection process shown in Figure 13(a), chips containing "pass" shots are selected from the n chips. This completes the third process.

[0138] Next, Figure 15 shows how the chips selected in steps 1 to 3 are bonded together. Figure 15 shows a cross-section along the X direction of the portion that will later become the memory area MR. The bonding process shown in Figure 15 is performed as part of the manufacturing process of the semiconductor device 1.

[0139] Although not shown in the diagram, the upper surfaces F15 of the individual laminated LM3 are bonded to the semiconductor substrate SB, which includes multiple peripheral circuits CBA, corresponding to multiple shots provided on the semiconductor substrate SB.

[0140] Each of these laminates LM3 and peripheral circuit CBA can be joined by, for example, activating the insulating layer 40 (see Figure 1(a)) covering the upper surface F15 of the laminate and the peripheral circuit CBA in advance through plasma treatment or the like. This electrically connects the laminate LM3 and the peripheral circuit CBA.

[0141] Next, as shown in Figure 15, the lower surface F14 of the laminate LM3 and the upper surface F13 of the laminate LM2, which has been cut from the substrate SB2 and selected, are bonded together.

[0142] Each of these laminates, LM2 and LM3, can be joined by, for example, activating the upper surface F14 and lower surface F13 in advance through plasma treatment or the like. When joining laminates LM2 and LM3, the pillar PL2, plate-like portion LI2, and contact CC2 (not shown) formed on laminate LM2 are aligned so that they overlap in the Z direction with the pillar PL3, plate-like portion LI3, and contact CC3 (not shown) formed on laminate LM3.

[0143] After joining laminates LM2 and LM3, an annealing process is performed. This electrically connects pillars PL2-PL3, plate-like sections LI2-LI3, and contacts CC2-CC3.

[0144] Next, the lower surface F12 of laminate LM2 and the lower surface F11 of laminate LM1 are bonded together in the same manner.

[0145] Next, the substrate SB1 and the insulating layer 60 are polished from below the substrate SB1 up to a predetermined position on the insulating layer 60 by CMP (Chemical Mechanical Polishing) or the like, and a plug PG is formed that penetrates the insulating layer 60 and reaches the source wire SL. At this time, the insulating layer 60 may be increased as needed. Next, an electrode film EL is formed below the plug PG.

[0146] With the above steps completed, the manufacturing of semiconductor device 1 is finished.

[0147] (Overview) Conventionally, with the miniaturization of semiconductor devices, it has been desirable to increase the number of stacked word lines and arrange more pillar patterns in order to form more memory cells in a given area of ​​the semiconductor device. High stacking of word lines and high density of pillar patterns can reduce the diameter of individual pillar patterns and cause them to be placed closer together. When word lines are stacked high and the diameter of pillar patterns decreases, etching defects such as poor pattern bottoming can occur. Such defects become more pronounced as the number of stacked word lines increases, i.e., as the aspect ratio of the pillar patterns increases. Furthermore, when pillar patterns are placed close together, short circuits can occur between them.

[0148] The semiconductor device 1 of this embodiment comprises a laminate LM1, a pillar PL1 extending in the Z direction within the laminate LM1, a laminate LM2, a pillar PL2 extending in the Z direction within the laminate LM2, and a bonding surface SP1 interposed between pillar PL1 and pillar PL2. Pillar PL1 and pillar PL2 are connected in the Z direction at the bonding surface SP1.

[0149] In this way, by connecting pillars PL1 and PL2, which are individually formed within different laminates, in the Z direction, pillar PL with a high aspect ratio can be easily formed.

[0150] Furthermore, in the semiconductor device 1 of the embodiment, the pillar PL2 has an extended portion PE2 extending in the Z direction within the laminate LM2, and a joint portion PJ1 connected to the lower end of the extended portion PE2 by a surface SE1 and connected to the upper end of the pillar PL1 by a surface SE2. The diameter of the joint portion PJ1 is greater than or equal to the diameter of the lower end of the extended portion PE2 and less than or equal to the diameter of the upper end of the extended portion PE2.

[0151] In this way, by making the diameter D2 of the joint PJ1 greater than or equal to the diameter D1 of the lower end of the extension PE2, a wide range of allowable misalignment can be secured when connecting pillar PL2 to the upper end of pillar PL1. Furthermore, by making the diameter D2 of the joint PJ1 less than or equal to the diameter D3 of the upper end of the extension PE2, pillar PL2 can be formed more closely together, and contact between adjacent pillar PL2 at the joint PJ1 can be suppressed.

[0152] Furthermore, in the manufacturing method of the semiconductor device 1 of the embodiment, when the substrate SB1 is separated into individual pieces, multiple laminates LM1 are inspected and the laminates LM1 that pass the inspection are selected, and when the substrate SB2 is separated into individual pieces, multiple laminates LM2 are inspected and the laminates LM2 that pass the inspection are selected. The selected laminates LM1 and the selected laminates LM2 are then bonded together.

[0153] By bonding the inspected laminates LM1 and LM2 together, defects in the formation of pillar PL can be reduced. For example, if the pillar PL is formed all at once instead of bonding the laminates LM1 and LM2 together, if there is a defect in either the part corresponding to pillar PL1 or the part corresponding to pillar PL2, the pillar PL as a whole will be judged as defective. By bonding the selected laminates together, the yield of the semiconductor device 1 can be improved.

[0154] (Variation 1) Figures 16 and 17 illustrate a part of the procedure for manufacturing a semiconductor device according to Modification 1. In the manufacturing method of the semiconductor device according to Modification 1, the timing of bonding the laminates together differs from that of the embodiment described above. In Modification 1 described below, in order to simplify the explanation, the procedure for manufacturing the part that will later become the memory area MR will be described mainly. Also, in the following, components that are the same as those in the embodiment described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0155] Figures 16 and 17(a) and (b) show cross-sections along the X direction of the portion that will later become the memory region MR.

[0156] First, an insulating layer 60, a source wire SL, and a laminate LMs1 are formed on the substrate SB1 to form memory holes MHA1. Next, a slit STA1 is formed, and after an inspection process of the memory holes MHA1, a CVD carbon layer or the like is embedded in the memory holes MHA1 and slit STA1.

[0157] Next, a laminate LMs2 and memory holes MHA2 are formed on the substrate SB2. After the memory holes MHA2 undergo an inspection process, slits STA2 are formed, and CVD carbon layers, etc., are embedded in the memory holes MHA2 and slits STA2. Each laminate LMs2 is then separated into individual pieces.

[0158] Next, a laminate LMs3 and memory holes MHA3 are formed on the substrate SB3. After the memory holes MHA3 undergo an inspection process, slits STA3 are formed, and CVD carbon layers, etc., are embedded in the memory holes MHA3 and slits STA3. In addition, an insulating layer 52 is formed on the insulating layer 51, and plugs CH, bit lines BL, and upper layer wiring MX are formed. Each laminate LMs3 is then separated into individual pieces.

[0159] Next, as shown in Figure 16, the upper surface F31 of the laminate LMs1 and the lower surface F32 of the laminate LMs2 are bonded together, and the upper surface F33 of the laminate LMs2 and the lower surface F34 of the laminate LMs3 are bonded together. In other words, in Modification 1, the individualized substrates SB2~SB3 are bonded onto the non-individualized substrate SB1. Each time these laminates LM2 and LM3 are bonded to laminates LM1 and LM2, the substrates SB2 and SB3 on these laminates LM2 and LM3 are removed by CMP or the like. Furthermore, when bonding the laminates LM2 and LM3 to laminate LM1, only laminates LM2 and LM3 from approved chips are used, and these laminates LM2 and LM3 are bonded only to laminates LM1 that have passed inspection.

[0160] Next, as shown in Figure 17(a), after removing the CVD carbon layer and the like, a memory film ME, channel layer CN, core layer CR, and cap layer CP are formed in the memory holes MHA1 to MHA3 to form pillars PL. Then, laminates LM1 to LM3 are formed by a replacement process. Liner layers LL and conductive parts EC are filled into the side walls of slits STA1 to 3 to form plate-shaped contacts LI.

[0161] Next, although not shown in the diagram, a semiconductor substrate SB containing peripheral circuits CBA is bonded to the upper surface F35 of the laminate LM3. After removing the substrate SB1 of the laminate LM1 by CMP or the like, as shown in Figure 17(b), a plug PG penetrating the insulating layer 60 and an electrode film EL are formed below the source wire SL. Then, the substrate SB is separated into individual pieces for each of the laminates LM1 to LM3 and the peripheral circuits CBA.

[0162] The semiconductor device of Modification 1 is manufactured as described above.

[0163] The semiconductor device and the method for manufacturing the semiconductor device according to Modification 1 provide the same effects as the embodiments described above.

[0164] [Differentiation 2] Next, a modified example 2 will be described using Figure 18. The semiconductor device of modified example 2 differs from embodiment 1 described above in the configuration of the stepped region ER.

[0165] Figure 18 shows a detailed configuration example of the stair region ER according to Modification 2. More specifically, Figure 18 is a cross-sectional view along the X direction in the stair region ER, and corresponds to Figure 3(a). Note that in Figure 18, the structures above the insulating layer 52 and below the insulating layer 60 are omitted. Furthermore, in the following, components similar to those in Embodiment 1 and Modification 1 described above are denoted by the same reference numerals, and their descriptions may be omitted.

[0166] As shown in Figure 18, multiple contacts CC1 are formed at the X-direction end of the laminate LM1. The multiple contacts CC1 extend in the Z-direction within the laminate LM1. That is, the laminate LM1 does not have a stepped section SR1 (Figure 3(a)). The lower end of each contact CC1 reaches each word line WL1 that constitutes the laminate LM1, and the upper end reaches the bonding surface SP1. The depth reached by the lower end of each contact CC1 gradually decreases when viewed from the X-direction end side of the laminate LM1.

[0167] Multiple contacts CC2 are formed at the X-direction end of the laminate LM2. The contacts CC2 extend in the Z-direction within the laminate LM2. That is, the laminate LM2 does not have a stepped section SR2 (Figure 3(a)). The lower ends of some of the contacts CC2 reach each word line WL2 that constitutes the laminate LM2, and their upper ends reach the bonding surface SP2. The depth reached by the lower ends of the contacts CC2 gradually decreases when viewed from the X-direction end side of the laminate LM2. In addition, the remaining lower ends of the contacts CC2 connect with contact CC1 in the Z-direction at the bonding surface SP1, and their upper ends reach the bonding surface SP2.

[0168] Multiple contacts CC3 are formed at the X-direction end of the laminate LM3. The contacts CC3 extend in the Z-direction within the laminate LM3. That is, the laminate LM3 does not have a stepped section SR3 (Figure 3(a)). The lower end of a portion of the contacts CC3 reaches the word line WL3 that constitutes the laminate LM3, and the upper end penetrates the insulating layer 51 to reach the insulating layer 52. The depth reached by the lower end of the contacts CC3 gradually decreases when viewed from the X-direction end side of the laminate LM3. In addition, the remaining lower end of the contacts CC3 connects with contacts CC2 at the bonding surface SP2, and the upper end penetrates the insulating layer 51 to reach the insulating layer 52.

[0169] As the contacts CC1 to CC3 described above are connected to each other, a contact CC is formed in which the depth gradually decreases from the end side in the X direction. Although not shown in the figures, the semiconductor device of Modification 2 may also have a configuration corresponding to the joint CJ1 and extension CE1 of Embodiment 1.

[0170] Although not shown in the diagram, the semiconductor device of the modified example 2 is manufactured by going through the first to third steps and the bonding step, similar to the first embodiment.

[0171] In the first step of forming contact CC1, after forming the laminate LMs1, a mask pattern having multiple openings is formed on the upper surface of the laminate LMs1. The mask pattern is, for example, a silicon oxide layer. Next, a resist pattern is formed that covers a portion of the mask pattern, and the laminate LMs1 is etched through the mask pattern exposed from the resist pattern. After this, the resist pattern is slimmed, and the etching is repeated while gradually exposing the openings of the mask pattern from the X-direction end. This forms contact holes that gradually become shallower from the X-direction end. Next, a replacement process is performed, and then the contact holes are filled with an insulating layer LE1 and a conductive layer EL1, respectively. As a result, contact CC1 is formed. After this, the first step is completed after sorting of acceptable chips.

[0172] In the second and third steps, contacts CC2 and CC3 are formed by going through the steps corresponding to the first step. Subsequently, after going through bonding steps and the like, the manufacturing of the semiconductor device of modified example 2 is completed.

[0173] The semiconductor device and the method for manufacturing the semiconductor device of Modification 2 provide the same effects as the above-described embodiment 1 and modification 1.

[0174] (Other variations) In the embodiments and modifications described above, the shape of the memory holes MHA1 to MHA3 was inspected during the inspection process. However, the objects of inspection are not limited to the memory holes MHA1 to MHA3. For example, the contact holes HLc, slits STA1 to STA3, or pillars PL1 to PL3 on which the memory film ME, channel layer CN, and core layer CR are formed may also be inspected.

[0175] In the embodiments and modifications described above, joints PJ1 and PJ2 were formed at the lower ends of pillars PL2 and PL3, respectively, while joints CJ1 and CJ2 were formed at the upper ends of contacts CC1 and CC2, respectively. However, the formation positions of the joints are not limited to those described above. For example, joints PJ1 and PJ2 may be formed at the upper ends of pillars 1 and PL2, and joints CJ1 and CJ2 may be formed at the lower ends of contacts CC2 and CC3. Furthermore, if the alignment accuracy when joining the individual laminates LM1 to LM3 is sufficient, the joints PJ1 and PJ2 of pillars PL2 and PL3, and the joints CJ1 and CJ2 of contacts CC2 and CC3 may not be formed.

[0176] In the embodiments and modifications described above, laminates LM1 to LM3 were formed on substrates SB1 to SB3, respectively, but it is not necessary to distinguish between the laminates LM1 to LM3. For example, laminates having the same structure may be formed on multiple substrates. Alternatively, laminates having the same structure may be formed on a single substrate. These are then separated into individual pieces, and suitable chips are selected from among them and sequentially bonded to substrates SB on which peripheral circuits CBA are formed, according to the procedure of either embodiment or modification 1 or 2. In this case, bit lines BL, upper layer wiring MX, plugs CH, etc., can be formed in advance on the peripheral circuit CBA side. Furthermore, by forming source lines SL, insulating layer 60, plugs PG, and electrode films EL on the side of the laminate LM opposite to the peripheral circuit CBA after bonding with the peripheral circuit CBA, a semiconductor device 1 similar to the embodiments described above can be obtained.

[0177] In the embodiments and modifications described above, the semiconductor device 1 includes three stacked structures LM1 to LM3. However, the number of stacked structures included in the semiconductor device 1 may be two, or four or more.

[0178] Furthermore, in the embodiments and modifications described above, pillars, etc., are formed while at least one of the substrates SB1 to SB3 is not fragmented. However, for example, all of the substrates SB1 to SB3 may be fragmented before forming the pillars, etc., and the pillars, etc., may be formed on the substrates SB1 to SB3 while they are fixed to a substrate that is not fragmented, which is different from the substrates SB1 to SB3.

[0179] In the embodiments and modifications described above, a case in which a three-dimensional non-volatile memory is formed as the semiconductor device 1 was explained, but the application of the present invention is not limited to three-dimensional non-volatile memory. The present invention can also be applied to other semiconductor devices having a high aspect ratio structure. For example, the present invention may be applied to volatile memory such as DRAM (Dynamic Random Access Memory).

[0180] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0181] 1... Semiconductor device, CC, CC1, CC2, CC3... Contacts, CE1, CE2, PE1, PE2... Stretched portion, CJ1, CJ2, PJ1, PJ2... Joint portion, CN, CN1, CN2, CN3... Channel layer, CR, CR1, CR2, CR3... Core layer, D1, D2, D3, D4, D5... Diameter, EL1, EL2, EL3... Conductive portion, ER... Stepped region, LI1, LI2, LI3... Plate-like portion, LM1 LM2,LM3,LMs1,LMs2,LMs3,LMs21...Laminate, NL1,NL2,NL3...Sacrificial layer, ME,ME1,ME2,ME3...Memory film, OL1,OL2,OL3...Insulating layer, 100,SB1,SB2,SB3...Substrate, SP1,SP2...Bonding surface, SR1,SR2,SR3...Staircase section, WL1,WL2,WL3...Word line, PL,PL1,PL2,PL3...Pillar.

Claims

1. The first structure and A first columnar body extending in a first direction within the first structure, The second structure, A second columnar body extending in the first direction within the second structure, A bonding surface interposed between the first structure and the second structure, Equipped with, In the bonding surface, the first columnar body and the second columnar body are connected in the first direction. Semiconductor equipment.

2. The first structure is, It is configured as a first laminate in which multiple first conductive layers and multiple first insulating layers are alternately stacked one layer at a time. The first columnar body is The first pillar is configured to have a first semiconductor layer extending in the first direction within the first laminate, The second structure described above is It is configured as a second laminate in which multiple second conductive layers and multiple second insulating layers are alternately stacked one layer at a time. The second columnar body is The second pillar is configured to have a second semiconductor layer extending in the first direction within the second laminate, The semiconductor device according to claim 1.

3. The second pillar is The second laminate contains an extended portion extending in the first direction, The extension portion has a joint that is connected on the first surface to the end on the bonding surface side of the extension portion and on the second surface to the end on the bonding surface side of the first pillar, The diameter of the joint is, The diameter of the end of the extended portion on the bonding surface side is greater than or equal to the diameter of the other end of the extended portion. The semiconductor device according to claim 2.

4. The first structure is, Multiple first conductive layers and multiple first insulating layers are alternately laminated one layer at a time, and the multiple first conductive layers are configured as a first laminate including a first stepped portion processed in a stepped manner that extends in a second direction intersecting the first direction. The first step section is covered with a third insulating layer. The first columnar body is The third insulating layer is configured as a first contact that extends in the first direction and is connected to one of the first conductive layers of the plurality of first conductive layers which are processed in a stepped manner. The second structure described above is Multiple second conductive layers and multiple second insulating layers are alternately laminated one layer at a time, and the multiple second conductive layers are configured as a second laminate including the first stepped portion and a second stepped portion processed in a stepped shape that is continuous in the second direction. The second step section is covered with a fourth insulating layer. The second columnar body is The fourth insulating layer is configured as a second contact that extends in the first direction and is connected to one of the second conductive layers of the plurality of second conductive layers which are processed in a stepped manner. The semiconductor device according to claim 1.

5. The first and second contacts have conductive portions containing a conductive material, The diameter of the conductive portion on the bonding surface of the first contact is greater than the diameter of the conductive portion on the bonding surface of the second contact. The semiconductor device according to claim 4.

6. The first structure comprises a first plate-like portion extending in a first direction and a second direction intersecting the first direction, The second structure comprises a second plate-like portion extending in the first direction and the second direction, Furthermore, The first plate-like portion and the second plate-like portion are connected in the first direction at the bonding surface. The semiconductor device according to claim 2.

7. A first structure and a first columnar body extending in a first direction within the first structure are formed on the first substrate. A second substrate is formed with a second structure and a second columnar body extending in the first direction within the second structure. The first columnar body and the second columnar body are bonded together, with the first surface of the first structure intersecting the first direction and the second surface of the second structure intersecting the first direction serving as bonding surfaces, such that the first columnar body and the second columnar body are connected in the first direction. A method for manufacturing a semiconductor device.

8. When forming the first structure and the first columnar body, A plurality of first structures including the first structure are formed, A plurality of first columnar bodies, including the first columnar body, are formed in each of the plurality of first structures. When forming the second structure and the second columnar body, A plurality of second structures including the second structure are formed, A plurality of second columnar bodies, including the second columnar body, are formed in each of the plurality of second structures. Before bonding the first structure and the second structure, For each of the plurality of first structures, the first substrate is made into individual pieces. The second substrate is divided into individual pieces for each of the plurality of second structures. The method for manufacturing a semiconductor device according to claim 7.

9. When bonding the first structure and the second structure, The plurality of first structures are inspected, and the first structures that pass the inspection are selected. The inspection of the plurality of second structures is performed, and the second structures that pass the inspection are selected. The first and second substrates, including the selected first and second structures, are bonded together. The method for manufacturing a semiconductor device according to claim 8.

10. The first structure is, It is configured as a first laminate in which multiple first conductive layers and multiple first insulating layers are alternately stacked one layer at a time. The first columnar body is The first pillar is configured to have a first semiconductor layer extending in the first direction within the first laminate, The second structure described above is It is configured as a second laminate in which multiple second conductive layers and multiple second insulating layers are alternately stacked one layer at a time. The second columnar body is The second pillar is configured to have a second semiconductor layer extending in the first direction within the second laminate, The method for manufacturing a semiconductor device according to claim 7.

Images