Multilayer devices, semiconductor devices

Abstract

This invention provides a stacked device that can expand the implementation range of the cutoff frequency of a low-pass filter. [Solution] The laminated device 21 comprises a support 31 and a laminated structure 33, the laminated structure 33 includes at least one capacitor portion 35 and resistor portions (37, 39) in a first region 31f of the main surface 31b of the support 31, the resistor portions (37, 39) include a first resistor portion 37 and a second resistor portion 39, the capacitor portion 35, the first resistor portion 37, and the second resistor portion 39 are laminated in the direction of the lamination axis AxS intersecting the main surface 31b, the capacitor portion 35 includes a capacitor element 35b, the first resistor portion 37 includes a first resistor element 37b comprising a first resistor material, the second resistor portion 39 includes a second resistor element 39b comprising a second resistor material different from the first resistor material, and the laminated structure 33 includes an insulating region that separates the first resistor element 37b from the second resistor element 39b in the direction of the lamination axis AxS.

Description

Technical Field

[0001] The present invention relates to a stacked device and a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a temperature adjustment circuit that adjusts the oscillation characteristics of a crystal oscillation circuit and a low-pass filter connected to the output signal of the temperature adjustment circuit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A semiconductor device for a crystal oscillation circuit is connected to a crystal oscillator and provides functions for starting up and stably oscillating the crystal oscillator. Also, such a semiconductor device is mounted on a board on which a plurality of other semiconductor devices are mounted and provides a clock signal for the operation of the other semiconductor devices. Accordingly, the chip size of the semiconductor device cannot be increased due to the functions of the product and the convenience of the usage environment.

[0005] In Patent Document 1, the cut-off frequency of the low-pass filter is specified by the element constants of passive elements, specifically, a resistance element and a capacitor element, and is associated with the reciprocal of the product of the element constants of the resistance element and the capacitor element. Lowering the cut-off frequency of the low-pass filter increases the element size of the passive element. Therefore, in the semiconductor device of Patent Document 1, reducing the cut-off frequency of the low-pass filter increases the size of the semiconductor device.

[0006] What is required in semiconductor devices for crystal oscillator circuits is to broaden the implementation range of the low-pass filter's cutoff frequency, taking into account the technical background described above.

[0007] The present invention aims to provide a multilayer device and a semiconductor device that can expand the implementation range of the cutoff frequency of a low-pass filter. [Means for solving the problem]

[0008] A laminated device according to a first aspect of the present invention comprises a support having a main surface and a laminated structure including a plurality of passive elements, wherein the laminated structure includes at least one capacitor portion and a plurality of resistor portions in a first region of the main surface of the support, the resistor portion includes at least a first resistor portion and a second resistor portion, the first resistor portion, the second resistor portion and the capacitor portion are arranged in the direction of a laminated axis intersecting the main surface, the capacitor portion includes a capacitor element as one of the passive elements, the first resistor portion includes a first resistor element comprising a first resistor material as one of the passive elements, and the second resistor portion includes a second resistor element comprising a second resistor material different from the first resistor material as one of the passive elements.

[0009] A semiconductor device according to a second aspect of the present invention comprises a multilayer device as described in the first aspect, a resonant circuit connected to the multilayer device, and a control circuit configured to control the resonant circuit and connected to the multilayer device, wherein the capacitor element, the first resistor element, and the second resistor element are connected to constitute a low-pass filter, and the control circuit includes a circuit configured to adjust the temperature characteristics of the oscillation frequency of the resonant circuit. [Effects of the Invention]

[0010] According to the above embodiment, a stacked device and a semiconductor device can be provided that can expand the implementation range of the cutoff frequency of the low-pass filter. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a schematic plan view showing the oscillator according to this embodiment. [Figure 2] Figure 2 is a schematic diagram showing a semiconductor device according to this embodiment in a cross-section taken along the line II-II shown in Figure 1. [Figure 3] Figure 3 is a diagram showing the circuit connections of the stacked device, resonant circuit, and control circuit in the semiconductor device according to this embodiment. [Figure 4] Figure 4 is a diagram showing the equivalent circuit of an exemplary multilayer device. [Figure 5] Figure 5 is a diagram showing exemplary noise characteristics. [Figure 6] Figure 6 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 7] Figure 7 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 8] Figure 8 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 9] Figure 9 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 10] Figure 10 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 11] Figure 11 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 12] Figure 12 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 13] Figure 13 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 14] Figure 14 is a cross-sectional view showing intermediate products of the main steps in the method for manufacturing a semiconductor device according to this embodiment. [Figure 15] FIG. 15 is a cross-sectional view showing an intermediate product of a main process in a method of manufacturing a semiconductor device according to the present embodiment. [Figure 16] FIG. 16 is a cross-sectional view showing an intermediate product of a main process in a method of manufacturing a semiconductor device according to the present embodiment. [Figure 17] FIG. 17 is a cross-sectional view showing an intermediate product of a main process in a method of manufacturing a semiconductor device according to the present embodiment. [Figure 18] FIG. 18 is a cross-sectional view showing an intermediate product of a main process in a method of manufacturing a semiconductor device according to the present embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing an intermediate product of a main process in a method of manufacturing a semiconductor device according to the present embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing an intermediate product of a main process in a method of manufacturing a semiconductor device according to the present embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0012] Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. The same parts are denoted by the same reference numerals, and redundant descriptions are omitted.

[0013] FIG. 1 is a drawing schematically showing an oscillation device according to the present embodiment. FIG. 2 is a drawing schematically showing a semiconductor device according to the present embodiment in a cross section taken along line II-II shown in FIG. 1. FIG. 3 is a drawing showing circuit connections of a stacked device, a resonance circuit, and a control circuit in the semiconductor device according to the present embodiment. FIG. 4 is a drawing showing an equivalent circuit of an exemplary stacked device. FIG. 5 is a drawing showing exemplary noise characteristics.

[0014] The exemplary oscillation device can be a crystal oscillation device. However, the oscillation device is not limited to those using a resonator using a crystal.

[0015] The following explanation will focus on a crystal oscillator as an example of an oscillator.

[0016] Referring to Figure 1, System 11 comprises a semiconductor device 13, a wiring board 15, and a crystal oscillator 17. The wiring board 15 mounts the semiconductor device 13 and has a wiring layer 15b. The semiconductor device 13 and the crystal oscillator 17 are mounted on the wiring board 15. The crystal oscillator 17 is connected to the semiconductor device 13. An exemplary semiconductor device 13 is configured to integrate a multilayer device 21, a crystal oscillator circuit 23, and a control circuit 25. In the subsequent description, the multilayer device 21, the crystal oscillator circuit 23, and the control circuit 25 are integrated on a single semiconductor substrate. However, the disclosure is not limited thereto.

[0017] An exemplary semiconductor device 13 comprises a multilayer device 21, a crystal oscillator circuit 23, and a control circuit 25. The crystal oscillator circuit 23 includes an amplifier 23b and is connected to the multilayer device 21. The amplifier 23b is configured to cause a crystal oscillator 17 to oscillate. The control circuit 25 is configured to control the crystal oscillator circuit 23 and is also connected to the multilayer device 21.

[0018] An exemplary semiconductor device 13 includes a semiconductor chip 12 on which a semiconductor integrated circuit (e.g., a stacked device 21, a crystal oscillator circuit 23, and a control circuit 25) is mounted, and a package 14 that houses the semiconductor chip 12. The package 14 has electrodes 14b for electrical connections and a container that protects the semiconductor chip 12. The semiconductor chip 12 includes electrodes 13b, such as pad electrodes, that connect the semiconductor integrated circuit to an external device (e.g., a crystal oscillator 17). The pad electrodes are connected to the electrodes 14b of the package 14 via a conductor 14c, such as a bonding wire. Referring to Figure 1, the crystal oscillator 17 is located outside the package 14 and is not housed inside the package 14. However, both the external device, such as the crystal oscillator 17, and the semiconductor chip 12 can be housed inside the package 14. For housing, the crystal oscillator 17 can be connected via a conductor such as a wire and / or bump electrodes.

[0019] Referring to Figures 1 and 2, the laminated device 21 comprises a support 31 and a laminated structure 33. The support 31 has a main surface 31b.

[0020] The laminated structure 33 includes a plurality of passive elements. The passive elements are provided in a first region 31f of the main surface 31b of the support 31. An exemplary passive element includes at least one capacitor section 35 and a plurality of resistor sections (37, 39, described later). The resistor section includes at least a first resistor section 37 and a second resistor section 39. The capacitor section 35, the first resistor section 37, and the second resistor section 39 are stacked in the direction of the stacking axis AxS intersecting the main surface 31b.

[0021] The laminated device 21 may further include an interlayer region 32 between the support 31 and the laminated structure 33. The support 31, the interlayer region 32, and the laminated structure 33 are stacked in order in the direction of the stacking axis AxS.

[0022] An exemplary capacitor section 35 includes a capacitor element 35b as a passive element. An exemplary first resistor section 37 includes a first resistor element 37b as a passive element, and the first resistor element 37b may comprise a first resistor material. An exemplary second resistor section 39 includes a second resistor element 39b as a passive element, and the second resistor element 39b may comprise a second resistor material different from the first resistor material.

[0023] The exemplary first resistive material may be either a polysilicon layer or a metal thin film, and the exemplary second resistive material may be the other of a polysilicon layer or a metal thin film. However, the resistive materials of this disclosure are not limited to polysilicon layers and metal thin films.

[0024] In the exemplary multilayer device 21, the first resistive element 37b, the second resistive element 39b, and the capacitor element 35b can be arranged sequentially in the direction of the stacking axis AxS.

[0025] An exemplary first resistive section 37 may have a first resistive layer 37c, a first element isolation layer 37d, a first conductive layer 37f, and a first wiring isolation layer 37g.

[0026] In the first resistive section 37, the first resistive layer 37c may include either a polysilicon layer or a metal thin film. The first element isolation layer 37d may cover the first resistive layer 37c. The first conductive layer 37f may be provided on the first element isolation layer 37d. The first wiring isolation layer 37g may cover the first conductive layer 37f.

[0027] The first conductive layer 37f may include a first electrode 37h and a second electrode 37j, the first electrode 37h being connected to one end of the first resistive layer 37c and the second electrode 37j being connected to the other end of the first resistive layer 37c.

[0028] An exemplary second resistive section 39 may have a second resistive layer 39c, a second element isolation layer 39d, a second conductive layer 39f, and a second wiring isolation layer 39g.

[0029] In the second resistive section 39, the second resistive layer 39c may include either a polysilicon layer or a metal thin film. The second element isolation layer 39d may cover the second resistive layer 39c. The second conductive layer 39f may be provided on the second element isolation layer 39d. The second wiring isolation layer 39g may cover the second conductive layer 39f.

[0030] The second conductive layer 39f may include a first electrode 39h and a second electrode 39j. The first electrode 39h is connected to one end of the second resistive layer 39c, and the second electrode 39j is connected to the other end of the second resistive layer 39c.

[0031] The laminated structure 33 may include an insulating region 41 that separates the first resistive element 37b from the second resistive element 39b in the direction of the laminate axis AxS. An exemplary insulating region 41 may include silicon oxide.

[0032] The first resistive layer 37c can be provided on the interlayer region 32. The second resistive layer 39c can be provided on the insulating region 41, specifically on the first wiring isolation layer 37g.

[0033] The capacitor element 35b may have a lower conductive layer 35c, a first isolation layer 35d, an upper conductive layer 35f, and a second isolation layer 35g.

[0034] In the capacitor element 35b, the first isolation layer 35d can cover the lower conductive layer 35c. The upper conductive layer 35f can be provided on top of the first isolation layer 35d. The second isolation layer 35g can cover the upper conductive layer 35f.

[0035] The lower conductive layer 35c may include a first capacitor electrode 35h. The upper conductive layer 35f may include a second capacitor electrode 35j.

[0036] The first isolation layer 35d may include a dielectric layer 35di between the first capacitor electrode 35h and the second capacitor electrode 35j, such as silicon oxide and / or silicon nitride.

[0037] The exemplary capacitor element 35b may have a parallel plate type. The multilayer device 21 may include a MIM capacitor as the capacitor element 35b.

[0038] In the exemplary capacitor element 35b, the lower conductive layer 35c can be provided on the second wiring isolation layer 39g.

[0039] The second isolation layer 35g has an opening 35n at the location of the upper conductive layer 35f for external connections such as pad electrodes. The upper conductive layer 35f is exposed at the opening 35n.

[0040] The semiconductor device 13 includes a passivation film 40 that covers the second isolation layer 35g. The passivation film 40 covers the edges of the second isolation layer 35g and the opening 35n.

[0041] The first resistive layer 37c can be connected to the first electrode 37h and the second electrode 37j of the first conductive layer 37f via interconnects (37p, 37q), respectively. The first conductive layer 37f further includes a first interconnect 37k, which can be connected to an interlayer interconnect 32c via an opening in the first element isolation layer 37d and the interlayer insulating region 32b.

[0042] The second resistive layer 39c can be connected to the first electrode 39h and the second electrode 39j of the second conductive layer 39f via interconnects (39p, 39q), respectively. The second conductive layer 39f further includes a second interconnect 39k, which can be connected to the first conductive layer 37f via openings in the first wiring isolation layer 37g and the second element isolation layer 39d.

[0043] The lower conductive layer 35c includes a third interconnect 35k, which can be connected to the second conductive layer 39f via an opening in the second wiring isolation layer 39g.

[0044] The upper conductive layer 35f includes a fourth interconnect 35m, which can be connected to the lower conductive layer 35c through an opening in the first isolation layer 35d.

[0045] As already explained, the laminated device 21 may further include an interlayer region 32 between the support 31 and the laminated structure 33.

[0046] The interlayer region 32 may include an interlayer insulation region 32b and an interlayer interconnect 32c.

[0047] The interlayer interconnect 32c can be connected to a circuit region including a semiconductor element through an opening in the interlayer insulating region 32b.

[0048] The support 31 may include one or more semiconductor elements formed in the circuit regions (23, 24, 25). Specifically, the exemplary circuit regions (23, 24, 25) may include a crystal oscillator circuit 23 and a control circuit 25, and may further include a switching circuit 24. The exemplary switching circuit 24 may be configured to switch the passive elements of the multilayer device 21. From the viewpoint of noise propagation, the circuit regions may not be located in the region directly beneath the multilayer device 21. Alternatively, a conductive layer may be placed on the support 31 directly beneath the multilayer device 21, and this conductive layer may be grounded, for example.

[0049] Referring to Figure 1, the exemplary amplifier 23b may have an inverting amplifier comprising a transistor, and a feedback resistor connecting the input and output of the inverting amplifier.

[0050] The crystal oscillator circuit 23 may include one or more first capacitors 23c and one or more second capacitors 23d. One end of the exemplary first capacitor 23c may be connected to the input of amplifier 23b, and one end of the second capacitor 23d may be connected to the output of amplifier 23b.

[0051] The first capacitor 23c may include a variable capacitance diode, and the second capacitor 23d may also include a variable capacitance diode. The other ends of these variable capacitance diodes can be connected to the control output of the control circuit 25, specifically, they can receive control signals from the control output of the control circuit 25 via the multilayer device 21. The oscillation characteristics of the crystal oscillator circuit 23 can be changed in response to the control signals from the control circuit 25.

[0052] Referring to Figures 3(a) and 3(b), the exemplary control circuit 25 may include a circuit configured to adjust the temperature characteristics of the oscillation frequency of the crystal oscillator circuit 23. Specifically, the exemplary control circuit 25 may include a temperature sensor 25b, a temperature compensation circuit 25c, and an amplification circuit 25d.

[0053] The control circuit 25 generates a control signal that adjusts the temperature characteristics of the oscillation frequency of the crystal oscillator circuit 23 in response to the sensor signal from the temperature sensor 25b. The control circuit 25 is configured to control the variable capacitance capacitors (VP1, VP2) of the crystal oscillator circuit 23, as shown in Figures 3(a) and 3(b). The control of the variable capacitance capacitors (VP1, VP2) can be performed in common or individually.

[0054] The oscillation characteristics of the crystal oscillator circuit 23 can be changed in response to a control signal from the control circuit 25. Furthermore, the oscillation characteristics of the crystal oscillator circuit 23 can be changed according to the time constant of the passive elements of the multilayer device 21.

[0055] As shown in Figures 1 and 3, the output of the control circuit 25 can be connected to the input of the stacked device 21, and the output of the stacked device 21 can be connected to the control input of the crystal oscillator circuit 23. The crystal oscillator circuit 23 can be controlled by the control circuit 25 via the stacked device 21.

[0056] As shown in Figure 4, the passive elements of the exemplary multilayer device 21 can be connected to each other to form a filter circuit. The exemplary filter circuit may include a low-pass filter. However, the connection of the passive elements is not limited to a filter circuit, specifically a low-pass filter. The exemplary connection of the passive elements may include a series connection of the first resistive element 37b and the second resistive element 39b. However, the connection of the passive elements is not limited to a series connection.

[0057] In the exemplary multilayer device 21, the capacitor element 35b, the first resistor element 37b, and the second resistor element 39b are connected to form a low-pass filter. The exemplary time constant of the low-pass filter can be in the range of, for example, 2ms to 50ms, specifically 32ms.

[0058] The crystal oscillator circuit 23 can receive control signals from the control circuit 25 via the multilayer device 21. As shown in Figure 2, the multilayer device 21 may include one or more vertical interconnect regions (31j, 31k) that enable vertical electrical connections at the level of each section of the multilayer region (31m) including the stacked capacitor section 35, the first resistor section 37, and the second resistor section 39. The vertical interconnect regions (31j, 31k) may be located on one side, two sides, opposing sides, and / or around the perimeter of the multilayer region (31m).

[0059] Figure 5 shows the noise characteristics of the control signal from the control circuit 25 and the control signal through the low-pass filter. The horizontal axis represents frequency, and the vertical axis represents the noise characteristics as input-referred noise voltage density. The unit is volts / sqrt(Hz). All noise appearing at the output of the control circuit 25 (e.g., amplifier circuit 25d) is calculated by considering it as if it originated at the input. This allows the effect of the gain of the amplifier circuit to be removed from the noise characteristics. Input-referred noise can be calculated by dividing the output noise by the gain. The time constant of the low-pass filter in the circuit in which the characteristics of Figure 5 were measured was 32 ms.

[0060] In the exemplary semiconductor device 13, the crystal oscillator circuit 23, the control circuit 25, and the multilayer device 21 can be connected to a common ground wire. The crystal oscillator circuit 23 generates an oscillating signal with a certain amplitude through the electrical resonance of the amplifier 23b and the crystal oscillator 17. The operation of the crystal oscillator circuit 23 may affect the operation of the control circuit 25. A low-pass filter can attenuate components in the control signal from the control circuit 25 that exceed the cutoff frequency.

[0061] Furthermore, the passive elements of a low-pass filter can also generate noise depending on the characteristic values ​​of those passive elements, such as sheet resistance. The characteristics in Figure 5 show that the characteristics of a circuit including a low-pass filter have lower noise in the low-frequency range compared to the characteristics of a circuit without a low-pass filter. This difference in characteristics indicates that a circuit including a low-pass filter is suitable for removing 1 / f noise.

[0062] Referring again to Figure 1, the stacked device 21 can be provided in the first region 31f of the main surface 31b of the support 31. The main surface 31b of the support 31 may further include a second region 31g and a third region 31h. The crystal oscillator circuit 23 can be provided in the third region 31h of the support 31, and the control circuit 25 can be provided in the second region 31g of the support 31.

[0063] The support 31 may have one or more conductive layers and one or more insulating regions for the semiconductor device 13, where the insulating regions, such as shallow trench isolation (STI), insulate the conductive layers, such as impurity-doped silicon regions. The conductive layers and insulating regions are arranged to constitute the transistors of the crystal oscillator circuit 23 and the control circuit 25.

[0064] The electrical vibrations of the crystal oscillator circuit 23 can propagate to the control circuit 25 via a conductor or as radiation.

[0065] As shown in the cross-section of Figure 2, the laminated device 21 includes multiple conductive layers and multiple insulating layers, as well as interconnects connecting the multiple conductive layers, in the direction of the lamination axis AxS. The stacking of conductors can act to shield against radiation.

[0066] As can be seen from the cross-section in Figure 2, the stacked device 21 is located in the upper part of the semiconductor device 13, while the circuit regions, such as the crystal oscillator circuit 23 and the control circuit 25, include transistors located in the lower part of the semiconductor device 13.

[0067] As can be understood from the above explanation, each of the second region 31g and the third region 31h is configured to include active elements. The exemplary multilayer device 21 can be configured to include only passive elements, and the first region 31f may not include active elements.

[0068] Referring to Figure 1, in the exemplary semiconductor device 13, the first region 31f can be provided between the second region 31g and the third region 31h.

[0069] The stacked device 21 in the first region 31f can separate one of the control circuit 25 in the second region 31g and the crystal oscillator circuit 23 in the third region 31h from the other.

[0070] Furthermore, the second region 31g, the first region 31f, and the third region 31h can be arranged along the direction of the first axis Ax1.

[0071] The stacked device 21 in the first region 31f can separate the control circuit 25 in the second region 31g from the crystal oscillator circuit 23 in the third region 31h with respect to the direction of the first axis Ax1 at a position defined in the direction of the second axis Ax2 which intersects the first axis Ax1 and the stacking axis AxS.

[0072] As can be understood from the above description, the area of ​​the multilayer device 21 can be used as dedicated areas for the capacitor section 35, the first resistor section 37, and the second resistor section 39 at each of the multilayer element levels of the multilayer structure 33. Multiple types of resistor elements with different resistivity (or sheet resistance) make it possible to expand the implementation range of the low-pass filter's cutoff frequency when the multilayer device 21 functions as a low-pass filter.

[0073] The area occupied by the multilayer device 21 on the main surface 31b of the support 31 is smaller than the combined area of ​​the capacitor portion 35, the first resistor portion 37, and the second resistor portion 39. On the other hand, each of the areas of the capacitor portion 35, the first resistor portion 37, and the second resistor portion 39 is smaller than the area of ​​the first region 31f in terms of element area. Where possible, the mounting area of ​​the first resistor layer 37c and / or the second resistor layer 39c can be extended outside the multilayer device 21 so as not to interfere with the longitudinal interconnect.

[0074] Figures 6 to 20 show cross-sections of intermediate products in the main steps of the method for manufacturing a semiconductor device according to this embodiment. These cross-sections correspond to the cross-sections shown in Figure 3. Figures 6 to 20 show the progress of the intermediate products processed according to the application of the steps of the manufacturing method according to this embodiment. In the following description, identical or similar parts of already described components will be denoted by the same or similar reference numerals for ease of understanding.

[0075] Referring to Figure 6, the manufacturing method includes step S101. In step S101, a support 31 such as a semiconductor substrate (e.g., a silicon wafer) is prepared, and an intermediate product 51 is fabricated on the semiconductor substrate by applying a semiconductor process, for example, one used to fabricate complementary transistors. The support 31 thus obtained may include one or more semiconductor elements formed in circuit regions (23, 24, 25). Specifically, the exemplary circuit regions (23, 25) may include a crystal oscillator circuit 23 and a control circuit 25, and may further include a switching circuit 24. The exemplary switching circuit 24 may be configured to switch the passive elements of the stacked device 21.

[0076] Referring to Figure 7, this manufacturing method includes step S102. In step S102, an interlayer region 32 is created on the intermediate product 51 to obtain an intermediate product 54. Specifically, an inorganic insulating film, such as silicon oxide, is deposited on the support 31 by chemical vapor deposition (CVD), and the surface of this inorganic insulating film is planarized to form an inorganic insulating layer. Openings to the circuit regions (23, 24, 25) of the lower layer are formed in this inorganic insulating layer by photolithography and etching to obtain an inorganic insulating layer 52. After this, a metal film is deposited on the inorganic insulating layer 52, and this metal film is processed by photolithography and etching to form an interlayer interconnect 32c. After forming the patterned metal film, specifically the interlayer interconnect 32c, an inorganic insulating film such as silicon oxide covering the interlayer interconnect 32c is deposited by CVD, and the surface of the inorganic insulating film is planarized to form an inorganic insulating layer 53, thereby producing the intermediate product 54.

[0077] Referring to Figure 8, the manufacturing method includes step S103. In step S103, a first resistive layer 37c is formed on the intermediate product 54 to form an intermediate product 55. Specifically, a polysilicon film is deposited by CVD, and a pattern is formed on the polysilicon film by photolithography and etching to obtain the first resistive layer 37c. The polysilicon film may have a desired dopant added to it.

[0078] Referring to Figure 9, the manufacturing method includes step S104. In step S104, a wiring structure is formed on the first resistive layer 37c of the intermediate product 55 to form the intermediate product 56. Specifically, an inorganic insulating film such as silicon oxide is deposited so as to cover the first resistive layer 37c, and the surface of the thus deposited inorganic insulating film is planarized to form an inorganic insulating layer. This inorganic insulating layer is processed by photolithography and etching to form the first element isolation layer 37d. The first element isolation layer 37d has an opening to the interlayer interconnect 32c of the lower layer. After forming the opening in the inorganic insulating layer, a metal film is deposited on the first element isolation layer 37d, and this metal film is processed by photolithography and etching to form the first conductive layer 37f (first electrode 37h and second electrode 37j).

[0079] Referring to Figure 10, the manufacturing method includes step S105. In step S105, a planarized film is grown to produce an intermediate product 58. Specifically, an inorganic insulating film covering the patterned first conductive layer 37f (first electrode 37h and second electrode 37j) is deposited by CVD, and the surface of the thus deposited inorganic insulating film is planarized to form an inorganic insulating layer 57. The inorganic insulating film may include, for example, silicon oxide.

[0080] Referring to Figure 11, this manufacturing method includes step S106. In step S106, a second resistive layer 39c is formed on the intermediate product 58 to form an intermediate product 59. Specifically, a metal film is deposited on the inorganic insulating layer 57, for example by sputtering, and a pattern is formed on the metal film by lift-off to obtain the second resistive layer 39c.

[0081] Referring to Figure 12, this manufacturing method includes step S107. In step S107, a wiring structure is formed on the second resistive layer 39c of the intermediate product 59 to form the intermediate product 60. Specifically, an inorganic insulating film such as silicon oxide is deposited, and the surface of the inorganic insulating film is planarized to form an inorganic insulating layer. This inorganic insulating layer is processed by photolithography and etching to form an element isolation layer 39d having an opening to the lower first conductive layer 37f. After this, a metal film is deposited on the element isolation layer 39d, and this metal film is processed by photolithography and etching to form a second conductive layer 39f (first electrode 39h and second electrode 39j).

[0082] Referring to Figure 13, this manufacturing method includes step S108. In step S108, a planarized film is formed to produce an intermediate product 62. Specifically, an inorganic insulating film is deposited to cover the second conductive layer 39f (first electrode 39h and second electrode 39j), and the surface of the inorganic insulating film is planarized to form an inorganic insulating layer 61, thereby obtaining the intermediate product 62.

[0083] Referring to Figure 14, the manufacturing method includes step S109. In step S109, a wiring structure is formed on the intermediate product 62 to form the intermediate product 63. Specifically, the inorganic insulating layer 61 is processed by photolithography and etching to form the second wiring isolation layer 39g from the inorganic insulating layer 61. The second wiring isolation layer 39g has openings to the lower second conductive layer 39f (first electrode 39h and second electrode 39j). After forming the openings, a metal film is deposited on the second wiring isolation layer 39g and a pattern is formed on this metal film to form the lower conductive layer 35c and the first capacitor electrode 35h to obtain the intermediate product 63.

[0084] Referring to Figure 15, the manufacturing method includes step S110. In step S110, an inorganic insulating layer 64 is formed to insulate the lower conductive layer 35c from the upper conductive layer 35f, thereby forming an intermediate product 65. For example, an inorganic insulating film, specifically a dielectric film for the capacitor element 35b, is deposited to cover the lower conductive layer 35c and the first capacitor electrode 35h, and the surface of the inorganic insulating film is planarized to form the inorganic insulating layer 64, thereby obtaining the intermediate product 65. The inorganic insulating layer 64 may contain silicon oxide. The thickness of the inorganic insulating layer 64 on the first capacitor electrode 35h defines the distance between the electrodes of the capacitor element 35b.

[0085] Referring to Figure 16, the manufacturing method includes step S111. In step S111, a wiring structure is formed on the inorganic insulating layer 64 of the intermediate product 65 to form the intermediate product 66. Specifically, the inorganic insulating layer 64 is processed by photolithography and etching to form a first isolation layer 35d from the inorganic insulating layer 64. The first isolation layer 35d has openings to the lower conductive layer 35c and the first capacitor electrode 35h of the lower layer. After forming the openings, a patterned metal film is formed on the first isolation layer 35d to obtain the upper conductive layer 35f and the second capacitor electrode 35j. This gives the intermediate product 66.

[0086] Referring to Figure 17, the manufacturing method includes step S112. In step S112, an inorganic insulating film 68 is deposited to cover the upper conductive layer 35f and the second capacitor electrode 35j of the intermediate product 66, thereby forming an intermediate product 67. Specifically, the inorganic insulating film 68 is deposited on the upper conductive layer 35f and the second capacitor electrode 35j by CVD. The inorganic insulating film 68 may contain silicon oxide.

[0087] These processes are used to fabricate the stacked device 21.

[0088] In this embodiment, since the upper conductive layer 35f is the uppermost conductive layer of the semiconductor device 13, one electrode of the upper conductive layer 35f is prepared as a pad electrode for external connection.

[0089] Referring to Figure 18, the manufacturing method includes step S113. In step S113, an inorganic insulating film 68 covering the upper conductive layer 35f, which serves as a pad electrode for external connection, is processed to form an intermediate product 69. Specifically, an opening is formed in the inorganic insulating film 68 covering the electrode of the upper conductive layer 35f by photolithography and etching to form a second isolation layer 35g. An opening 35n is provided in the second isolation layer 35g. The electrode surface of the upper conductive layer 35f is exposed in the opening 35n.

[0090] Referring to Figure 19, the manufacturing method includes step S114. In step S114, a passivation coating 70 is deposited on the intermediate product 69 by plasma CVD to obtain an intermediate product 71. The coating 70 covers the second isolation layer 35g and the opening 35n. The coating 70 may contain silicon nitride.

[0091] Referring to Figure 20, the manufacturing method includes step S115. In step S115, an opening is formed in the coating film 70 by photolithography and etching to form an intermediate product 72. Specifically, the passivation film 40 is provided with an opening 40n. The passivation film 40 covers the second isolation layer 35g and the edge of the opening 35n.

[0092] The intermediate product 72 is separated along isolation regions such as scribe areas to produce the semiconductor chip 12.

[0093] As can be understood from the above description, according to this embodiment, a multilayer device, semiconductor device, crystal oscillator, and system can be provided that can expand the implementation range of the cutoff frequency of the low-pass filter.

[0094] This embodiment has various aspects as described below.

[0095] The first side of the stacked device according to this embodiment comprises a support having a main surface and a stacked structure including a plurality of passive elements, wherein the stacked structure includes at least one capacitor portion and a plurality of resistor portions in a first region of the main surface of the support, the resistor portion includes at least a first resistor portion and a second resistor portion, the first resistor portion, the second resistor portion and the capacitor portion are arranged in the direction of the stacking axis intersecting the main surface, the capacitor portion includes a capacitor element as one of the passive elements, the first resistor portion includes a first resistor element comprising a first resistor material as one of the passive elements, and the second resistor portion includes a second resistor element comprising a second resistor material different from the first resistor material as one of the passive elements.

[0096] In the stacked device of the second side surface according to the first side surface of this embodiment, the first resistive portion has a first resistive layer including either a polysilicon layer or a metal thin film, a first element isolation layer covering the first resistive layer, a first conductive layer provided on the first element isolation layer, and a first wiring isolation layer covering the first conductive layer, wherein the first conductive layer may include a first electrode connected to one end of the first resistive layer and a second electrode connected to the other end of the first resistive layer.

[0097] In a laminated device of the third side according to the second side according to this embodiment, the laminated device further comprises an interlayer region between the support and the laminated structure, the interlayer region includes an interlayer insulating region and an interlayer interconnect, the first conductive layer includes a first interconnect, the first interconnect is connected to the interlayer interconnect via an opening in the interlayer insulating region, the support includes one or more semiconductor elements, and the interlayer interconnect can be connected to the semiconductor elements via an opening in the interlayer insulating region.

[0098] In the laminated device of the second or third side according to this embodiment, the second resistive portion has a second resistive layer including either the polysilicon layer or the metal thin film, a second element isolation layer covering the second resistive layer, a second conductive layer provided on the second element isolation layer, and a second wiring isolation layer covering the second conductive layer, wherein the second conductive layer may include a first electrode connected to one end of the second resistive layer and a second electrode connected to the other end of the second resistive layer.

[0099] In the stacked device of the fifth side according to the fourth side according to this embodiment, the first resistive element, the second resistive element, and the capacitor element can be arranged in order in the direction of the stacking axis.

[0100] In the stacked device of the sixth side according to the fifth side according to this embodiment, the second conductive layer includes a second interconnect, the second interconnect can be connected to the first conductive layer through openings in the first wiring isolation layer and the second element isolation layer.

[0101] In the laminated device of the fifth or sixth side according to this embodiment, the capacitor portion comprises a lower conductive layer, a first isolation layer covering the lower conductive layer, an upper conductive layer provided on the first isolation layer, and a second isolation layer covering the upper conductive layer, wherein the lower conductive layer includes a first capacitor electrode, the upper conductive layer includes a second capacitor electrode, and the first isolation layer may include a dielectric layer between the first capacitor electrode and the second capacitor electrode.

[0102] In the laminated device of the eighth side according to the seventh side according to this embodiment, the lower conductive layer includes a third interconnect, the third interconnect can be connected to the second conductive layer through an opening in the second wiring isolation layer.

[0103] In the laminated device with a ninth side according to the seventh or eighth side according to this embodiment, the upper conductive layer includes a fourth interconnect, which can be connected to the lower conductive layer through an opening in the first isolation layer.

[0104] The semiconductor device according to the tenth side of this embodiment comprises a multilayer device described on any one of the first to ninth sides, a resonant circuit connected to the multilayer device, and a control circuit configured to control the resonant circuit and also connected to the multilayer device, wherein the capacitor element, the first resistor element, and the second resistor element are connected to constitute a low-pass filter, and the control circuit may include a circuit configured to adjust the temperature characteristics of the oscillation frequency of the resonant circuit.

[0105] In the semiconductor device relating to the 11th side according to the 10th side of this embodiment, the main surface of the support further includes a second region and a third region, the resonant circuit is provided in the second region of the support, the control circuit is provided in the third region of the support, and the first region can be provided between the second region and the third region.

[0106] In a semiconductor device according to the twelfth aspect of the eleventh aspect of this embodiment, the resonant circuit may include an amplifier configured to cause a crystal oscillator to oscillate.

[0107] In the semiconductor device according to the 13th aspect of the 12th aspect of this embodiment, the stacked device, the resonant circuit, and the control circuit are mounted on a semiconductor chip, the semiconductor device comprises a package that houses the semiconductor chip, and the crystal oscillator can be housed in the package.

[0108] In a semiconductor device relating to the 14th aspect according to the 12th aspect of this embodiment, the stacked device, the resonant circuit, and the control circuit are mounted on a semiconductor chip, the semiconductor device comprises a package housing the semiconductor chip, and the crystal oscillator is not housed in the package.

[0109] The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit of the invention. All of these modifications are included in the technical concept of the present invention. [Explanation of Symbols]

[0110] 11...system, 12. Semiconductor chips, 13. Semiconductor equipment, 13b...electrode, 14. Package, 14b...electrode, 14c...conductor 15. Wiring board, 15b...Wiring layer, 17...Crystal oscillator, 21. Stacked devices, 23. Crystal oscillator circuit, 23b... Amplifier, 23c, 23d...capacitors, 24... Switching circuit, 25...control circuit, 25b...Temperature sensor, 25c...Temperature compensation circuit, 25d... Amplifier circuit, 31...Support, 31b...principal surface, 31f...first area, 31g...Second area, 31h...Second area, 32...interlayer area, 32b...Interlayer insulation region, 32c... Inter-floor interconnect, 33. Laminated structures, 35. Capacitor section, 35b... Capacitor element, 35c...lower conductive layer, 35d...Isolation layer, 35f...upper conductive layer, 35g...Isolation layer, 35h...First capacitor electrode, 35j...Second capacitor electrode, 35k...1st interconnect, 35m...Second interconnect, 35n...Aperture, 35di...dielectric layer, 37...first resistor section, 37b...First resistive element, 37c...first resistance layer, 37d...First element isolation layer, 37f...conductive layer, 37g...First wiring isolation layer, 37h...1st electrode, 37j...Second electrode, 37k...interconnect, 39...Second resistance section, 39b...Second resistance element, 39c...Second resistance layer, 39d... Inorganic insulating layer, 39d...Second element isolation layer, 39f...conductive layer, 39g...Second wiring isolation layer 39h...1st electrode, 39j...Second electrode, 39k...interconnect, 40... Passivation membrane, 40n...Aperture, 41...Insulation area, 50, 52, 53, 57, 61, 64... Inorganic insulating layer, 51, 54-56, 58-60, 62, 63, 65-68, 70, 71... Intermediate products, 69...Coating film, Ax1...1st axis, Ax2...2nd axis, AxS...Stacked axis.

Claims

1. A support having a main surface, A laminated structure containing multiple passive elements, Equipped with, The laminated structure includes at least one capacitor portion and a plurality of resistor portions in the first region of the main surface of the support, The resistive section includes at least a first resistive section and a second resistive section. The first resistor, the second resistor, and the capacitor are arranged in the direction of the stacking axis intersecting the main surface. The capacitor section includes a capacitor element as one of the passive elements, The first resistive section includes a first resistive element comprising a first resistive material as one of the passive elements, The second resistive section includes a second resistive element, which is made of a second resistive material different from the first resistive material, as one of the passive elements. Stacked devices.

2. The first resistive portion comprises a first resistive layer containing either a polysilicon layer or a metal thin film, a first element isolation layer covering the first resistive layer, a first conductive layer provided on the first element isolation layer, and a first wiring isolation layer covering the first conductive layer. The first conductive layer includes a first electrode connected to one end of the first resistive layer and a second electrode connected to the other end of the first resistive layer. A stacked device as described in claim 1.

3. The laminated device further comprises an interlayer region between the support and the laminated structure, The interlayer region includes an interlayer insulation region and an interlayer interconnect. The first conductive layer includes a first interconnect. The first interconnect is connected to the interlayer interconnect via an opening in the interlayer insulation region, The support comprises one or more semiconductor elements. The interlayer interconnect is connected to the semiconductor element via an opening in the interlayer insulating region. The stacked device according to claim 2.

4. The second resistive portion comprises a second resistive layer containing either the polysilicon layer or the metal thin film, a second element isolation layer covering the second resistive layer, a second conductive layer provided on the second element isolation layer, and a second wiring isolation layer covering the second conductive layer. The second conductive layer includes a first electrode connected to one end of the second resistive layer and a second electrode connected to the other end of the second resistive layer. The stacked device according to claim 2.

5. The first resistive element, the second resistive element, and the capacitor element are arranged in order in the direction of the stacking axis. The stacked device according to claim 4.

6. The second conductive layer includes a second interconnect. The second interconnect is connected to the first conductive layer through openings in the first wiring isolation layer and the second element isolation layer. The stacking device according to claim 5.

7. The capacitor portion comprises a lower conductive layer, a first isolation layer covering the lower conductive layer, an upper conductive layer provided on the first isolation layer, and a second isolation layer covering the upper conductive layer. The lower conductive layer includes the first capacitor electrode, The upper conductive layer includes a second capacitor electrode. The first isolation layer includes a dielectric layer between the first capacitor electrode and the second capacitor electrode. The stacking device according to claim 5.

8. The lower conductive layer includes a third interconnect. The third interconnect is connected to the second conductive layer through an opening in the second wiring isolation layer. The stacked device according to claim 7.

9. The upper conductive layer includes a fourth interconnect. The fourth interconnect is connected to the lower conductive layer via an opening in the first isolation layer. The stacked device according to claim 7.

10. A stacked device as described in any one of claims 1 to 9, A resonant circuit connected to the aforementioned multilayer device, A control circuit configured to control the resonant circuit and connected to the multilayer device, Equipped with, The capacitor element, the first resistor element, and the second resistor element are connected to form a low-pass filter. The control circuit includes a circuit configured to adjust the temperature characteristics of the oscillation frequency of the resonant circuit. Semiconductor equipment.

11. The main surface of the support further includes a second region and a third region, The resonant circuit is provided in the second region of the support, The control circuit is provided in the third region of the support, The first region is provided between the second region and the third region. The semiconductor device described in claim 10.

12. The aforementioned resonant circuit includes an amplifier configured to cause a crystal oscillator to oscillate. The semiconductor device according to claim 11.

13. The stacked device, the resonant circuit, and the control circuit are mounted on a semiconductor chip. The semiconductor device comprises a package that houses the semiconductor chip, The crystal oscillator is housed in the package, The semiconductor device according to claim 12.

14. The stacked device, the resonant circuit, and the control circuit are mounted on a semiconductor chip. The semiconductor device comprises a package that houses the semiconductor chip, The crystal oscillator is not housed in the package. The semiconductor device according to claim 12.

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