Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor device that can form marks more appropriately. [Solution] The method for manufacturing a semiconductor device according to this embodiment comprises forming an insulating film on a substrate. The manufacturing method also comprises forming a recess on the upper surface of the insulating film. The manufacturing method also comprises forming a hydrophobic first film on the upper surface of the insulating film and on the inner surface of the recess. The manufacturing method also comprises making the upper surface of the first film hydrophilic. The manufacturing method also comprises polishing the first film until the upper surface of the insulating film is exposed.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device.

Background Art

[0002] In the manufacturing process of a semiconductor device, when multiple exposure processes are performed, the position of the alignment mark may be detected, and the next exposure process may be performed based on the position of the alignment mark. For the overlay accuracy between the previous exposure process and the next exposure process, it is desirable to form an alignment mark with good visibility.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a method for manufacturing a semiconductor device and a semiconductor device that can form a mark more appropriately.

Means for Solving the Problems

[0005] The method for manufacturing a semiconductor device according to this embodiment comprises forming an insulating film on a substrate. The manufacturing method also comprises forming a recess on the upper surface of the insulating film. The manufacturing method also comprises forming a hydrophobic first film on the upper surface of the insulating film and on the inner surface of the recess. The manufacturing method also comprises making the upper surface of the first film hydrophilic. The manufacturing method also comprises polishing the first film until the upper surface of the insulating film is exposed. [Brief explanation of the drawing]

[0006] [Figure 1] This is a perspective view showing the configuration of a semiconductor device according to the first embodiment. [Figure 2] This is a block diagram showing the configuration of a semiconductor device according to the first embodiment. [Figure 3] This is a circuit diagram showing the configuration of the memory cell array in the first embodiment. [Figure 4] This is a cross-sectional view showing the configuration of the memory cell array in the first embodiment. [Figure 5] This is an enlarged cross-sectional view showing the configuration of the memory cell array in the first embodiment. [Figure 6A] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6B] This is a cross-sectional view showing a method for manufacturing a semiconductor device, following Figure 6A. [Figure 6C] This is a cross-sectional view showing a method for manufacturing a semiconductor device, following Figure 6B. [Figure 6D] Figure 6C is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 6E] Figure 6D is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 6F] This is a cross-sectional view showing a method for manufacturing a semiconductor device, following Figure 6E. [Figure 6G] Figure 6F is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 6H] Figure 6G is a cross-sectional view showing a method for manufacturing a semiconductor device. [Figure 6I]It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 6H. [Figure 7] It is a cross-sectional view showing the configuration of a mark according to the first embodiment. [Figure 8A] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8B] It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 8A. [Figure 8C] It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 8B. [Figure 8D] It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 8C. [Figure 8E] It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 8D. [Figure 9] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example. [Figure 10] It is a cross-sectional view showing the configuration of a mark according to the second embodiment. [Figure 11A] It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 11B] It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 11A. [Figure 11C] It is a cross-sectional view showing a method for manufacturing a semiconductor device following FIG. 11B.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the previous drawings, and detailed descriptions are omitted as appropriate.

[0008] (First Embodiment) The semiconductor device according to the first embodiment has a three-dimensional structure in which a columnar semiconductor film penetrates a laminate in which multiple conductive layers are stacked with an insulating layer in between, and the portions in close proximity between each conductive layer and the semiconductor film function as memory cells. This semiconductor device incorporates features to improve operational reliability.

[0009] The semiconductor device 1 is configured as shown in Figure 1. Figure 1 is a perspective view showing the schematic configuration of the semiconductor device 1.

[0010] In the following explanation, the directions that are orthogonal to each other in a plane parallel to the surface of the substrate SUB are defined as the X and Y directions. More specifically, the X direction is the direction in which the word line WL extends, and the Y direction is the direction in which the bit line BL extends. The Z direction is the direction perpendicular to the surface of the substrate SUB. Therefore, the Z direction is perpendicular to the X and Y directions.

[0011] As shown in Figure 1, the semiconductor device 1 includes a selection gate SGS, a word line WL, and a selection gate SGD. The selection gate SGS is laminated on the substrate SUB via an insulating layer 7. In the example in Figure 1, three layers of selection gate SGS are provided. The word line WL is laminated on top of the uppermost selection gate SGS via an insulating layer 7. In the example in Figure 1, multiple layers of word line WL are provided alternately with the insulating layer 7 along the Z direction. The selection gate SGD is laminated on top of the uppermost word line WL via an insulating layer 7. The selection gate SGS, word line WL, and selection gate SGD are plate-shaped and extend in the X and Y directions, respectively.

[0012] In the example shown in Figure 1, the selection gate SGD, word line WL, and selection gate SGS are separated and insulated in the Y direction by the slit ST. The source line SL is located on the +Z side of the substrate SUB via the interlayer insulating film 81. The slit ST is provided on the +Z side of the source line SL and extends in the X and Z directions.

[0013] The selection gate SGD is divided in the Y direction by, for example, a dividing film SHE. In the example in Figure 1, selection gates SGD0 and SGD1 divided in the Y direction are shown. The dividing film SHE is provided above the word line WL (+Z side) and extends in the X and Z directions. Therefore, selection gates SGD0 and SGD1 are arranged side by side in the Y direction on the word line WL. In the example in Figure 1, three layers each of selection gates SGD0 and SGD1 are provided.

[0014] The substrate SUB is, for example, a silicon substrate. The select gate SGS, word line WL, and select gate SGD are, for example, metal layers containing tungsten (W). The insulating layer 7 and the interlayer insulating film 81 are, for example, insulators containing silicon oxide.

[0015] The semiconductor device 1 further comprises a plurality of columnar bodies 4. The columnar bodies 4 extend in the Z direction, which is the stacking direction, through the selection gate SGS, the word line WL, and the selection gate SGD. The semiconductor device 1 further comprises a plurality of bit lines BL provided above the selection gate SGD.

[0016] Each of the columnar bodies 4 is electrically connected to the bit line BL via a contact plug 31. For example, one of the columnar bodies 4 that share selection gate SGD0 and one of the columnar bodies 4 that share selection gate SGD1 are electrically connected to the same bit line BL.

[0017] Note that in Figure 1, the interlayer insulating film provided between the selection gate SGD and the bit line BL has been omitted for the sake of simplicity in the illustration.

[0018] In semiconductor device 1, the selection gate SGD, word line WL, and selection gate SGS are each composed of conductive layers. On the +Z side of the source line SL, a laminate SST is formed in which conductive layers and insulating layers 7 are alternately stacked. The laminate SST is penetrated by a columnar body 4 to form a three-dimensional arrangement of memory cells (memory cell array).

[0019] In other words, in the semiconductor device 1, the portion where the word line WL intersects with the columnar body 4 is configured to function as a memory cell, and a memory cell array 2 is formed in which multiple memory cells are arranged three-dimensionally. Furthermore, the portion where the selection gate SGS intersects with the columnar body 4 functions as the source-side selection gate, and the portion where the selection gates SGD0, SGD1 intersect with the columnar body 4 functions as the drain-side selection gate. In the semiconductor device 1, by increasing the number of stacked word lines WL in the stacked body SST, it is possible to increase the storage capacity without using finer patterning techniques.

[0020] Figure 2 is a block diagram showing the schematic configuration of the semiconductor device 1.

[0021] As shown in Figure 2, the semiconductor device 1 has a memory cell array 2, peripheral circuits 100, and an interface 200. The peripheral circuits 100 include a WL drive circuit 110, an SGS drive circuit 120, an SGD drive circuit 130, an SL drive circuit 140, and a sense amplifier circuit 150.

[0022] The WL drive circuit 110 controls the voltage applied to the word line WL, and the SGS drive circuit 120 controls the voltage applied to the selection gate SGS. The SGD drive circuit 130 controls the voltage applied to the selection gate SGD, and the SL drive circuit 140 controls the voltage applied to the source line SL. The sense amplifier circuit 150 controls the voltage applied to the bit line BL and also determines the data read out according to the signal from the selected memory cell.

[0023] The peripheral circuit 100 controls the operation of the semiconductor device 1 based on instructions input from an external source (for example, the memory controller of the memory system to which the semiconductor device 1 is applied) via the interface 200.

[0024] Next, the circuit configuration of memory cell array 2 will be explained using Figure 3. Figure 3 is a circuit diagram showing the configuration of memory cell array 2.

[0025] The memory cell array 2 has multiple blocks BLK, each of which is a collection of multiple memory cell transistors MT. Hereafter, we will simply refer to the memory cell transistors MT as memory cells MT.

[0026] Each block BLK has multiple string units SU0, SU1, SU2, SU3, which are sets of memory cells MT associated with word lines WL and bit lines BL. Each string unit SU0 to SU3 has multiple memory strings MST, in which memory cells MT are connected in series. The number of memory strings MST within each string unit SU0 to SU3 is arbitrary.

[0027] Multiple string units SU0, SU1, SU2, and SU3 correspond to multiple selection gates SGD0, SGD1, SGD2, and SGD3, and share a selection gate SGS, functioning as multiple drive units in block BLK. Each string unit SU can be driven by its corresponding selection gate SGD and selection gate SGS. Each string unit SU also contains multiple memory strings MST.

[0028] Each memory string MST contains, for example, 10 memory cells MT (MT0 to MT9) and selection transistors DGT and SGT. Each memory cell MT has a control gate and a charge storage film, and stores data non-volatilely. The 10 memory cells MT are connected in series between the source of the selection transistor DGT and the drain of the selection transistor SGT. Note that the number of memory cells MT in a memory string MST is not limited to 10.

[0029] The gates of the selection transistors DGT in each string unit SU0 to SU3 are connected to the selection gates SGD0 to SGD3, respectively. In contrast, the gates of the selection transistors SGT in each string unit SU are connected to a common selection gate, for example, SGS.

[0030] The drains of the selection transistor DGT of each memory string MST within each string unit SU are connected to different bit lines BL0 to BLk (where k is any integer greater than or equal to 2). Furthermore, the bit lines BL0 to BLk connect a single memory string MST within each string unit SU across multiple blocks BLK. Additionally, the sources of each selection transistor SGT are commonly connected to the source line SL.

[0031] In other words, a string unit SU is a collection of memory strings MST connected to different bit lines BL0~BLk and the same selection gate SGD. Each block BLK is a collection of multiple string units SU0~SU3 that share a common word line WL. And memory cell array 2 is a collection of multiple block BLKs that share a common bit line BL0~BLk.

[0032] If we refer to a group of memory cells (MTs) that share a word line (WL) as a "memory cell group (MCG)," then a memory cell group (MCG) is the smallest unit of a collection of memory cells (MTs) to which a predetermined voltage (e.g., write voltage, read voltage) can be applied collectively via the word line (WL).

[0033] Furthermore, dummy word lines DWL1 and DWL2 are provided between word line WL4 and word line WL5. Between memory cell MT4 and memory cell MT5 in each memory string MST, dummy memory cells DMT1 and DMT2 are provided corresponding to dummy word lines DWL1 and DWL2. Dummy memory cells DMT1 and DMT2 have the same structure as memory cells MT and are not used for data storage.

[0034] Next, the cross-sectional configuration of the memory cell array 2 will be explained using Figure 4. Figure 4 is a cross-sectional view showing the configuration of the memory cell array 2.

[0035] In the semiconductor device 1, a conductive layer 3 is disposed on the +Z side of the substrate SUB via an interlayer insulating film 81. The conductive layer 3 may be formed from a material mainly composed of a semiconductor containing impurities (e.g., silicon) or a material mainly composed of a conductive material (e.g., a metal such as tungsten). The conductive layer 3 extends in a plate-like manner in the XY direction and functions as a source line SL (see Figure 1). Multiple columnar bodies 4 are disposed on the +Z side of the conductive layer 3. The multiple columnar bodies 4 are arranged in the XY direction. Each columnar body 4 extends in the Z direction and penetrates the laminate SST (see Figure 1).

[0036] The laminated SST has a structure in which multiple laminates SST1 and SST2 are stacked. Figure 4 illustrates a structure in which the laminated SST is divided into two laminates SST1 and SST2, but the laminated SST may be divided into three or more.

[0037] In each columnar body 4 shown in Figure 4, a tier 4a, a joint portion 4b, a tier 4c, and a cap layer 4d are sequentially laminated on the +Z side of the conductive layer 3. In the laminated SST, laminated SST1, a joint layer JL, and laminated SST2 are sequentially laminated on the +Z side of the conductive layer 3. Laminated SST1 and SST2 are each constructed by laminating conductive layers 6, which function as word lines WL, etc., via insulating layers 7. Tear 4a extends in the Z direction and penetrates laminated SST1. Joint portion 4b has a Z position corresponding to joint layer JL. Joint layer JL can be formed from a material mainly composed of oxides (e.g., silicon oxide). Tear 4c extends in the Z direction and penetrates laminated SST2. The +Z end of tier 4a is joined to tier 4c via joint portion 4b. The cap layer 4d extends in a plate-like manner in the XY direction and covers the +Z end of tier 4c. The cap layer 4d may be formed from a material mainly composed of a semiconductor containing impurities (e.g., polysilicon). A conductive layer 9 is arranged on the +Z side of the laminate SST2 via interlayer insulating films 82 and 83. The conductive layer 9 may be formed from a material mainly composed of a conductor (e.g., a metal such as tungsten). The conductive layer 9 extends linearly in the Y direction and functions as a bit line BL (see Figure 1). The cap layer 4d is connected to the bit line BL via a contact plug 31.

[0038] As shown in Figure 5, each tier 4a, 4c has a columnar shape with central axes CA1, CA3 along the Z direction, for example, a substantially cylindrical shape. Figure 5 is an enlarged cross-sectional view showing the configuration near the joint portion 4b, and is an enlarged cross-sectional view of portion A in Figure 4. Each tier 4a, 4c may have a tapered shape in which the diameter at the -Z side end is narrower than the diameter at the +Z side end. Each tier 4a, 4c may have a bowing shape in which the diameter at the -Z side end is narrower than the diameter at the +Z side end, and the diameter widens at a predetermined Z position between the +Z side end and the -Z side end. The diameter at the -Z side end of tier 4c is smaller than the diameter at the +Z side end of tier 4a.

[0039] The joint portion 4b has a central axis CA2 along the Z direction and a disc shape extending in the XY direction. The -Z side of the joint portion 4b contacts the +Z side end of tier 4a, and the +Z side contacts the -Z side end of tier 4c. The joint portion 4b connects the +Z side end of tier 4a to the -Z side end of tier 4c, connecting tier 4a and tier 4c in the Z direction. The joint portion 4b has a diameter larger than the diameter of the +Z side end of tier 4a and a diameter larger than the diameter of the -Z side end of tier 4c. The XY position of the central axis CA2 of the joint portion 4b may be offset from the XY position of the central axis CA1 of tier 4a and / or the XY position of the central axis CA3 of tier 4c. That is, the XY position of the central axis CA1 of tier 4a and the XY position of the central axis CA3 of tier 4c may be offset from each other. This ensures a margin for XY alignment of tier 4a and tier 4c. The joint portion 4b has a width in the Z direction greater than the thickness in the Z direction of the conductive layer 6 and a width in the Z direction greater than the thickness in the Z direction of the insulating layer 7. This ensures a bonding margin between tiers 4a and tier 4c. Accordingly, the joint layer JL has a thickness in the Z direction greater than the thickness in the Z direction of the conductive layer 6 and a thickness in the Z direction greater than the thickness in the Z direction of the insulating layer 7.

[0040] As shown in Figure 5, tier 4a has, in order from the central axis CA1 side, a core member CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, and an insulating film BLK1. The core member CR is positioned near the central axis CA1 of tier 4a and has a substantially cylindrical shape extending along the central axis CA1 of tier 4a. The core member CR may be formed from a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide). The semiconductor film CH is positioned to surround the core member CR from the outside and has a substantially cylindrical shape extending along the central axis CA1 of tier 4a. The semiconductor film CH further covers the -Z end of the core member CR and is connected to the conductive layer 3. The semiconductor film CH may be formed from a material mainly composed of a substantially impurity-free semiconductor (e.g., polysilicon). The insulating film TNL is positioned to surround the semiconductor film CH from the outside and has a substantially cylindrical shape extending along the central axis CA1 of tier 4a. The insulating film TNL may be formed from a material mainly composed of an oxide (e.g., silicon oxide or silicon oxynitride). The charge storage film CT is positioned to surround the insulating film TNL from the outside and has a substantially cylindrical shape extending along the central axis CA1 of tier 4a. The charge storage film CT may be formed from a material mainly composed of nitrides (e.g., silicon nitride). The insulating film BLK1 is positioned to surround the charge storage film CT from the outside and has a substantially cylindrical shape extending along the central axis CA1 of tier 4a. The insulating film BLK1 may be formed from a material mainly composed of oxides (e.g., silicon oxide, metal oxide, or a stack thereof). This may result in an ONO-type three-layer structure in which the charge storage film CT is sandwiched between a pair of insulating films TNL and BLK1.

[0041] The joint portion 4b has, in order from the central axis CA2 side, a core member CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, and an insulating film BLK1. In the joint portion 4b, the core member CR has a substantially disc shape with a larger diameter than the core member CR of tier 4a. The semiconductor film CH has a hollow disc shape with a larger diameter than the semiconductor film CH of tier 4a. The insulating film TNL has a hollow disc shape with a larger diameter than the insulating film TNL of tier 4a. The charge storage film CT has a hollow disc shape with a larger diameter than the charge storage film CT of tier 4a. The insulating film BLK1 has a hollow disc shape with a larger diameter than the insulating film BLK1 of tier 4a.

[0042] Tier 4c comprises, in order from the central axis CA3 side, a core member CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, and an insulating film BLK1. The core member CR is positioned near the central axis CA3 of Tier 4c and has a substantially cylindrical shape extending along the central axis CA3 of Tier 4c. The semiconductor film CH is positioned to surround the core member CR from the outside and has a substantially cylindrical shape extending along the central axis CA3 of Tier 4c. The insulating film TNL is positioned to surround the semiconductor film CH from the outside and has a substantially cylindrical shape extending along the central axis CA3 of Tier 4c. The charge storage film CT is positioned to surround the insulating film TNL from the outside and has a substantially cylindrical shape extending along the central axis CA3 of Tier 4c. The insulating film BLK1 is positioned to surround the charge storage film CT from the outside and has a substantially cylindrical shape extending along the central axis CA3 of Tier 4c. The core component CR, semiconductor film CH, insulating film TNL, charge storage film CT, and insulating film BLK1 of tier 4c are formed from the same materials as the core component CR, semiconductor film CH, insulating film TNL, charge storage film CT, and insulating film BLK1 of tier 4a and joint portion 4b, respectively. This allows for the formation of an ONO-type three-layer structure in which the charge storage film CT is sandwiched between a pair of insulating films TNL and BLK1.

[0043] The semiconductor film CH of tier 4a is connected to the conductive layer 3 as the source line SL on the -Z side and to the semiconductor film CH of joint 4b on the +Z side. The semiconductor film CH of joint 4b is connected to the semiconductor film CH of tier 4c on the +Z side. The semiconductor film CH of tier 4c has its +Z end connected to the conductive layer 9, which functions as the bit line BL, via the cap layer 4d and contact plug 31. In other words, the semiconductor film CHs of tier 4a, joint 4b, and tier 4c include the channel region (active region) in the memory string MST.

[0044] In the laminates SST1 and SST2 shown in Figure 4, conductive layers 6 and insulating layers 7 are repeatedly and alternately laminated. Each conductive layer 6 extends in a plate-like shape in the XY direction. Each conductive layer 6 may be formed from a material mainly composed of a conductor (e.g., a metal such as tungsten). Each conductive layer 6 may be covered with an insulating film BLK2 on the +Z side, the -Z side, and the side facing tiers 4a and 4c. The insulating film BLK2 may have a different composition from the insulating film BLK1. The insulating film BLK2 may be formed from a material mainly composed of an insulator (e.g., metal oxides such as aluminum oxide, zirconium oxide, and hafnium oxide). Each insulating layer 7 extends in a plate-like shape in the XY direction. Each insulating layer 7 may be formed from a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide).

[0045] In the laminate SST1, of the multiple conductive layers 6 spaced apart from each other in the Z direction, at least the conductive layer 6 furthest to -Z functions as a selective gate SGS, at least the conductive layer 6 furthest to +Z functions as a dummy word line DWL1, and the other conductive layers 6 function as word lines WL0 to WL4. As shown in Figure 1, multiple conductive layers 6 on the -Z side may function as selective gate SGS, or similarly, multiple conductive layers 6 that function as dummy word lines DWL1 may be provided on the +Z side.

[0046] A selection transistor SGT is formed at the location where the conductive layer 6 of the selection gate SGS intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT0 is formed at the location where the conductive layer 6 of the word line WL0 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT1 is formed at the location where the conductive layer 6 of the word line WL1 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT2 is formed at the location where the conductive layer 6 of the word line WL2 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT3 is formed at the location where the conductive layer 6 of the word line WL3 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT4 is formed at the location where the conductive layer 6 of the word line WL4 intersects with the semiconductor film CH and the charge storage film CT. A dummy memory cell DMT1 is formed at the location where the conductive layer 6 of the dummy word line DWL1 intersects with the semiconductor film CH and the charge storage film CT. In addition, in tier 4a, the charge storage film CT and insulating film BLK1 may be partially omitted at the position where they intersect with the conductive layer 6 of the selected gate SGS.

[0047] In a laminate SST2 laminated on a laminate SST1 via a joint layer JL, of the multiple conductive layers 6 spaced apart from each other in the Z direction, at least the conductive layer 6 furthest to +Z functions as a selection gate SGD, at least the conductive layer 6 furthest to -Z functions as a dummy word line DWL2, and the other conductive layers 6 function as word lines WL5 to WL9. As shown in Figure 1, multiple conductive layers 6 on the +Z side may function as selection gate SGDs, or similarly, multiple conductive layers 6 that function as dummy word lines DWL2 may be provided on the -Z side.

[0048] A dummy memory cell DMT2 is formed at the location where the conductive layer 6 of the dummy word line DWL2 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT5 is formed at the location where the conductive layer 6 of the word line WL5 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT6 is formed at the location where the conductive layer 6 of the word line WL6 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT7 is formed at the location where the conductive layer 6 of the word line WL7 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT8 is formed at the location where the conductive layer 6 of the word line WL8 intersects with the semiconductor film CH and the charge storage film CT. A memory cell MT9 is formed at the location where the conductive layer 6 of the word line WL9 intersects with the semiconductor film CH and the charge storage film CT. A selection transistor DGT is formed at the location where the conductive layer 6 of the selection gate SGD intersects with the semiconductor film CH and the charge storage film CT. In addition, at the position where tier 4c intersects with the conductive layer 6 of the selected gate SGD, the charge storage film CT and insulating film BLK1 may be partially omitted.

[0049] In the process of writing information to a memory cell MT, a write voltage is applied to the conductive layer 6 of the selected word line WL, a transfer voltage is applied to the conductive layer 6 of the non-selected word line WL, and a reference voltage is applied to the semiconductor film CH. The write voltage has a potential (e.g., 20V) for injecting charge (electrons) from the semiconductor film CH into the charge storage film CT. The transfer voltage has a potential (e.g., 10V) between the write voltage and the reference voltage. The reference voltage has a reference potential (e.g., 0V). As a result, charge is accumulated in the charge storage film CT of the selected memory cell MT at the intersection of the conductive layer 6 of the selected word line WL and the semiconductor film CH, and information is written to the selected memory cell MT.

[0050] In the information erasure process for memory cells MT, a reference voltage is applied to the conductive layer 6 of each word line WL, an erasure voltage is applied to the semiconductor film CH, and an intermediate voltage between the two is applied to the selection gates SGS and SGD. The erasure voltage has a potential (e.g., 20V) for injecting the opposite charge (holes) of the semiconductor film CH into the charge storage film CT. The reference voltage has a reference potential (e.g., 0V). The intermediate voltage has a potential (e.g., 5V) between the erasure process and the reference voltage. Through this control, electron-hole pairs are generated by GIDL (Gate Induced Drain Leakage) near the drains of the selection transistors SGT and DGT, and the opposite charge (holes) is injected from the semiconductor film CH into the charge storage film CT. As a result, the charge stored in the charge storage film CT is erased, and the information in the memory cell MT can be erased.

[0051] At this time, as shown in Figure 5, the conductive layer 6 of the dummy word line DWL1 has a Z-direction gap G with the conductive layer 6 on the +Z side due to the presence of the joint portion 4b. D1D2 The distance G in the Z direction between the conductive layer 6 on the -Z side and the -Z side W4D1 It is larger. As a result, the electric field in the direction from the conductive layer 6 of the dummy word line DWL1 to the charge storage film CT is less affected by the voltage of the conductive layer 6 on the +Z side than by the voltage of the conductive layer 6 on the -Z side. Therefore, electric field concentration may occur at the corners of the +Z side surface 6a of the conductive layer 6 of the dummy word line DWL1. As a result, a back-tunneling phenomenon may occur in which charge tunneled through the insulating film BLK1 from the corners of the +Z side surface 6a of the conductive layer 6 of the dummy word line DWL1 is accumulated in the charge storage film CT near the joint 4b. The flow of charge that tunnels from the conductive layer 6 through the insulating film BLK1 and is accumulated in the charge storage film CT is also called a back-tunneling current. When the back-tunneling phenomenon occurs, unintended information is written to the charge storage film CT near the joint 4b, but since the conductive layer 6 of the word line WL does not exist near the joint 4b, it is difficult to erase the charge by injecting the opposite charge from the semiconductor film CH into the charge storage film CT.

[0052] On the other hand, the conductive layer 6 of the word line WL4 has a Z-direction gap G with respect to the conductive layer 6 on the +Z side. W4D1 The distance G in the Z direction between the conductive layer 6 on the -Z side and the -Z side W3W4 It is uniform. As a result, electric field concentration is less likely to occur in the conductive layer 6 of the word line WL4, unlike in the conductive layer 6 of the dummy word line DWL1.

[0053] Next, the manufacturing method of the semiconductor device 1 will be explained using Figures 6A to 6I. Figures 6A to 6I are cross-sectional views showing the manufacturing method of the semiconductor device 1, respectively.

[0054] In the process shown in Figure 6A, a transistor is formed on the substrate SUB (see Figure 1), and contact plugs, wiring films, via plugs, etc. are formed on the substrate SUB, and an interlayer insulating film 81 is formed around them. This forms the peripheral circuit 100. The interlayer insulating film 81 can be formed by depositing a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide) on the +Z side of the substrate SUB (see Figure 4). A conductive layer 3 is deposited on the +Z side of the interlayer insulating film 81. The conductive layer 3 can be formed from a material mainly composed of a semiconductor (e.g., silicon) containing impurities or a material mainly composed of a conductor (e.g., a metal such as tungsten).

[0055] A laminate SST1i is formed by alternately depositing an insulating layer 7i and a sacrificial layer 5i multiple times on the +Z side of the conductive layer 3. The insulating layer 7i may be made of a material mainly composed of oxides (e.g., silicon oxide). The sacrificial layer 5i may be made of a material mainly composed of nitrides (e.g., silicon nitride). Each insulating layer 7i and each sacrificial layer 5i may be deposited with approximately the same film thickness.

[0056] A joint layer JLi is deposited on the +Z side of the laminate SST1i. The joint layer JLi may be formed from a material mainly composed of oxides (e.g., silicon oxide). The joint layer JLi is formed to a thickness greater than the thickness of the insulating layer 7i and greater than the thickness of the sacrificial layer 5i.

[0057] In the process shown in Figure 6B, a resist pattern with openings for the formation of memory holes 10 is formed on the joint layer JLi. Anisotropic etching, such as RIE (Reactive Ion Etching), is performed using the resist pattern as a mask to form memory holes 10 that penetrate the joint layer JLj and the laminate SST1j and reach the conductive layer 3.

[0058] In the process shown in Figure 6C, a resist pattern with openings for the formation of joint holes 11 is formed on the joint layer JLj. The openings in the resist pattern are formed so that they include the memory holes 10i when viewed from the Z direction. Anisotropic etching, such as the RIE method, is performed using the resist pattern as a mask to form the joint holes 11 in the joint layer JL. The joint holes 11 are formed with a diameter larger than the memory holes 10i and a depth shallower than the thickness of the joint layer JL. The depth of the joint holes 11 can be adjusted by the etching time of the anisotropic etching.

[0059] In the process shown in Figure 6D, a sacrificial film 14 is embedded in the memory hole 10i and the joint hole 11. The sacrificial film 14 may be formed from a material (for example, a carbon-containing material) that can ensure an etching selectivity ratio with respect to the insulating layer 7 and the sacrificial layer 5. The sacrificial film 14 includes a columnar portion 12 embedded in the memory hole 10i and a disc-shaped portion 13 embedded in the joint hole 11.

[0060] In the process shown in Figure 6E, an insulating layer 7i and a sacrificial layer 5i are alternately deposited multiple times on the +Z side of the joint layer JL and the sacrificial film 14 to form a laminate SST2i. The insulating layer 7i may be formed from a material mainly composed of oxides (e.g., silicon oxide). The sacrificial layer 5i may be formed from a material mainly composed of nitrides (e.g., silicon nitride). Each insulating layer 7i and each sacrificial layer 5i may be deposited with a film thickness approximately the same as that of each insulating layer 7i and each sacrificial layer 5i in the laminate SST1i (see Figure 6A).

[0061] In the process shown in Figure 6F, a resist pattern with openings for the formation of memory holes 15 is formed on the laminate SST2i. Anisotropic etching such as RIE is performed using the resist pattern as a mask to form memory holes 15 that penetrate the laminate SST2j and expose the +Z side of the sacrificial film 14.

[0062] In the process shown in Figure 6G, the sacrificial film 14 is removed. This forms memory holes 16 that penetrate the laminate SST2j, the joint layer JL, and the laminate SST1k and reach the conductive layer 3 (see Figure 4). The memory holes 16 include, in order, memory hole 10j, joint hole 11, and memory hole 15 on the +Z side of the conductive layer 3.

[0063] In the process shown in Figure 6H, an insulating film BLK1, a charge storage film CT, and an insulating film TNL are deposited sequentially on the side and bottom surfaces of the memory hole 16. The insulating film BLK1 may be formed from a material mainly composed of oxides (e.g., silicon oxide, metal oxide, or a stack thereof). The charge storage film CT may be formed from a material mainly composed of nitrides (e.g., silicon nitride). The insulating film TNL may be formed from a material mainly composed of oxides (e.g., silicon oxide or silicon oxynitride). After the portions of the insulating film BLK1, charge storage film CT, and insulating film TNL on the bottom surface of the memory hole 16 are selectively removed, a semiconductor film CH is deposited on the side and bottom surfaces of the memory hole 16. The semiconductor film CH may be formed from a material mainly composed of a substantially impurity-free semiconductor (e.g., polysilicon). Then, a core member CR is embedded in the memory hole 16. The core member CR may be formed from a material mainly composed of an insulator (e.g., a semiconductor oxide such as silicon oxide). This forms a columnar body 4 that penetrates the laminate SST1k, the joint layer JL, and the laminate SST2j in the Z direction. The columnar body 4 includes, in order, a tier 4a that penetrates the laminate SST1k in the Z direction, a joint portion 4b that almost penetrates the joint layer JL in the Z direction, and a tier 4c that penetrates the laminate SST2j in the Z direction, on the +Z side of the conductive layer 3.

[0064] In the process shown in Figure 6I, the sacrificial layer 5 of laminate SST1k and the sacrificial layer 5 of laminate SST2j are removed, respectively. An insulating film BLK2 is deposited on the exposed surface of the void formed by the removal. The insulating film BLK2 can be formed from a material mainly composed of an insulator (e.g., metal oxides such as aluminum oxide, zirconium oxide, or hafnium oxide). Then, a conductive layer 6 is embedded in the void. The conductive layer 6 can be formed from a material mainly composed of a conductor (e.g., a metal such as tungsten). As a result, laminate SST1 is formed in which conductive layers 6 and insulating layers 7 are repeatedly stacked alternately, and laminate SST2 is formed in which conductive layers 6 and insulating layers 7 are repeatedly stacked alternately.

[0065] Next, I will explain the configuration of the Mark 310.

[0066] Figure 7 is a cross-sectional view showing the configuration of the mark 310 according to the first embodiment. Figure 7 shows the configuration of the tier 4a, the joint portion 4b, and the area around the mark 310. Note that in Figure 7, films such as the charge storage film CT are omitted.

[0067] Mark 310 is an alignment mark. Mark 310 is provided on the upper surface of the interlayer insulating film 320. The interlayer insulating film 320 is provided on the substrate SUB. Mark 310 is positioned in a different location from the stacked structure SST in the XY direction. Mark 310 is provided, for example, in the kerf portion between adjacent chips on which the semiconductor device 1 is provided. Mark 310 is provided, for example, on the wafer between the dicing line and the memory cell array 2.

[0068] Mark 310 has a broad line shape when viewed from the Z direction, for example. The length of Mark 310 when viewed from the Z direction is, for example, 5 μm, and its width is, for example, 1 μm. The width of Mark 310 is, for example, about 10 times the width of the memory hole 10. Multiple marks may be arranged adjacent to each other when viewed from the Z direction.

[0069] Mark 310 has a recess 311, a sacrificial film 14, and an upper layer member 312.

[0070] The recess 311 extends, for example, from the upper surface of the joint portion 4b in the -Z direction. In the example shown in Figure 7, the recess 311 extends into the interior of the laminate SST1, with the laminate SST1 located below the mark 310. Also, the position of the joint portion 4b from the substrate SUB (position of the joint portion 4b in the Z direction) is the same as the position of the mark 310 from the substrate SUB (position of the mark 310 in the Z direction). As will be explained later, the recess 311 is formed simultaneously with the memory hole 10 of tier 4a.

[0071] The sacrificial film 14 is provided on the inner surface and bottom surface of the recess 311. The sacrificial film 14 is hydrophobic. As will be explained later, the upper surface of the sacrificial film 14 is hydrophilic.

[0072] The sacrificial film 14 contains carbon, such as diamond carbon or amorphous carbon. Furthermore, the sacrificial film 14 is not limited to carbon and may also contain polycrystalline silicon, amorphous silicon, silicon carbide, or silicon nitride.

[0073] The upper layer member 312 is provided on the joint layer JL, and a portion of it is provided to embed the recess 311. Figure 7 shows a portion of the upper layer member 312 embedded in the recess 311. In the example shown in Figure 7, the portion of the upper layer member 312 embedded in the recess 311 is part of the laminate SST2. Near the mark 310, a portion of the sacrificial layer 5 of the laminate SST2j may remain without being replaced as the conductive layer 6 of the laminate SST2. A step is created in the upper layer member 312 above the recess 311 due to the recess 311.

[0074] Next, the details of the process for forming mark 310, as shown in Figures 6B to 6D, will be explained.

[0075] Figures 8A to 8E are cross-sectional views showing a method for manufacturing a semiconductor device 1 according to the first embodiment. Figure 8A corresponds to the process shown in Figure 6B. Figure 8B corresponds to the process shown in Figure 6C. Figures 8C to 8E correspond to the process shown in Figure 6D.

[0076] After the laminate SST1i and the interlayer insulating film 320 surrounding the laminate SST1i are formed (see Figure 6A), the memory holes 10 and recesses 311 are formed as shown in Figure 8A. That is, the memory holes 10 and recesses 311 are formed simultaneously (in parallel). The recesses 311 are formed at the location of the marks 310.

[0077] Next, as shown in Figure 8B, a joint hole 11 is formed in the joint layer JL.

[0078] Next, as shown in Figure 8C, the sacrificial film 14 is embedded in the memory holes 10i and joint holes 11, and the sacrificial film 14 is formed on the upper surface of the interlayer insulating film 320, and on the inner and bottom surfaces of the recesses 311. Many -CH groups and -CH3 groups are present on the surface of the sacrificial film 14. Since the -CH groups and -CH3 groups are hydrophobic, the sacrificial film 14 is hydrophobic.

[0079] Next, as shown in Figure 8D, the upper surface of the sacrificial film 14 is hydrophilized. The hydrophilization of the sacrificial film 14 is preferably performed in an apparatus used to polish the sacrificial film 14 in a later step. Hydrophilization can be achieved, for example, by chemical oxidation, plasma exposure (oxygen plasma), ion beam irradiation, or heat treatment in an oxygen atmosphere.

[0080] Chemical oxidation is a wet treatment using, for example, O3, H2O2, or HNO3.

[0081] In plasma exposure, oxygen gas is flowed through electrodes, and high frequency and high voltage are applied. The oxygen gas is converted into plasma, generating oxygen radicals. These oxygen radicals irradiate the surface of the hydrophobic sacrificial film 14. If the sacrificial film 14 is silicon carbide, amorphous carbon, or diamond carbon, hydrophobic CH bonds and C-CH3 bonds are broken on its surface, and hydrophilic groups such as -C-OH and -C=O are generated. These are highly polar hydrophilic groups, improving the hydrophilicity of the surface of the sacrificial film 14. If the sacrificial film 14 is silicon nitride, amorphous silicon, or polycrystalline silicon, Si-O bonds are formed on its surface, improving its hydrophilicity.

[0082] In the ion beam irradiation method, electrons collide with oxygen gas to generate oxygen ions. These oxygen ions are irradiated when the sacrificial film 14 is amorphous silicon or polycrystalline silicon, etc. The oxygen ions penetrate into the silicon (Si) solid, and only the surface of the sacrificial film 14 becomes silicon oxide (SiO2), thereby hydrophilizing the sacrificial film 14.

[0083] In the example shown in Figure 8D, hydrophilization results in the presence of -COH groups and -COOH groups on the surface of the sacrificial film 14. Since -COH groups and -COOH groups are hydrophilic, the upper surface of the sacrificial film 14 (the inner surface of the recess 311) is hydrophilic.

[0084] Next, as shown in Figure 8E, the sacrificial film 14 is polished until the upper surface of the joint layer JL (interlayer insulating film 320) is exposed. The sacrificial film 14 is polished, for example, by CMP (Chemical Mechanical Polishing).

[0085] The upper surface of the sacrificial film 14 (the inner surface of the recess 311) is hydrophilic, and for example, the contact angle between the sacrificial film 14 and water is less than 15°. Generally, hydrophobic dust adheres easily to hydrophobic surfaces and less easily to hydrophilic surfaces. Therefore, hydrophobic dust does not easily adhere to the surface of the recess 311 having a hydrophilic sacrificial film 14. In addition, the liquid used during polishing by CMP (for example, containing water as the main component) flows efficiently into the recess 311, making it easier to remove any residue of the sacrificial film 14 that adheres to the sacrificial film 14 after polishing. As a result, the residue of the sacrificial film 14 after polishing is less likely to solidify in the recess 311 as dust D (see Figure 9).

[0086] Subsequently, the steps shown in Figure 6E and subsequent figures are performed. As shown in Figure 7, the sacrificial film 14 remains inside the recess 311.

[0087] As described above, according to the first embodiment, a hydrophobic sacrificial film 14 is formed on the upper surface of the interlayer insulating film 320 and on at least the inner surface of the recess 311. Furthermore, the upper surface of the sacrificial film 14 is made hydrophilic. In addition, the sacrificial film 14 is polished until the upper surface of the interlayer insulating film 320 is exposed. This prevents dust D from adhering to and clogging the recess 311. As a result, a decrease in the overlapping accuracy can be suppressed.

[0088] (Comparative example) Figure 9 is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to a comparative example. The comparative example differs from the first embodiment in that hydrophilization is not performed. Figure 9 corresponds to the diagram.

[0089] After the sacrificial layer 14 is formed (see Figure 8C), the sacrificial layer 14 is polished until the joint layer JL is exposed, as shown in Figure 9. The polishing of the sacrificial layer 14 is performed, for example, by CMP.

[0090] The sacrificial film 14, which is the residue after polishing, is hydrophobic. The surface of the sacrificial film 14 inside the recess 311 is also hydrophobic. Because hydrophobic films tend to adsorb to each other in water, the residue tends to adhere to the sacrificial film 14 inside the recess 311, and water does not flow easily over the surface of the recess 311. Therefore, dust D may easily adhere to the inside of the recess 311. Adhered dust D is difficult to remove by cleaning after polishing. The visibility of the mark 310 clogged with dust D deteriorates. For example, if dust D adheres to the inner surface (side wall) of the recess 311, the step on the inner surface of the recess 311 becomes lower, making it difficult to recognize the step. As a result, the overlapping accuracy decreases.

[0091] In contrast, in the first embodiment, the hydrophobic sacrificial film 14 is made hydrophilic before polishing. This prevents dust D from adhering to and clogging the recess 311. As a result, a decrease in the overlapping accuracy can be suppressed.

[0092] (Second embodiment) Figure 10 is a cross-sectional view showing the configuration of the mark 310 according to the second embodiment. The second embodiment differs from the first embodiment in that a hydrophobic film 313 is provided instead of hydrophobic treatment of the sacrificial film 14.

[0093] Mark 310 further has a film 313. The film 313 is provided on the sacrificial film 14. The film 313 is hydrophobic. As a result, the recess 311 has hydrophilicity on its inner surface. The film 313 contains, for example, SiO2.

[0094] Figures 11A to 11C are cross-sectional views showing a method for manufacturing the semiconductor device 1 according to the second embodiment.

[0095] After forming the sacrificial film 14 (see Figure 8C), a film 313 is formed on the sacrificial film 14, as shown in Figure 11A. The film 313 can be formed from a material mainly composed of oxides (e.g., silicon oxide). The film 313 is formed, for example, by CVD (Chemical Vapor Deposition).

[0096] Next, as shown in Figure 11B, the sacrificial film 14 and film 313 are polished until the joint layer JL (interlayer insulating film 320) is exposed. The polishing of the sacrificial film 14 and film 313 is performed, for example, by CMP. Since the hydrophilic film 313 is formed on the inner surface and bottom surface of the recess 311, the residue of the sacrificial film 14 after polishing is less likely to adhere to the recess 311 as dust D. Furthermore, because film 313 is hydrophilic, the residue of film 313 is less likely to form large dust particles D.

[0097] Next, as shown in Figure 11C, a portion of the upper surface of the film 313, specifically the surface portion 313a, is removed. The removal of the surface portion 313a is performed, for example, as part of cleaning the equipment after CMP. If the film 313 contains silicon oxide, the removal of the surface portion 313a is performed, for example, using DHF (Dilute Hydrogen Fluoride). If dust D is adhering to the recess 311, the dust D is removed along with the surface portion 313a. This further suppresses the adhesion of dust D to the recess 311. Note that the steps shown in Figure 11C may be omitted.

[0098] As in the second embodiment, a hydrophobic film 313 may be provided. The semiconductor device 1 according to the second embodiment can obtain the same effects as in the first embodiment.

[0099] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0100] 1 Semiconductor device, 4 Columnar body, 4b Joint portion, 5i Sacrificial layer, 6 Conductive layer, 7 Insulating layer, 7i Insulating layer, 14 Sacrificial film, 313 Film, 313a Surface portion, CH Semiconductor film, CT Charge storage film, DMT1, DMT2 Dummy memory cell, MT, MT0~MT9 Memory cell, SST, SST1, SST1i, SST1j, SST1k, SST2, SST2i, SST2j Stacked body, SUB Substrate.

Claims

1. An insulating film is formed on the substrate, A recess is formed on the upper surface of the insulating film, A hydrophobic first film is formed on the upper surface of the insulating film and on the inner surface of the recess. The upper surface of the first film is made hydrophilic, The first film is polished until the upper surface of the insulating film is exposed. A method for manufacturing a semiconductor device, comprising the following:

2. The method for manufacturing a semiconductor device according to claim 1, wherein hydrophilizing the upper surface of the first film includes chemical oxidation treatment, plasma exposure, ion beam irradiation, or heat treatment in an oxygen atmosphere.

3. The method for manufacturing a semiconductor device according to claim 1, wherein making the upper surface of the first film hydrophilic includes forming a hydrophilic second film on the first film.

4. The second film is made of SiO ２ A method for manufacturing a semiconductor device according to claim 3, including the method described in claim 3.

5. The method for manufacturing a semiconductor device according to claim 3, further comprising polishing the first film and then removing a portion of the upper surface of the second film.

6. Before forming the insulating film, a laminate is formed on the substrate in which insulating layers and sacrificial layers are alternately stacked. Forming the recess includes forming a plurality of holes that penetrate the laminate parallel to the recess, The method for manufacturing a semiconductor device according to claim 1, wherein forming the first film further includes embedding the first film inside a plurality of holes.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the first film comprises diamond carbon, amorphous carbon, polycrystalline silicon, amorphous silicon, silicon carbide, or silicon nitride.

8. circuit board and An insulating film provided on the substrate, A mark provided on the upper surface of the insulating film, Equipped with, The aforementioned mark is, A recess provided on the upper surface of the insulating film, A first film having hydrophobic properties is provided on the inner surface of the recess, A semiconductor device having

9. The semiconductor device according to claim 8, wherein the upper surface of the first film is hydrophilic.

10. The semiconductor device according to claim 8, wherein the mark further comprises a second film provided on the first film and having hydrophilic properties.

11. The second film is made of SiO ２ The semiconductor device according to claim 10, including the above.

12. A laminate provided on the aforementioned substrate, wherein insulating layers and conductive layers are alternately stacked, Multiple columnar bodies penetrating the aforementioned laminate, The semiconductor device according to claim 8, further comprising:

13. The columnar body is The first columnar part, The second columnar part, A joint portion provided between the first columnar portion and the second columnar portion, It has, The semiconductor device according to claim 12, wherein the position of the joint portion relative to the substrate is the same as the position of the mark relative to the substrate.

14. The semiconductor device according to claim 8, wherein the first film comprises diamond carbon, amorphous carbon, polycrystalline silicon, amorphous silicon, silicon carbide, or silicon nitride.

Images