Manufacturing method for semiconductor devices

Abstract

The present invention provides a method for manufacturing a semiconductor device that can suitably form holes within a predetermined film. [Solution] According to one embodiment, a method for manufacturing a semiconductor device includes forming a laminated film that alternately includes a plurality of first insulating films and a plurality of first layers in a first direction, forming first and second portions within the laminated film, forming first and second holes within the second portions, and forming a second layer within the first and second holes. The method further includes etching the laminated film and the second layer such that a third hole is formed within the first portion and a fourth hole is formed within the second layer of the second hole, and removing the second layer after the third and fourth holes have been formed. The method further includes forming a support portion including a second insulating film within the first and second holes, forming a columnar portion including a charge storage layer and a semiconductor layer within the third hole, and then replacing the plurality of first layers with a plurality of electrode layers.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device.

Background Art

[0002] When forming a plurality of holes in a predetermined film of a three-dimensional semiconductor memory, some holes may not be formed appropriately. For example, when cryo-etching is performed to form holes for support portions (beam portions) in the stepped portions of a stacked film and holes for columnar portions (memory holes) in the non-stepped portions of the stacked film, the holes for columnar portions may not be formed appropriately near the boundary between the stepped portions and the non-stepped portions.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a method for manufacturing a semiconductor device capable of preferably forming holes in a predetermined film.

Means for Solving the Problems

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes forming a laminated film that alternately includes a plurality of first insulating films and a plurality of first layers in a first direction, forming a first portion and a second portion within the laminated film, forming a first hole and a second hole within the second portion, and forming a second layer within the first hole and the second hole. The method further includes etching the laminated film and the second layer so that a third hole is formed within the first portion and a fourth hole is formed within the second layer of the second hole, and removing the second layer after the third hole and the fourth hole have been formed. The method further includes forming a support portion including a second insulating film within the first hole and the second hole, forming a columnar portion including a charge storage layer and a semiconductor layer within the third hole, and replacing the plurality of first layers with a plurality of electrode layers after the support portion and the columnar portion have been formed. [Brief explanation of the drawing]

[0006] [Figure 1] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 2] This is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 3] This is a plan view showing the structure of the first embodiment of the semiconductor device. [Figure 4] These are a plan view and a cross-sectional view (1 / 10 scale) showing the manufacturing method of the semiconductor device according to the first embodiment. [Figure 5] These are a plan view and a cross-sectional view (2 / 10) showing the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] These are a plan view and a cross-sectional view (3 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] These are a plan view and a cross-sectional view (4 / 10) showing a method for manufacturing the semiconductor device of the first embodiment. [Figure 8] This is a plan view and a cross-sectional view (5 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] These are a plan view and a cross-sectional view (6 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] It is a plan view and a cross-sectional view (7 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] It is a plan view and a cross-sectional view (8 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] It is a plan view and a cross-sectional view (9 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] It is a plan view and a cross-sectional view (10 / 10) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] It is a cross-sectional view showing a method for manufacturing a semiconductor device of the first comparative example of the first embodiment. [Figure 15] It is a cross-sectional view showing a method for manufacturing a semiconductor device of the second comparative example of the first embodiment. [Figure 16] It is a cross-sectional view showing a method for manufacturing a semiconductor device of the third comparative example of the first embodiment. [Figure 17] It is a cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 18] It is a plan view showing the structure of a semiconductor device according to the second embodiment. [Figure 19] It is a plan view (1 / 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 20] It is a plan view (2 / 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 21] It is a plan view (3 / 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 22] It is a plan view (4 / 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 23] It is a plan view (5 / 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 24] It is a plan view (6 / 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 25] It is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. [Figure 26] It is an enlarged cross-sectional view showing the structure of a semiconductor device according to the third embodiment. [Figure 27]It is a cross-sectional view (1 / 2) showing a method of manufacturing a semiconductor device according to the third embodiment. [Figure 28] It is a cross-sectional view (2 / 2) showing a method of manufacturing a semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 28, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment. FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 3 is a plan view showing the structure of the semiconductor device according to the first embodiment.

[0009] The semiconductor device of the present embodiment is, for example, a three-dimensional semiconductor memory. Hereinafter, the structure of the semiconductor device of the present embodiment will be mainly described with reference to FIG. 1. In this description, FIGS. 2 and 3 will also be referred to as appropriate.

[0010] The semiconductor device of the present embodiment includes a substrate 1, a stacked film 2, an interlayer insulating film 3, a plurality of columnar portions 4, and a plurality of support portions (beam portions) 5. The stacked film 2 includes a plurality of insulating films 2a and a plurality of electrode layers 2b. Each columnar portion 4 includes a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e (FIG. 2). Each support portion 5 includes an insulating film 5a. Each insulating film 2a in the stacked film 2 is an example of a first insulating film. The insulating film 5a in each support portion 5 is an example of a second insulating film. The interlayer insulating film 3 is an example of a third insulating film. The channel semiconductor layer 4d is an example of a semiconductor layer. The stacked film 2 is an example of a first film.

[0011] Substrate 1 is a semiconductor substrate, such as a Si (silicon) substrate. Figure 1 shows the X and Y directions, which are parallel to and perpendicular to the surface of substrate 1, and the Z direction, which is perpendicular to the surface of substrate 1. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity. The Z direction is an example of the first direction. The X direction is an example of the second direction.

[0012] The laminated film 2 is formed on the substrate 1 and alternately includes a plurality of insulating films 2a and a plurality of electrode layers 2b in the Z direction. Each insulating film 2a is, for example, an SiO2 film (silicon oxide film). Each electrode layer 2b includes, for example, a metal layer such as a W (tungsten) layer. In this embodiment, each electrode layer 2b functions as a word line or selection line in a three-dimensional semiconductor memory. The laminated film 2 may be formed directly on the substrate 1 or on the substrate 1 via another film.

[0013] The laminated film 2 includes a non-stepped (flat) portion R1 and a stepped portion R2. The non-stepped portion R1 has a top surface with a non-stepped shape (flat shape). The stepped portion R2 has a top surface and side surfaces with a stepped shape. In Figure 1, the stepped portion R2 is formed in the X direction of the non-stepped portion R1. The non-stepped portion R1 is an example of the first part. The stepped portion R2 is an example of the second part.

[0014] The interlayer insulating film 3 is formed on the stepped portion R2 so as to eliminate the step difference between the upper surface of the non-stepped portion R1 and the upper surface of the stepped portion R2. The interlayer insulating film 3 is, for example, a TEOS (tetraethyl orthosilicate) film or an SiO2 film.

[0015] Figure 1 shows a plurality of memory holes MH formed within the non-staired section R1. These memory holes MH are arranged in a triangular grid shape in plan view (Figure 3), but may be arranged in other grid shapes. Figure 3 shows an XY cross-section of one of the insulating films 2a within the laminated film 2. Each memory hole MH in this embodiment has a circular shape with a diameter D1 in plan view. As shown in Figure 1, each memory hole MH in this embodiment extends in the Z direction and penetrates the laminated film 2 in the Z direction to reach the substrate 1. Each memory hole MH is an example of a third hole. Diameter D1 is an example of a second diameter.

[0016] Each columnar portion 4 is formed within a corresponding memory hole MH. Therefore, in plan view, each columnar portion 4 of this embodiment has a circular shape with a diameter D1. Furthermore, each columnar portion 4 of this embodiment has a columnar shape extending in the Z direction, penetrating the laminated film 2 in the Z direction to reach the substrate 1.

[0017] Each columnar portion 4, as shown in Figure 2, includes a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e, which are sequentially formed on the side surface of the laminated film 2. The block insulating film 4a is, for example, an SiO2 film. The charge storage layer 4b is, for example, a SiN film (silicon nitride film). The charge storage layer 4b in this embodiment is capable of storing signal charges in a three-dimensional semiconductor memory. The tunnel insulating film 4c is, for example, an SiO2 film. The channel semiconductor layer 4d is, for example, a polysilicon layer. The channel semiconductor layer 4d in this embodiment functions as a channel for multiple cell transistors (memory cells) and multiple selection transistors in a three-dimensional semiconductor memory. The core insulating film 4e is, for example, an SiO2 film.

[0018] Figure 1 shows a plurality of holes HR formed within the stepped section R2 (or within the interlayer insulating film 3 and the stepped section R2). These holes HR are arranged in a triangular grid shape in plan view (Figure 3), but may be arranged in other grid shapes. Each hole HR in this embodiment has a circular shape with a diameter D2 in plan view. In this embodiment, diameter D2 is larger than diameter D1. As shown in Figure 1, each hole HR in this embodiment extends in the Z direction and penetrates the laminated film 2 (or the interlayer insulating film 3 and the laminated film 2) in the Z direction to reach the substrate 1. Each hole HR is an example of a first and second hole. Diameter D2 is an example of a first diameter.

[0019] Each support column 5 is formed within a corresponding hole HR. Therefore, each support column 5 in this embodiment has a circular shape with a diameter D2 in plan view. Furthermore, each support column 5 in this embodiment has a columnar shape that extends in the Z direction, similar to each columnar portion 4, and penetrates the laminated film 2 (or the interlayer insulating film 3 and the laminated film 2) in the Z direction to reach the substrate 1.

[0020] Each support column 5 includes an insulating film 5a, as shown in Figure 1. The insulating film 5a is, for example, an SiO2 film. In this embodiment, each support column (beam) 5 functions as a support column (beam) that suppresses the collapse of the laminated film 2 during replacement processes, etc.

[0021] Figures 4 to 13 are plan views and cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. Figures 4(a), 5(a), ..., and 13(a) are plan views corresponding to Figure 3. Figures 4(b), 5(b), ..., and 13(b) are cross-sectional views corresponding to Figure 1.

[0022] First, multiple insulating films 2a and multiple sacrificial layers 2c are alternately formed on the substrate 1 to form a laminated film 2 on the substrate 1 (Figures 4(a) and 4(b)). As a result, the laminated film 2 is formed to alternately contain multiple insulating films 2a and multiple sacrificial layers 2c in the Z direction. Each sacrificial layer 2c is, for example, a SiN film. Each sacrificial layer 2c is an example of the first layer.

[0023] Next, recesses H1 are formed within the laminated film 2 by lithography and RIE (Reactive Ion Etching) (Figures 5(a) and 5(b)). As a result, non-stepped sections R1 and stepped sections R2 are formed within the laminated film 2. In Figures 4(a) and 4(b) above, for the sake of clarity, the area where the non-stepped section R1 should be formed is indicated by the symbol R1, and the area where the stepped section R2 should be formed is indicated by the symbol R2.

[0024] Next, an interlayer insulating film 3 is formed on the stepped section R2 (Figures 6(a) and 6(b)). As a result, the recessed section H1 is filled with the interlayer insulating film 3.

[0025] Next, a mask layer 11 is formed on the laminated film 2, and multiple holes HR are formed in the mask layer 11 and within the stepped portion R2 (or within the mask layer 11, the interlayer insulating film 3, and the stepped portion R2) by lithography and RIE (Figures 7(a) and 7(b)). In this embodiment, each hole HR is formed to have a circular shape with a diameter D2 (see Figure 1) in plan view. In addition, each hole HR in this embodiment is formed to extend in the Z direction and reach the substrate 1. The mask layer 11 is, for example, an APF (Advanced Patterning Film).

[0026] Next, a sacrificial layer 12 is formed over the entire surface of the substrate 1 (Figures 8(a) and 8(b)). As a result, a sacrificial layer 12 is formed in each hole HR. The sacrificial layer 12 is, for example, a metal layer such as a W (tungsten) layer. The sacrificial layer 12 may be a metal layer other than the W layer, or a non-metallic layer such as a C (carbon) layer. It is desirable that the sacrificial layer 12 be formed from a material that is difficult to process by cryo-etching but easy to remove. The sacrificial layer 12 is an example of a second layer.

[0027] Next, multiple memory holes MH are formed in the mask layer 11 and the non-staircase portion R1 by lithography and dry etching (Figures 9(a) and 9(b)). Each memory hole MH in this embodiment is formed to have a circular shape with a diameter D1 (see Figure 1) in plan view. Furthermore, each memory hole MH in this embodiment is formed to extend in the Z direction and reach the substrate 1.

[0028] The dry etching performed in the process shown in Figures 9(a) and 9(b) is, for example, cryo-etching. In this cryo-etching, the mask layer 11 and the laminated film 2 are processed by etching at a low temperature using a predetermined gas. Note that the process shown in Figures 9(a) and 9(b) may also be performed by etching other than cryo-etching (for example, RIE).

[0029] The dry etching process shown in Figures 9(a) and 9(b) is carried out such that multiple memory holes MH are formed within the mask layer 11 and the non-staired portion R1, and one or more dummy memory holes MH' are formed within the sacrificial layer 12 of one or more holes HR. Each dummy memory hole MH' in this embodiment is formed to have a circular shape with a diameter D1 in plan view, similar to each memory hole MH. On the other hand, each dummy memory hole MH' in this embodiment is formed to extend in the Z direction, but not to reach the substrate 1. Therefore, each dummy memory hole MH' shown in Figure 9(b) does not penetrate the sacrificial layer 12 in the Z direction. This can be achieved, for example, by increasing the etching selectivity ratio between the laminated film 2 and the sacrificial layer 12. Because each dummy memory hole MH' does not penetrate the sacrificial layer 12, it is possible to suppress the etching of each dummy memory hole MH' from damaging the substrate 1. Each dummy memory hole MH' is an example of a fourth hole.

[0030] As shown in Figures 9(a) and 9(b), each dummy memory hole MH' in this embodiment does not penetrate the sacrificial layer 12 formed on the bottom surface of the hole HR, nor does it penetrate the sacrificial layer 12 formed on the side surface of the hole HR. This makes it possible to suppress the etching of each dummy memory hole MH' from damaging the laminated film 2.

[0031] Figures 9(a) and 9(b) show multiple holes HR within the staircase section R2. In this embodiment, one or more dummy memory holes MH' are formed within some of the holes HR in the staircase section R2. Specifically, dummy memory holes MH' are formed in holes HR close to the boundary between the non-staircase section R1 and the staircase section R2, but not in holes HR far from the boundary between the non-staircase section R1 and the staircase section R2. The distance between the former holes HR and the non-staircase section R1 is smaller than the distance between the latter holes HR and the non-staircase section R1. The former holes HR are an example of a second hole, and the latter holes HR are an example of a first hole. The distance between each hole HR and the non-staircase section R1 can be determined in any way; for example, it may be the distance between each hole HR and the boundary, or it may be the distance between each hole HR and the centroid of the non-staircase section R1.

[0032] When multiple memory holes MH are formed within a non-staired section R1, the memory holes MH may not be properly formed near the boundary between the non-staired section R1 and the staired section R2. For example, the memory holes MH near this boundary may not penetrate the laminated film 2. The reason this phenomenon occurs near the boundary is thought to be that the region where memory holes MH are formed (non-staired section R1) and the region where memory holes MH are not formed (staired section R2) are swapped near the boundary. This phenomenon occurs, for example, when memory holes MH are formed by cryo-etching.

[0033] Therefore, the dry etching process shown in Figures 9(a) and 9(b) is performed such that multiple memory holes MH are formed within the non-staired section R1, and one or more dummy memory holes MH' are formed near the boundary. As a result, the above phenomenon occurs not near the boundary between the region where memory holes MH are formed (non-staired section R1) and the region where memory holes MH are not formed (staired section R2), but near the boundary between the region where memory holes MH or dummy memory holes MH' are formed and the region where memory holes MH and dummy memory holes MH' are not formed. This makes it possible to replace improperly formed holes from memory holes MH to dummy memory holes MH', and also makes it possible to properly form memory holes MH near the boundary between the non-staired section R1 and the staired section R2.

[0034] It is also conceivable to provide a portion (hereinafter referred to as the "dummy portion") between the non-staired portion R1 and the staired portion R2 for forming a dummy memory hole MH'. However, providing a dummy portion between the non-staired portion R1 and the staired portion R2 would necessitate either reducing the area of ​​the non-staired portion R1 or the staired portion R2 in a plan view, or increasing the area of ​​the semiconductor device (semiconductor chip) of this embodiment in a plan view. On the other hand, according to this embodiment, by forming a dummy memory hole MH' within the staired portion R2 and then removing the dummy memory hole MH', it is possible to suppress the area problem described above.

[0035] Next, the mask layer 11 and the sacrificial layer 12 are removed (Figures 10(a) and 10(b)). The mask layer 11 and the sacrificial layer 12 may be removed simultaneously or sequentially.

[0036] Next, an insulating film 5a is formed inside each hole HR (Figures 11(a) and 11(b)). As a result, a support column 5 is formed inside each hole HR.

[0037] Next, a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e are formed in order within each memory hole MH (Figures 11(a) and 11(b)). As a result, columnar portions 4 are formed within each memory hole MH. Note that the columnar portions 4 may be formed before the support portions 5 are formed.

[0038] Next, a slit (not shown) is formed within the laminated film 2, and the multiple sacrificial films 2c are removed by wet etching from the slit (Figures 12(a) and 12(b)). As a result, multiple cavities H2 are formed within the laminated film 2.

[0039] Next, multiple electrode layers 2b are formed within the multiple cavities H2 (Figures 13(a) and 13(b)). In this way, a replacement process is performed in which multiple sacrificial films 2c are replaced with multiple electrode layers 2b. Through this replacement process, the laminated film 2 is processed to alternately contain multiple insulating films 2a and multiple electrode layers 2b in the Z direction. After that, various processes are carried out to manufacture the semiconductor device shown in Figures 1 to 3.

[0040] Figure 14 is a cross-sectional view showing a method for manufacturing a semiconductor device of the first comparative example of the first embodiment.

[0041] First, a laminated film 2 is formed on the substrate 1, and non-stair sections R1 and stair sections R2 are formed within the laminated film 2, and an interlayer insulating film 3 is formed on the stair section R2 (Figure 14(a)). Next, lithography and cryo-etching are performed to form multiple holes HR within the stair section R2 (or within the interlayer insulating film 3 and stair section R2), and multiple memory holes MH are formed within the non-stair section R1 (Figure 14(b)).

[0042] In this comparative example, multiple holes HR and multiple memory holes MH are formed simultaneously by cryo-etching. When the insulating film 2a, sacrificial layer 2c, and interlayer insulating film 3 are SiO2 film, SiN film, and TEOS film, respectively, cryo-etching generally allows for high-speed etching of the laminated film 2, but not of the interlayer insulating film 3. Therefore, it is difficult to simultaneously form multiple holes HR and multiple memory holes MH by cryo-etching.

[0043] Figure 15 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second comparative example of the first embodiment.

[0044] First, a multilayer film 2 is formed on the substrate 1 (Figure 15(a)). Next, lithography and cryo-etching are performed to form multiple holes HR and multiple memory holes MH within the multilayer film 2 (Figure 15(a)). Each hole HR is formed within the region where the stepped portion R2 is to be formed, and each memory hole MH is formed within the region where the non-stepped portion R1 is to be formed.

[0045] Next, support columns 5 are formed in each hole HR, and columnar sections 4 are formed in each memory hole MH (Figure 15(b)). As a result, multiple support columns 5 are formed in the area where the stepped section R2 is to be formed, and multiple columnar sections 4 are formed in the area where the non-stepped section R1 is to be formed. Next, the laminated film 2 and some of the support columns 5 are processed to form the non-stepped section R1 and the stepped section R2, and an interlayer insulating film 3 is formed on the stepped section R2 and some of the support columns 5 (Figure 15(b)).

[0046] In this comparative example, multiple holes HR and multiple memory holes MH are formed simultaneously by cryo-etching before the formation of the non-staired section R1 and the staired section R2. This makes it possible to avoid etching the interlayer insulating film 3, and facilitates the simultaneous formation of multiple holes HR and multiple memory holes MH by cryo-etching. However, the staired section R2 in this comparative example is difficult to process because it is formed by processing not only the laminated film 2 but also the support section 5.

[0047] Figure 16 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third comparative example of the first embodiment.

[0048] First, a laminated film 2 is formed on the substrate 1, and a non-staired section R1 and a staired section R2 are formed within the laminated film 2, and an interlayer insulating film 3 is formed on the staired section R2 (Figure 16(a)). Next, multiple holes HR are formed within the staired section R2 (or within the interlayer insulating film 3 and the staired section R2) by lithography and RIE (Figure 16(a)). Next, multiple memory holes MH are formed within the staired section R2 by lithography and cryo-etching (Figure 16(b)).

[0049] In this comparative example, multiple holes HR are formed by RIE, and then multiple memory holes MH are formed by cryo-etching. This makes it possible to avoid the problems of the first and second comparative examples. However, in this comparative example, as described above, memory holes MH may not be properly formed near the boundary between the non-staired portion R1 and the staired portion R2. This problem in the third comparative example can be avoided by the dummy memory holes MH' of this embodiment, as described above.

[0050] As described above, in this embodiment, when forming multiple memory holes MH by etching, the etching is performed such that multiple memory holes MH are formed within the non-staircase portion R1, and one or more dummy memory holes MH' are formed within the sacrificial layer 12 of one or more holes HR. Therefore, according to this embodiment, it is possible to suitably form memory holes MH within the laminated film 2.

[0051] (Second Embodiment) Figure 17 is a cross-sectional view showing the structure of the semiconductor device of the second embodiment. Figure 18 is a plan view showing the structure of the semiconductor device of the second embodiment.

[0052] The semiconductor device of this embodiment (Figures 17 and 18) includes, in addition to the same components as the semiconductor device of the first embodiment (Figures 1 to 3), a slit ST formed in the laminated film 2 and an insulating film 6 formed in the slit ST. The insulating film 6 includes a plurality of portions 6a and a plurality of portions 6b, as shown in Figure 18. The slit ST is an example of a recess.

[0053] Figures 1 and 2 show the XZ cross-section of the semiconductor device of the first embodiment, while Figure 17 shows the YZ cross-section of the semiconductor device of this embodiment. The structure of the semiconductor device of this embodiment will be described below, mainly with reference to Figure 17. Figure 18 will also be referred to as appropriate in this description.

[0054] Figures 17 and 18 show regions R1a and R1b within the non-staired section R1, and regions R2a and R2b within the staired section R2. The slit ST extends in the X and Z directions, penetrating the laminated film 2 in the Z direction to reach the substrate 1. Specifically, the slit ST is formed continuously within the non-staired section R1 and the staired section R2, between region R1a and region R1b, and between region R2a and region R2b. Regions R1a and R2a form one finger portion within the laminated film 2, and regions R1b and R2b form another finger portion within the laminated film 2.

[0055] The insulating film 6 extends in the X and Z directions within the slit ST, penetrating the laminated film 2 in the Z direction to reach the substrate 1. The insulating film 6 is, for example, an SiO2 film. As shown in Figure 18, the insulating film 6 alternately comprises a plurality of portions 6a and a plurality of portions 6b in the X direction. Each portion 6a has a columnar shape extending in the Z direction, penetrating the laminated film 2 in the Z direction to reach the substrate 1. Similarly, each portion 6b has a columnar shape extending in the Z direction, penetrating the laminated film 2 in the Z direction to reach the substrate 1. The insulating film 6 is formed continuously within the non-staired portion R1 and the stepped portion R2, and is formed between region R1a and region R1b, and between region R2a and region R2b.

[0056] Figures 19 to 24 are plan views showing the manufacturing method of the semiconductor device according to the second embodiment. Figures 19 to 24 are corresponding plan views of Figure 18.

[0057] First, the steps shown in Figures 4(a) to 7(b) are performed. However, in the steps shown in Figures 7(a) and 7(b), a mask layer 11 is formed on the laminated film 2, and multiple holes HR and multiple dummy holes HR' are formed in the mask layer 11 and the laminated film 2 by lithography and RIE (Figure 19). Each dummy hole HR' in this embodiment is formed to have a circular shape with a diameter D2 (see Figure 3) in a plan view, similar to each hole HR. Also, each dummy hole HR' in this embodiment is formed to extend in the Z direction and reach the substrate 1, similar to each hole HR. In Figure 19, multiple dummy holes HR' are formed between regions R1a and R1b, and between regions R2a and R2b, and are spaced apart from each other in the X direction. Each dummy hole HR' is an example of a fifth hole.

[0058] Next, in the process shown in Figures 8(a) and 8(b), a sacrificial layer 12 is formed over the entire surface of the substrate 1 (Figure 20). As a result, a sacrificial layer 12 is formed in each hole HR, and a sacrificial layer 12 is also formed in each dummy hole HR'.

[0059] Next, in the process shown in Figures 9(a) and 9(b), multiple memory holes MH are formed in the mask layer 11 and the laminated film 2 by lithography and dry etching (Figure 21). The dry etching is, as described above, for example, cryo-etching. The dry etching is carried out so that multiple memory holes MH are formed in the non-staircase portion R1, one or more dummy memory holes MH' are formed in the sacrificial layer 12 of one or more holes HR, and one or more dummy memory holes MH' are formed in the sacrificial layer 12 of one or more dummy holes HR'. Hereinafter, the former dummy memory holes MH' will be referred to as "dummy memory hole MH'[HR]", and the latter dummy memory holes MH' will be referred to as "dummy memory hole MH'[HR']". In Figure 21, dummy memory holes MH'[HR] are formed only in some of the holes HR, and dummy memory holes MH'[HR'] are also formed only in some of the dummy holes HR'. Dummy memory holes MH'[HR'] are an example of the sixth hole.

[0060] Each dummy memory hole MH'[HR'] in this embodiment is formed to have a circular shape with a diameter D1 (see Figure 3) in a plan view, similar to each memory hole MH and each dummy memory hole MH'[HR]. Furthermore, each dummy memory hole MH'[HR'] in this embodiment is formed so as not to penetrate the sacrificial layer 12 formed on the bottom and sides of the dummy memory hole HR', similar to each dummy memory hole MH'[HR].

[0061] When multiple memory holes MH are formed within a non-staired section R1, memory holes MH may not be properly formed near the boundary between regions R1a, R2a and regions R1b, R2b. The reason is the same as when memory holes MH are not properly formed near the boundary between the non-staired section R1 and the staired section R2. Therefore, the dry etching described above is performed so that one or more dummy memory holes MH'[HR'] are formed near the boundary between regions R1a, R2a and regions R1b, R2b. This makes it possible to properly form memory holes MH near the boundary between regions R1a, R2a and regions R1b, R2b. These dummy memory holes MH'[HR'] are formed within dummy holes HR' provided within region R1, or within dummy holes HR' provided near region R1 in region R2.

[0062] Next, the mask layer 11 and the sacrificial layer 12 are removed in the process shown in Figures 10(a) and 10(b) (Figure 22).

[0063] Next, in the process shown in Figures 11(a) and 11(b), an insulating film 5a is formed in each hole HR (Figure 23). As a result, a support column 5 is formed in each hole HR. Next, in the process shown in Figures 11(a) and 11(b), a block insulating film 4a, a charge storage layer 4b, a tunnel insulating film 4c, a channel semiconductor layer 4d, and a core insulating film 4e are formed sequentially in each memory hole MH (Figure 23). As a result, a columnar portion 4 is formed in each memory hole MH.

[0064] Next, in the process shown in Figures 12(a) and 12(b), a slit ST is formed in the laminated film 2, and the multiple sacrificial layers 2c are removed by wet etching from the slit ST (Figure 24). When forming the slit ST, multiple holes H are formed between the multiple dummy holes HR' by wet etching from the multiple dummy holes HR'. As a result, the multiple dummy holes HR' are connected to each other by these holes H. In this embodiment, the slit ST is formed to alternately include multiple dummy holes HR' and multiple holes H in the X direction.

[0065] Next, the steps shown in Figures 13(a) and 13(b) are performed. Furthermore, an insulating film 6 is formed in the slit ST. In this way, the semiconductor device shown in Figures 17 and 18 is manufactured. Note that each portion 6a represents the insulating film 6 formed in one dummy hole HR', and each portion 6b represents the insulating film 6 formed in one hole H (see Figure 18).

[0066] The slit ST in this embodiment may be formed to have a shape other than that shown in Figure 24. For example, each hole H in this embodiment may be formed to have a shape other than that shown in Figure 24.

[0067] Furthermore, in this embodiment, multiple slits ST may be formed within the laminated film 2. In this case, the slits ST shown in Figures 17 to 24 correspond to one of these multiple slits ST.

[0068] As described above, in this embodiment, when forming multiple memory holes MH by etching, the etching is performed such that multiple memory holes MH are formed within the non-staircase portion R1, and one or more dummy memory holes MH'[HR'] are formed within the sacrificial layer 12 of one or more dummy holes HR'. Therefore, according to this embodiment, it is possible to suitably form memory holes MH within the laminated film 2.

[0069] Furthermore, when the semiconductor device of the first or second embodiment is manufactured by bonding substrate 1 to another substrate, the finished semiconductor device does not need to have substrate 1. An example of such a semiconductor device will be described in the third embodiment.

[0070] (Third embodiment) Figure 25 is a cross-sectional view showing the structure of a semiconductor device according to the third embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0071] The semiconductor device of this embodiment comprises an array chip 21 and a circuit chip 22 bonded together. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer containing the array chip 21 and a circuit wafer containing the circuit chip 22 together.

[0072] The array chip 21 comprises a memory cell array 31 containing multiple memory cells, an insulating film 32 on the memory cell array 31, and an interlayer insulating film 33 below the memory cell array 31. The insulating film 32 is, for example, an SiO2 film. The interlayer insulating film 33 is, for example, a laminated film containing an SiO2 film and other insulating films. A portion of the memory cell array 31 in this embodiment corresponds to the laminated film 2 of the first or second embodiment.

[0073] The circuit chip 22 is located beneath the array chip 21. The symbol S indicates the bonding surface between the array chip 21 and the circuit chip 22. The circuit chip 22 comprises an interlayer insulating film 34 beneath the interlayer insulating film 33 and a substrate 35 beneath the interlayer insulating film 34. The interlayer insulating film 34 is, for example, a multilayer film including an SiO2 film and other insulating films. The substrate 35 is, for example, a semiconductor substrate such as a Si substrate.

[0074] Figure 25 shows the X and Y directions, which are parallel to and perpendicular to the surface of the substrate 35, and the Z direction, which is perpendicular to the surface of the substrate 35. The X, Y, and Z directions intersect each other. In this embodiment, as in the first and second embodiments, the +Z direction is treated as the upward direction and the -Z direction is treated as the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0075] The array chip 21 includes multiple word lines WL as multiple electrode layers within the memory cell array 31. Figure 25 shows a stepped structure 41 within the memory cell array 31 and multiple support columns (beams) 42 provided within the stepped structure 41. Each word line WL extends in the X direction and is electrically connected to the word wiring layer 44 via a contact plug 43. Each columnar portion CL that penetrates the multiple word lines WL is electrically connected to the bit line BL via a via plug 45 and is also electrically connected to the source line SL. The bit line BL extends in the Y direction and is located below the multiple word lines WL. The source line SL extends in the X direction and is located above the multiple word lines WL. The stepped structure 41, support columns 42, columnar portion CL, and word lines WL in this embodiment correspond to the stepped portion R2, support column 5, columnar portion 4, and electrode layer 2b of the first or second embodiment, respectively.

[0076] The circuit chip 22 comprises a plurality of transistors 51. Each transistor 51 includes a gate insulating film 51a and a gate electrode 51b, which are sequentially provided on the substrate 35, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 35. The circuit chip 22 also comprises a plurality of contact plugs 52 provided on the gate electrode 51b, source diffusion layer, or drain diffusion layer of the plurality of transistors 51. The circuit chip 22 also comprises a wiring layer 53, a wiring layer 54, and a wiring layer 55. The wiring layer 53 contains a plurality of wires and is provided on the plurality of contact plugs 52. The wiring layer 54 contains a plurality of wires and is provided on the wiring layer 53. The wiring layer 55 contains a plurality of wires and is provided on the wiring layer 54.

[0077] The circuit chip 22 further comprises a plurality of via plugs 56 provided on the wiring layer 55, and a plurality of metal pads 57 provided on the plurality of via plugs 56. The metal pads 57 are, for example, metal layers including a Cu (copper) layer. The circuit chip 22 functions as a logic circuit that controls the operation of the array chip 21. This logic circuit is composed of transistors 51 and the like, and is electrically connected to the metal pads 57.

[0078] The array chip 21 comprises a plurality of metal pads 61 provided on the plurality of metal pads 57, and a plurality of via plugs 62 provided on the plurality of metal pads 61. The metal pads 61 are, for example, metal layers including a Cu layer. The array chip 21 also comprises a wiring layer 63 and a wiring layer 64. The wiring layer 63 includes a plurality of wires and is provided on the plurality of via plugs 62. The wiring layer 64 includes a plurality of wires and is provided on the wiring layer 63. The bit line BL is contained within the wiring layer 64. The logic circuit is electrically connected to the memory cell array 31 via the metal pads 61, 57, etc., and controls the operation of the memory cell array 31 via the metal pads 61, 57, etc.

[0079] The array chip 21 further comprises a plurality of via plugs 65 provided on the wiring layer 64, and metal pads 66 provided on the plurality of via plugs 65 and on the insulating film 32. The array chip 21 also comprises a passivation insulating film 67 provided on the metal pads 66 and on the insulating film 32. The metal pads 66 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device in this embodiment. The passivation insulating film 67 is, for example, a multilayer film including an SiO2 film and a SiN film, and has an opening P that exposes the upper surface of the metal pads 66. The metal pads 66 can be electrically connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, etc. through the opening P.

[0080] Figure 26 is an enlarged cross-sectional view showing the structure of a semiconductor device according to the third embodiment.

[0081] Figure 26 shows the memory cell array 31 shown in Figure 25. The memory cell array 31 comprises a laminated film 71 including a plurality of electrode layers 71a and a plurality of insulating films 71b that are alternately stacked in the Z direction. The plurality of electrode layers 71a function, for example, as the word lines WL described above. Each electrode layer 71a includes, for example, a metal layer such as a W (tungsten) layer. Each insulating film 71b is, for example, an SiO2 film. The laminated film 71, electrode layers 71a, and insulating films 71b in this embodiment correspond to the laminated film 2, electrode layer 2b, and insulating film 2a of the first or second embodiment, respectively.

[0082] Figure 26 further shows one of the multiple columnar sections CL shown in Figure 25. Each columnar section CL includes a memory insulating film 72, a channel semiconductor layer 73, and a core insulating film 74, arranged sequentially on the side surface of the laminated film 71. The memory insulating film 72 includes a block insulating film 72a, a charge storage layer 72b, and a tunnel insulating film 72c, arranged sequentially on the side surface of the laminated film 71. The block insulating film 72a is, for example, an SiO2 film. The charge storage layer 72b is, for example, an insulating film such as a SiN film. The charge storage layer 72b may also be a semiconductor layer such as a polysilicon layer. The charge storage layer 72b is capable of storing signal charges in a three-dimensional semiconductor memory. The tunnel insulating film 72c is, for example, an SiO2 film. The channel semiconductor layer 73 is, for example, a polysilicon layer. The channel semiconductor layer 73 functions as a channel in the three-dimensional semiconductor memory. The core insulating film 74 is, for example, an SiO2 film. The block insulating film 72a, charge storage layer 72b, tunnel insulating film 72c, channel semiconductor layer 73, and core insulating film 74 of this embodiment correspond to the block insulating film 4a, charge storage layer 4b, tunnel insulating film 4c, channel semiconductor layer 4d, and core insulating film 4e of the first or second embodiment, respectively.

[0083] Figures 27 and 28 are cross-sectional views showing a method for manufacturing a semiconductor device according to a third embodiment.

[0084] Figure 27 shows an array wafer W1 containing multiple array chips 21 and a circuit wafer W2 containing multiple circuit chips 22. The orientation of the array wafer W1 in Figure 27 is the opposite of the orientation of the array chips 21 in Figure 25. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 27 shows the array wafer W1 before its orientation is reversed for bonding, and Figure 25 shows the array chips 21 after their orientation has been reversed for bonding, and after bonding and dicing.

[0085] In Figure 27, reference numeral S1 indicates the upper surface of the array wafer W1, and reference numeral S2 indicates the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 36 provided beneath the insulating film 32. The substrate 36 is, for example, a semiconductor substrate such as a Si substrate. The substrate 36 in this embodiment corresponds to the substrate 1 in the first or second embodiment.

[0086] In this embodiment, first, as shown in Figure 27, a memory cell array 31, insulating film 32, interlayer insulating film 33, metal pads 61, via plugs 65, etc. are formed on the substrate 36 of the array wafer W1, and an interlayer insulating film 34, transistors 51, metal pads 57, etc. are formed on the substrate 35 of the circuit wafer W2. Next, as shown in Figure 28, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that surfaces S1 and S2 face each other. This bonds the interlayer insulating film 33 and the interlayer insulating film 34. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pads 61 and 57. In this way, the substrates 36 and 35 are bonded together via the interlayer insulating films 33 and 34.

[0087] Subsequently, the substrate 36 is removed by CMP (Chemical Mechanical Polishing), and the substrate 35 is thinned by CMP. Then, the array wafer W1 and the circuit wafer W2 are cut into multiple chips (dicing). In this way, the semiconductor device shown in Figure 25 is manufactured. The metal pad 66 and the passivation insulating film 67 are formed on the insulating film 32 after the removal of the substrate 36 and the thinning of the substrate 35.

[0088] Figure 25 shows the interface between the interlayer insulating film 33 and the interlayer insulating film 34, and the interface between the metal pad 61 and the metal pad 57. However, after the annealing described above, these interfaces are generally no longer visible. Nevertheless, the locations where these interfaces were located can be estimated, for example, by detecting the inclination of the side surfaces of the metal pad 61 and the metal pad 57, or by detecting the positional displacement between the side surfaces of the metal pad 61 and the metal pad 57.

[0089] According to this embodiment, the semiconductor device and its manufacturing method according to the first or second embodiment can be applied to this embodiment.

[0090] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel methods described herein can be carried out in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of Symbols]

[0091] 1: Substrate, 2: Multilayer film, 2a: Insulating film, 2b: Electrode layer, 2c: Sacrificial layer 3: Interlayer insulating film, 4: Columnar portion, 4a: Block insulating film, 4b: Charge storage layer, 4c: Tunnel insulating film, 4d: Channel semiconductor layer, 4e: Core insulating film 5: Support column (beam), 5a: Insulating film, 6: Insulating film, 6a: Part, 6b: Part 11: Mask layer, 12: Sacrifice layer, 21: Array chip, 22: Circuit chip, 31: Memory cell array, 32: Insulating film, 33: Interlayer insulating film, 34: Interlayer insulating film, 35: Substrate, 36: Substrate, 41: Stair structure section, 42: Support section (beam section), 43: Contact plug, 44: Word wiring layer, 45: Via plug, 51: Transistor, 51a: Gate insulator, 51b: Gate electrode, 52: Contact plug, 53: Wiring layer, 54: Wiring layer, 55: Wiring layer, 56: Via plug, 57: Metal pad, 61: Metal pad, 62: Via plug, 63: Wiring layer, 64: Wiring layer, 65: Via plug, 66: Metal pad, 67: Passivation insulating film, 71: Multilayer film, 71a: Electrode layer, 71b: Insulating film, 72: Memory insulating film, 72a: Block insulating film, 72b: Charge storage layer, 72c: Tunnel insulating film, 73: Channel semiconductor layer, 74: Core insulating film

Claims

1. A laminated film is formed in which a plurality of first insulating films and a plurality of first layers are alternately arranged in the first direction. A first portion and a second portion are formed within the laminated film. A first hole and a second hole are formed within the second portion. A second layer is formed within the first hole and the second hole. The laminated film and the second layer are etched such that a third hole is formed in the first portion and a fourth hole is formed in the second layer of the second hole. After the third hole and the fourth hole are formed, the second layer is removed. A support column including a second insulating film is formed within the first hole and the second hole. Within the third hole, a columnar portion including a charge storage layer and a semiconductor layer is formed. After the support portion and the columnar portion are formed, the plurality of first layers are replaced with a plurality of electrode layers. A method for manufacturing a semiconductor device, including the following.

2. The first portion is the non-step portion of the laminated film, The second portion is the stepped portion of the laminated film. A method for manufacturing a semiconductor device according to claim 1.

3. The process further includes forming a third insulating film on the stepped portion before forming the first and second holes, The method for manufacturing a semiconductor device according to claim 2, wherein at least the first hole among the first and second holes is formed within the stepped portion and the third insulating film.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the distance between the second hole and the first portion is smaller than the distance between the first hole and the first portion.

5. The first hole and the second hole have a first diameter in plan view, The method for manufacturing a semiconductor device according to claim 1, wherein the third hole and the fourth hole have a second diameter smaller than the first diameter in a plan view.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the first hole and the second hole are formed so as to penetrate the laminated film.

7. The third hole is formed to penetrate the laminated film, The fourth hole is formed so as not to penetrate the second layer. A method for manufacturing a semiconductor device according to claim 1.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the second layer is a metal layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the metal layer is a tungsten layer.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the second layer is a carbon layer.

11. The method for manufacturing a semiconductor device according to claim 1, wherein the etching of the laminated film and the second layer is cryo-etching.

12. The process further includes forming a recess within the laminated film after the support portion and the columnar portion have been formed. The method for manufacturing a semiconductor device according to claim 1, wherein the substitution of the plurality of first layers to the plurality of electrode layers is performed by etching from the recess.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the recess is formed within the first portion and the second portion.

14. The second portion is formed in a second direction of the first portion, The recess is formed to extend in the second direction, The method for manufacturing a semiconductor device according to claim 12.

15. The further includes forming a plurality of fifth holes within the laminated film, The method for manufacturing a semiconductor device according to claim 12, wherein the recess is formed by connecting the plurality of fifth holes.

16. The method for manufacturing a semiconductor device according to claim 15, wherein the plurality of fifth holes are formed by etching that forms the first hole and the second hole.

17. The method for manufacturing a semiconductor device according to claim 15, wherein the second layer is formed within the first hole, the second hole, and the plurality of fifth holes.

18. The method for manufacturing a semiconductor device according to claim 15, wherein the etching of the laminated film and the second layer is carried out such that a third hole is formed in the first portion, a fourth hole is formed in the second layer of the second hole, and a sixth hole is formed in the second layer of at least one of the plurality of fifth holes.

19. Forming the first film, A first portion and a second portion are formed within the first film. A first hole and a second hole are formed within the second portion. A second layer is formed within the first hole and the second hole. The first film and the second layer are etched such that a third hole is formed in the first portion and a fourth hole is formed in the second layer of the second hole. After the third hole and the fourth hole are formed, the second layer is removed. A support column including a second insulating film is formed within the first hole and the second hole. Within the third hole, a columnar portion including a charge storage layer and a semiconductor layer is formed. A method for manufacturing a semiconductor device, including the following.

20. The first film is a laminated film comprising a plurality of first insulating films and a plurality of first layers alternately in a first direction, The method for manufacturing a semiconductor device according to claim 19, further comprising replacing the plurality of first layers with a plurality of electrode layers after the support portion and the columnar portion have been formed.

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