Interconnection module substrate for semiconductor packages, semiconductor package elements including the same, and methods for manufacturing the same.

Abstract

The present invention provides interconnection module substrates for semiconductor packages, semiconductor package elements including the same, and methods for manufacturing them. [Solution] The interconnection module substrate M10 for semiconductor packages includes a plurality of via limiting structures VD10, each containing a base material unit U10 and a conductive via element V10 that penetrates the base material unit U10 vertically, and arranged horizontally apart from each other; at least one interconnection bridge member BG10 arranged horizontally apart from or adjacent to the plurality of via limiting structures VD10; and a substrate material layer SL10 that fills the space between and around the plurality of via limiting structures VD10 and the interconnection bridge member BG10, forming a single substrate shape together with them, and exposing the plurality of via limiting structures VD10 and the interconnection bridge member BG10.

Description

Technical Field

[0001] The present invention relates to technologies and methods related to semiconductor packages, and more particularly to a substrate for a semiconductor package, a semiconductor package element including the same, and a manufacturing method thereof.

Background Art

[0002] The semiconductor process can be divided into an electrical process of manufacturing a wafer and etching a circuit, and a post-process of packaging a chip. As semiconductor miniaturization technology approaches its limit, the importance of the post-process is gradually increasing. In this regard, advanced packaging technologies for integrating different semiconductor chips with each other or vertically connecting many chips are emerging as important technologies.

[0003] 2.5D (2.5-dimensional) packaging is a packaging technology that horizontally arranges many semiconductor chips (dies) and integrates them into a single package. The difference between 2.5D packaging and 3D packaging is that each chip is arranged on an interposer, which is a packaging component. Logic chips, memory chips, etc. can be horizontally arranged on the interposer. By connecting each chip with interconnect technology, the connectivity between chips can be improved.

[0004] EMIB (embedded multi-die interconnect bridge) technology uses a silicon interposer to connect dissimilar semiconductor chips (dies), with the silicon interposer integrated into an FC-BGA (flip chip ball grid array) substrate, which is called a "silicon bridge." EMIB technology offers advantages such as reduced board area and package height, and lower power consumption. Because the silicon bridge area is smaller than that of a typical silicon interposer, production costs can be reduced. However, in the case of package substrates with integrated silicon bridges used in EMIB, there is insufficient capacity to adequately handle differences in electrode pitch and pattern resolution, making it difficult to mount two or more chips with different electrode pitches on a single substrate. Furthermore, EMIB package substrates can be difficult to apply to various semiconductor package designs, manufacturing methods can be complex, and there may be issues with reduced durability due to deformation.

[0005] Therefore, there is a need to develop interconnection substrates for semiconductor packages that are easy to design in various ways according to the user's requirements and purposes, and that are easy to manufacture. Furthermore, there is a need to develop interconnection substrates for semiconductor packages that can be manufactured in accordance with various semiconductor package designs, have the capability to accommodate various electrode pitches, and possess excellent performance and durability. [Overview of the project] [Problems that the invention aims to solve]

[0006] The technical problem that this invention aims to solve is to provide an interconnection module substrate for semiconductor packages that is easy to design in a variety of ways to suit the user's requirements and purposes, and is easy to manufacture.

[0007] Furthermore, the technical problem that the present invention aims to solve is to provide an interconnection module substrate for semiconductor packages that can be manufactured in accordance with various semiconductor package designs, can accommodate various electrode pitches, and has excellent performance and durability.

[0008] Furthermore, a technical problem that the present invention aims to solve is to provide a semiconductor package element to which the interconnection module substrate is applied.

[0009] Furthermore, the technical problem that the present invention aims to solve is to provide a method for manufacturing the interconnection module substrate and semiconductor package elements.

[0010] The problems that this invention aims to solve are not limited to those mentioned above, and other problems not mentioned will be understandable to those skilled in the art from the following description. [Means for solving the problem]

[0011] According to one embodiment of the present invention, an interconnection module substrate for a semiconductor package is provided, comprising: a plurality of via limiting structures, each including a base material unit and a conductive via element that penetrates the base material unit vertically, and arranged horizontally apart from each other; at least one interconnection bridge member arranged horizontally apart from or adjacent to the plurality of via limiting structures; and a substrate material layer configured to fill the space between and around the plurality of via limiting structures and the interconnection bridge member, forming a single substrate shape together, and exposing the plurality of via limiting structures and the interconnection bridge member.

[0012] The plurality of via-limiting structures include a first via-limiting structure, the first via-limiting structure includes first and second conductive via elements spaced apart from each other, and the first and second conductive via elements may have the same spacing at their upper and lower ends.

[0013] The plurality of via-limiting structures include a first via-limiting structure, the first via-limiting structure includes first and second conductive via elements spaced apart from each other, and the first and second conductive via elements may have a first spacing at their upper ends and a second spacing at their lower ends that is larger than the first spacing.

[0014] At least one of the first and second conductive via elements may have a refracted structure.

[0015] The interconnection bridge member may include a first connection pad portion electrically connected to a first semiconductor chip, and a second connection pad portion electrically connected to a second semiconductor chip.

[0016] The interconnection bridge member may include a base portion and a wiring structure formed on the base portion.

[0017] The interconnection bridge member may have a thickness thinner than the substrate material layer.

[0018] The interconnection bridge member has the same thickness as or substantially the same thickness as the substrate material layer, and the interconnection bridge member may include a TSV (through silicon via) or a corresponding through electrode.

[0019] According to another embodiment of the present invention, a semiconductor package is provided that includes the interconnection module substrate described above and a plurality of semiconductor chips mounted on the upper surface of the interconnection module substrate, spaced apart from each other or adjacent to each other in the horizontal direction.

[0020] The plurality of semiconductor chips include first and second semiconductor chips, the plurality of via-limiting structures include first and second via-limiting structures, the at least one interconnection bridge member includes a first interconnection bridge member positioned between the first and second via-limiting structures, the first semiconductor chip is connected to the conductive via elements of the first via-limiting structure and the first connection pad portion of the first interconnection bridge member, and the second semiconductor chip may be connected to the conductive via elements of the second via-limiting structure and the second connection pad portion of the first interconnection bridge member.

[0021] A first electrical connection element is arranged between the interconnection module substrate and the semiconductor chip, and a second electrical connection element connected to the conductive via element may be arranged on the lower surface of the interconnection module substrate.

[0022] According to another embodiment of the present invention, a method for manufacturing an interconnection module substrate for a semiconductor package is provided, comprising the steps of: arranging a plurality of preformed via-limiting structures, each including a base material unit and conductive via elements penetrating the base material unit vertically, and at least one interconnection bridge member horizontally spaced apart from or adjacent to each other; forming a substrate material layer on the temporary substrate, filling the spaces between and around the plurality of preformed via-limiting structures and the interconnection bridge member to form a single substrate shape together; and removing the temporary substrate from the interconnection module substrate comprising the plurality of preformed via-limiting structures, the interconnection bridge member, and the substrate material layer.

[0023] The process may further include polishing at least one of the upper and lower surfaces of the interconnection module substrate.

[0024] The plurality of pre-formed via confinement structures includes a first via confinement structure, and the first via confinement structure includes first and second conductive via elements spaced apart from each other, and the first and second conductive via elements may have the same spacing at the upper and lower ends.

[0025] The plurality of pre-formed via confinement structures includes a first via confinement structure, and the first via confinement structure includes first and second conductive via elements spaced apart from each other, and the first and second conductive via elements have a first spacing at the upper end and may have a second spacing greater than the first spacing at the lower end.

[0026] At least one of the first and second conductive via elements may have a refracted structure.

[0027] The interconnecting bridge member may have a thickness thinner than the substrate material layer.

[0028] The interconnecting bridge member has the same thickness or substantially the same thickness as the substrate material layer, and the interconnecting bridge member may include a TSV (through silicon via) or a corresponding through electrode.

[0029] According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor package element, including the step of providing an interconnect module substrate using the method described above, and the step of horizontally spacing apart or adjacently mounting a plurality of semiconductor chips on the upper surface of the interconnect module substrate.

[0030] The method may further include the step of forming an electrical connection element connected to the conductive via element on the lower surface of the interconnect module substrate.

Advantages of the Invention

[0031] According to embodiments of the present invention, it is possible to realize an interconnection module substrate for semiconductor packages that is easy to design in a variety of ways to suit the user's requirements and purposes, and is easy to manufacture. Furthermore, according to embodiments of the present invention, it is possible to realize an interconnection module substrate for semiconductor packages that can be manufactured in accordance with a variety of semiconductor package designs, can be made compatible with a variety of electrode pitches, and has excellent performance and durability. In particular, according to one embodiment of the present invention, by forming the interconnection module substrate using a preformed 3D via-limiting structure and interconnection bridge members, for example by a molding method, it is possible to realize a variety of designs in an easy manner.

[0032] By using the interconnection module substrate according to the embodiment of the present invention, semiconductor package elements with excellent performance can be easily manufactured.

[0033] However, the effects of the present invention are not limited to those described above, and can be extended in various ways without departing from the technical idea and domain of the present invention. [Brief explanation of the drawing]

[0034] [Figure 1] This is a schematic cross-sectional view showing an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 2] This is a schematic cross-sectional view showing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 3] This is a schematic cross-sectional view showing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view showing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 5]This is a schematic cross-sectional view showing a semiconductor package element including an interconnection module substrate for a semiconductor package according to one embodiment of the present invention. [Figure 6] This is a schematic cross-sectional view showing a semiconductor package element including an interconnection module substrate for a semiconductor package according to another embodiment of the present invention. [Figure 7] This is a cross-sectional view illustrating an example of a via-limited structure applicable to an interconnection module substrate for semiconductor packages according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating an example of a via-limited structure applicable to an interconnection module substrate for semiconductor packages according to an embodiment of the present invention. [Figure 9] This is a cross-sectional view illustrating an example of a via-limited structure applicable to an interconnection module substrate for semiconductor packages according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view illustrating an example of a via-limited structure applicable to an interconnection module substrate for semiconductor packages according to an embodiment of the present invention. [Figure 11] This is a plan view illustrating a via-limited structure applicable to an interconnection module substrate for semiconductor packages according to an embodiment of the present invention. [Figure 12a] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 12b] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 12c] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 12d] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 13a]This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 13b] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 13c] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 13d] This is a cross-sectional view illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 14a] This is a cross-sectional view illustrating an exemplary method for manufacturing a semiconductor package element using an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 14b] This is a cross-sectional view illustrating an exemplary method for manufacturing a semiconductor package element using an interconnection module substrate for semiconductor packages according to one embodiment of the present invention. [Figure 15a] This is a cross-sectional view illustrating an exemplary method for manufacturing a semiconductor package element using an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Figure 15b] This is a cross-sectional view illustrating an exemplary method for manufacturing a semiconductor package element using an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. [Modes for carrying out the invention]

[0035] Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The sizes and thicknesses of areas and parts shown in the accompanying drawings may be slightly exaggerated for clarity and ease of explanation. Throughout the detailed description, the same reference numerals indicate the same components.

[0036] Figure 1 is a schematic cross-sectional view showing an interconnection module substrate M10 for semiconductor packages according to one embodiment of the present invention.

[0037] Referring to Figure 1, the interconnection module substrate M10 according to an embodiment of the present invention may include a plurality of via-defining structures VD10, at least one interconnection bridge member BG10, and a substrate material layer SL10.

[0038] Each of the multiple via-limited structures VD10 may include a substrate material unit U10 and a conductive via element V10 that penetrates the substrate material unit U10 vertically. The substrate material unit U10 may have, for example, a polygonal prism shape or a block shape with a predetermined thickness, and its planar shape when viewed from above can vary in many ways. Via holes or similar through-holes (through-spaces) can be formed in the substrate material unit U10, and conductive via elements V10 can be formed within the via holes or through-holes (through-spaces). The substrate material unit U10 may contain organic or inorganic materials, and may contain both organic and inorganic materials together. The substrate material unit U10 may be formed from organic materials, inorganic materials, or a composite material of organic and inorganic materials. As a non-restrictive example, the substrate material unit U10 may contain organic materials used as substrate materials in the PCB (printed circuit board) field, or it may contain inorganic materials such as silicon. If the base material unit U10 contains silicon, the conductive via element V10 can be considered a type of TSV (through silicon via). The base material unit U10 may contain at least one of an insulating material and a semiconductor material.

[0039] The conductive via element V10 may be positioned to penetrate the substrate material unit U10 vertically. The conductive via element V10 may extend from the bottom surface to the top surface of the substrate material unit U10. The conductive via element V10 may be exposed on the bottom and top sides of the substrate material unit U10. The conductive via element V10 can also be called a "via-type wiring," "via-containing wiring," or "via plug." The conductive via element V10 may contain at least one of metals and metal compounds. Conductive materials applicable to general via structures are applicable to the conductive via element V10. Although not shown in Figure 1, via lands, i.e., via extensions, may be present at both ends (bottom and top) of the conductive via element V10.

[0040] Multiple via limit structures VD10 can be arranged horizontally, spaced apart from one another. At least some of the multiple via limit structures VD10 may have different configurations or different sizes. At least some of the multiple via limit structures VD10 may also provide different pitch characteristics between vias. In Figure 1, for convenience, three via limit structures VD10 are shown, but in reality, a larger number of via limit structures VD10 can be arranged. When considering the manufacturing process, the via limit structures VD10 can be said to be preformed via limit structures. Furthermore, the via limit structures VD10 can be said to have a three-dimensional (3D) structure. Therefore, the via limit structures VD10 can be said to be preformed 3D via limit structures.

[0041] At least one interconnection bridge member BG10 may be positioned horizontally separated from or adjacent to a plurality of via limiting structures VD10. Here, "adjacent" can include not only the general concept of adjacentness, but also the concepts of approaching or touching. The interconnection bridge member BG10 may be positioned between at least two of the plurality of via limiting structures VD10. Multiple interconnection bridge members BG10 may be used as needed.

[0042] The interconnection bridge member BG10 can serve to electrically connect a first semiconductor chip (i.e., die) and a second semiconductor chip (i.e., die) to each other. The interconnection bridge member BG10 may include a base portion B10 and a wiring structure formed on the base portion B10. The wiring structure may include a first connection pad portion P10 and a second connection pad portion P20. The first connection pad portion P10 can be electrically connected to the first semiconductor chip, and the second connection pad portion P20 can be electrically connected to the second semiconductor chip. The first connection pad portion P10 and the second connection pad portion P20 can be electrically connected to each other. A single interconnection bridge member BG10 may be provided with a plurality of first connection pad portions P10 and a plurality of second connection pad portions P20.

[0043] The base portion B10 may include, for example, a semiconductor substrate portion. The semiconductor substrate portion may include, for example, silicon (Si), germanium (Ge), or silicon germanium (SiGe). As a specific example, the semiconductor substrate portion may include silicon (Si). However, the specific material of the semiconductor substrate portion is not limited to those described above and can vary in many ways. A predetermined circuit portion can be formed on the base portion B10, and the circuit portion may include first and second connection pad portions P10 and P20. When considering the manufacturing process, the interconnection bridge member BG10 can be said to be a preformed interconnection bridge.

[0044] The substrate material layer SL10 can fill the spaces between and around multiple via-limiting structures VD10 and interconnection bridge members BG10, and together with them, form a single substrate shape. The substrate material layer SL10 can be a material layer for forming the substrate structure while physically binding the multiple via-limiting structures VD10 and interconnection bridge members BG10 together. The substrate material layer SL10 can be formed, for example, by a molding method.

[0045] The substrate material layer SL10 can be configured to expose multiple via limiting structures VD10 and interconnection bridge members BG10. The lower and upper surfaces of the via limiting structures VD10 can be exposed on the lower and upper sides of the substrate material layer SL10, respectively. The upper surface of the interconnection bridge member BG10 can also be exposed on the upper side of the substrate material layer SL10. The via limiting structures VD10 can be considered to be arranged to penetrate the substrate material layer SL10 in the vertical direction, i.e., vertically. The interconnection bridge member BG10 can be considered to be embedded in the upper surface of the substrate material layer SL10. The first and second connection pad portions P10 and P20 can be exposed on the upper side of the substrate material layer SL10.

[0046] The upper surface of the via limiting structure VD10, the upper surface of the interconnection bridge member BG10, and the upper surface of the substrate material layer SL10 may be at the same level (height) or at approximately the same level. The lower surface of the via limiting structure VD10 and the lower surface of the substrate material layer SL10 may be at the same level (height) or at approximately the same level. The via limiting structure VD10 may have the same or similar thickness as the substrate material layer SL10. The interconnection bridge member BG10 may have a thinner thickness than the substrate material layer SL10.

[0047] The substrate material layer SL10 may, for example, contain or be formed from an organic material. As a non-limiting example, the substrate material layer SL10 may be or contain a molding compound. The substrate material layer SL10 may be an insulator. The substrate material layer SL10 may be a separate material layer from the base material unit U10. The substrate material layer SL10 and the base material unit U10 may have different material compositions. However, in some cases, the substrate material layer SL10 and the base material unit U10 may contain the same material or similar materials.

[0048] In embodiments of the present invention, a semiconductor package interconnection module substrate M10 can be manufactured by forming a substrate material layer SL10 after manufacturing and arranging a plurality of via limiting structures VD10 and at least one interconnection bridge member BG10 to suit the requirements and purposes. According to such embodiments of the present invention, it is possible to realize a semiconductor package interconnection module substrate that is easy to manufacture and can be easily designed to suit the user's requirements and purposes. Furthermore, it is possible to manufacture in accordance with a variety of semiconductor package designs, ensure compatibility with a variety of electrode pitches, and realize a semiconductor package interconnection module substrate with excellent performance and durability.

[0049] In the embodiment shown in Figure 1, the multiple via-limiting structures VD10 may include a first via-limiting structure, the first via-limiting structure may correspond, for example, to the leftmost via-limiting structure VD10 in Figure 1. The first via-limiting structure may include first and second conductive via elements V1a and V1b spaced apart from each other. The first and second conductive via elements V1a and V1b may have the same spacing at their upper and lower ends. In other words, the spacing between the upper ends of the first and second conductive via elements V1a and V1b may be the same as, or substantially the same as, the spacing between the lower ends of the first and second conductive via elements V1a and V1b. In this case, the first via-limiting structure can be said to provide the same electrode pitch characteristics at its upper and lower ends. Here, each of the first and second conductive via elements V1a and V1b may have a structure that extends perpendicularly in a linear shape.

[0050] Figure 2 is a schematic cross-sectional view showing an interconnection module substrate M11 for semiconductor packages according to another embodiment of the present invention.

[0051] Referring to Figure 2, the interconnection module substrate M11 according to this embodiment can include a plurality of via limiting structures VD11, at least one interconnection bridge member BG10, and a substrate material layer SL10. Each of the plurality of via limiting structures VD11 can include a base material unit U11 and a conductive via element V11 that penetrates the base material unit U11 vertically. The plurality of via limiting structures VD11 can be arranged horizontally apart from each other. At least one interconnection bridge member BG10 can be arranged horizontally apart from or adjacent to the plurality of via limiting structures VD11. The substrate material layer SL10 can fill the space between and around the plurality of via limiting structures VD11 and the interconnection bridge member BG10, and together with them can form a single substrate shape, and can be formed to expose the plurality of via limiting structures VD11 and the interconnection bridge member BG10.

[0052] In this embodiment, the multiple via-limiting structures VD11 may include a first via-limiting structure, the first via-limiting structure may correspond, for example, to the leftmost via-limiting structure VD11 in Figure 2. The first via-limiting structure may include first and second conductive via elements V1c and V1d spaced apart from each other. The first and second conductive via elements V1c and V1d may have different spacings at their upper and lower ends. In other words, the spacing between the upper ends of the first and second conductive via elements V1c and V1d may differ from the spacing between the lower ends of the first and second conductive via elements V1c and V1d. In this case, the first via-limiting structure can be said to provide different electrode pitch characteristics at its upper and lower ends. Here, at least one of the first and second conductive via elements V1c and V1d may have a refracted structure. Each of the first and second conductive via elements V1c and V1d may have a refracted structure.

[0053] For example, the first and second conductive via elements V1c and V1d may have a first spacing at their upper ends and a second spacing at their lower ends that is larger than the first spacing. Thus, the electrode pitch can be extended at the bottom of the first via-limiting structure by the first and second conductive via elements V1c and V1d. The first conductive via element V1c may have a structure that is refracted at least twice as it goes from bottom to top. The first conductive via element V1c may be refracted closer to the second conductive via element V1d as it goes upward. In this case, the first conductive via element V1c may include one or more vertical components and one or more horizontal components. The vertical components can be called via plug components, and the horizontal components can be called pattern layer components. Also, if necessary, the base material unit U11 may have a multilayer structure of two or more layers. On the other hand, the second conductive via element V1d may have a structure symmetrical to or similar to that of the first conductive via element V1c. However, the specific structures of the first and second conductive via elements V1c and V1d described in Figure 2 are merely illustrative and can be modified in various ways depending on the circumstances.

[0054] In Figure 2, the configuration and characteristics of the interconnection bridge member BG10 and the substrate material layer SL10 are the same as those described in Figure 1, so a repeated explanation will be omitted.

[0055] Figure 3 is a schematic cross-sectional view showing an interconnection module substrate M12 for semiconductor packages according to another embodiment of the present invention.

[0056] Referring to Figure 3, the interconnection module substrate M12 according to this embodiment can include a plurality of via limiting structures VD10, at least one interconnection bridge member BG11, and a substrate material layer SL10. Each of the plurality of via limiting structures VD10 can include a base material unit U10 and a conductive via element V10 that penetrates the base material unit U10 vertically. The plurality of via limiting structures VD10 can be arranged horizontally apart from each other. At least one interconnection bridge member BG11 can be arranged horizontally apart from or adjacent to the plurality of via limiting structures VD10. The substrate material layer SL10 can fill the space between and around the plurality of via limiting structures VD10 and the interconnection bridge member BG11, and together with them can form a single substrate shape, and can be formed to expose the plurality of via limiting structures VD10 and the interconnection bridge member BG11.

[0057] In this embodiment, the interconnection bridge member BG11 may have the same or substantially the same thickness as the substrate material layer SL10. The interconnection bridge member BG11 may have the same or substantially the same thickness as the via-limiting structure VD10. The interconnection bridge member BG11 can be considered as being positioned to penetrate the substrate material layer SL10 in the vertical direction, i.e., vertically. The interconnection bridge member BG11 may further include a through electrode T11. The through electrode T11 may be formed to penetrate the interconnection bridge member BG11 in the vertical direction, i.e., vertically. The through electrode T11 may be a TSV (through silicon via) or a corresponding electrode. The position of the through electrode T11 shown in Figure 3 is illustrative only, and its position may vary. One or more through electrodes T11 may be provided in a single interconnection bridge member BG11. The through electrode T11 can provide electrical connectivity between at least one semiconductor chip and an external circuit. The through electrode T11 can provide the effect of improving routing density.

[0058] In Figure 3, reference numeral B11 indicates the base portion of the interconnection bridge member BG11, P11 indicates the first connection pad portion, and P21 indicates the second connection pad portion. The base portion B11 may have the same thickness as or substantially the same thickness as the substrate material layer SL10. The through electrode T11 may be formed to penetrate the base portion B11.

[0059] Figure 4 is a schematic cross-sectional view showing an interconnection module substrate M13 for semiconductor packages according to another embodiment of the present invention.

[0060] Referring to Figure 4, the interconnection module substrate M13 according to this embodiment may include a plurality of via limiting structures VD11, at least one interconnection bridge member BG11, and a substrate material layer SL10. The via limiting structures VD11 are the same as those described in Figure 2, and the interconnection bridge member BG11 may be the same as those described in Figure 3.

[0061] Depending on the circumstances, features of at least two of the embodiments shown in Figures 1 to 4 can be combined on a single interconnection module board.

[0062] Figure 5 is a schematic cross-sectional view showing a semiconductor package element including an interconnection module substrate M10 for semiconductor packages according to one embodiment of the present invention.

[0063] Referring to Figure 5, the semiconductor package element according to an embodiment of the present invention may include an interconnection module substrate M10 and a plurality of semiconductor chips (i.e., dies) C10 mounted horizontally spaced apart from each other or adjacent to each other on the upper surface of the interconnection module substrate M10. Exemplaryly, three semiconductor chips C10 are shown, which can be called the first, second, and third semiconductor chips C1a, C1b, and C1c. The interconnection module substrate M10 may have a configuration such as that described in Figure 1. The interconnection module substrate M10 may include a plurality of via-limiting structures VD10, at least one interconnection bridge member BG10, and a substrate material layer SL10.

[0064] The plurality of semiconductor chips C10 may include first and second semiconductor chips C1a and C1b, and the plurality of via-limiting structures VD10 may include first and second via-limiting structures VD1a and VD1b. The at least one interconnection bridge member BG10 may include a first interconnection bridge member BG1a disposed between the first and second via-limiting structures VD1a and VD1b. The first semiconductor chip C1a may be connected to the conductive via element V10 of the first via-limiting structure VD1a and the first connection pad portion P10 of the first interconnection bridge member BG1a. The second semiconductor chip C1b may be connected to the conductive via element V10 of the second via-limiting structure VD1b and the second connection pad portion P20 of the first interconnection bridge member BG1a.

[0065] The semiconductor package element may further include a first electrical connection element CE10 disposed between the interconnection module substrate M10 and the semiconductor chip C10. The semiconductor package element may further include a second electrical connection element CE20 disposed on the lower surface of the interconnection module substrate M10 to connect to a conductive via element V10. Multiple first electrical connection elements CE10 and multiple second electrical connection elements CE20 can be provided. The first electrical connection element CE10 may, as an unrestricted example, be a bump or microbump. The second electrical connection element CE20 may, as an unrestricted example, be a solder ball. However, the specific types of the first and second electrical connection elements CE10 and CE20 are not limited to those described above and can vary. Furthermore, a predetermined re-distribution layer (RDL) may be formed on the upper surface of the interconnection module substrate M10.

[0066] At least two of the multiple semiconductor chips C10 may be heterogeneous chips. In other words, the multiple semiconductor chips C10 may include heterogeneous chips. For example, the multiple semiconductor chips C10 may include memory chips and logic chips, and may further include other types of chips. Depending on the case, one or more semiconductor chips (i.e., dies) may be further stacked (mounted) on at least one of the multiple semiconductor chips C10. The interconnection module substrate according to the embodiment of the present invention can be used for 2.5D packages or 3D packages.

[0067] Figure 6 is a schematic cross-sectional view showing a semiconductor package element including an interconnection module substrate M11 for semiconductor packages according to another embodiment of the present invention.

[0068] Referring to Figure 6, the semiconductor package element according to this embodiment may include an interconnection module substrate M11 and a plurality of semiconductor chips C10 mounted horizontally spaced apart from each other or adjacent to each other on the upper surface of the interconnection module substrate M11. Exemplary, three semiconductor chips C10 are shown, which can be referred to as the first, second, and third semiconductor chips C1a, C1b, and C1c. The interconnection module substrate M11 may have a configuration as described in Figure 2, for example. The interconnection module substrate M11 may include a plurality of via-limiting structures VD11, at least one interconnection bridge member BG10, and a substrate material layer SL10.

[0069] In this embodiment, the multiple via limiting structures VD11 may include a first via limiting structure, the first via limiting structure may correspond, for example, to the leftmost via limiting structure VD11 in Figure 6. The first via limiting structure may include first and second conductive via elements V1c and V1d spaced apart from each other. The first and second conductive via elements V1c and V1d may have different spacings at their upper and lower ends. In this case, the first via limiting structure can be said to provide different electrode pitch characteristics at its upper and lower ends. For example, the first and second conductive via elements V1c and V1d may have a first spacing at their upper ends and a second spacing at their lower ends that is larger than the first spacing. Thus, the pitch between the second electrical connection elements CE20 can be maintained to be the same as or similar to that in Figure 5. A predetermined rearrangement layer (RDL) can be formed on the upper surface of the interconnection module substrate M11.

[0070] As shown and explained in Figures 5 and 6, semiconductor package elements can be manufactured using interconnection module substrates M12 and M13 according to the embodiments in Figures 3 and 4.

[0071] Figures 7 to 10 are cross-sectional views illustrating via-limiting structures VD15 to VD18 applicable to interconnection module substrates for semiconductor packages according to embodiments of the present invention.

[0072] Referring to Figure 7, the via-limiting structure VD15 may include a base material unit U15 and a conductive via element V15 that penetrates the base material unit U15 vertically. Via lands, i.e., via extensions (via pads), may be present at both ends of the conductive via element V15. The via lands may protrude slightly from the base material unit U15.

[0073] Referring to Figure 8, the via-limiting structure VD16 may include a base material unit U16 and a conductive via element V16 that penetrates the base material unit U16 perpendicularly. Via lands, i.e., via extensions (via pads), may be present at both ends of the conductive via element V16. The via lands do not have to protrude from the base material unit U16. In this case, the base material unit U16 and the conductive via element V16 may have the same thickness or substantially the same thickness.

[0074] Referring to Figure 9, the via limiting structure VD17 may include a base material unit U17 and a conductive via element V17 that penetrates the base material unit U17 vertically. The conductive via element V17 has a columnar or pipe shape with a hollow section, and via lands, i.e., via extension sections (via pad sections), may be present at both ends. The via lands may protrude slightly from the base material unit U17. The hollow section of the via limiting structure VD17 may also be filled with a predetermined material.

[0075] Referring to Figure 10, the via-limiting structure VD18 may include a base material unit U18 and a conductive via element V18 that penetrates the base material unit U18 vertically. The conductive via element V18 has a columnar or pipe shape with a hollow portion, and via lands, i.e., via extensions (via pads), may be present at both ends. The via lands do not have to protrude from the base material unit U18. In this case, the thickness in the Z-axis direction of the base material unit U18 and the conductive via element V18 may be the same or substantially the same. The hollow portion of the conductive via element V18 may also be filled with a predetermined material.

[0076] The configurations of the via-limited structures VD15-VD18 described in Figures 7-10, or modified configurations thereof, can be applied to the embodiments shown in Figures 1-6. The conductive via elements V15-V18 of the via-limited structures VD15-VD18 are deformable into a bent structure. In embodiments of the present invention, the conductive via elements can be formed by a filling method or a plating method, and their specific structure / morphology can be varied in many ways.

[0077] Figure 11 is a plan view illustrating a via-limited structure VD19 applicable to an interconnection module substrate for semiconductor packages according to an embodiment of the present invention.

[0078] Referring to Figure 11, the via-limiting structure VD19 can include a base material unit U19 and conductive via elements V19 that penetrate the base material unit U19 vertically. Multiple conductive via elements V19 can be arranged in a predetermined manner. Multiple conductive via elements V19 can be arranged in a single row, in multiple rows, or in a zigzag (staggered) arrangement. The arrangement of multiple conductive via elements V19 can be varied in various ways as needed. In addition, the number of conductive via elements V19 included in a single via-limiting structure VD19, the size of the via-limiting structure VD19, and the overall shape of the via-limiting structure VD19 can be varied in various ways.

[0079] Figures 12a to 12d are cross-sectional views illustrating an exemplary method for manufacturing an interconnection module substrate for semiconductor packages according to one embodiment of the present invention.

[0080] Referring to Figure 12a, multiple preformed via-limiting structures VD10 and at least one interconnection bridge member BG10 can be arranged horizontally, spaced apart from each other or adjacent to each other, on the temporary substrate TS10. Multiple preformed via-limiting structures VD10 and at least one interconnection bridge member BG10 can be attached to the upper surface of the temporary substrate TS10 in a state where they are overlapping each other vertically. Multiple preformed via-limiting structures VD10 can be arranged approximately two-dimensionally on a plane.

[0081] Multiple pre-formed via-limiting structures VD10 can serve to provide vertical electrical connectivity. Each of the multiple pre-formed via-limiting structures VD10 may include a substrate material unit U10 and a conductive via element V10 that penetrates the substrate material unit U10 vertically. Multiple pre-formed via-limiting structures VD10 can be easily manufactured in the PCB (printed circuit board) manufacturing process, as an unrestricted example. A large number of conductive via elements V10 can be formed on a single board substrate, and multiple pre-formed via-limiting structures VD10 can be manufactured by appropriately cutting the board substrate on which the large number of conductive via elements V10 are formed according to a predetermined design.

[0082] The interconnection bridge member BG10 can serve to electrically connect a first semiconductor chip (i.e., die) and a second semiconductor chip (i.e., die) to each other. The interconnection bridge member BG10 may include a base portion B10 and a wiring structure formed on the base portion B10. The wiring structure may include a first connection pad portion P10 and a second connection pad portion P20. The first connection pad portion P10 can be electrically connected to the first semiconductor chip, and the second connection pad portion P20 can be electrically connected to the second semiconductor chip. The first connection pad portion P10 and the second connection pad portion P20 can be electrically connected to each other. A single interconnection bridge member BG10 can be provided with a plurality of first connection pad portions P10 and a plurality of second connection pad portions P20. The base portion B10 may include, for example, a semiconductor substrate portion. The semiconductor substrate portion may include, for example, silicon (Si), germanium (Ge), or silicon germanium (SiGe). As a specific example, the semiconductor substrate portion may include silicon (Si). However, the specific material of the semiconductor substrate portion is not limited to those mentioned above and can vary widely. A circuit portion can be formed on the base portion B10, and the circuit portion may include first and second connection pad portions P10 and P20.

[0083] Referring to Figure 12b, a substrate material layer SL10 can be formed on the temporary substrate TS10, filling the spaces between and around multiple pre-formed via-limiting structures VD10 and interconnection bridge members BG10, thereby forming a single substrate shape together. The substrate material layer SL10 can be a material layer for forming the substrate structure while physically binding the multiple via-limiting structures VD10 and interconnection bridge members BG10 together. The substrate material layer SL10 can be formed, for example, by a molding method. The manufacturing process, including the formation of the substrate material layer SL10, can be easily carried out using a fan-out process, a type of semiconductor packaging process, as an unrestricted example. The multiple pre-formed via-limiting structures VD10, interconnection bridge members BG10, and substrate material layer SL10 can be said to constitute the interconnection module substrate M10.

[0084] Referring to Figure 12c, the temporary board (TS10 in Figure 12b) can be removed from the interconnection module board M10. The temporary board (TS10 in Figure 12b) can be separated and removed from the interconnection module board M10.

[0085] Referring to Figure 12d, the resulting product of Figure 12c can be placed upside down. If necessary, a further step of grinding at least one of the upper and lower surfaces of the interconnection module substrate M10 can be performed. This grinding can remove any residue or foreign matter from the upper or lower surface of the interconnection module substrate M10, exposing the conductive material (e.g., metal, metal compound, etc.). The grinding can also improve the flatness of the upper or lower surface of the interconnection module substrate M10. If a temporary protective material has been applied to the upper or lower surface of the interconnection module substrate M10, it can be removed. Furthermore, if necessary, a rearrangement layer (RDL) process can be further performed on the upper surface of the interconnection module substrate M10.

[0086] The result shown in Figure 12d may correspond to the interconnection module substrate M10 described with reference to Figure 1. Therefore, all the information described with reference to Figure 1 can be applied to the interconnection module substrate M10 in Figure 12d. In the interconnection module substrate M10 of Figure 12d, the first and second conductive via elements V1a and V1b may have the same spacing at their upper and lower ends.

[0087] In embodiments of the present invention, a semiconductor package interconnection module substrate M10 can be manufactured by forming a substrate material layer SL10 after manufacturing and arranging a plurality of via limiting structures VD10 and at least one interconnection bridge member BG10 to suit the requirements and purposes. According to such embodiments of the present invention, it is possible to realize a semiconductor package interconnection module substrate that is easy to manufacture and can be easily designed to suit the user's requirements and purposes. Furthermore, it is possible to manufacture in accordance with a variety of semiconductor package designs, ensure compatibility with a variety of electrode pitches, and realize a semiconductor package interconnection module substrate with excellent performance and durability.

[0088] Figures 13a to 13d are cross-sectional views illustrating a method for manufacturing an interconnection module substrate for semiconductor packages according to another embodiment of the present invention. This embodiment illustrates a method for manufacturing the interconnection module substrate M12 shown in Figure 3.

[0089] Referring to Figure 13a, multiple pre-formed via-limiting structures VD10 and at least one interconnection bridge member BG11 can be arranged horizontally, spaced apart from each other or adjacent to each other, on the temporary substrate TS10. Multiple pre-formed via-limiting structures VD10 and at least one interconnection bridge member BG11 can be attached to the upper surface of the temporary substrate TS10 in a state where they are overlapping each other vertically.

[0090] The interconnection bridge member BG11 may have the same or approximately the same thickness as the via limiting structure VD10. The interconnection bridge member BG11 may include a base portion B11 and a wiring structure formed on the base portion B11. The wiring structure may include a first connection pad portion P11 and a second connection pad portion P21. The interconnection bridge member BG11 may further include a through electrode T11. The through electrode T11 may be formed to penetrate the interconnection bridge member BG11 in the vertical direction. The through electrode T11 may be a TSV (through silicon via) or a corresponding electrode. The position of the through electrode T11 shown in Figure 13a is illustrative and may vary. One or more through electrodes T11 may be provided on a single interconnection bridge member BG11. The through electrode T11 can provide electrical connectivity between at least one semiconductor chip and an external circuit. The through electrode T11 may be formed to penetrate the base portion B11.

[0091] Referring to Figure 13b, a substrate material layer SL10 can be formed on the temporary substrate TS10, filling the spaces between and around multiple pre-formed via-limiting structures VD10 and interconnection bridge members BG11, thereby forming a single substrate shape together. The substrate material layer SL10 can be a material layer for forming the substrate structure while physically binding the multiple via-limiting structures VD10 and interconnection bridge members BG11 together. The substrate material layer SL10 can be formed, for example, by a molding method. The multiple pre-formed via-limiting structures VD10, interconnection bridge members BG11, and substrate material layer SL10 can be said to constitute the interconnection module substrate M12.

[0092] Referring to Figure 13c, the temporary board (TS10 in Figure 13b) can be removed from the interconnection module board M12. The temporary board (TS10 in Figure 13b) can be separated and removed from the interconnection module board M12.

[0093] Referring to Figure 13d, the result of Figure 13c can be placed upside down. If necessary, a further step of polishing at least one of the upper and lower surfaces of the interconnection module substrate M12 can be performed. Also, if necessary, a rearrangement layer (RDL) process can be further performed on the upper surface of the interconnection module substrate M12.

[0094] The result shown in Figure 13d can correspond to the interconnection module board M12 described with reference to Figure 3. Therefore, all the information described with reference to Figure 3 can be applied to the interconnection module board M12 in Figure 13d. If the interconnection bridge member BG11 of the interconnection module board M12 further includes through electrodes T11, the through electrodes T11 can provide the effect of improving routing density.

[0095] Although not shown in the figures, the interconnection module substrates M11 and M13 in Figures 2 and 4 can also be easily manufactured using a method similar to the manufacturing methods described in Figures 12a to 12d and 13a to 13d. This is easily understood from the above explanation. Similar to the interconnection module substrates M11 and M13 in Figures 2 and 4, if the first and second conductive via elements V1c and V1d have different spacings at their upper and lower ends, the via-limited structure including them can provide different electrode pitch characteristics at its upper and lower ends. The first and second conductive via elements V1c and V1d may have a first spacing at their upper ends and a second spacing at their lower ends that is larger than the first spacing.

[0096] Figures 14a and 14b are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package element using an interconnection module substrate for semiconductor packages according to one embodiment of the present invention.

[0097] Referring to Figure 14a, an interconnection module substrate M10 can be provided. The interconnection module substrate M10 may have a configuration such as that described in Figure 1. The interconnection module substrate M10 may include a plurality of via limiting structures VD10, at least one interconnection bridge member BG10, and a substrate material layer SL10.

[0098] Next, multiple semiconductor chips C10 can be mounted horizontally on the upper surface of the interconnection module substrate M10, spaced apart from each other or adjacent to each other. Exemplarily, three semiconductor chips C10 are shown, which can be referred to as the first, second, and third semiconductor chips C1a, C1b, and C1c.

[0099] A first electrical connection element CE10 can be placed between the interconnection module substrate M10 and the semiconductor chip C10. Multiple first electrical connection elements CE10 may be provided. The first electrical connection element CE10 may, as an unrestricted example, be a bump or a microbump. However, the specific type of the first electrical connection element CE10 is not limited to those described above and can vary. A predetermined rearrangement layer (RDL) can be formed on the upper surface of the interconnection module substrate M10.

[0100] Referring to Figure 14b, a second electrical connection element CE20 connected to a conductive via element V10 can be formed on the underside of the interconnection module substrate M10. Multiple second electrical connection elements CE20 can be provided corresponding to at least multiple conductive via elements V10. A non-limiting example of the second electrical connection element CE20 is a solder ball. The solder ball can be attached to the underside of the interconnection module substrate M10 by a predetermined adhesion process. However, the specific type of the second electrical connection element CE20 is not limited to those described above and can vary.

[0101] Figures 15a and 15b are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package element using an interconnection module substrate for semiconductor packages according to another embodiment of the present invention.

[0102] Referring to Figure 15a, an interconnection module substrate M11 can be provided. The interconnection module substrate M11 may have a configuration such as that described in Figure 2. The interconnection module substrate M11 may include a plurality of via limiting structures VD11, at least one interconnection bridge member BG10, and a substrate material layer SL10. Then, a plurality of semiconductor chips C10 can be mounted on the upper surface of the interconnection module substrate M11, spaced apart from each other or adjacent to each other in the horizontal direction. A first electrical connection element CE10 can be placed between the interconnection module substrate M11 and the semiconductor chips C10.

[0103] Referring to Figure 15b, a second electrical connection element CE20 connected to a conductive via element V11 can be formed on the lower surface of the interconnection module substrate M11. Multiple second electrical connection elements CE20 can be provided corresponding to at least multiple conductive via elements V11.

[0104] Although not shown in the figures, semiconductor package elements can be manufactured using interconnection module substrates M12 and M13 according to the embodiments in Figures 3 and 4, similar to those described in the embodiments in Figures 14a and 14b and Figures 15a and 15b.

[0105] According to the embodiments of the present invention described above, it is possible to realize an interconnection module substrate for semiconductor packages that is easy to design in a variety of ways to meet the user's requirements and purposes, and is easy to manufacture. Furthermore, according to the embodiments of the present invention, it is possible to realize an interconnection module substrate for semiconductor packages that can be manufactured in accordance with a variety of semiconductor package designs, can be made compatible with a variety of electrode pitches, and has excellent performance and durability. In particular, according to one embodiment of the present invention, by forming the interconnection module substrate using a preformed 3D via-limiting structure and interconnection bridge members, for example by a molding method, it is possible to realize a variety of designs in an easy way. By using the interconnection module substrate according to the embodiments of the present invention, semiconductor package elements with excellent performance can be easily manufactured.

[0106] While this specification uses specific terms when disclosing preferred embodiments of the present invention, these are merely general terms used to facilitate the description of the invention and aid in its understanding, and are not intended to limit the scope of the invention. It will be apparent to those ordinary skill in the art to which the invention pertains that other modifications based on the technical idea of ​​the invention are possible in addition to the embodiments disclosed herein. Those ordinary skill in the art will see that the interconnection module substrates for semiconductor packages and semiconductor package elements including them, as well as methods for manufacturing them, as described in the embodiments with reference to Figures 1 to 15b, can be substituted, modified, and transformed in various ways without departing from the technical idea of ​​the invention. Therefore, the scope of the invention is not determined by the embodiments described herein, but rather by the technical idea described in the claims. [Explanation of symbols]

[0107] B10, B11 Base Layer BG10, BG11 Interconnection Bridge Members C1a~C1c, C10 semiconductor chips CE10 First electrical connection element CE20 Second Electrical Connection Element M10~M13 Interconnection Module Board P10, P11 First connection pad section P20, P21 Second connection pad section SL10 substrate material layer T11 Through electrode TS10 temporary board U10, U11, U15~U19 Base Material Unit V10, V11, V15~V19 Conductive via elements VD10, VD11, VD15~VD19 Via-only structure

Claims

1. Interconnection module substrate for semiconductor packages, A plurality of via-limiting structures are arranged horizontally apart from each other, each including a base material unit and a conductive via element that penetrates the base material unit vertically, At least one interconnection bridge member is arranged horizontally separated from or adjacent to the plurality of via-limiting structures, An interconnection module substrate for a semiconductor package, comprising: a substrate material layer configured to fill the spaces between and around the plurality of via limiting structures and the interconnection bridge member, thereby forming a single substrate shape together, and exposing the plurality of via limiting structures and the interconnection bridge member.

2. The plurality of via limiting structures include a first via limiting structure, The first via limiting structure includes first and second conductive via elements that are spaced apart from each other. The semiconductor package interconnection module substrate according to claim 1, wherein the first and second conductive via elements have the same spacing at their upper and lower ends.

3. The plurality of via limiting structures include a first via limiting structure, The first via limiting structure includes first and second conductive via elements that are spaced apart from each other. The interconnection module substrate for semiconductor packages according to claim 1, wherein the first and second conductive via elements have a first spacing at their upper ends and a second spacing at their lower ends that is larger than the first spacing.

4. The interconnection module substrate for semiconductor packages according to claim 3, wherein at least one of the first and second conductive via elements has a refracted structure.

5. The interconnection bridge member includes a first connection pad portion electrically connected to a first semiconductor chip and a second connection pad portion electrically connected to a second semiconductor chip, as described in claim 1, an interconnection module substrate for a semiconductor package.

6. The interconnection bridge member includes a base portion and a wiring structure formed on the base portion, as described in claim 1, an interconnection module substrate for a semiconductor package.

7. The interconnection bridge member has a thickness thinner than the substrate material layer, as described in claim 1, for an interconnection module substrate for a semiconductor package.

8. The interconnection bridge member has the same thickness as or substantially the same thickness as the substrate material layer. The interconnection bridge member includes a TSV (through silicon via) or a corresponding through-electrode, as described in claim 1, for the semiconductor package interconnection module substrate.

9. The interconnection module board according to claim 1, A semiconductor package element comprising a plurality of semiconductor chips mounted horizontally spaced apart from each other or adjacent to each other on the upper surface of the interconnection module substrate.

10. The plurality of semiconductor chips include the first and second semiconductor chips, The plurality of via limiting structures include first and second via limiting structures, The at least one interconnection bridge member includes a first interconnection bridge member positioned between the first and second via limiting structures, The first semiconductor chip is connected to the conductive via element of the first via-limiting structure and the first connection pad portion of the first interconnection bridge member. The semiconductor package element according to claim 9, wherein the second semiconductor chip is connected to the conductive via element of the second via-limiting structure and the second connection pad portion of the first interconnection bridge member.

11. A first electrical connection element is placed between the interconnection module substrate and the semiconductor chip. The semiconductor package element according to claim 9, wherein a second electrical connection element connected to the conductive via element is disposed on the lower surface of the interconnection module substrate.

12. A method for manufacturing an interconnection module substrate for semiconductor packages, The steps include arranging on a temporary substrate a plurality of pre-formed via-limiting structures, each including a base material unit and conductive via elements penetrating the base material unit vertically, and at least one interconnection bridge member, spaced apart from or adjacent to each other in the horizontal direction; The steps include: filling the spaces between and around the plurality of pre-formed via-limiting structures and the interconnection bridge members on the temporary substrate to form a substrate material layer that together forms a single substrate shape; A method for manufacturing an interconnection module substrate for a semiconductor package, comprising the step of removing the temporary substrate from an interconnection module substrate comprising the plurality of pre-formed via limiting structures, the interconnection bridge members, and the substrate material layer.

13. A method for manufacturing an interconnection module substrate for a semiconductor package according to claim 12, further comprising the step of polishing at least one of the upper and lower surfaces of the interconnection module substrate.

14. The plurality of pre-formed via-restricting structures include a first via-restricting structure, the first via-restricting structure includes first and second conductive via elements spaced apart from each other. The method for manufacturing an interconnection module substrate for a semiconductor package according to claim 12, wherein the first and second conductive via elements have the same spacing at their upper and lower ends.

15. The plurality of pre-formed via-restricting structures include a first via-restricting structure, the first via-restricting structure includes first and second conductive via elements spaced apart from each other. The method for manufacturing an interconnection module substrate for a semiconductor package according to claim 12, wherein the first and second conductive via elements have a first spacing at their upper ends and a second spacing at their lower ends that is larger than the first spacing.

16. A method for manufacturing an interconnection module substrate for a semiconductor package according to claim 15, wherein at least one of the first and second conductive via elements has a refracted structure.

17. The method for manufacturing an interconnection module substrate for a semiconductor package according to claim 12, wherein the interconnection bridge member has a thickness thinner than the substrate material layer.

18. The interconnection bridge member has the same thickness as or substantially the same thickness as the substrate material layer. The method for manufacturing an interconnection module substrate for a semiconductor package according to claim 12, wherein the interconnection bridge member includes a TSV (through silicon via) or a corresponding through-electrode.

19. A step of providing an interconnection module board using the method of claim 12, A method for manufacturing a semiconductor package element, comprising the step of mounting a plurality of semiconductor chips on the upper surface of the interconnection module substrate, spaced apart from each other or adjacent to each other in the horizontal direction.

20. The method for manufacturing a semiconductor package element according to claim 19, further comprising the step of forming an electrical connection element connected to the conductive via element on the lower surface of the interconnection module substrate.

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