Semiconductor packages

Abstract

We provide semiconductor packages that can increase the available free space within electronic products. [Solution] The semiconductor package according to the present invention includes a first redistribution structure, a first chiplet on the first redistribution structure, a second chiplet on the first redistribution structure, adjacent to the first chiplet in a horizontal direction parallel to the surface of the first redistribution structure, a second redistribution structure on the first chiplet and the second chiplet, and a communication chip on the second redistribution structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same.

Background Art

[0002] Semiconductor technology has been developed and used to manufacture an application processor (AP) by dividing it into chiplets according to the application or the process to be applied. If the application processor is manufactured by dividing it into chiplets, chiplets that do not require the use of the latest process can apply an inexpensive old process, so the manufacturing cost can be reduced. If a defect occurs in a chiplet to which the old process is applied, only the chiplet to which the old process is applied can be discarded, so the yield of the application processor can be improved. In addition, if the application processor is manufactured by dividing it into chiplets and the separately manufactured chiplets are made to operate together, the performance limit of a conventional single application processor can be overcome.

[0003] However, when the application processor is divided into chiplets, there is a problem that the space occupied by the application processor formed on the chiplet in the semiconductor package becomes larger than when a single application processor is adopted. Accordingly, conventionally, a communication chip package was formed separately from the semiconductor package, and the semiconductor package including the chiplet and the communication chip package were both mounted in an electronic product.

[0004] However, recently, due to the development of mobile devices, the demand for small-sized electronic products with a large battery capacity has been increasing. Therefore, in order to reduce the board size in an electronic product and secure space that can be occupied by a large-capacity battery, it is required to reduce the area occupied by the communication chip package in the electronic product.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the problems of the prior art described above, and the object of the present invention is to provide a semiconductor package in which the application processor is divided into a first chiplet and a second chiplet and mounted in a lower package of a package on package (PoP), thereby reducing the space occupied within an electronic product.

[0006] Furthermore, an object of the present invention is to provide a semiconductor package in which a communication chip is mounted on a package-on-package (PoP) top package, thereby increasing the available free space within the electronic product. [Means for solving the problem]

[0007] A semiconductor package according to one aspect of the present invention made to achieve the above objective may include a first redistribution structure, a first chiplet on the first redistribution structure, a second chiplet positioned on the first redistribution structure next to the first chiplet, a second redistribution structure on the first chiplet and the second chiplet, and a communication chip on the second redistribution structure.

[0008] To achieve the above objectives, a semiconductor package according to another aspect of the present invention may include a first redistribution structure, a plurality of chiplets on a first surface of the first redistribution structure, a plurality of connecting members arranged around the plurality of chiplets on the first surface of the first redistribution structure, a second redistribution structure on the plurality of chiplets and the plurality of connecting members, a communication chip on the second redistribution structure, and a plurality of memory structures arranged around the communication chip on the second redistribution structure.

[0009] To achieve the above objectives, a semiconductor package according to yet another aspect of the present invention may include a front redistribution structure, a first logic chiplet on the front redistribution structure, a second logic chiplet positioned next to the first logic chiplet on the front redistribution structure, a plurality of connecting members positioned next to the first logic chiplet on the front redistribution structure, a first molding material covering the first logic chiplet, the second logic chiplet, and the plurality of connecting members on the front redistribution structure, a rear redistribution structure on the first molding material, a memory structure on the rear redistribution structure, and a communication chip positioned next to the memory structure on the rear redistribution structure. [Effects of the Invention]

[0010] According to the present invention, since the communication chip is mounted on the upper package of a package-on-package (PoP) that includes an application processor divided into a first chiplet and a second chiplet, it is not necessary to form a separate communication chip package, and the space in the electronic product that would have been occupied by another communication chip package can be reduced.

[0011] Furthermore, by positioning the communication chip directly above the first and second chiplets, the heat generated from the first and second chiplets is efficiently dissipated to the outside via the communication chip. [Brief explanation of the drawing]

[0012] [Figure 1] This is a cross-sectional view showing a semiconductor package according to one embodiment. [Figure 2] This is a cross-sectional view showing a semiconductor package according to one embodiment. [Figure 3] This is a cross-sectional view showing a semiconductor package according to one embodiment. [Figure 4] Figures 1, 2, and 3 are plan views showing the top surface of a semiconductor package according to one embodiment. [Figure 5]This is a cross-sectional view showing a semiconductor package according to one embodiment. [Figure 6] Figure 5 is a plan view showing the top surface of a semiconductor package according to one embodiment. [Figure 7] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 8] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 9] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 10] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 11] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 12] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 13] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 14] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 15] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Figure 16] Figure 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to one embodiment. [Modes for carrying out the invention]

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, so that they can be easily implemented by a person with ordinary skill in the art to which the present invention pertains. The present invention can be embodied in a variety of different forms and is not limited to the embodiments described herein.

[0014] In the drawings, for the purpose of clearly explaining the present invention, parts not related to the explanation are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0015] In addition, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings.

[0016] Throughout the specification, when a part is "connected" to another part, this includes not only the case where it is "directly connected", but also the case where it is "indirectly connected" with other members interposed therebetween. Also, when a part "includes" a certain component, this does not exclude other components unless otherwise stated to the contrary, but means that it further includes other components.

[0017] Also, when a part such as a layer, film, region, plate, etc. is "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there are other parts in between. Conversely, when a part is "directly above" another part, it means that there are no other parts in between. Also, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being "above" in the direction opposite to gravity.

[0018] Also, throughout the specification, when it is said "on a plane", this means the case when the target part is viewed from above, and when it is said "in a cross section", this means the case when the cross section obtained by vertically cutting the target part is viewed from the side.

[0019] Hereinafter, referring to the drawings, a semiconductor package 100; 100A, 100B, 100C, and 100D according to an embodiment, and a manufacturing method therefor will be described.

[0020] FIG. 1 is a cross-sectional view showing a semiconductor package 100A according to an embodiment.

[0021] Referring to Figure 1, the semiconductor package 100A includes an external connection structure 110, a front redistribution structure (first redistribution structure; 120), a first chiplet 130, a second chiplet 140, a third connection member 150, a first molding material 160, a back redistribution structure (second redistribution structure; 170), a communication chip 180, a memory structure 190, and a second molding material 161. In one embodiment, the semiconductor package 100A includes a package-on-package (PoP). In one embodiment, the semiconductor package 100A is manufactured based on fan-out wafer-level package (FOWLP) or fan-out panel-level package (FOPLP) technology.

[0022] The external connection structure 110 is positioned on the lower surface (second surface) of the front redistribution structure 120. The external connection structure 110 includes conductive pads 111 and external connection members 112. Each conductive pad 111 electrically connects each of the first redistribution vias 122 of the front redistribution structure 120 to each of the external connection members 112. The external connection members 112 electrically connect the semiconductor package 100A to an external device (not shown).

[0023] The front redistribution structure 120 is positioned on the external connection structure 110. The front redistribution structure 120 includes a first dielectric 121, a first redistribution via 122 located within the first dielectric 121, a first redistribution line 123, a second redistribution via 124, a second redistribution line 125, a third redistribution via 126, and a first bonding pad 127 and a second bonding pad 128 on the first dielectric 121. In other embodiments, the front redistribution structure 120 including fewer or more redistribution lines, redistribution vias, and bonding pads is also within the scope of the present invention.

[0024] The first dielectric 121 protects and insulates the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, the second redistribution line 125, and the third redistribution via 126. The first chiplet 130, the second chiplet 140, the third connecting member 150, and the first molding material 160 are arranged on the upper surface of the first dielectric 121. The external connecting structure 110 is arranged on the lower surface of the first dielectric 121.

[0025] The first rewiring via 122, the first rewiring line 123, the second rewiring via 124, the second rewiring line 125, and the third rewiring via 126 are arranged sequentially from bottom to top, forming signal, ground, and power routing paths. Each of the first bonding pads 127 is positioned between each of the third rewiring vias 126 and each of the first connecting members 132, or between each of the third rewiring vias 126 and each of the second connecting members 142. Each of the first bonding pads 127 electrically connects each of the first connecting members 132 to each of the third rewiring vias 126, or each of the second connecting members 142 to each of the third rewiring vias 126, in a vertical direction perpendicular to the surface of the front rewiring structure 120 (e.g., the lower surface). Each of the second bonding pads 128 is positioned between each of the third rewiring vias 126 and each of the third connecting members 150. Each of the second bonding pads 128 electrically connects each of the third connecting members 150 in the vertical direction to each of the third rewiring vias 126. The horizontal diameter of each of the second bonding pads 128 parallel to the surface of the front rewiring structure 120 is greater than the horizontal diameter of each of the first bonding pads 127.

[0026] The first chiplet (first logic chiplet or first application processor) 130 and the second chiplet (second logic chiplet or second application processor) 140 are arranged on the upper surface (also called the first surface; the first surface is the opposite surface to the second surface) of the front rewiring structure 120. The first chiplet 130 is arranged next to the second chiplet 140. The first chiplet 130 and the second chiplet 140 are arranged side by side next to the third connecting member 150. In one embodiment, the first chiplet 130 and the second chiplet 140 may each include an application processor AP.

[0027] A chiplet is generally defined as a small, modular chip that performs a specific function. Chiplets are designed to combine with other chiplets, which are linked via a standardized, high-speed digital interface, to form a complete system-on-a-chip. A system-on-a-chip (SoC), such as an application processor, is divided into multiple chiplets. Multiple chiplets are manufactured separately using different process technologies, and multiple chiplets manufactured using separate processes function as a single application processor. Each chiplet is a core that is independently designed and configured to communicate with other chiplets via one or more common interfaces. In one embodiment, each of the multiple chiplets includes at least one of the following: global logic, interfaces, dispatch circuits, fabric circuits, logic, input / output (I / O) circuits, and memory. In one embodiment, the global logic includes at least one of the following: scheduler logic and power management logic. In one embodiment, the logic includes at least one of the following: a central processing unit (CPU), a graphics processing unit (GPU), and a codec. In one embodiment, the memory includes SRAM. In one embodiment, the first chiplet 130 may include at least one of global logic, interface, dispatch, fabric, and SRAM. In one embodiment, the second chiplet 140 may include at least one of logic, I / O, and memory.

[0028] The first chiplet 130 and the second chiplet 140 are electrically connected via a front rewiring structure 120, which routes electrical signals between them. In one embodiment, the signal of the first chiplet 130 is transmitted to the second chiplet 140 via a first signal path that passes through a first connection pad 131, a first connection member 132, a first bonding pad 127 connected to the first connection member 132, a third rewiring via 126, a second rewiring line 125, a third rewiring via 126, a first bonding pad 127 connected to the second connection member 142, a second connection member 142, and a second connection pad 141. The signal of the second chiplet 140 is transmitted to the first chiplet 130 via a second signal path that passes through the first signal path in the reverse direction.

[0029] Although the present invention has been described with reference to the first chiplet 130 and the second chiplet 140, it is not limited thereto, and a greater number of chiplets are included in the scope of the present invention, and one embodiment of the first chiplet 130 and the second chiplet 140 can be applied to a greater number of chiplets.

[0030] Each of the first connection pads 131 is positioned between each of the wirings of the first chiplet 130 and each of the first connection members 132. Each of the first connection pads 131 electrically connects each of the wirings of the first chiplet 130 to each of the first connection members 132. Each of the second connection pads 141 is positioned between each of the wirings of the second chiplet 140 and each of the second connection members 142. Each of the second connection pads 141 electrically connects each of the wirings of the second chiplet 140 to each of the second connection members 142. In one embodiment, the first connection pads 131 and the second connection pads 141 include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0031] Each of the first connecting members 132 is positioned between each of the first connecting pads 131 and each of the first bonding pads 127. Each of the first connecting members 132 electrically connects each of the first connecting pads 131 to each of the first bonding pads 127. Each of the second connecting members 142 is positioned between each of the second connecting pads 141 and each of the first bonding pads 127. Each of the second connecting members 142 electrically connects each of the second connecting pads 141 to each of the first bonding pads 127. In one embodiment, the first connecting members 132 and the second connecting members 142 include solder bumps. In one embodiment, the first connecting members 132 and the second connecting members 142 include at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0032] The third connecting member 150 is positioned on the upper surface (first surface) of the front rewiring structure 120. The third connecting member 150 is positioned next to the first chiplet 130 and the second chiplet 140. Each of the third connecting members 150 is positioned between each of the second bonding pads 128 of the front rewiring structure 120 and each of the fourth rewiring vias 172 of the rear rewiring structure 170. Each of the third connecting members 150 electrically connects each of the fourth rewiring vias 172 of the rear rewiring structure 170 to each of the second bonding pads 128 of the front rewiring structure 120. The third connecting member 150 is positioned through the first molding material 160. The sides of the third connecting member 150 are enclosed by the first molding material 160. In one embodiment, the third connecting member 150 includes a conductive post.

[0033] The first molding material 160 covers the first chiplet 130, the second chiplet 140, and the third connecting member 150 on the upper surface (first surface) of the front rewiring structure 120. The first molding material 160 protects the first chiplet 130, the second chiplet 140, and the third connecting member 150 from the external environment, thereby ensuring the electrical or mechanical stability of the semiconductor package 100.

[0034] The rear redistribution structure 170 is positioned on the first chiplet 130, the second chiplet 140, the third connecting member 150, and the first molding material 160. The rear redistribution structure 170 includes the second dielectric 171, the fourth redistribution via 172 located within the second dielectric 171, the third redistribution line 173, the fifth redistribution via 174, the fourth redistribution line 175, the sixth redistribution via 176, and the third bonding pad 177 on the second dielectric 171. In other embodiments, the rear redistribution structure 170 including fewer or more redistribution lines, redistribution vias, and bonding pads is also within the scope of the present invention.

[0035] The second dielectric 171 protects and insulates the fourth redistribution via 172, the third redistribution line 173, the fifth redistribution via 174, the fourth redistribution line 175, and the sixth redistribution via 176. The communication chip 180, the memory structure 190, the first underfill member 183, the second underfill member 193, and the second molding material 161 are arranged on the upper surface of the second dielectric 171. The third connecting member 150 and the first molding material 160 are arranged on the lower surface of the second dielectric 171.

[0036] The fourth rewiring via 172, the third rewiring line 173, the fifth rewiring via 174, the fourth rewiring line 175, and the sixth rewiring via 176 are arranged sequentially from the bottom (facing the front rewiring structure 120) to form signal, ground, and power routing paths. Each of the third bonding pads 177 is positioned between each of the sixth rewiring vias 176 and each of the fourth connecting members 182, or between each of the sixth rewiring vias 176 and each of the fifth connecting members 192. Each of the third bonding pads 177 electrically connects each of the fourth connecting members 182 in the vertical direction to each of the sixth rewiring vias 176, or each of the fifth connecting members 192 to each of the sixth rewiring vias 176.

[0037] The communication chip 180 is positioned on the rear rewiring structure 170. The communication chip 180 is positioned horizontally next to the memory structure 190. The communication chip 180 is electrically connected to the first chiplet 130 and the second chiplet 140 via the front rewiring structure 120, the third connecting member 150, and the rear rewiring structure 170. The communication chip 180 enables wireless communication for transmitting data to and from the first chiplet 130 and the second chiplet 140. The communication chip 180 communicates with various types of external devices using various communication methods and / or protocols. In one embodiment, the communication chip 180 communicates using various communication standards such as Wi-Fi®, Bluetooth®, Near-Field Communication (NFC), IEEE, Zigbee®, 3G (3rd Generation), 3GPP® (3rd Generation Partnership Project), LTE® (Long Term Evolution), and 5G (3rd Generation).

[0038] The third connection pads 181 are positioned on the lower surface of the communication chip 180. Each of the third connection pads 181 is positioned between each of the wirings of the communication chip 180 and each of the fourth connection members 182. Each of the third connection pads 181 electrically connects each of the wirings of the communication chip 180 to each of the fourth connection members 182. In one embodiment, the third connection pads 181 include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0039] Each of the fourth connecting members 182 is positioned between each of the third connecting pads 181 and each of the third bonding pads 177. Each of the fourth connecting members 182 electrically connects each of the third connecting pads 181 to each of the third bonding pads 177. In one embodiment, the fourth connecting member 182 includes a solder bump. In one embodiment, the fourth connecting member 182 includes at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0040] The first underfill member 183 is positioned between the rear rewiring structure 170 and the communication chip 180. The first underfill member 183 surrounds and protects the third bonding pad 177, the third connection pad 181, and the fourth connection member 182. In one embodiment, the first underfill member 183 includes a non-conductive film (NCF). In one embodiment, the first underfill member 183 includes a MUF (Moled Underfill).

[0041] The memory structure 190 is located on the rear rewiring structure 170. The memory structure 190 is located horizontally next to the communication chip 180. The memory structure 190 is electrically connected to the first chiplet 130 and the second chiplet 140 via the front rewiring structure 120, the third connecting member 150, and the rear rewiring structure 170. In one embodiment, the memory structure 190 may include a single chip such as DRAM or a multi-chip such as High Bandwidth Memory (HBM). The memory structure 190 may include memory banks.

[0042] The fourth connection pads 191 are positioned on the lower surface of the memory structure 190. Each of the fourth connection pads 191 is positioned between each of the wirings of the memory structure 190 and each of the fifth connection members 192. Each of the fourth connection pads 191 electrically connects each of the wirings of the memory structure 190 to each of the fifth connection members 192. In one embodiment, the fourth connection pads 191 include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0043] Each of the fifth connecting members 192 is positioned between each of the fourth connecting pads 191 and each of the third bonding pads 177. Each of the fifth connecting members 192 electrically connects each of the fourth connecting pads 191 to each of the third bonding pads 177. In one embodiment, the fifth connecting member 192 includes a solder bump. In one embodiment, the fifth connecting member 192 includes at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0044] The second underfill member 193 is positioned between the rear rewiring structure 170 and the memory structure 190. The second underfill member 193 surrounds and protects the third bonding pad 177, the fourth connection pad 191, and the fifth connection member 192. In one embodiment, the second underfill member 193 includes a non-conductive film NCF. In one embodiment, the second underfill member 193 may include an MUF.

[0045] The second molding material 161 covers the communication chip 180 and the memory structure 190 on the rear redistribution structure 170. The upper surfaces of the communication chip 180 and the memory structure 190 are exposed from the second molding material 161 and are at the same level as the upper surface of the second molding material 161. That is, the upper surfaces of the communication chip 180 and the memory structure 190 are in the same plane as the upper surface of the second molding material 161 in the vertical direction. The second molding material 161 protects the communication chip 180 and the memory structure 190 from the external environment, thereby ensuring the electrical or mechanical stability of the semiconductor package 100.

[0046] According to the present invention, in a semiconductor package 100A including an application processor divided into a plurality of chiplets (first chiplet 130 and second chiplet 140), the communication chip 180 is positioned on top of the plurality of chiplets. This eliminates the need to separately form a communication chip package within the electronic product, thereby reducing the space within the electronic product that would otherwise be occupied by the communication chip package.

[0047] Figure 2 is a cross-sectional view showing a semiconductor package 100B according to one embodiment.

[0048] Referring to Figure 2, the semiconductor package 100B includes a bridge die 210. The bridge die 210 is located on the second surface of the front redistribution structure 120. The bridge die 210 is located horizontally next to the external connection members 112 (for example, between adjacent external connection members 112). The bridge die 210 electrically connects the first chiplet 130 to the second chiplet 140 via the front redistribution structure 120. The first chiplet 130 and the second chiplet 140 are electrically connected to each other via the front redistribution structure 120 and via the bridge die 210, routing electrical signals between them. In one embodiment, the bridge die 210 may include a silicon bridge die.

[0049] The bridge die 210 includes a bridge die base 211, connection pads 212, and signal lines 213. The bridge die base 211 is a die formed from a wafer. In one embodiment, the bridge die base 211 includes silicon or other semiconductor material. The bridge die base 211 includes connection pads 212 and signal lines 213 inside. Each of the connection pads 212 is positioned between each of the signal lines 213 and each of the sixth connection members 214. Each of the connection pads 212 electrically connects each of the signal lines 213 to each of the sixth connection members 214. Each of the signal lines 213 is connected to a connection pad 212 and transmits signals between the first chiplet 130 and the second chiplet 140. In one embodiment, the connection pads 212 and signal lines 213 include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0050] The bridge die 210 is connected to the front rewiring structure 120 via fourth bonding pads 113 and sixth connecting members 214. The fourth bonding pads 113 are located on the lower surface (second surface) of the front rewiring structure 120. Each of the fourth bonding pads 113 is positioned between each of the sixth connecting members 214 and each of the first rewiring vias 122. Each of the fourth bonding pads 113 electrically connects each of the first rewiring vias 122 to each of the sixth connecting members 214. In one embodiment, the fourth bonding pads 113 include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0051] Each of the sixth connecting members 214 is positioned between each of the connecting pads 212 and each of the fourth bonding pads 113. Each of the sixth connecting members 214 electrically connects each of the fourth bonding pads 113 to each of the connecting pads 212. In one embodiment, the sixth connecting member 214 includes a solder bump. In one embodiment, the sixth connecting member 214 includes at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0052] Except for the explanation of semiconductor package 100B according to one embodiment in Figure 2, the explanation of semiconductor package 100A in Figure 1 applies.

[0053] Figure 3 is a cross-sectional view showing a semiconductor package 100C according to one embodiment.

[0054] Referring to Figure 3, the semiconductor package 100C includes an adhesive member 221 and a heat dissipation structure 222.

[0055] The adhesive member 221 is placed between the communication chip 180 and the heat dissipation structure 222, between the memory structure 190 and the heat dissipation structure 222, and between the second molding material 161 and the heat dissipation structure 222. The adhesive member 221 adheres the heat dissipation structure 222 to the communication chip 180, the memory structure 190, and the second molding material 161. In one embodiment, the adhesive member 221 includes a thermal interface material (TIM). The thermal interface material TIM is inserted between the heat-generating communication chip 180 and the memory structure 190 and the heat dissipation structure 222, which releases heat to the outside, improving the thermal coupling between the communication chip 180 and the heat dissipation structure 222, and between the memory structure 190 and the heat dissipation structure 222. The thermal interface material (TIM) plays a role in reducing thermal contact resistance by filling the air layer at the contact surfaces between the communication chip 180 and the heat dissipation structure 222, and between the memory structure 190 and the heat dissipation structure 222.

[0056] The heat dissipation structure 222 is placed on the second molding material 161, the communication chip 180, and the memory structure 190. The heat dissipation structure 222 is attached to the second molding material 161, the communication chip 180, and the memory structure 190 by an adhesive member 221. The heat dissipation structure 222 is thermally connected to the communication chip 180 and the memory structure 190. In one embodiment, the heat dissipation structure 222 includes a heat slag, a heat sink, or a heat spreader. In one embodiment, the heat dissipation structure 222 includes a conductive material having high thermal conductivity, such as copper or aluminum.

[0057] Except for the explanation regarding semiconductor package 100C in one embodiment shown in Figure 3, the explanation regarding semiconductor package 100A in Figure 1 applies.

[0058] Figure 4 is a plan view showing the top surfaces of semiconductor packages 100A, 100B, and 100C according to one embodiment of Figures 1, 2, and 3. In Figure 4, the communication chip 180 and the memory structure 190 are shown with solid lines, while the first chiplet 130, the second chiplet 140, and the third connecting member 150 are shown with dashed lines.

[0059] Referring to Figure 4, the first chiplet 130 and the second chiplet 140 are arranged side by side horizontally. The third connecting member 150 is positioned next to the first chiplet 130 and next to the second chiplet 140. The communication chip 180 and the memory structure 190 are arranged side by side.

[0060] The footprint of the communication chip 180 overlaps with the footprints of the first chiplet 130 and the second chiplet 140 in the vertical direction. The heat generated from the first chiplet 130 and the second chiplet 140 forms a hot spot between them, and the communication chip 180 is positioned on this hot spot. As a result, the heat generated from the first chiplet 130 and the second chiplet 140 is efficiently dissipated to the outside through the communication chip 180, which is made from silicon material. The footprint of the communication chip 180 does not overlap with the footprint of the third connector member 150. The footprint of the memory structure 190 overlaps with the footprint of the third connector member 150.

[0061] Figure 5 is a cross-sectional view showing a semiconductor package 100D according to one embodiment. Figure 6 is a plan view showing the top surface of the semiconductor package 100D according to one embodiment of Figure 5. In Figure 6, the communication chip 180 and the memory structure 190 are shown by solid lines, and the first chiplet 130, the second chiplet 140, and the third connecting member 150 are shown by dashed lines.

[0062] Referring to Figures 5 and 6, the semiconductor package 100D has a horizontally symmetrical structure. The semiconductor package 100D includes a third connecting member 150 arranged around a first chiplet 130 and a second chiplet 140. The semiconductor package 100D includes a memory structure 190 arranged around a communication chip 180. Each of the first chiplet 130 and the second chiplet 140 is electrically connected to each of the memory structures 190 via an adjacent third connecting member 150.

[0063] The footprint of the communication chip 180 overlaps with the footprints of the first chiplet 130 and the second chiplet 140. The heat generated from the first chiplet 130 and the second chiplet 140 forms a hot spot between them, and the communication chip 180 is positioned on this hot spot. As a result, the heat generated from the first chiplet 130 and the second chiplet 140 is efficiently dissipated to the outside through the communication chip 180, which is made from silicon material. The footprint of the communication chip 180 does not overlap with the footprint of the third connector member 150. The footprints of each component of the memory structure 190 overlap with the footprint of the third connector member 150.

[0064] Figures 7 to 16 are cross-sectional views illustrating a method for manufacturing semiconductor package 100A according to one embodiment of Figure 1. The method for manufacturing semiconductor package 100A according to one embodiment of Figure 1 is applicable to the methods for manufacturing semiconductor packages 100B, 100C, and 100D according to one embodiment of Figures 2, 3, and 5.

[0065] Figure 7 is a cross-sectional view showing the steps of forming the front rewiring structure 120 on the carrier C.

[0066] Referring to Figure 7, a front rewiring structure 120 is formed on the carrier C. First, the carrier C is provided. In one embodiment, the carrier C includes a silicon-based material such as glass or silicon oxide, an organic material, another material such as aluminum oxide, or any combination of these materials.

[0067] Subsequently, a first dielectric 121 is deposited on the carrier C. In one embodiment, the first dielectric 121 includes a photoimageable dielectric (PID) used in the redistribution process. In one embodiment, the photoimageable dielectric PID includes a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, a polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In one embodiment, the first dielectric 121 is formed by a spin coating process.

[0068] After forming the first dielectric 121, the first dielectric 121 is selectively etched to form via holes, and conductive material is used to fill the via holes to form the first redistribution via 122. After forming the first redistribution via 122, the first dielectric 121 is additionally formed on the first redistribution via 122 and the first dielectric 121, the additionally formed first dielectric 121 is selectively etched to form openings, and conductive material is used to fill the openings to form the first redistribution line 123. After forming the first redistribution line 123, the first dielectric 121 is additionally formed on the first redistribution line 123 and the first dielectric 121, the additionally formed first dielectric 121 is selectively etched to form via holes, and conductive material is used to fill the via holes to form the second redistribution via 124. After forming the second redistribution via 124, the first dielectric 121 is further formed on the second redistribution via 124 and the first dielectric 121, the further formed first dielectric 121 is selectively etched to form an opening, and a conductive material is filled into the opening to form the second redistribution line 125. After forming the second redistribution line 125, the first dielectric 121 is further formed on the second redistribution line 125 and the first dielectric 121, the further formed first dielectric 121 is selectively etched to form a via hole, and a conductive material is filled into the via hole to form the third redistribution via 126. After forming the third redistribution via 126, a photoresist is further deposited on the third redistribution via 126 and the first dielectric 121, the photoresist is selectively exposed and developed to form a photoresist pattern including via holes, and a conductive material is filled into the via holes to form the first bonding pad 127 and the second bonding pad 128.

[0069] In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, the second redistribution line 125, the third redistribution via 126, the first bonding pad 127, and the second bonding pad 128 each contain at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, the second redistribution line 125, the third redistribution via 126, the first bonding pad 127, and the second bonding pad 128 are each formed by a sputtering process. In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, the second redistribution line 125, the third redistribution via 126, the first bonding pad 127, and the second bonding pad 128 are each formed by performing an electroplating process after forming a seed metal layer.

[0070] Figure 8 is a cross-sectional view showing the step of forming the third connecting member 150 on the front rewiring structure 120.

[0071] Referring to Figure 8, a third connecting member 150 is formed on the second bonding pad 128 of the front rewiring structure 120. The third connecting member 150 is formed by depositing a photoresist, selectively exposing and developing the photoresist to form a photoresist pattern including holes, and filling the holes with a conductive material. In one embodiment, the third connecting member 150 is formed by a sputtering process. In one embodiment, the third connecting member 150 is formed by forming a seed metal layer followed by an electroplating process. In one embodiment, the third connecting member 150 includes at least one of copper, aluminum, tungsten, nickel, gold, silver, chromium, antimony, tin, titanium, and alloys thereof.

[0072] Figure 9 is a cross-sectional view showing the stage of mounting the first chiplet 130 and the second chiplet 140 on the front rewiring structure 120.

[0073] Referring to Figure 9, the first chiplet 130 and the second chiplet 140 are mounted on the first bonding pad 127 of the front redistribution structure 120. In one embodiment, the first chiplet 130 and the second chiplet 140 are bonded to the first bonding pad 127 of the front redistribution structure 120 by a flip-chip bonding process. The first chiplet 130 is bonded to the first bonding pad 127 of the front redistribution structure 120 by a first connecting member 132, and the second chiplet 140 is bonded to the first bonding pad 127 of the front redistribution structure 120 by a second connecting member 142, thereby electrically connecting the first chiplet 130 and the front redistribution structure 120 via the first connecting pad 131 of the first chiplet 130, and the second chiplet 140 and the front redistribution structure 120 via the second connecting pad 141 of the second chiplet 140.

[0074] Figure 10 is a cross-sectional view showing the process of molding the first chiplet 130, the second chiplet 140, and the third connecting member 150 on the front rewiring structure 120.

[0075] Referring to Figure 10, the first chiplet 130, the second chiplet 140, and the third connecting member 150 are covered by the first molding material 160 on the front rewiring structure 120. In one embodiment, the molding process with the first molding material 160 includes a compression molding or transfer molding process. In one embodiment, the first molding material 160 includes an epoxy molding compound (EMC).

[0076] Figure 11 is a cross-sectional view showing the stage in which the first molding material 160 undergoes a chemical mechanical planarization (CMP) process.

[0077] Referring to Figure 11, a chemical mechanical planarization (CMP) process is performed to level the upper surface of the first molding material 160, thereby flattening the upper surface of the first molding material 160. After the chemical mechanical planarization (CMP) process, the upper surface of the third connecting member 150 is exposed.

[0078] Figure 12 is a cross-sectional view showing the steps of forming the rear rewiring structure 170 on the third connecting member 150 and the first molding material 160.

[0079] Referring to Figure 12, a second dielectric film 171 is formed on the third connecting member 150 and the first molding material 160. In one embodiment, the second dielectric film 171 includes a photosensitive dielectric PID used in the rewiring process. In one embodiment, the photosensitive dielectric PID includes a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, a polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In one embodiment, the second dielectric film 171 is formed by a spin coating process.

[0080] After forming the second dielectric 171, the second dielectric 171 is selectively etched to form via holes, and conductive material is used to fill the via holes to form the fourth redistribution via 172. After forming the fourth redistribution via 172, the second dielectric 171 is additionally formed on the fourth redistribution via 172 and the second dielectric 171, the additionally formed second dielectric 171 is selectively etched to form openings, and conductive material is used to fill the openings to form the third redistribution line 173. After forming the third redistribution line 173, the second dielectric 171 is additionally formed on the third redistribution line 173 and the second dielectric 171, the additionally formed second dielectric 171 is selectively etched to form via holes, and conductive material is used to fill the via holes to form the fifth redistribution via 174. After forming the fifth redistribution via 174, the second dielectric 171 is further formed on the fifth redistribution via 174 and the second dielectric 171, the further formed second dielectric 171 is selectively etched to form an opening, and the opening is filled with a conductive material to form the fourth redistribution line 175. After forming the fourth redistribution line 175, the second dielectric 171 is further formed on the fourth redistribution line 175 and the second dielectric 171, the further formed second dielectric 171 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form the sixth redistribution via 176. After forming the sixth redistribution via 176, photoresist is further deposited on the sixth redistribution via 176 and the second dielectric 171, the photoresist is selectively exposed and developed to form a photoresist pattern including via holes, and the via hole is filled with a conductive material to form the third bonding pad 177.

[0081] In one embodiment, the fourth redistribution via 172, the third redistribution line 173, the fifth redistribution via 174, the fourth redistribution line 175, the sixth redistribution via 176, and the third bonding pads 177 each contain at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the fourth redistribution via 172, the third redistribution line 173, the fifth redistribution via 174, the fourth redistribution line 175, the sixth redistribution via 176, and the third bonding pad 177 are each formed by a sputtering process. In one embodiment, the fourth redistribution via 172, the third redistribution line 173, the fifth redistribution via 174, the fourth redistribution line 175, the sixth redistribution via 176, and the third bonding pad 177 are each formed by an electroplating process after forming a seed metal layer.

[0082] Figure 13 is a cross-sectional view showing the stage in which the communication chip 180 and the memory structure 190 are mounted (attached) onto the rear rewiring structure 170.

[0083] Referring to Figure 13, the communication chip 180 and the memory structure 190 are mounted (attached) on the rear rewiring structure 170. A thermocompression bonding process is performed on the communication chip 180 to which the first underfill member 183 is attached and the memory structure 190 to which the second underfill member 193 is attached, and the communication chip 180 and the memory structure 190 are bonded onto the third bonding pad 177 of the rear rewiring structure 170. The communication chip 180 is bonded to the third bonding pad 177 of the rear rewiring structure 170 by the fourth connecting member 182, and the memory structure 190 is bonded to the third bonding pad 177 of the rear rewiring structure 170 by the fifth connecting member 192, thereby electrically connecting the communication chip 180 and the rear rewiring structure 170 via the third connecting pad 181 of the communication chip 180, and the memory structure 190 and the rear rewiring structure 170 via the fourth connecting pad 191 of the memory structure 190.

[0084] Figure 14 is a cross-sectional view showing the process of molding the communication chip 180 and the memory structure 190 on the rear rewiring structure 170.

[0085] Referring to Figure 14, the communication chip 180 and the memory structure 190 are covered by a second molding material 161 on the rear rewiring structure 170. In one embodiment, the molding process with the second molding material 161 includes a compression molding or transfer molding process. In one embodiment, the second molding material 161 includes an epoxy molding compound EMC.

[0086] Figure 15 is a cross-sectional view showing the stage in which the second molding material 161 undergoes a chemical mechanical planarization (CMP) process.

[0087] Referring to Figure 15, a chemical mechanical planarization (CMP) process is performed to level the upper surface of the second molding material 161, thereby flattening the upper surface of the second molding material 161. After the chemical mechanical planarization (CMP) process, the upper surfaces of the communication chip 180 and the memory structure 190 are exposed.

[0088] Figure 16 is a cross-sectional view showing the step of removing carrier C from the front rewiring structure 120.

[0089] Referring to Figure 16, carrier C is removed from the lower surface of the front rewiring structure 120. Then, as shown in Figure 1, an external connection structure 110 is formed on the lower surface of the front rewiring structure 120. A conductive pad 111 is formed below the first rewiring via 122 of the front rewiring structure 120. In one embodiment, the conductive pad 111 includes at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. In one embodiment, the conductive pad 111 is formed by a sputtering process or by an electroplating process after forming a seed metal layer. Then, an external connection member 112 is formed below the conductive pad 111. In one embodiment, the external connection member 112 includes at least one of tin, silver, lead, nickel, copper, and alloys thereof.

[0090] Although preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and can be implemented in various ways within the scope of the detailed description and drawings of the invention, and these also naturally fall within the scope of the present invention. [Explanation of symbols]

[0091] 100, 100A, 100B, 100C, 100D semiconductor packages 110 External connection structure 111 Conductive pad 112 External connection member 113. Fourth bonding pad 120 Front rewiring structure 121 First Dielectric 122 First Rewiring Via 123 First rewiring line 124 Second rewiring via 125 Second rewiring line 126 Third Rewiring Via 127 First Bonding Pad 128 Second Bonding Pad 130 First Chiplet 131 First connection pad 132 First connecting member 140 Second Chiplet 141 Second connection pad 142 Second connecting member 150 Third connecting member 160 First Molding Material 161 Second Molding Material 170 Rear rewiring structure 171 Second Dielectric 172 Fourth Rewiring Via 173 Third rewiring line 174 Fifth rewiring via 175 Fourth rewiring line 176. Via No. 6 (Rewiring) 177 Third Bonding Pad 180 communication chips 181 Third connection pad 182 Fourth connecting member 183 First underfill member 190 Memory Structures 191 4th connection pad 192 Fifth connecting member 193 Second underfill member 210 Bridge Die 211 Bridge Die Base 212 Connection Pads 213 Signal Line 214 Sixth connecting member 221 Adhesive material 222 Heat dissipation structure

Claims

1. First rewiring structure and The first chiplet on the first rewiring structure, A second chiplet positioned next to the first chiplet on the first rewiring structure, The second rewiring structure on the first chiplet and the second chiplet, The communication chip on the second rewiring structure, A semiconductor package characterized by including the following.

2. The semiconductor package according to claim 1, characterized in that the footprint of the communication chip overlaps with at least a portion of the footprint of the first chiplet and the footprint of the second chiplet in a first direction perpendicular to the surface of the first redistribution structure.

3. The semiconductor package according to claim 1, characterized in that the first chiplet and the second chiplet are electrically connected to each other via the first redistribution structure.

4. The semiconductor package according to claim 1, characterized in that the first chiplet includes at least one of global logic, an interface, a dispatch circuit, and a fabric circuit.

5. The semiconductor package according to claim 1, characterized in that the second chiplet includes at least one of logic, input / output (I / O) circuits, and memory.

6. First rewiring structure and A plurality of chiplets on the first surface of the first rewiring structure, A plurality of connecting members arranged around the plurality of chiplets on the first surface of the first rewiring structure, The plurality of chiplets and the second rewiring structure on the plurality of connecting members, The communication chip on the second rewiring structure, A plurality of memory structures arranged around the communication chip on the second rewiring structure, A semiconductor package characterized by including the following.

7. The first rewiring structure further includes a bridge die on the second surface, The semiconductor package according to claim 6, characterized in that the second surface is the surface opposite to the first surface in a first direction perpendicular to the surface of the first redistribution structure.

8. The semiconductor package according to claim 7, characterized in that the plurality of chiplets are electrically connected to one another via the first redistribution structure and the bridge die.

9. The semiconductor package according to claim 6, characterized in that each of the plurality of connecting members includes a conductive post.

10. The semiconductor package according to claim 6, characterized in that the footprints of the plurality of memory structures overlap at least a portion of the footprints of the plurality of connecting members in a first direction perpendicular to the surface of the first redistribution structure.

11. The semiconductor package according to claim 6, characterized in that at least one of the plurality of memory structures includes a high-bandwidth memory (HBM).

12. The semiconductor package according to claim 6, characterized in that at least one of the plurality of memory structures includes a DRAM chip.

13. Front rewiring structure and The first logic chiplet on the front rewiring structure, A second logic chiplet is positioned on the front rewiring structure, adjacent to the first logic chiplet in a first direction parallel to the surface of the front rewiring structure, A plurality of connecting members arranged on the front rewiring structure, adjacent to the first logic chiplet in the first direction, The first logic chiplet, the second logic chiplet, and the first molding material on the plurality of connecting members, The rear rewiring structure on the first molding material, The memory structure on the rear rewiring structure, A communication chip positioned on the rear rewiring structure, adjacent to the memory structure in the first direction, A semiconductor package characterized by including the following.

14. The semiconductor package according to claim 13, characterized in that the first logic chiplet and the second logic chiplet each include an application processor (AP).

15. The semiconductor package according to claim 13, further comprising the memory structure and the second molding material on the communication chip.

16. The semiconductor package according to claim 15, characterized in that the upper surface of the second molding material is in the same plane as the upper surface of the memory structure and the upper surface of the communication chip in a second direction perpendicular to the surface of the front rewiring structure.

17. The semiconductor package according to claim 15, further comprising the second molding material, the memory structure, and the heat dissipation structure on the communication chip.

18. The semiconductor package according to claim 17, characterized in that the heat dissipation structure includes a heat spread.

19. The semiconductor package according to claim 17, further comprising adhesive members between the memory structure and the heat dissipation structure, and between the communication chip and the heat dissipation structure.

20. The semiconductor package according to claim 19, characterized in that the adhesive member includes a thermal interface material (TIM).

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