Semiconductor device and recording head

Abstract

The present invention provides a semiconductor device that allows for easy determination of the remaining number of rewrites in a counter circuit and whether or not the upper limit has been reached. [Solution] The semiconductor device is configured by combining an antifuse element A and fuse elements F1 and F2, and includes a counter circuit CM1 in which a count value is set by the combination of the conduction state and non-conduction state of the fuse elements F1 and F2 and the antifuse element A. The count value set in the counter circuit CM1 is incremented by sequentially rewriting the fuse elements F1 and F2 from the conduction state to the non-conduction state and the antifuse element A from the non-conduction state. The counter circuit CM1 has an output unit 10 that outputs a signal corresponding to the combination of the conduction state and non-conduction state of the fuse elements F1 and F2 and the antifuse element A.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a recording head provided with a counter circuit.

Background Art

[0002] Semiconductor devices provided with rewritable counter circuits and memory circuits using fuse elements and anti-fuse elements are known. Patent Document 1 describes an electric circuit in which a fuse element and an anti-fuse element are combined to enable rewriting of 1-bit (binary) information a plurality of times. Recently, in recording devices and recording heads, OTP (One Time Programmable) memories are used to record product-specific information such as chip IDs and setting parameters. Patent Document 2 describes a recording head provided with a memory using a fuse element. The results of measuring the optimum driving conditions of the recording head are stored in the memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Generally, rewritable counter circuits using fuse elements or antifuse elements, including the electrical circuit described in Patent Document 1, have an upper limit on the number of rewrites. In semiconductor devices equipped with this type of counter circuit, there was no function to recognize how many times the counter circuit had been rewritten. Therefore, the system would repeatedly rewrite the data (count value), and only when it finally failed to reach the desired value would it be recognized that the upper limit on the number of rewrites had been reached. For this reason, there was a need for a semiconductor device that could easily determine the remaining number of rewrites of the counter circuit, or that could easily determine whether or not the upper limit on the number of rewrites had been reached. The recording head described in Reference Document 2 does not allow for memory rewriting. If the electrical circuit described in Patent Document 1 were applied to the memory, it would be possible to rewrite the memory, but even in this case, it would not be easy to determine whether the remaining number of rewrites or the upper limit had been reached.

[0005] The object of the present invention is to provide a semiconductor device that allows for easy determination of the remaining number of rewrites and whether or not the upper limit has been reached. [Means for solving the problem]

[0006] According to one aspect of the present invention, a semiconductor device comprising a counter circuit configured by combining an antifuse element and a fuse element, wherein a count value is set by the combination of the conductive state and the non-conductive state of the fuse element and the antifuse element, and the count value set in the counter circuit is incremented by sequentially rewriting the fuse element from a conductive state to a non-conductive state and the antifuse element from a non-conductive state to a conductive state, wherein A semiconductor device is provided, characterized in that it has an output unit that outputs a signal corresponding to the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element in the counter circuit. [Effects of the Invention]

[0007] According to the present invention, the remaining number of rewrites of the counter circuit can be easily determined, or it can be easily determined whether or not the number of rewrites has reached its upper limit. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view showing the schematic configuration of a recording device to which the recording head of the present invention can be attached. [Figure 2] Figure 1 is a perspective view of the recording head mounted on the recording device shown. [Figure 3] This is a schematic diagram illustrating a recording head according to a first embodiment of the present invention. [Figure 4] This is a schematic diagram illustrating the recording unit. [Figure 5A] This is a schematic diagram illustrating the state of the counter circuit. [Figure 5B] This is a schematic diagram illustrating another state of the counter circuit. [Figure 5C] This is a schematic diagram illustrating yet another state of the counter circuit. [Figure 5D] This is a schematic diagram illustrating yet another state of the counter circuit. [Figure 6] This table shows an example of a counter's truth value. [Figure 7] This is a schematic diagram illustrating a recording head according to a second embodiment of the present invention. [Figure 8A] This is a schematic diagram illustrating the state of the counter circuit. [Figure 8B] This is a schematic diagram illustrating another state of the counter circuit. [Figure 8C] This is a schematic diagram illustrating yet another state of the counter circuit. [Figure 8D] This is a schematic diagram illustrating yet another state of the counter circuit. [Figure 9] This table shows an example of a counter's truth value. [Figure 10]It is a schematic diagram for explaining a recording head according to a third embodiment of the present invention. [Figure 11A] It is a schematic diagram for explaining the state of the memory circuit. [Figure 11B] It is a schematic diagram for explaining another state of the memory circuit. [Figure 12A] It is a schematic diagram for explaining the state of the memory circuit. [Figure 12B] It is a schematic diagram for explaining another state of the memory circuit. [Figure 13A] It is a schematic diagram for explaining the state of the counter circuit. [Figure 13B] It is a schematic diagram for explaining another state of the counter circuit. [Figure 13C] It is a schematic diagram for explaining yet another state of the counter circuit. [Figure 13D] It is a schematic diagram for explaining yet another state of the counter circuit. [Figure 13E] It is a schematic diagram for explaining yet another state of the counter circuit. [Figure 13F] It is a schematic diagram for explaining yet another state of the counter circuit. [Figure 13G] It is a schematic diagram for explaining yet another state of the counter circuit. [Figure 13H] It is a schematic diagram for explaining yet another state of the counter circuit. [Figure 13I] It is a schematic diagram for explaining yet another state of the counter circuit.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the embodiments are merely illustrative and are not intended to limit the scope of the present invention to those embodiments.

[0010] (First Embodiment) Figure 1 is a perspective view showing a schematic configuration of a recording device to which the recording head of the present invention can be mounted. The recording device 900 has a recording head 810 that ejects a liquid such as ink. The recording head 810 performs recording, for example, according to an inkjet method. The recording head 810 is mounted on a carriage 920. The carriage 920 is attached to a lead screw 904 having a helical groove 921. By the rotation of the lead screw 904, the recording head 810 can move together with the carriage 920 along a guide 919 in the direction of arrow a or arrow b. The carriage 920 is equipped with a carriage substrate (not shown) for electrical connection to the contact pads of the recording head 810, which will be described later. The recording paper P is transported onto a platen 906 by a paper transport unit (not shown). A paper press plate 905 presses the recording paper P against the platen 906 along the carriage movement direction. Recording on the recording paper P is performed by repeatedly moving the recording head 810 back and forth and transporting the recording paper P.

[0011] Figure 2 is a perspective view of the recording head 810 mounted on the recording device 900 shown in Figure 1. Multiple nozzles 813 are formed in a row on the element substrate 100 as discharge ports for discharging liquid. Various circuits (not shown) including energy generating elements for generating liquid discharge energy are formed on the element substrate 100. The element substrate 100 is electrically connected to a contact pad 815 for electrical connection with the recording device 900 via a flexible film wiring board 814.

[0012] The recording head 810 includes an ink tank 812. The ink tank 812 has, for example, a fibrous or porous ink-retaining material (not shown), which holds the ink. The recording head 810 receives electrical signals from the carriage substrate mounted on the carriage 920 via a contact pad 815 and ejects ink according to these electrical signals. Although the recording head 810 shown in Figure 2 has an integrated configuration of the element substrate 100 and the ink tank 812, it is also possible to have a configuration in which the ink tank can be separated.

[0013] Figure 3 is a schematic diagram illustrating the configuration of a recording head 810 according to a first embodiment of the present invention. In Figure 3, the electrical connection between the main body 900a of the recording device 900 and the element substrate 100 of the recording head 810 is schematically shown. The element substrate 100 is an example of a semiconductor device. The main body 900a of the recording device 900 includes a power generation circuit 201, a recording device control circuit 202, a VH control circuit 203, a VHT control circuit 204, a VDD control circuit 205, a constant current control circuit 206, and a constant voltage control circuit 207. The power generation circuit 201 provides the power necessary to operate the recording device 900, as well as the power and ground potential GND necessary to operate the element substrate 100. The power generation circuit 201 supplies power to the VH control circuit 203, VHT control circuit 204, VDD control circuit 205, constant current control circuit 206, and constant voltage control circuit 207.

[0014] The recording device control circuit 202 provides the necessary data and clock to operate the element board 100. The VH control circuit 203 supplies the power supply voltage VH to the element board 100. The VHT control circuit 204 supplies the power supply voltage VHT to the element board 100. The VDD control circuit 205 supplies the power supply voltage VDD to the element board 100. The constant current control circuit 206 supplies a constant current to the element board 100. The constant voltage control circuit 207 supplies a constant voltage to the element board 100.

[0015] The element board 100 includes a counter circuit CM1, recording units H1 to H4, a shift register 110, and a step-down circuit 120. The counter circuit CM1 holds the number of times the recording head 810 has been reused as a counter value. The counter circuit CM1 can count up to the maximum number of reuses. Generally, the recording head is reused about 2 to 3 times, so here the maximum number of reuses is set to 3. The counter circuit CM1 is configured as a 2-bit counter by combining an antifuse element and a fuse element.

[0016] The shift register 110 holds data for turning the transistors provided in the counter circuit CM1 and the recording units H1 to H4 ON / OFF. The shift register 110 can rewrite the data it holds according to the data from the recording device control circuit 202, and can switch the transistors ON / OFF. For example, the shift register 110 can turn the transistors ON / OFF when writing data to the counter circuit CM1 or reading data from the counter circuit CM1. The shift register 110 can also turn the transistors ON / OFF when driving the recording units H1 to H4.

[0017] The step-down circuit 120 reduces the power supply voltage VHT supplied from the VHT control circuit 204 to a voltage suitable for driving the transistors provided in the counter circuit CM1 and the recording units H1 to H4, respectively. In this embodiment, four recording units H1 to H4 are provided, but this is not limited to this. It is also possible to use four or more recording units.

[0018] Next, we will explain recording units H1 to H4 in detail. Since recording units H1 to H4 all have the same configuration, we will refer to them as recording unit H and explain their configuration in detail.

[0019] Figure 4 is a schematic diagram of the recording unit H. The recording unit H has a recording element Rh. The recording element Rh is an element (such as an electrothermal conversion element or heater) that generates energy to eject a liquid such as ink from the ejection port. One end of the recording element Rh is connected to terminal VH, and the other end of the recording element Rh is grounded via transistor J1. A power supply voltage VH (for example, 24V) is supplied to terminal VH from the VH control circuit 203.

[0020] Transistor J1 is, for example, a MOS (metal-oxide-semiconductor) type FET (field-effect transistor). One terminal (source or drain) of transistor J1 is connected to the recording element Rh, and the other terminal of transistor J1 is connected to ground potential (GND). A drive voltage conversion element K1, which generates the driving voltage for transistor J1, is connected to the gate terminal of transistor J1. When the voltage value supplied to the gate terminal exceeds a threshold, transistor J1 transitions from a non-conductive state to a conductive state. When transistor J1 becomes conductive, the power supply voltage VH is supplied to the recording element Rh, and current flows through the recording element Rh. By energizing the recording element Rh in this way and generating heat, ink can be ejected.

[0021] Next, we will explain the counter circuit CM1 in detail. Figures 5A to 5D are schematic diagrams illustrating the write and read operations of the counter circuit CM1. As shown in Figure 5A, the counter circuit CM1 has an antifuse element A and fuse elements F1 and F2. Fuse element F1 is connected in parallel to the series section in which antifuse element A and fuse element F2 are connected. Fuse element F2 can be called the first fuse element, and fuse element F1 can be called the second fuse element. One end of fuse element F2 is connected to node N_A, and the other end of fuse element F2 is connected to node N_B. One end of antifuse element A is connected to node N_B, and the other end of antifuse element A is grounded via transistor J2.

[0022] Transistor J2 is similar to transistor J1 shown in Figure 4, with one terminal (source or drain) connected to node N_B and the other terminal connected to ground potential (GND). A drive voltage conversion element K2, which generates the drive voltage for transistor J2, is connected to the gate terminal of transistor J2. When the voltage value supplied to the gate terminal exceeds a threshold, transistor J2 transitions from a non-conductive state to a conductive state. The power supply voltage VHT is supplied from terminal VHT to the drive voltage conversion element K2 via a step-down circuit 120. The step-down circuit 120, for example, steps down the power supply voltage VHT from 24[V] to 5.3[V] and supplies it to the drive voltage conversion element K2.

[0023] The counter circuit CM1 further includes an output unit 10. The output unit 10 outputs a signal corresponding to the combination of conduction and non-conduction states of the fuse elements F1, F2 and antifuse element A in the counter circuit CM1. The output unit 10 includes a buffer element L, logic elements AND1, AND2, voltage comparators CMP1, CMP2, and logic element OR1. Logic element AND1 compares the voltage at node N_A with the voltage at node N_B. Buffer element L outputs the voltage at node N_A as the lower bit 0 of the counter. Voltage comparator CMP1 compares the voltage at node N_B with the reference voltage Vref0. Voltage comparator CMP2 compares the voltage at node N_B with the reference voltage Vref1. Logic element AND2 compares the output voltage of voltage comparator CMP1 with the output voltage of voltage comparator CMP2. Logic element OR1 compares the output of logic element AND1 with the output of logic element AND2 and outputs the comparison result as the upper bit 1 of the counter.

[0024] The counter circuit CM1 in Figure 5A is in its initial state. In the initial state of the counter circuit CM1, antifuse element A is in its initial non-conducting state, and fuse elements F1 and F2 are both in their initial short-circuit (conducting) state. By sequentially disconnecting (non-conducting) fuse element F1, short-circuiting (conducting) antifuse element A, and disconnecting (non-conducting) fuse element F2, the count value of the counter circuit CM1 can be incremented.

[0025] First, let's explain how to disconnect (make non-conductive) the fuse element F1. To disconnect the fuse element F1, the transistor J2 is turned ON to allow current to flow through the fuse element F1. Specifically, the constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element board 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815.

[0026] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM1 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied across the fuse element F1. Because the resistance of fuse element F1 is very small, a large current flows through it. As a result, fuse element F1 heats up and then melts. Figure 5B schematically shows the state of the counter circuit CM1 with fuse element F1 in a non-conducting state.

[0027] Next, we will explain how to short-circuit (conduct) the antifuse element A. To short-circuit the antifuse element A, the transistor J2 is turned ON and a high voltage is applied between the two electrodes that make up the antifuse element A. Specifically, the constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element substrate 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815.

[0028] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM1 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to the antifuse element A. By rapidly switching the voltage application ON / OFF on the antifuse element A, the gate oxide film between the two electrodes of the antifuse element A is broken down, resulting in conductivity. For example, by repeatedly switching the voltage application ON / OFF at a frequency of 6[MHz], the antifuse element A can be made to conduct. Figure 5C schematically shows the state of the counter circuit CM1 with the antifuse element A in a conductive state. On average, the number of ON / OFF cycles of voltage application is about 10,000, but due to individual differences in the elements, some elements may require about 60,000 cycles to conduct. For this reason, in this embodiment, the number of ON / OFF cycles of voltage application is set to the maximum of 60,000.

[0029] Next, we will explain how to disconnect (make non-conductive) the fuse element F2. After making the antifuse element A conductive, the fuse element F2 is disconnected using the same procedure as for the fuse element F1. In this embodiment, the fuse element F2 is designed to melt when a current of 70mA or more flows through it. Figure 5D schematically shows the state of the counter circuit CM1 with the fuse element F2 in a non-conductive state.

[0030] Next, we will explain how to read the counter value of the counter circuit CM1. Figure 6 shows the truth table of the counter corresponding to each state of the counter circuit CM1 shown in Figures 5A to 5D. In Figure 6, state (a) corresponds to the state in Figure 5A, state (b) corresponds to the state in Figure 5B, state (c) corresponds to the state in Figure 5C, and state (d) corresponds to the state in Figure 5D.

[0031] To read the counter value, first, a constant current is applied to terminal IM of the element substrate 100, and the shift register 110 is controlled to turn on transistor J2. In this embodiment, the constant current control circuit 206 applies a current of 65 [μA] to terminal IM. The reference voltage Vref0 is set to 0.5 [V], and the reference voltage Vref1 is set to 1.5 [V]. The voltage between node N_A and GND is supplied to buffer element L, and the voltage between node N_B and GND is supplied to voltage comparators CMP1 and CMP2, respectively. In this state, the recording device control circuit 202 reads the counter value from the voltages of the terminal of the lower bit 0 and the terminal of the upper bit 1 of the counter. Bits 0 and 1 of the counter are in the 3.3 [V] system, with a Low level or "0" when around 0.0 [V], and a High level or "1" when around 3.3 [V].

[0032] The method for reading the counter value of the counter circuit CM1 in its initial state as shown in Figure 5A is described below. The resistance values ​​of fuse elements F1 and F2 are both approximately 400 [Ω], and the resistance value of antifuse element A is approximately 100 [kΩ]. When a current of 65 [μA] is supplied to terminal IM and transistor J2 is turned ON, the current flows from terminal IM through fuse element F1 and transistor J1 to GND. At this time, the voltages at nodes N_A and N_B are 26 [mV]. Since the input voltage of buffer element L (node ​​N_A) is below the threshold value of 2.0 [V], counter bit 0, which is the output of buffer element L, becomes low level.

[0033] The output of logic element AND1 is Low level, derived from the voltages at node N_A and node N_B. The output of voltage comparator CMP1 is High level, derived from the voltage at node N_A and Vref0. The output of voltage comparator CMP2 is Low level, derived from the voltage at node N_A and Vref1. The output of logic element AND2 is Low level, derived from the output of voltage comparator CMP1 (High level) and the output of voltage comparator CMP2 (Low level). Counter bit1, which is the output of logic element OR1, is Low level, derived from the output of logic element AND1 (Low level) and the output of logic element AND2 (Low level). As a result, as shown in state (a) of the truth table in Figure 6, the counter value of counter circuit CM1 becomes 0, derived from the value of counter bit0 (Low level: 0) and the value of counter bit1 (Low level: 0).

[0034] Next, we will explain how to read the counter value of the counter circuit CM1 in Figure 5B. The resistance of fuse element F1 is approximately 1 [MΩ], the resistance of fuse element F2 is approximately 400 [Ω], and the resistance of antifuse element A is approximately 100 [kΩ]. When 65 [μA] is supplied to terminal IM and transistor J2 is turned ON, the voltages at node N_A and node N_B both become 3.3 [V], which is close to the power supply voltage of the constant current control circuit 206. Since the input voltage of buffer element L is above the threshold value of 2.0 [V], counter bit 0, which is the output of buffer element L, becomes high level.

[0035] The output of logic element AND1 is Low level, derived from the voltages of node N_A and node N_B. The output of voltage comparator CMP1 is High level, derived from the voltage of node N_A and Vref0. The output of voltage comparator CMP2 is Low level, derived from the voltage of node N_A and Vref1. The output of logic element AND2 is Low level, derived from the output of voltage comparator CMP1 (High level) and the output of voltage comparator CMP2 (Low level). Counter bit1, which is the output of logic element OR1, is Low level, derived from the output of logic element AND1 (Low level) and the output of logic element AND2 (Low level). As a result, as shown in state (b) of the truth table in Figure 6, the counter value of counter circuit CM1 is 1, derived from the value of counter bit0 (Low level: 0) and the value of counter bit1 (High level: 1).

[0036] Next, we will explain how to read the counter value of the counter circuit CM1 in Figure 5C. The resistance of fuse element F1 is approximately 1 [MΩ], the resistance of fuse element F2 is approximately 400 [Ω], and the resistance of antifuse element A is approximately 20 [kΩ]. When 65 [μA] is supplied to terminal IM and transistor J2 is turned ON, the voltages at node N_A and node N_B are both approximately 1.3 [V], which is near the power supply voltage of the constant current control circuit 206. Since the input voltage of buffer element L is below the threshold value of 2.0 [V], counter bit 0, which is the output of buffer element L, becomes low.

[0037] The output of logic element AND1 is Low level, derived from the voltages of node N_A and node N_B. The output of voltage comparator CMP1 is High level, derived from the voltage of node N_A and Vref0. The output of voltage comparator CMP2 is High level, derived from the voltage of node N_A and Vref1. The output of logic element AND2 is High level, derived from the output of voltage comparator CMP1 (High level) and the output of voltage comparator CMP2 (High level). Counter bit1, which is the output of logic element OR1, is High level, derived from the output of logic element AND1 (Low level) and the output of logic element AND2 (High level). As a result, as shown in state (c) of the truth table in Figure 6, the counter value of counter circuit CM1 is 2, derived from the value of counter bit0 (High level: 1) and the value of counter bit1 (Low level: 0).

[0038] Next, we will explain how to read the counter value of the counter circuit CM1 in Figure 5D. The resistance values ​​of the fuse elements F1 and F2 are both about 1 [MΩ], and the resistance value of the antifuse element A is about 20 [kΩ]. When 65 [μA] is supplied to terminal IM and transistor J2 is turned ON, the voltage at node N_A becomes 3.3 [V], which is close to the power supply voltage of the constant current control circuit 206, and the voltage at node N_B becomes about 0.0 [V], which is the GND of the constant current control circuit 206. Since the input voltage of buffer element L is above the threshold value of 2.0 [V], counter bit 0, which is the output of buffer element L, becomes high level.

[0039] The output of logic element AND1 is high level, derived from the voltages of node N_A and node N_B. The output of voltage comparator CMP1 is high level, derived from the voltage of node N_A and Vref0. The output of voltage comparator CMP2 is high level, derived from the voltage of node N_A and Vref1. The output of logic element AND2 is high level, derived from the output of voltage comparator CMP1 (high level) and the output of CMP2 (high level). Counter bit1, which is the output of logic element OR1, is high level, derived from the output of logic element AND1 (high level) and the output of logic element AND2 (high level). As a result, as shown in state (d) of the truth table in Figure 6, the counter value of counter circuit CM1 is 3, derived from the value of counter bit0 (high level: 1) and the value of counter bit1 (high level: 1). The above explains how to write and read the counter value of the counter circuit CM1.

[0040] As described above, with the recording head 810 of this embodiment, the counter circuit CM1, which combines the antifuse element A and fuse elements F1 and F2, can be rewritten multiple times, and the remaining number of rewrites can be easily determined based on the output of the output unit 10. For example, the recording device control circuit 202 may acquire the counter value of the counter circuit CM1 based on the value of counter bit 0 and the value of counter bit 1 according to the truth table of the counter shown in Figure 6, and display the acquired counter value on a display unit (not shown). This allows the user to easily determine the remaining number of rewrites of the counter circuit CM1 based on the displayed count value.

[0041] From an environmental protection perspective, recycling and reuse of goods are considered important, and the reuse of the recording head 810 is also gaining attention. Normally, if the recording head 810 is reused more than a specified number of times, it may deteriorate and the print quality may decrease, so it is necessary to record the number of reuses within the recording head 810.

[0042] As an example, we will explain how to manage the number of reuses of the recording head 810 using the counter circuit CM1. Below, we will explain the processing procedure for determining whether it is possible to count the counter value of the counter circuit CM1, that is, whether it is reusable, and how to save data to the counter circuit CM1. Note that "saving" data to the counter circuit CM1 is sometimes referred to as "rewriting" it.

[0043] Whether the recording head 810 is reusable can be determined by checking whether the counter value, which is determined by the state of bits 0 and 1 of the counter circuit CM1, has reached its upper limit (in this case, "3"). This determination is made by the recording device control circuit 202. The counter circuit CM1 of the recording head 810, which has never been reused, is in the state shown in Figure 5A. In this case, the counter value of the counter circuit CM1 is 0, and the upper limit has not been reached, so the recording device control circuit 202 determines that it is reusable.

[0044] If the recording head 810 is reused (for the first time), the counter circuit CM1 will be in the state shown in Figure 5B. In this case, the counter value of the counter circuit CM1 is 1, and since the upper limit has not been reached, the recording device control circuit 202 determines that it is reusable. Furthermore, if the recording head 810 is reused (for the second time), the counter circuit CM1 will be in the state shown in Figure 5C. In this case, the counter value of the counter circuit CM1 is 2, and since it has not reached the upper limit, the recording device control circuit 202 determines that it is reusable. Furthermore, if the recording head 810 is reused (for the third time), the counter circuit CM1 will be in the state shown in Figure 5D. In this case, the counter value of the counter circuit CM1 is 3, which has reached the upper limit, so the recording device control circuit 202 determines that it cannot be reused.

[0045] The determination of whether or not the recording device can be reused by the recording device control circuit 202 described above may be made, for example, when the amount of ink stored in the ink tank 812 reaches a predetermined amount (any amount including 0). In this case, the recording device control circuit 202 may display the determination result of whether or not the recording device can be reused on a display unit (not shown). This allows the user to understand whether or not the recording device can be reused based on the displayed result. Alternatively, the control device of the regeneration equipment for performing the reuse of the recording head may perform the above-mentioned determination of whether or not the recording device can be reused and display the determination result. In this case, the reuse worker can understand whether or not the recording device can be reused based on the displayed result.

[0046] (Second embodiment) Figure 7 is a schematic diagram illustrating the configuration of a recording head 810 according to a second embodiment of the present invention. In Figure 7, the electrical connection between the main body 900a of the recording device 900 and the element substrate 100 in the recording head 810 is schematically shown.

[0047] The recording head 810 of this embodiment differs from that of the first embodiment in that a counter circuit CM2 is provided on the element substrate 100 in place of the counter circuit CM1, but the other configurations are basically the same as those of the first embodiment. The main body 900a of the recording device 900 differs from that of the first embodiment in that it has a recording device control circuit 214 in place of the recording device control circuit 202, but the other configurations are basically the same as those of the first embodiment. The same reference numerals are used for the same components, and their detailed descriptions are omitted.

[0048] The element board 100 of the recording head 810 includes a counter circuit CM2. The counter circuit CM2 outputs a count-up enable / disable flag C_UP (flag signal) indicating whether the counter value has reached its upper limit. The element board 100 has an output terminal C_UP for outputting the count-up enable / disable flag C_UP. The recording device control circuit 214 has an input terminal C_UP to which the count-up enable / disable flag C_UP from the counter circuit CM2 is input.

[0049] Figures 8A to 8D are schematic diagrams illustrating the write and read operations of the counter circuit CM2. The counter circuit CM2 differs from the counter circuit CM1 in that its output unit 10 outputs a count-up enable / disable flag C_UP. In the output unit 10, the output of logic element AND1 is split into two; one is supplied to logic element OR1, and the other is supplied to output terminal C_UP. The output of logic element AND1 is used as the count-up enable / disable flag C_UP. The write and read operations of the counter value in the counter circuit CM2 are basically the same as those of the counter circuit CM1, so a detailed explanation is omitted here.

[0050] In this embodiment as in the first embodiment, when reading the counter value, a constant current is supplied to terminal IM of the counter circuit CM2, and the shift register 110 is controlled to turn on transistor J2. The constant current control circuit 206 supplies a current of 65 [μA] to terminal IM of the counter circuit CM2. The reference voltage Vref0 is set to 0.5 [V], and the reference voltage Vref1 is set to 1.5 [V]. The voltage between node N_A and GND is supplied to buffer element L, and the voltage between node N_B and GND is supplied to voltage comparators CMP1 and CMP2, respectively. In this state, the recording device control circuit 214 reads the counter value from the voltages of the terminal of the lower bit 0 and the terminal of the upper bit 1 of the counter. Bits 0 and 1 of the counter are in the 3.3 [V] system, set to Low level or "0" when around 0.0 [V], and High level or "1" when around 3.3 [V].

[0051] In this embodiment, when reading the counter value of the counter circuit CM2, the count-up enable / disable flag C_UP is used to determine whether the counter value of the counter circuit CM2 has reached its upper limit. Figure 9 shows the truth tables of the counter corresponding to each state of the counter circuit CM2 shown in Figures 8A to 8D. In Figure 9, state (a) corresponds to the state in Figure 8A, state (b) corresponds to the state in Figure 8B, state (c) corresponds to the state in Figure 8C, and state (d) corresponds to the state in Figure 8D.

[0052] The following explains the determination using the count-up permission flag C_UP when reading the counter value in each state of the counter circuit CM2 shown in Figures 8A to 8D. The state of counter circuit CM2 shown in Figure 8A is the same initial state as counter circuit CM1 shown in Figure 5A. In this initial state, as shown in state (a) of the truth table in Figure 9, the counter value of counter circuit CM1 is 0, based on the value of counter bit 0 (Low level: 0) and the value of counter bit 1 (Low level: 0). In this state, the output of logic element AND1 is at a Low level, so the count-up enable / disable flag C_UP is at a Low level. Since the count-up enable / disable flag C_UP is at a Low level, it can be determined that the counter value of counter circuit CM2 has not reached its upper limit.

[0053] The state of counter circuit CM2 shown in Figure 8B is the same as the state of counter circuit CM1 shown in Figure 5B. In this state, as shown in state (b) of the truth table in Figure 9, the counter value of counter circuit CM1 is 1, based on the value of counter bit 0 (Low level: 0) and the value of counter bit 1 (High level: 1). In this state, the output of logic element AND1 is at a Low level, so the count-up enable / disable flag C_UP is at a Low level. Since the count-up enable / disable flag C_UP is at a Low level, it can be determined that the counter value of counter circuit CM2 has not reached its upper limit.

[0054] The state of counter circuit CM2 shown in Figure 8C is the same as the state of counter circuit CM1 shown in Figure 5C. In this state, as shown in state (c) of the truth table in Figure 9, the counter value of counter circuit CM1 is 2, based on the value of counter bit 0 (High level: 1) and the value of counter bit 1 (Low level: 0). In this state, the output of logic element AND1 is Low level, so the count-up enable / disable flag C_UP is Low level. Since the count-up enable / disable flag C_UP is Low level, it can be determined that the counter value of counter circuit CM2 has not reached its upper limit.

[0055] The state of counter circuit CM2 shown in Figure 8D is the same as the state of counter circuit CM1 shown in Figure 5D. In this state, as shown in state (d) of the truth table in Figure 9, the counter value of counter circuit CM1 becomes 3 from the value of counter bit 0 (High level: 1) and the value of counter bit 1 (High level: 1). In this state, the output of logic element AND1 is at a High level, so the count-up enable / disable flag C_UP is at a High level. Since the count-up enable / disable flag C_UP is at a High level, it can be determined that the counter value of counter circuit CM2 has reached its upper limit. In other words, when the combination of conduction and non-conduction states of fuse elements F1, F2 and antifuse element A becomes a predetermined combination, the output unit 10 outputs a flag signal indicating that the count value has reached its upper limit.

[0056] In the recording head 810 of this embodiment, as in the first embodiment, the counter circuit CM2 can be rewritten multiple times, and the remaining number of rewrites can be easily determined based on the output of the output unit 10. For example, the recording device control circuit 214 may acquire the counter value of the counter circuit CM1 based on the value of counter bit 0 and the value of counter bit 1 according to the truth table of the counter shown in Figure 9, and display the acquired counter value on a display unit (not shown). This allows the user to easily determine the remaining number of rewrites of the counter circuit CM2 based on the displayed count value.

[0057] Furthermore, it is possible to determine whether the count value of the counter circuit CM2 has reached its upper limit based on the count-up permission flag C_UP. For example, the recording device control circuit 214 may display information on an unillustrated display unit indicating whether the count value of the counter circuit CM2 has reached its upper limit based on the count-up permission flag C_UP. This allows the user to easily determine whether the count value of the counter circuit CM2 has reached its upper limit based on the displayed information.

[0058] In this embodiment, as in the first embodiment, the number of reuses can be managed using the counter circuit CM2. In addition, it is possible to determine whether the recording head 810 is reusable based on the count-up availability flag C_UP. For example, if the count-up availability flag C_UP is at a low level, it can be determined that it is reusable. If the count-up availability flag C_UP is at a high level, it can be determined that it is not reusable. The determination of reusability based on the count value is as described in the first embodiment. The following describes in detail the process of determining reusability using the count-up availability flag C_UP.

[0059] The counter circuit CM2 of the recording head 810, which has never been reused, is in the state shown in Figure 8A. In this case, the count-up feasibility flag C_UP is at a low level, so the recording device control circuit 214 determines that it is reusable. If the recording head 810 is reused (for the first time), the counter circuit CM2 will be in the state shown in Figure 8B. In this case, since the count-up feasibility flag C_UP is at a low level, the recording device control circuit 214 determines that it is reusable.

[0060] Furthermore, if the recording head 810 is reused (for the second time), the counter circuit CM2 will be in the state shown in Figure 8C. In this case, since the count-up feasibility flag C_UP is at a low level, the recording device control circuit 214 determines that it is reusable. Furthermore, if the recording head 810 is reused (for the third time), the counter circuit CM2 will be in the state shown in Figure 8D. In this case, since the count-up feasibility flag C_UP is at a high level, the recording device control circuit 214 determines that reuse is not possible.

[0061] The determination of whether or not the item can be reused by the recording device control circuit 214 described above may be made, for example, when the amount of ink stored in the ink tank 812 reaches a predetermined amount. In this case, the recording device control circuit 214 may display the determination result of whether or not the item can be reused on a display unit (not shown). This allows the user to understand whether or not the item can be reused based on the displayed result. Alternatively, the control device of the recycling equipment used for the reuse process may perform the above-mentioned determination of whether or not the item can be reused and display the determination result. In this case, the reuse worker can understand whether or not the item can be reused based on the displayed result.

[0062] (Third embodiment) Figure 10 is a schematic diagram illustrating the configuration of a recording head 810 according to a third embodiment of the present invention. In Figure 10, the electrical connection between the main body 900a of the recording device 900 and the element substrate 100 in the recording head 810 is schematically shown.

[0063] The recording head 810 of this embodiment includes a ROM writing power control element 130 and memory circuits M101 to M120, and the counter circuit CM2 is configured to count the number of memory rewrites. Except for this configuration, it is basically the same as that of the second embodiment. The main body 900a of the recording device 900 has a shift register 111 instead of a shift register 110. The shift register 111 has the same number of bits as the transistors (described later) formed in the memory circuits M101 to M120 and the counter circuit CM2. Except for this configuration, it is basically the same as that of the second embodiment. The same reference numerals are used for the same components, and their detailed descriptions are omitted.

[0064] We will now explain memory circuits M101 to M120 in detail. Since memory circuits M101 to M120 all have the same configuration, we will refer to them simply as memory circuit M and describe their configuration in detail.

[0065] Figure 11A is a schematic diagram of the memory circuit M. The memory circuit M has an antifuse element A1. One end of the antifuse element A1 is connected to terminal VHT via a ROM write power supply control element 130, and the other end of the antifuse element A1 is grounded via a transistor J3. The ROM write power supply control element 130 is an element that applies an antifuse element write power supply to the antifuse element A1 when the recording device control circuit 214 sets the memory circuit M to the write state.

[0066] Transistor J3 is similar to transistor J1 shown in Figure 4, with one terminal (source or drain) connected to antifuse element A1 and the other terminal connected to ground potential (GND). A drive voltage conversion element K3, which generates the drive voltage for transistor J3, is connected to the gate terminal of transistor J3. When the voltage value supplied to the gate terminal exceeds a threshold, transistor J3 transitions from a non-conductive state to a conductive state. The power supply voltage VHT is supplied from terminal VHT to the drive voltage conversion element K3 via the step-down circuit 120.

[0067] The method for short-circuiting (conducting) the antifuse element A1 is described below. By turning on the ROM writing power control element 130 and the transistor J3, a high voltage is applied between the two electrodes constituting the antifuse element A1. This causes dielectric breakdown of the gate oxide film between the two electrodes, resulting in a conductive state. Figure 11B schematically shows the state of the memory circuit M with the antifuse element A1 in a conductive state.

[0068] The recording device control circuit 214 can short-circuit (open) the antifuse element A1 of any of the memory circuits M101 to M120 by controlling the shift register 111. Below, as an example, the procedure for short-circuiting (opening) the antifuse element A1 of memory circuit M101 will be described.

[0069] The constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element substrate 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815. Next, the recording device control circuit 214 outputs a signal to the shift register 111, controlling the drive voltage conversion element K3 of memory circuit M101 to a high level and the drive voltage conversion elements K3 of the other memory circuits M102~M120 to a low level. As a result, in memory circuit M101, transistor J3 turns ON, and the 24[V] voltage supplied to terminal IM is applied to the antifuse element A1. By rapidly switching the voltage application ON / OFF on the antifuse element A1, the gate oxide film between the two electrodes of the antifuse element A1 is broken down, and it becomes conductive. For example, by repeatedly switching the voltage application ON / OFF at a frequency of 6[MHz], the antifuse element A1 can be made conductive. In this embodiment, the number of ON / OFF cycles of voltage application is set to 60,000.

[0070] In this embodiment, the optimal driving conditions for the recording head 810 are maintained using memory circuits M101 to M120. For example, when current is supplied to the recording element Rh, ink is ejected from the nozzle 813. However, due to individual differences in the element substrate 100, the optimal energy for ejection differs slightly for each element substrate 100. Therefore, when shipping the recording head 810, it is necessary to measure the optimal ejection energy using a dedicated inspection device and store this information in the memory of the recording head 810. In this embodiment, the optimal ejection energy is managed as rank values ​​1 to 31, and the optimal rank values ​​are stored in memory circuits M101 to M120.

[0071] The memory circuits M101 to M120 are divided into four blocks. The first block consists of memory circuits M101 to M105, the second block consists of memory circuits M106 to M110, the third block consists of memory circuits M111 to M115, and the fourth block consists of memory circuits M116 to M120. In the first block, memory circuit M101 is used as the least significant bit and memory circuit M105 as the most significant bit, allowing for the setting of 5 bits of data (32 combinations). Similarly, the least significant bit and most significant bit are set in the other blocks, allowing for the setting of 5 bits of data (32 combinations). In this embodiment, the optimal rank value can be held on a block-by-block basis, so the optimal rank value can be saved up to four times. In this case, if the state in which the optimal rank value is saved in the first block is considered the initial state, it can be rewritten three times using the remaining second to third blocks.

[0072] The counter circuit CM2 is the same as that described in the second embodiment and can count up to the upper limit of 3. The counter circuit CM2 is configured to count the number of times the optimal rank value is rewritten in block units in the memory circuits M101 to M120. In this embodiment, when reading the counter value of the counter circuit CM2, the count-up permission flag C_UP is used to determine whether the counter value of the counter circuit CM2 has reached the upper limit. Here, the upper limit of the counter circuit CM2 means the upper limit of the number of memory rewrites. In other words, the count-up permission flag C_UP can be used to determine whether or not the memory can be rewritten.

[0073] For example, when the optimal rank value is stored in the first block (memory circuits M101 to M105), the counter circuit CM2 is in the initial state shown in Figure 8A. In this initial state, the counter value of the counter circuit CM2 is 0, and the count-up enable / disable flag C_UP is at a low level. The recording device control circuit 214 can determine that memory rewriting is possible because the count-up enable / disable flag C_UP is at a low level.

[0074] Next, when the optimal rank value is saved in the second block (memory circuits M106~M110), the counter circuit CM2 is in the state shown in Figure 8B. In this state, the counter value of the counter circuit CM2 becomes 1, and the count-up permission flag C_UP becomes low. The recording device control circuit 214 can determine that memory rewriting is possible because the count-up permission flag C_UP is low.

[0075] Next, when the optimal rank value is saved in the third block (memory circuits M111~M115), the counter circuit CM2 is in the state shown in Figure 8C. In this state, the counter value of the counter circuit CM2 becomes 2, and the count-up enable / disable flag C_UP is at a low level. The recording device control circuit 214 can determine that memory rewriting is possible because the count-up enable / disable flag C_UP is at a low level.

[0076] Finally, when the optimal rank value is saved in the fourth block (memory circuits M116~M120), the counter circuit CM2 is in the state shown in Figure 8D. In this state, the counter value of the counter circuit CM2 becomes 3, and the count-up permission flag C_UP is at a high level. The recording device control circuit 214 can determine that memory rewriting is not possible because the count-up permission flag C_UP is at a high level.

[0077] In the recording head 810 of this embodiment, the recording device control circuit 214 may also display the count value of the counter circuit CM2 and the result of the determination of whether the memory can be rewritten based on the count-up flag C_UP on a display unit (not shown). This allows the user to easily understand the remaining number of rewrites for the counter circuit CM2 and whether the memory can be rewritten based on the display result.

[0078] In this embodiment, as in the first and second embodiments, the number of reuses can be managed using the counter circuit CM2. In addition, it is possible to determine whether the recording head 810 is reusable based on the count-up availability flag C_UP. The process for determining reusability using the count-up availability flag C_UP will be described in detail below.

[0079] Generally, when reusing a recording head, for example, the inside of a recording head that has run out of ink is cleaned and then refilled with ink. In this case, the optimal ejection energy may have changed since the last shipment, so it is necessary to measure the optimal ejection energy again and rewrite the rank value stored in the memory circuit. The following describes the procedure for rewriting the data in the memory circuit and determining whether or not to reuse the recording head 810 when reusing it.

[0080] When the recording head 810 is shipped, the optimal ejection energy is measured using a dedicated inspection device, and the optimal rank value is stored in the first block (memory circuits M101 to M105). At this time, the counter circuit CM2 of the recording head 810 is in the state shown in Figure 8A. In the recording device 900 equipped with the shipped recording head 810, for example, when the remaining ink reaches a predetermined amount, the recording device control circuit 214 determines whether it can be reused based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a low level, the device control circuit 214 determines that it can be reused and displays the determination result on an unshown display unit. The user can understand from the displayed determination result that the recording head 810 can be reused.

[0081] When reusing the recording head 810 after the ink has run out (first time), the recording head 810 is mounted on the control device of the regeneration equipment. The control device determines whether or not it can be reused based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a low level, the control device determines that it can be reused and displays the determination result. The operator can understand from the displayed determination result that the recording head 81 can be reused. Since it can be reused, the optimal ejection energy is measured using a dedicated inspection device, and the optimal rank value is stored in the second block (memory circuits M106~M110). At this time, the counter circuit CM2 of the recording head 810 is in the state shown in Figure 8B.

[0082] In a recording device 900 equipped with a recording head 810 that has been reused for the first time, for example, when the remaining ink level reaches a predetermined amount, the recording device control circuit 214 determines whether or not to reuse the recording head based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a low level, the device control circuit 214 determines that it is reusable and displays the determination result on an unshown display unit. The user can understand from the displayed determination result that the recording head 810 is reusable.

[0083] When reusing the recording head 810 after the ink has run out (for the second time), the recording head 810 is mounted on the control device of the regeneration equipment. The control device determines whether or not it can be reused based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a low level, the control device determines that it can be reused and displays the result. The operator can understand from the displayed result that the recording head 810 can be reused. Since it can be reused, the optimal ejection energy is measured using a dedicated inspection device, and the optimal rank value is stored in the third block (memory circuits M111~M115). At this time, the counter circuit CM2 of the recording head 810 is in the state shown in Figure 8C.

[0084] In a recording device 900 equipped with a recording head 810 that has been reused for the second time, for example, when the remaining ink level reaches a predetermined amount, the recording device control circuit 214 determines whether or not to reuse the recording head based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a low level, the device control circuit 214 determines that it is reusable and displays the determination result on an unshown display unit. The user can understand from the displayed determination result that the recording head 810 is reusable.

[0085] When reusing the recording head 810 after running out of ink (for the third time), the recording head 810 is mounted on the control device of the regeneration equipment. The control device determines whether or not it can be reused based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a low level, the control device determines that it can be reused and displays the result. The operator can understand from the displayed result that the recording head 810 can be reused. Since it can be reused, the optimal ejection energy is measured using a dedicated inspection device, and the optimal rank value is stored in the fourth block (memory circuits M116~M120). At this time, the counter circuit CM2 of the recording head 810 is in the state shown in Figure 8D.

[0086] In a recording device 900 equipped with a recording head 810 that has been reused for the third time, for example, when the remaining ink level reaches a predetermined amount, the recording device control circuit 214 determines whether or not to reuse the head based on the count-up feasibility flag C_UP. In this case, since the count-up feasibility flag C_UP is at a high level, the device control circuit 214 determines that reuse is not possible and displays the determination result on an unshown display unit. The user can understand from the displayed determination result that the recording head 810 cannot be reused.

[0087] As described above, with the recording head 810 of this embodiment, it is possible to easily determine whether the memory circuit can be rewritten or reused based on the count-up flag C_UP. As a result, for example, when performing reuse, the optimal conditions for the recording head 810 can be quickly saved.

[0088] (Fourth embodiment) The recording head 810 according to the fourth embodiment of the present invention differs from that of the third embodiment in that it has a fuse element F4 instead of the antifuse element A1 in each of the memory circuits M101 to M120. Aside from this configuration, it is basically the same as that of the third embodiment.

[0089] Memory circuits M101 to M120 will be referred to as memory circuit M, and its configuration will be described in detail. Figure 12A is a schematic diagram of memory circuit M. This memory circuit M is the same as memory circuit M shown in Figure 11A, but with the antifuse element A1 replaced by the fuse element F4. The same components are denoted by the same reference numerals, and their detailed explanations are omitted.

[0090] One end of the fuse element F4 is connected to terminal VHT via the ROM write power supply control element 130, and the other end of the fuse element F4 is grounded via transistor J3. The ROM write power supply control element 130 is an element that applies write power to the fuse element F4 when the recording device control circuit 214 sets the memory circuit M to the write state. Power VHT is applied to the fuse element F4 via the ROM write power supply control element 130. Transistor J3, drive voltage conversion element K3, and step-down circuit 120 are the same as those described in the third embodiment.

[0091] The method for disconnecting (making non-conductive) the fuse element F4 is described below. To disconnect the fuse element F4, the ROM writing power control element 130 is turned ON and transistor J3 is turned ON, allowing current to flow through the fuse element F4. A large current flows through the fuse element F4, causing it to heat up, and then it melts and becomes non-conductive. Figure 12B schematically shows the memory circuit M with the fuse element F4 in a non-conductive state.

[0092] The recording device control circuit 214 can disconnect the fuse element F4 of any of the memory circuits M101 to M120 by controlling the shift register 111. The following describes the procedure for disconnecting the fuse element F4 of memory circuit M101 as an example.

[0093] The constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element substrate 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815. Next, the recording device control circuit 214 outputs a signal to the shift register 111, controlling the drive voltage conversion element K3 of memory circuit M101 to a high level and the drive voltage conversion elements K3 of the other memory circuits M102~M120 to a low level. In memory circuit M101, transistor J3 turns ON, and the 24[V] voltage supplied to terminal IM is applied to fuse element F4. Because the resistance value of fuse element F4 is very small, a large current flows through fuse element F4. As a result, fuse element F4 heats up and then melts.

[0094] In the recording head 810 of this embodiment, as in the third embodiment, the optimal driving conditions for the recording head 810 are maintained using memory circuits M101 to M120. Specifically, the optimal ejection energy is managed as rank values ​​1 to 31, and the optimal rank value is stored for each block of memory circuits M101 to M120.

[0095] In the recording head 810 of this embodiment, the recording device control circuit 214 may also display the count value of the counter circuit CM2 and the result of the determination of whether the memory can be rewritten based on the count-up flag C_UP on a display unit (not shown). This allows the user to easily understand the remaining number of rewrites for the counter circuit CM2 and whether the memory can be rewritten based on the display result.

[0096] Furthermore, in the recording head 810 of this embodiment, the number of reuses can be managed using the counter circuit CM2, similar to the first and second embodiments. In addition, it is possible to determine whether the recording head 810 is reusable based on the count-up feasibility flag C_UP. The process for determining reusability using the count-up feasibility flag C_UP is the same as in the third embodiment, so its explanation will be omitted.

[0097] (Fifth embodiment) A recording head 810 according to a fifth embodiment of the present invention has a counter circuit in which a plurality of series sections, each consisting of an antifuse element and a fuse element connected in series, are connected in parallel. The counter circuit is configured such that a count value is set based on the combination of the conduction state and the non-conduction state of the fuse element and antifuse element in each series section. The counter circuit has an output section that outputs a count value corresponding to the combination of the conduction state and the non-conduction state of the fuse element and antifuse element in each series section.

[0098] Figures 13A to 13I are schematic diagrams illustrating an example of the counter circuit of the recording head 810 in this embodiment. Referring to Figures 13A to 13I, the element substrate 100 of the recording head 810 has a counter circuit CM3, a step-down circuit 120, and a shift register 110. The step-down circuit 120 and the shift register 110 are the same as those described in the first embodiment.

[0099] The counter circuit CM3 has first to fourth series sections connected in parallel, an output section 10, a transistor J2, and a drive voltage conversion element K2. The transistor J2 and the drive voltage conversion element K2 are the same as those described in the first embodiment. The first series section consists of an antifuse element A11 and a fuse element F11 connected in series. The second series section consists of an antifuse element A12 and a fuse element F12 connected in series. The third series section consists of an antifuse element A13 and a fuse element F13 connected in series. The fourth series section consists of an antifuse element A14 and a fuse element F14 connected in series. One end of each series section (the part to which one end of fuse elements F11 to F14 is connected) is connected to terminal IM and also to terminal MN via buffer element L1. The other end of each series section (the part to which one end of antifuse elements A11 to A14 is connected) is grounded via transistor J2. Note that the number of series sections connected in parallel is not limited to four. The number of series connections may be three or five or more.

[0100] The output unit 10 outputs a signal indicating a count value corresponding to the combination of conduction and non-conduction states of each series fuse element (F11~F14) and antifuse element (A11~A14). The output unit 10 has inverting buffers NOT1~4. Inverting buffer NOT1 takes the voltage at the connection point (node) of the first series fuse element F11 and antifuse element A11 as input and supplies the inverted output of the input voltage to the bit0 terminal. Inverting buffer NOT2 takes the voltage at the connection point (node) of the second series fuse element F12 and antifuse element A12 as input and supplies the inverted output of the input voltage to the bit1 terminal. Inverting buffer NOT3 takes the voltage at the connection point (node) of the third series fuse element F13 and antifuse element A13 as input and supplies the inverted output of the input voltage to the bit2 terminal. The inverting buffer NOT4 takes the voltage at the connection point (node) between the fourth series fuse element F14 and the antifuse element A14 as input, and supplies the inverted output of the input voltage to the bit3 terminal.

[0101] The counter circuit CM3 is configured to count up in the order of 0, 2, 4, 6, and 8, and the counter value can be read when terminal MN is at a high level. The operation of writing the count value to the counter circuit CM3 is described below.

[0102] Figure 13A shows the initial state of the counter circuit CM3. In the initial state of the counter circuit CM3, antifuse elements A11 to A14 are all in a non-conducting state, and fuse elements F11 to F14 are all in a conducting state. In this case, the input voltages of inverting buffers NOT1 to NOT4 are all at a high level, so the outputs of inverting buffers NOT1 to NOT4 are all at a low level. The count value can be read by setting terminal MN to a high level.

[0103] Next, we will explain the procedure for setting the count value "2" in the counter circuit CM3. First, in order to activate the antifuse element A11, the constant voltage control circuit 207 outputs a DC voltage of 24[V] to terminal IM of the element board 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815.

[0104] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to the antifuse element A11. By rapidly switching the voltage application ON / OFF on the antifuse element A11, the gate oxide film between the two electrodes of the antifuse element A11 is broken down, resulting in conductivity. For example, by repeatedly switching the voltage application ON / OFF at a frequency of 6[MHz], the antifuse element A11 can be made to conduct. The number of ON / OFF cycles of voltage application is set to a maximum of 60,000 times.

[0105] Figure 13B schematically shows the state of the counter circuit CM3 with the antifuse element A11 in the conductive state. In this case, since the input voltages of inverting buffers NOT1 to NOT4 are all at a low level, the outputs of inverting buffers NOT1 to NOT4 are all at a high level. Since terminal MN is at a low level, the count value is not read out.

[0106] After the antifuse element A11 is made conductive, the fuse element F11 is then disconnected. Specifically, the constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element board 100. The 24[V] voltage is supplied to terminal IM via the contact pad 815.

[0107] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to fuse element F11. Because the resistance of fuse element F11 is very small, a large current flows through it. As a result, fuse element F11 heats up and then melts. For example, fuse element F11 melts when a current of 70mA or more flows through it.

[0108] Figure 13C schematically shows the state of the counter circuit CM3 when the fuse element F11 is in a non-conducting state. In this case, the input voltage of inverting buffer NOT1 is at a low level, and the input voltages of inverting buffers NOT2 to NOT4 are all at a high level. Therefore, the output of inverting buffer NOT1 is at a high level, and the outputs of inverting buffers NOT2 to NOT4 are all at a low level. The count value can be read by setting terminal MN to a high level.

[0109] Next, we will explain the procedure for setting the count value "4" in the counter circuit CM3. First, in order to activate the antifuse element A12, the constant voltage control circuit 207 outputs a DC voltage of 24[V] to terminal IM of the element board 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815.

[0110] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to the antifuse element A12. By rapidly switching the voltage application to the antifuse element A12 ON and OFF, the antifuse element A12 becomes conductive. This operation is the same as when the antifuse element A11 is conductive.

[0111] Figure 13D schematically shows the state of the counter circuit CM3 with the antifuse element A12 in the conductive state. In this case, since the input voltages of inverting buffers NOT1 to NOT4 are all at a low level, the outputs of inverting buffers NOT1 to NOT4 are all at a high level. Since terminal MN is at a low level, the count value is not read out.

[0112] After the antifuse element A12 is made conductive, the fuse element F12 is subsequently disconnected. Specifically, the constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element board 100. The 24[V] voltage is supplied to terminal IM via the contact pad 815.

[0113] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to fuse element F12. Because the resistance of fuse element F12 is very small, a current (e.g., 70mA) flows through fuse element F12. As a result, fuse element F12 heats up and then melts.

[0114] Figure 13E schematically shows the state of the counter circuit CM3 when the fuse element F12 is in a non-conducting state. In this case, the input voltages of inverting buffers NOT1 and NOT2 are both at a low level, and the input voltages of inverting buffers NOT3 and NOT4 are both at a high level. Therefore, the outputs of inverting buffers NOT1 and NOT2 are both at a high level, and the outputs of inverting buffers NOT3 and NOT4 are both at a low level. The count value can be read by setting terminal MN to a high level.

[0115] Next, we will explain the procedure for setting the count value "6" in the counter circuit CM3. First, in order to activate the antifuse element A13, the constant voltage control circuit 207 outputs a DC voltage of 24[V] to terminal IM of the element board 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815.

[0116] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to the antifuse element A13. By rapidly switching the voltage application to the antifuse element A13 ON and OFF, the antifuse element A13 becomes conductive. This operation is the same as when the antifuse element A11 is conductive.

[0117] Figure 13F schematically shows the state of the counter circuit CM3 with the antifuse element A13 in the conductive state. In this case, since the input voltages of inverting buffers NOT1 to NOT4 are all at a low level, the outputs of inverting buffers NOT1 to NOT4 are all at a high level. Since terminal MN is at a low level, the count value is not read out.

[0118] After the antifuse element A13 is made conductive, the fuse element F13 is then disconnected. Specifically, the constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element board 100. The 24[V] voltage is supplied to terminal IM via the contact pad 815.

[0119] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to fuse element F13. Because the resistance of fuse element F13 is very small, a current (e.g., 70mA) flows through fuse element F13. As a result, fuse element F13 heats up and then melts.

[0120] Figure 13G schematically shows the state of the counter circuit CM3 when fuse element F13 is in a non-conducting state. In this case, the input voltages of inverting buffers NOT1 to NOT3 are all at a low level, and the input voltage of inverting buffer NOT4 is at a high level. Therefore, the outputs of inverting buffers NOT1 to NOT3 are all at a high level, and the output of inverting buffer NOT4 is at a low level. The count value can be read by setting terminal MN to a high level.

[0121] Next, we will explain the procedure for setting the count value "8" in the counter circuit CM3. First, in order to activate the antifuse element A14, the constant voltage control circuit 207 outputs a DC voltage of 24[V] to terminal IM of the element board 100. The DC voltage of 24[V] is supplied to terminal IM via the contact pad 815.

[0122] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to the antifuse element A14. By rapidly switching the voltage application to the antifuse element A14 ON and OFF, the antifuse element A14 becomes conductive. This operation is the same as when the antifuse element A11 is conductive.

[0123] Figure 13H schematically shows the state of the counter circuit CM3 with the antifuse element A14 in the conductive state. In this case, since the input voltages of inverting buffers NOT1 to NOT4 are all at a low level, the outputs of inverting buffers NOT1 to NOT4 are all at a high level. Since terminal MN is at a low level, the count value is not read out.

[0124] After the antifuse element A14 is made conductive, the fuse element F14 is then disconnected. Specifically, the constant voltage control circuit 207 supplies a DC voltage of 24[V] to terminal IM of the element board 100. The 24[V] voltage is supplied to terminal IM via the contact pad 815.

[0125] Next, the recording device control circuit 202 outputs a signal to the shift register 110, controlling the drive voltage conversion element K2 of the counter circuit CM3 to a high level. As a result, transistor J2 turns ON, and the 24[V] voltage supplied to terminal IM is applied to fuse element F14. Because the resistance of fuse element F14 is very small, a current (e.g., 70mA) flows through fuse element F14. As a result, fuse element F14 heats up and then melts.

[0126] Figure 13I schematically shows the state of the counter circuit CM3 when fuse element F14 is in a non-conducting state. In this case, since the input voltages of inverting buffers NOT1 to NOT4 are all at a low level, the outputs of inverting buffers NOT1 to NOT4 are all at a high level. By setting terminal MN to a high level, the count value can be read out.

[0127] Next, we will explain how to read the counter value of the counter circuit CM3. To read the counter value, first, a constant current is applied to terminal IM of the element board 100, and the shift register 110 is controlled to turn on transistor J2. In this embodiment, the constant current control circuit 206 applies a current of 65 [μA] to terminal IM. In this state, the recording device control circuit 202 reads the counter value from the voltages of the terminal of the lower bit 0 and the terminal of the upper bit 3 of the counter. Bits 0 and 3 of the counter are in the 3.3 [V] system, with a low level or "0" when around 0.0 [V] and a high level or "1" when around 3.3 [V]. In each series section, the resistance value of the antifuse elements A11 to A14 after conduction is designed to be 2 [kΩ].

[0128] In the initial state of the counter circuit CM3 shown in Figure 13A, the resistance values ​​of the fuse elements F11 to F14 are all approximately 400[Ω], and the resistance values ​​of the antifuse elements A11 to A14 are all approximately 100[kΩ]. The input voltage of buffer element L1 is 3.3[V], which is close to the power supply voltage of the constant current control circuit 206, and therefore exceeds the input threshold value of buffer element L1 of 2.0[V]. As a result, the output of buffer element L1 becomes high level, and terminal MN becomes high level. The input voltages of inverting buffers NOT1 to NOT4 are also 3.3[V], which is close to the power supply voltage of the constant current control circuit 206, and therefore exceed the input threshold value of inverting buffers NOT1 to NOT4 of 2.0[V]. As a result, the outputs of inverting buffers NOT1 to NOT4 become low level, and counter bits 0 to 3 become low level. Based on counter bits 0 to 3 at this time, the count value "0" can be read.

[0129] In the counter circuit CM3 shown in Figure 13B, the resistance values ​​of fuse elements F11 to F14 are all approximately 400[Ω], and the resistance value of antifuse element A11 is approximately 2[kΩ]. 65[μA] is applied to terminal IM to turn on transistor J2. The input voltage of buffer element L1 becomes 1.3[V], which is below the input threshold value of buffer element L1 (2.0[V]). Therefore, the output of buffer element L1 becomes low, and terminal MN becomes low. The input voltage of inverting buffers NOT1 to NOT4 also becomes 1.3[V], which is below the input threshold value of inverting buffers NOT1 to NOT4 (2.0[V]). Therefore, the outputs of inverting buffers NOT1 to NOT4 become high. Since terminal MN is low, the counter value is undefined.

[0130] In the counter circuit CM3 shown in Figure 13C, the resistance of fuse element F11 is 1 [MΩ], and the resistance of antifuse element A11 is approximately 2 [kΩ]. 65 [μA] is applied to terminal IM, turning on transistor J2. The input voltage of buffer element L1 becomes 3.3 [V], near the power supply voltage of the constant current control circuit 206, thus exceeding the input threshold of buffer element L1. As a result, the output of buffer element L1 becomes high, and terminal MN becomes high. The input voltage of inverting buffer NOT1 becomes 0.0 [V], and the output of inverting buffer NOT1 becomes high. The input voltages of inverting buffers NOT2 to NOT4 become 3.3 [V], near the power supply voltage of the constant current control circuit 206, and the outputs of inverting buffers NOT2 to NOT4 become low. As a result, counter bit0 becomes high, and counter bits 1 to 3 become low. Based on counter bits 0 to 3 at this time, the count value "2" can be read.

[0131] In the counter circuit CM3 shown in Figure 13D, the resistance values ​​of fuse elements F12 to F14 are all 400 [kΩ], and the resistance values ​​of antifuse elements A11 and A12 are all approximately 2 [kΩ]. 65 [μA] is applied to terminal IM, and transistor J2 is turned ON. The input voltage of buffer element L1 becomes 0.286 [V], which is below the input threshold value of buffer element L1, 2.0 [V]. Therefore, the output of buffer element L1 becomes low, and terminal MN becomes low. The input voltage of inverting buffers NOT1 to NOT4 also becomes 1.3 [V], which is below the input threshold value of inverting buffers NOT1 to NOT4, 2.0 [V]. Therefore, the output of inverting buffers NOT1 to NOT4 becomes high. Since terminal MN is low, the counter value is undefined.

[0132] In the counter circuit CM3 shown in Figure 13E, the resistance values ​​of fuse elements F11 and F12 are both 1 [MΩ], and the resistance values ​​of antifuse elements A11 and A12 are both approximately 2 [kΩ]. 65 [μA] is applied to terminal IM to turn on transistor J. The input voltage of buffer element L1 becomes 3.3 [V], near the power supply voltage of the constant current control circuit 206, and exceeds the input threshold of buffer element L1. Therefore, the output of buffer element L1 becomes high, and terminal MN also becomes high. The input voltages of inverting buffers NOT1 and NOT2 become 0.0 [V], and the outputs of inverting buffers NOT1 and NOT2 become high. The input voltages of inverting buffers NOT3 and NOT4 become 3.3 [V], near the power supply voltage of the constant current control circuit 206, and the outputs of inverting buffers NOT3 and NOT4 become low. As a result, counter bits 0 and 1 become high, and counter bits 2 and 3 become low. Based on the counter bits 0 to 3 at this time, the count value "4" can be read.

[0133] In the counter circuit CM3 shown in Figure 13F, the resistance values ​​of fuse elements F13 and F14 are both 400[Ω], and the resistance values ​​of antifuse elements A11~A13 are both 2[kΩ]. 65[μA] is applied to terminal IM to turn on transistor J2. The input voltage of buffer element L1 becomes 0.416[V], which is below the input threshold voltage of buffer element L1, 2.0[V]. Therefore, the output of buffer element L1 becomes low, and terminal MN also becomes low. Since terminal MN is low, the counter value is undefined.

[0134] In the counter circuit CM3 shown in Figure 13G, the resistance values ​​of the fuse elements F11 to F13 are all 1 [MΩ], and the resistance values ​​of the antifuse elements A11 to A13 are all approximately 2 [kΩ]. 65 [μA] is applied to terminal IM to turn on transistor J2. The input voltage of buffer element L1 becomes 3.3 [V], near the power supply voltage of the constant current control circuit 206, and exceeds the input threshold of buffer element L1. As a result, the output of buffer element L1 becomes high, and terminal MN also becomes high. The input voltage of inverting buffers NOT1 to NOT3 becomes 0.0 [V], and the outputs of inverting buffers NOT1 to NOT3 become high. The input voltage of inverting buffer NOT4 becomes 3.3 [V], near the power supply voltage of the constant current control circuit 206, and the output of inverting buffer NOT4 becomes low. As a result, counter bits 0 to 2 become high, and counter bit 3 becomes low. Based on the counter bits 0 to 3 at this time, the count value "6" can be read.

[0135] In the counter circuit CM3 shown in Figure 13H, the resistance of fuse element F14 is 400[Ω], and the resistances of antifuse elements A11~A14 are all 2[kΩ]. 65[μA] is applied to terminal IM, turning on transistor J2. The input voltage of buffer element L1 becomes 0.546[V], which is below the input threshold voltage of buffer element L1 (2.0[V]). Therefore, the output of buffer element L1 becomes low, and terminal MN also becomes low. Since terminal MN is low, the counter value is undefined.

[0136] In the counter circuit CM3 shown in Figure 13I, the resistance values ​​of the fuse elements F11 to F14 are all 1 [MΩ], and the resistance values ​​of the antifuse elements A11 to A14 are all approximately 2 [kΩ]. 65 [μA] is applied to terminal IM to turn on transistor J2. The input voltage of buffer element L1 becomes 3.3 [V], which is close to the power supply voltage of the constant current control circuit 206, and thus exceeds the input threshold of buffer element L1. As a result, the output of buffer element L1 becomes high, and terminal MN also becomes high. The input voltage of inverting buffers NOT1 to NOT4 becomes 0.0 [V], and the outputs of inverting buffers NOT1 to NOT3 become high. Consequently, counter bits 0 to 3 become high. Based on counter bits 0 to 3 at this time, the count value "8" can be read. The above explains how to write and read the counter value of the counter circuit CM3.

[0137] According to the recording head 810 of this embodiment, the counter circuit CM3 can be rewritten multiple times, and the remaining number of rewrites can be easily determined based on the output (count value) of the output unit 10. For example, the recording device control circuit 202 may acquire the counter value of the counter circuit CM3 based on the values ​​of counter bits 0 to 3, and display the acquired counter value on a display unit (not shown). This allows the user to easily determine the remaining number of rewrites of the counter circuit CM3 based on the displayed count value.

[0138] In the recording head 810 of this embodiment, the number of memory rewrites may be counted using a counter circuit CM3. This makes it easy to determine whether the memory can be rewritten based on the count value of the counter circuit CM3. Furthermore, a logic element AND may be provided to take the logical AND operation between the output of buffer element L1 and the output of inverting buffer NOT4, and the output of this logic element AND may be used as the count-up permission flag C_UP. This makes it easy to determine whether the counter circuit CM3 can be rewritten or whether the memory can be rewritten based on the count-up permission flag C_UP.

[0139] This embodiment includes the following configuration. (Composition 1) A semiconductor device comprising a counter circuit configured by combining an antifuse element and a fuse element, wherein a count value is set by the combination of the conductive state and the non-conductive state of the fuse element and the antifuse element, and the count value set in the counter circuit is incremented by sequentially rewriting the fuse element from a conductive state to a non-conductive state and the antifuse element from a non-conductive state to a conductive state, A semiconductor device characterized by having an output unit that outputs a signal corresponding to the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element in the counter circuit. (Configuration 2) The semiconductor device according to configuration 1, wherein the output unit outputs a signal indicating a count value corresponding to the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element. (Composition 3) The semiconductor device according to configuration 1, wherein the output unit outputs a flag signal indicating that the count value has reached its upper limit when the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element reaches a predetermined combination. (Composition 4) The counter circuit comprises a series section in which an antifuse element and a first fuse element are connected in series, and a second fuse element connected in parallel to the series section, and the count value is set by the combination of the conduction state and the non-conduction state of the first and second fuse elements and the antifuse element, as described in any one of configurations 1 to 3. (Composition 5) The semiconductor device according to any one of configurations 1 to 3, characterized in that the counter circuit has a plurality of series sections, each consisting of an antifuse element and a fuse element connected in series, connected in parallel, and the count value is set by the combination of the conduction state and the non-conduction state of the fuse element and antifuse element in each series section. (Composition 6) It has a memory circuit that allows data to be written to and rewritten, and has an upper limit on the number of rewrites. The semiconductor device according to any one of configurations 1 to 5, characterized in that the counter circuit is configured to count the number of times the memory circuit is rewritten. (Composition 7) The semiconductor device according to configuration 6, characterized in that the output unit outputs a flag signal indicating whether or not the count value of the counter circuit has reached the upper limit of the number of rewrites of the memory circuit. (Composition 8) The semiconductor device according to configuration 6 or 7, characterized in that the memory circuit has a plurality of memory circuits each consisting of a fuse element or an antifuse element, and each memory circuit is connected in parallel with the others. (Composition 9) It has an element substrate on which a recording element for discharging liquid is formed, The recording head is characterized in that the element substrate includes a semiconductor device described in any one of configurations 1 to 8. (Composition 10) The recording head according to configuration 9, characterized in that the counter circuit is configured to count the number of times the recording head is reused. (Composition 11) The recording head according to configuration 9, wherein the element substrate has a data rewritable memory circuit using an antifuse element or a fuse element, and the counter circuit counts the number of times the memory circuit is rewritten. (Composition 12) The recording head according to configuration 11, characterized in that it stores data relating to the energy for discharging the liquid in the memory circuit. (Composition 13) A recording head according to any one of configurations 9 to 12, characterized in that the element substrate has terminals for outputting the signal output by the output section of the counter circuit. [Explanation of Symbols]

[0140] 10 Output section CM1 Counter Circuit F1, F2 fuse elements A Antifuse element 100 element substrate

Claims

1. A semiconductor device comprising a counter circuit configured by combining an antifuse element and a fuse element, wherein a count value is set by the combination of the conductive state and the non-conductive state of the fuse element and the antifuse element, and the count value set in the counter circuit is incremented by sequentially rewriting the fuse element from a conductive state to a non-conductive state and the antifuse element from a non-conductive state to a conductive state, A semiconductor device characterized by having an output unit that outputs a signal corresponding to the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element in the counter circuit.

2. The semiconductor device according to claim 1, wherein the output unit outputs a signal indicating a count value corresponding to the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element.

3. The semiconductor device according to claim 1, characterized in that the output unit outputs a flag signal indicating that the count value has reached its upper limit when the combination of the conduction state and the non-conduction state of the fuse element and the antifuse element reaches a predetermined combination.

4. The semiconductor device according to claim 1, wherein the counter circuit comprises a series section in which an antifuse element and a first fuse element are connected in series, and a second fuse element connected in parallel to the series section, and the count value is set by the combination of the conduction state and the non-conduction state of the first and second fuse elements and the antifuse element, respectively.

5. The semiconductor device according to claim 1, characterized in that the counter circuit has a plurality of series sections, each consisting of an antifuse element and a fuse element connected in series, connected in parallel, and the count value is set by the combination of the conduction state and the non-conduction state of the fuse element and antifuse element in each series section.

6. It has a memory circuit that allows data to be written to and rewritten, and has an upper limit on the number of rewrites. The semiconductor device according to any one of claims 1 to 5, characterized in that the counter circuit is configured to count the number of times the memory circuit is rewritten.

7. The semiconductor device according to claim 6, characterized in that the output unit outputs a flag signal indicating whether or not the count value of the counter circuit has reached the upper limit of the number of rewrites of the memory circuit.

8. The semiconductor device according to claim 6, characterized in that the memory circuit has a plurality of memory circuits each consisting of a fuse element or an antifuse element, and each memory circuit is connected in parallel with the others.

9. It has an element substrate on which a recording element for discharging liquid is formed, The recording head is characterized in that the element substrate includes the semiconductor device described in claim 1.

10. The recording head according to claim 9, characterized in that the counter circuit is configured to count the number of times the recording head is reused.

11. The recording head according to claim 9, wherein the element substrate has a data rewritable memory circuit using an antifuse element or a fuse element, and the counter circuit counts the number of times the memory circuit is rewritten.

12. The recording head according to claim 11, characterized in that it stores data relating to the energy for discharging the liquid in the memory circuit.

13. The recording head according to claim 9, characterized in that the element substrate has terminals for outputting the signal output by the output section of the counter circuit.

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