Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can reduce both conduction loss and turn-off loss. [Solution] The semiconductor device of the embodiment has a first electrode and a second electrode spaced apart in a first direction. It has a plurality of control electrodes spaced apart in a second direction. It has a connecting electrode electrically connected to the first electrode. It has a first semiconductor layer of a first conductivity type electrically connected to the first electrode. It has a second semiconductor layer of a first conductivity type insulated from the first electrode. The plurality of regions sandwiched between adjacent control electrodes are either channel regions where the first semiconductor layer is located or floating regions where the second semiconductor layer is located. The plurality of control electrodes include a plurality of first control electrodes and a plurality of second control electrodes. The floating region includes a first floating region where at least one of the control electrodes sandwiching the floating region is a second control electrode. The connecting electrode is located in the first floating region.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] As semiconductor devices, bipolar elements such as IGBTs are well known. Compared to unipolar elements, bipolar elements can increase the carrier concentration in the base layer when on (conducting). This makes it easier to reduce the electrical resistance of the base layer in the on state, and thus easier to reduce conduction losses. However, bipolar elements require time to discharge the carriers accumulated in the base layer when turned off, making it difficult to reduce turn-off losses. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 6407455 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can reduce both conduction loss and turn-off loss. [Means for solving the problem]

[0005] The semiconductor device of the embodiment has a first electrode and a second electrode spaced apart from each other in a first direction. It has a plurality of control electrodes spaced apart along a second direction intersecting the first direction, and positioned between the first electrode and the second electrode. It has a connecting electrode electrically connected to the first electrode. It has a first semiconductor layer of a first conductivity type electrically connected to the first electrode. It has a second semiconductor layer of a first conductivity type electrically insulated from the first electrode. It has a third semiconductor layer of a second conductivity type positioned between the second electrode and each of the first and second semiconductor layers. It has a fourth semiconductor layer of a first conductivity type positioned between the second electrode and the third semiconductor layer. Each of the first, second, third, and fourth semiconductor layers is positioned between the first and second electrodes. Each of the plurality of regions sandwiched between adjacent control electrodes positioned in the second direction is either a channel region where the first semiconductor layer is positioned, or a floating region where the second semiconductor layer is positioned. The multiple control electrodes include a plurality of first control electrodes to which a first voltage is applied, and a plurality of second control electrodes to which a second voltage is applied. The floating region includes a first floating region to which at least one of the control electrodes flanking the floating region is a second control electrode. A connecting electrode is placed in the first floating region. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view showing a semiconductor device of the first embodiment. [Figure 2] A schematic diagram showing a semiconductor device of the first embodiment. [Figure 3] A timing chart showing the control signal, first voltage, and second voltage of a semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view showing the carrier behavior of the semiconductor device of the first embodiment during the first period. [Figure 5] A schematic cross-sectional view showing the carrier behavior of the semiconductor device of the first embodiment during the second period. [Figure 6] A schematic cross-sectional view showing the carrier behavior of the semiconductor device in the second period of the comparative example. [Figure 7]A schematic cross-sectional view showing the carrier behavior of the semiconductor device of the first embodiment during the third period. [Figure 8] A schematic cross-sectional view showing a semiconductor device of the second embodiment. [Figure 9] A schematic cross-sectional view showing the carrier behavior of the semiconductor device of the second embodiment during the second period. [Figure 10] A schematic cross-sectional view showing a semiconductor device of the third embodiment. [Figure 11] A schematic cross-sectional view showing the carrier behavior of the semiconductor device of the third embodiment during the second period. [Modes for carrying out the invention]

[0007] The semiconductor device of the embodiment will be described below with reference to the drawings.

[0008] The first direction D1, as shown appropriately in each drawing, is parallel to the thickness direction of the semiconductor device. The side in which the arrow of the first direction D1 points (+D1 side) is the upper side of the semiconductor device. The side opposite to the direction in which the arrow of the first direction D1 points (-D1 side) is the lower side of the semiconductor device. In the following explanation, the upper side of the semiconductor device will be simply referred to as the "upper side," and the lower side of the semiconductor device will be simply referred to as the "lower side." Note that "upper side" and "lower side" are not terms that indicate a relationship to the direction of gravity.

[0009] The second direction D2, as shown appropriately in each drawing, is the direction that intersects with the first direction D1. In this embodiment, the second direction D2 is perpendicular to the first direction D1. The second direction D2 does not have to be perpendicular to the first direction D1. The side in which the arrow of the second direction D2 points (+D2 side) is the right side of the semiconductor device. The side opposite to the side in which the arrow of the second direction D2 points (-D2 side) is the left side of the semiconductor device. In the following description, the right side of the semiconductor device will be simply referred to as the "right side," and the left side of the semiconductor device will be simply referred to as the "left side."

[0010] The third direction D3, as shown appropriately in each drawing, is a direction perpendicular to the first direction D1 and the second direction D2, respectively.

[0011] Note that "upper side," "lower side," "right side," and "left side" are merely names used to describe the arrangement of the various parts that make up the semiconductor device, and the actual arrangement may differ from those indicated by these names.

[0012] In this specification, terms such as "orthogonal," "identical," "similar," and "parallel," as well as length values, which specify the shape of each part constituting a semiconductor device and the degree of the relative arrangement between each part, shall not be bound by their strict meaning, but shall be interpreted to include a range within which similar functions can be expected and the range of design tolerances.

[0013] In this specification, N + , N, N - , P + The notation , and P represent the relative magnitudes of carrier concentrations in each conductivity type. + This indicates that the concentration of N-type carriers is relatively higher than that of N. - This indicates that the concentration of N-type carriers is relatively lower than that of N. + This indicates that the carrier concentration of type P is relatively higher than that of type P. Furthermore, in this specification, type P is the first conductivity type, and type N is the second conductivity type.

[0014] In this specification, the carrier concentration in a semiconductor region can be measured, for example, using a cyclic voltammetry (CV) detector. Alternatively, the carrier concentration in a semiconductor region may be calculated from the impurity concentration measured, for example, using a secondary ion mass spectrometer (SIMS). The relative magnitudes of the carrier concentrations in two semiconductor regions can be determined, for example, using a scanning capacitance microscope (SCM). Furthermore, the distribution and absolute values ​​of the carrier concentrations can be measured, for example, using spreading resistance analysis (SRA).

[0015] (First Embodiment) FIG. 1 is a schematic cross-sectional view showing a semiconductor device 20 of the present embodiment. The semiconductor device 20 of the present embodiment is a bipolar element such as an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 20 is used as a power semiconductor device. The semiconductor device 20 can be used as a switching element. As shown in FIG. 1, the semiconductor device 20 includes an emitter electrode 21, a collector electrode 23, an insulating layer 24, an N + type emitter layer 25, a P + type contact layer 27, a P-type base layer 29, a P-type floating layer 30, an N - type base layer 31, a P-type collector layer 33, a control electrode 35, a first insulating film 37, a second insulating film 40, a connection electrode 43, and a third insulating film 44.

[0016] The emitter electrode 21 extends in a direction orthogonal to the first direction D1. In the present embodiment, the emitter electrode 21 is a first electrode. That is, the semiconductor device 20 includes a first electrode. The emitter electrode 21 may contain a metal that exhibits Schottky characteristics with respect to an N-type semiconductor. The emitter electrode 21 is composed of, for example, at least one metal material selected from aluminum, copper, tantalum, silver, molybdenum, tungsten, cobalt, chromium, ruthenium, gold, palladium, nickel, and platinum.

[0017] The collector electrode 23 extends in a direction orthogonal to the first direction D1. The collector electrode 23 is arranged at a distance from the emitter electrode 21 in the first direction D1. The collector electrode 23 is arranged on the lower side (-D1 side) of the emitter electrode 21. In the present embodiment, the collector electrode 23 is a second electrode. That is, the semiconductor device 20 includes a second electrode. The collector electrode 23 is made of metal.

[0018] The insulating layer 24 is positioned between the emitter electrode 21 and the collector electrode 23. The insulating layer 24 extends in a direction perpendicular to the first direction D1. The upper side (+D1 side) of the insulating layer 24 is in contact with the lower side (-D1 side) of the emitter electrode 21. The insulating layer 24 has insulating properties. For example, silicon oxide can be used as the material constituting the insulating layer 24. The insulating layer 24 is provided with a plurality of holes that penetrate the insulating layer 24 in the first direction D1. Each hole accommodates a protrusion 21a, which is part of the emitter electrode 21 and protrudes downward.

[0019] The control electrode 35 is an electrode that controls the on and off operation of the semiconductor device 20. The control electrode 35 is positioned between the emitter electrode 21, i.e., the first electrode, and the collector electrode 23, i.e., the second electrode. The control electrode 35 extends in both the first direction D1 and the third direction D3. The upper (+D1 side) end of the control electrode 35 is in contact with the lower (-D1 side) surface of the insulating layer 24. The control electrode 35 is made of a semiconductor material with impurities added. The semiconductor device 20 comprises a plurality of control electrodes 35. Each control electrode 35 is spaced apart along the second direction D2. The plurality of control electrodes 35 includes a plurality of first control electrodes 36 and a plurality of second control electrodes 39.

[0020] A first voltage Vg1, described later, is applied to each first control electrode 36. Each first control electrode 36 is arranged with a gap between them in the second direction D2.

[0021] A second voltage Vg2, described later, is applied to each second control electrode 39. In this embodiment, by controlling the second voltage Vg2, N - The discharge of holes accumulated in the mold base layer 31 is controlled. In this embodiment, each second control electrode 39 is positioned between two pairs of first control electrodes 36. In this embodiment, each first control electrode 36 and each second control electrode 39 are made of the same material.

[0022] Although Figure 1 shows an example where the structure of the first control electrode 36 and the structure of the second control electrode 39 are the same, the structures of the first control electrode 36 and the second control electrode 39 may be different from each other. For example, the dimensions of the first control electrode 36 in the first direction D1 and the dimensions of the second direction D2 may be different from the dimensions of the second control electrode 39 in the first direction D1 and the dimensions of the second direction D2, respectively. Furthermore, the number of first control electrodes 36 and the number of second control electrodes 39 are not limited to the numbers shown in Figure 1.

[0023] In this embodiment, each of the multiple regions sandwiched between adjacent control electrodes 35 in the second direction D2 is either a channel region Rc or a floating region Rf. In this embodiment, the channel region Rc is the region between adjacent first control electrodes 36 and the region between adjacent second control electrodes 39. The channel region Rc is N + Type emitter layer 25, P + Type contact layer 27, P-type base layer 29, and N - This is the region where a part of the type base layer 31 is arranged. In this embodiment, the floating region Rf is the region other than the channel region Rc among a plurality of regions sandwiched between control electrodes 35 arranged adjacent to each other in the second direction D2. The floating region Rf is the region where the P-type floating layer 30, the connecting electrode 43, and the third insulating film 44 are arranged. In this embodiment, the floating region Rf includes the first floating region Rf1. In this embodiment, the floating region Rf includes only the first floating region Rf1.

[0024] The first floating region Rf1 is a region in which at least one of the control electrodes 35 flanking the floating region Rf is a second control electrode 39. In this embodiment, the first floating region Rf1 is sandwiched between one first control electrode 36 and one second control electrode 39. In this embodiment, the channel region Rc and the first floating region Rf1 are alternately provided along the second direction D2.

[0025] The first insulating film 37 is an insulating film that covers the first control electrode 36. The upper (D1 side) edge of the first insulating film 37 is in contact with the lower (-D1 side) surface of the insulating layer 24. For example, silicon oxide can be used as the material constituting the first insulating film 37. The semiconductor device 20 comprises a plurality of first insulating films 37. Each first insulating film 37 covers a different first control electrode 36.

[0026] The second insulating film 40 is an insulating film that covers the second control electrode 39. The upper (D1 side) edge of the second insulating film 40 is in contact with the lower (-D1 side) surface of the insulating layer 24. For example, silicon oxide can be used as the material constituting the second insulating film 40. The semiconductor device 20 comprises a plurality of second insulating films 40. Each second insulating film 40 covers a different second control electrode 39.

[0027] N + The type emitter layer 25 is located in the channel region Rc. + The type emitter layer 25 is located between the first control electrodes 36, which are arranged adjacent to each other in the second direction D2, or between the second control electrodes 39, which are arranged adjacent to each other in the second direction D2. + The upper (+D1 side) end of the type emitter layer 25 contacts the insulating layer 24 and the protruding portion 21a of the emitter electrode 21. As a result, N + The type emitter layer 25 is electrically connected to the emitter electrode 21. + The lower (-D1) end of the type emitter layer 25 is located above the lower end of the control electrode 35. + The N-type carrier concentration in the emitter layer 25 is, for example, 1 × 10⁻⁶. 19 [cm -3 ] Above, 1 x 10 20 [cm -3 The following applies. In this embodiment, the semiconductor device 20 has multiple N + It is equipped with a type emitter layer 25. Each channel region Rc contains N + A type emitter layer 25 is arranged. In each channel region Rc, N + The type emitter layer 25 contacts either the first insulating film 37 or the second insulating film 40 in the second direction D2. This results in N +The type emitter layer 25 is insulated from the control electrode 35.

[0028] P + The type contact layer 27 is located in the channel region Rc. + The upper (+D1 side) end of the type contact layer 27 contacts the protruding portion 21a of the emitter electrode 21. As a result, P + The type contact layer 27 is electrically connected to the emitter electrode 21. + The lower (-D1) end of the type contact layer 27 is located above the lower end of the control electrode 35. + The P-type carrier concentration in the type contact layer 27 is, for example, 1 × 10⁻⁶ 19 [cm -3 ] Above, 1 x 10 20 [cm -3 The following applies. In this embodiment, the semiconductor device 20 has multiple P + It is equipped with a type contact layer 27. Each P + The type contact layers 27 are arranged in different channel regions Rc. + The contact layer 27 is N + It comes into contact with the type emitter layer 25.

[0029] The P-type base layer 29 is a P-type, i.e., first conductivity type semiconductor layer. In this embodiment, the P-type base layer 29 is the first semiconductor layer. The P-type base layer 29 is placed between the emitter electrode 21 and the collector electrode 23. The P-type base layer 29 is placed in the channel region Rc. That is, the P-type base layer 29, i.e., the first semiconductor layer, is placed in the channel region Rc. The P-type base layer 29 is placed between the first control electrodes 36 which are placed adjacent to each other in the second direction D2, or between the second control electrodes 39 which are placed adjacent to each other in the second direction D2. The P-type base layer 29 is N + Type emitter layer 25 and P + It is placed between the type contact layer 27 and the collector electrode 23. The upper (+D1 side) end of the P-type base layer 29 is N + Type emitter layer 25 and P + It comes into contact with each of the type contact layers 27. As a result, the P-type base layer 29 is N+ Type emitter layer 25 and P + The emitter electrode 21, i.e., the first electrode, is electrically connected via the P-type contact layer 27. The lower (-D1) end of the P-type base layer 29 is located above the lower end of the control electrode 35. The P-type carrier concentration of the P-type base layer 29 is, for example, 1 × 10⁻⁶. 17 [cm -3 It is approximately [ ]. In this embodiment, the semiconductor device 20 comprises a plurality of P-type base layers 29. The carrier concentration of each P-type base layer 29 is P + The carrier concentration is lower than that of the type contact layer 27. Each P-type base layer 29 is positioned in a different channel region Rc from each other. Each P-type base layer 29 is in contact with either the first insulating film 37 or the second insulating film 40 in the second direction D2. This insulates each P-type base layer 29 from the control electrode 35.

[0030] The P-type floating layer 30 is a P-type, i.e., first conductivity type semiconductor layer. In this embodiment, the P-type floating layer 30 is a second semiconductor layer. The P-type floating layer 30 is placed between the emitter electrode 21 and the collector electrode 23. The P-type floating layer 30 is placed in the first floating region Rf1. That is, the P-type floating layer 30, i.e., the second semiconductor layer, is placed in the floating region Rf. The P-type floating layer 30 is placed between the insulating layer 24 and the collector electrode 23. The upper (+D1 side) end of the P-type floating layer 30 is in contact with the insulating layer 24. As a result, the P-type floating layer 30 is electrically insulated from the emitter electrode 21, i.e., the first electrode. In the first direction D1, the position of the lower (-D1 side) end of the P-type floating layer 30 and the lower end of the control electrode 35 are approximately the same. The lower end of the P-type floating layer 30 may be located above or below the lower end of the control electrode 35. When the lower end of the P-type floating layer 30 is located below the lower end of the control electrode 35, it is possible to suppress the concentration of the electric field at the lower corner of the control electrode 35 when a voltage is applied to the control electrode 35. This suppresses avalanche breakdown caused by the control electrode 35, and thus improves the reliability of the operation of the semiconductor device 20. The P-type carrier concentration of the P-type floating layer 30 is, for example, 1 × 10⁻⁶ 17 [cm -3 This is the extent of the effect. In this embodiment, the semiconductor device 20 comprises a plurality of P-type floating layers 30. Each P-type floating layer 30 is located in a different first floating region Rf1. Each P-type floating layer 30 is in contact with at least one of the first insulating film 37 and the second insulating film 40 in the second direction D2. This insulates each P-type floating layer 30 from the control electrode 35.

[0031] N - The base layer 31 is an N-type, i.e., second-conductivity semiconductor layer. In this embodiment, N - The base layer 31 is the third semiconductor layer. -The base layer 31 is placed between the emitter electrode 21 and the collector electrode 23. - The P-type base layer 31 is positioned between the collector electrode 23 and each of the P-type base layer 29, the P-type floating layer 30, and the control electrode 35. That is, N - The base layer 31 is placed between the second electrode and the first semiconductor layer and the second semiconductor layer, respectively. - A portion of the type base layer 31 protrudes into each channel region Rc and contacts the P-type base layer 29. - The rest of the mold base layer 31 is in contact with the P-type floating layer 30. This results in N - The P-type base layer 31 is in contact with the P-type base layer 29 and the P-type floating layer 30, respectively. - The mold base layer 31 comes into contact with the first insulating film 37 and the second insulating film 40, respectively. This allows N - The mold base layer 31 is insulated from the control electrode 35. - The N-type carrier concentration in the base layer 31 is, for example, 1 × 10⁻⁶. 13 [cm -3 It is to that extent. - The N-type carrier concentration in the base layer 31 is N + It is lower than the carrier concentration in the type emitter layer 25. - The N-type carrier concentration in the base layer 31 can be set to any carrier concentration by the voltage withstand design of the semiconductor device 20, etc.

[0032] The P-type collector layer 33 is a P-type, i.e., first conductivity type semiconductor layer. In this embodiment, the P-type collector layer 33 is the fourth semiconductor layer. The carrier concentration of the P-type collector layer 33 is higher than that of the P-type base layer 29. The P-type collector layer 33 is placed between the emitter electrode 21 and the collector electrode 23. The P-type collector layer 33 is connected to the collector electrode 23, i.e., the second electrode, and N - It is placed between the P-type base layer 31, i.e., the third semiconductor layer. The P-type collector layer 33 is positioned between the collector electrode 23 and N - Each of the base layers 31 is in contact with the other.

[0033] The connecting electrode 43 is made of an insulating layer 24 and N- It is positioned between the base layer 31 and the connecting electrode 43. The connecting electrode 43 extends in the first direction D1 and the third direction D3, respectively. The upper (+D1 side) end of the connecting electrode 43 contacts the lower (-D1 side) surface of the insulating layer 24 and the protrusion 21a of the emitter electrode 21. This electrically connects the connecting electrode 43 to the emitter electrode 21, i.e., the first electrode. The connecting electrode 43 is made of a semiconductor material with impurities added. The semiconductor device 20 comprises a plurality of connecting electrodes 43. Each connecting electrode 43 is spaced apart along the second direction D2. Each connecting electrode 43 is positioned in a different first floating region Rf1. That is, a connecting electrode 43 is positioned in the first floating region Rf1. As described above, in this embodiment, the first floating region Rf1 is sandwiched between one first control electrode 36 and one second control electrode 39. Therefore, each connecting electrode 43 is sandwiched between one first control electrode 36 and one second control electrode 39. In this embodiment, the distance G2 between the connecting electrode 43 and the second control electrode 39 is greater than the distance G1 between the connecting electrode 43 and the first control electrode 36. Note that the distance G2 between the connecting electrode 43 and the second control electrode 39 may be smaller than the distance G1 between the connecting electrode 43 and the first control electrode 36, or it may be the same dimension as the distance G1 between the connecting electrode 43 and the first control electrode 36.

[0034] The third insulating film 44 is an insulating film that covers the connecting electrode 43. The upper (D1 side) end of the third insulating film 44 is in contact with the lower (-D1 side) surface of the insulating layer 24. For example, silicon oxide can be used as the material constituting the third insulating film 44. The semiconductor device 20 comprises a plurality of third insulating films 44. Each third insulating film 44 covers a different connecting electrode 43. Each third insulating film 44 is a P-type floating layer 30 and N - It comes into contact with the P-type base layer 31. As a result, the connecting electrode 43 comes into contact with the P-type floating layer 30 and N - Each of the mold base layers 31 is insulated from it.

[0035] Next, the electrical connection relationship between the first control electrode 36 and the second control electrode 39 will be described. In this embodiment, each first control electrode 36 is electrically connected to the first gate pad 52 via wiring 58. Each second control electrode 39 is electrically connected to the second gate pad 56 via wiring 59. A first voltage Vg1, which is the first gate-emitter voltage, is applied to the first gate pad 52. As a result, the first voltage Vg1 is applied to each first control electrode 36. A second voltage Vg2, which is the second gate-emitter voltage, is applied to the second gate pad 56. As a result, the second voltage Vg2 is applied to each second control electrode 39. Therefore, different voltages can be applied to the first control electrode 36 and the second control electrode 39.

[0036] Figure 2 is a schematic diagram showing the semiconductor device 20 of this embodiment. Figure 3 is a timing chart showing the control signals, the first voltage Vg1, and the second voltage Vg2 of the semiconductor device 20 of this embodiment. Figure 4 is a schematic cross-sectional view showing the carrier behavior of the semiconductor device 20 of this embodiment during the first period P1. Figure 5 is a schematic cross-sectional view showing the carrier behavior of the semiconductor device 20 of this embodiment during the second period P2. Figure 6 is a schematic cross-sectional view showing the carrier behavior of the semiconductor device 920 of a comparative example during the second period P2. Figure 7 is a schematic cross-sectional view showing the carrier behavior of the semiconductor device 20 of this embodiment during the third period P3. As shown in Figure 2, the semiconductor device 20 includes a voltage control circuit 50.

[0037] The voltage control circuit 50 can control the first voltage Vg1 applied to the first gate pad 52 and the second voltage Vg2 applied to the second gate pad 56 at different timings. The voltage control circuit 50 includes a first control circuit 51 and a second control circuit 55.

[0038] The first control circuit 51 applies a first voltage Vg1 to the first control electrode 36 via the first gate pad 52 based on an externally input control signal S. The second control circuit 55 applies a second voltage Vg2 to the second control electrode 39 via the second gate pad 56 based on an externally input control signal S. As shown in Figure 3, the control signal S is a binary signal consisting of Hs and Ls. Note that the first control circuit 51 and the second control circuit 55 may each be input to different control signals.

[0039] The first control circuit 51 applies either a first high voltage Hg1 or a first low voltage Lg1 as a first voltage Vg1 to each first control electrode 36 based on the control signal S. The first high voltage Hg1 is higher than the threshold voltage Vth at which a channel is formed in the semiconductor device 20. The first low voltage Lg1 is lower than the threshold voltage Vth. Therefore, when the first high voltage Hg1 is applied to the first control electrode 36, the semiconductor device 20 turns ON (conducts). At this time, current flows from the collector electrode 23 to the emitter electrode 21 through the channel region Rc provided between adjacent first control electrodes 36. When the first low voltage Lg1 is applied to the first control electrode 36, the semiconductor device 20 turns OFF.

[0040] The second control circuit 55 applies either a second high voltage Hg2 or a second low voltage Lg2 as a second voltage Vg2 to each second control electrode 39 based on the control signal S. The second high voltage Hg2 is higher than the threshold voltage Vth at which a channel is formed in the semiconductor device 20. The second low voltage Lg2 is lower than the threshold voltage Vth. Therefore, when the second high voltage Hg2 is applied to the second control electrode 39, the semiconductor device 20 turns on, and current flows from the collector electrode 23 to the emitter electrode 21 through the channel region Rc provided between adjacent second control electrodes 39. When the second low voltage Lg2 is applied to the second control electrode 39, the semiconductor device 20 turns off.

[0041] Next, the switching timings for the first voltage Vg1 and the second voltage Vg2 will be explained. T0, T1, T2, T3, and T4 in Figure 3 represent times, and time progresses in this order. In this embodiment, the semiconductor device 20 turns ON when the control signal S switches from Ls to Hs. Note that the relationship between the control signal S and the ON state of the semiconductor device 20 may be the reverse of the above. That is, the semiconductor device 20 may turn OFF when the control signal S switches from Ls to Hs.

[0042] From time T0 to time T1, the control signal S input to the voltage control circuit 50 is Ls. The first control circuit 51 outputs a first low voltage Lg1 as the first voltage Vg1. The second control circuit 55 outputs a second low voltage Lg2 as the second voltage Vg2. As a result, the semiconductor device 20 is in an off state where no current flows from the collector electrode 23 to the emitter electrode 21.

[0043] At time T1, the control signal S input to the voltage control circuit 50 switches from Ls to Hs. At time T1, the first control circuit 51 switches the first voltage Vg1 to the first high voltage Hg1. The second control circuit 55 switches the second voltage Vg2 to the second high voltage Hg2. As a result, at time T1, as shown in Figure 4, electrons move from the emitter electrode 21 to the collector electrode 23 through each channel region Rc. This causes the semiconductor device 20 to enter an ON state in which current flows from the collector electrode 23 to the emitter electrode 21. In other words, the semiconductor device 20 turns ON at time T1, switching from the OFF state to the ON state.

[0044] As shown in Figure 3, in this embodiment, the control signal S input to the voltage control circuit 50 is Hs from time T1 to time T2. In the following description, the period from time T1 to time T2 will be referred to as the first period P1. During the first period P1, the semiconductor device 20 is in the ON state. As described above, the semiconductor device 20 in this embodiment is a bipolar element. Therefore, although not shown in the figures, in the ON state, N -Electrons and holes are injected into the type base layer 31. This results in N - Because the carrier concentration of the base layer 31 can be increased, compared to a unipolar element, in the ON state, N - The electrical resistance of the base layer 31 can be reduced. Therefore, the semiconductor device 20 of this embodiment can reduce conduction loss in the ON state compared to a unipolar element.

[0045] Furthermore, when turning on the semiconductor device 20, the timing of switching the first voltage Vg1 to the first high voltage Hg1 and the timing of switching the second voltage Vg2 to the second high voltage Hg2 may be simultaneous or may be staggered.

[0046] In this embodiment, at time T2, the control signal S input to the voltage control circuit 50 switches from Hs to Ls. At time T2, the semiconductor device 20 is first turned off. At time T2, the first control circuit 51 maintains the first voltage Vg1 at the first high voltage Hg1. The second control circuit 55 switches the second voltage Vg2 to the second low voltage Lg2. As a result, at time T2, as shown in Figure 5, the state in which electrons move from the emitter electrode 21 to the collector electrode 23 through the channel region Rc provided between the adjacent first control electrodes 36 is maintained. This also maintains the state in which current flows from the collector electrode 23 to the emitter electrode 21. On the other hand, in the channel region Rc provided between the adjacent second control electrodes 39, the movement of electrons from the emitter electrode 21 to the collector electrode 23 stops.

[0047] Also, N - Holes accumulated in the base layer 31 are discharged to the emitter electrode 21 through a channel region Rc provided between adjacent second control electrodes 39. More specifically, N -Of the P-type base layer 31, holes accumulated in the hole emission region Rd, which overlaps with the space between the two connecting electrodes 43 when viewed from the first direction D1, are discharged to the emitter electrode 21. Some of the holes accumulated in the hole emission region Rd are discharged to the emitter electrode 21 via the carrier accumulation layer 70 and the P-type base layer 29, etc. Other holes accumulated in the hole emission region Rd move to the P-type floating layer 30 and are then discharged to the emitter electrode 21 via the carrier accumulation layer 70 and the P-type base layer 29, etc.

[0048] As shown in Figure 3, in this embodiment, the first turn-off continues until time T3, which is a predetermined time after time T2. In the following description, the period from time T2 to time T3 will be referred to as the second period P2. As shown in Figure 5, in the second period P2, the semiconductor device 20 is in an ON state in which current flows from the collector electrode 23 to the emitter electrode 21 through the channel region Rc provided between the adjacent first control electrodes 36, as described above. Also, in the second period P2, as described above, some of the holes accumulated in the hole emission region Rd are discharged to the emitter electrode 21, so N - The carrier concentration accumulated in the base layer 31 can be reduced.

[0049] The comparative example semiconductor device 920 shown in Figure 6 does not have a connecting electrode 43. Therefore, in the second period P2, the hole emission region Rd of the semiconductor device 920 is N - In the base layer 31, when viewed from the first direction D1, it overlaps with the space between the first control electrodes 36 and the second control electrode 39. In this case, because the range of the hole emission region Rd in the second direction D2 is large, the amount of carriers emitted to the emitter electrode 21 becomes too large during the second period P2. As a result, during the second period P2, N - The carrier concentration accumulated in the base layer 31 becomes too low. Therefore, in the semiconductor device 920, N - As the electrical resistance of the base layer 31 increases, the conduction loss in the second period P2 increases.

[0050] In contrast, the semiconductor device 20 of this embodiment includes a connecting electrode 43, and as shown in Figure 5, the range of the hole emission region Rd in the second direction D2 can be made smaller compared to the hole emission region Rd of the semiconductor device 920 described above. This is because the portion of the P-type floating layer 30 sandwiched between the first control electrode 36 and the connecting electrode 43 is not electrically connected to the P-type base layer 29 via the carrier storage layer 70, and therefore does not contribute to hole emission. As a result, it is possible to suppress the amount of carriers emitted to the emitter electrode 21 from becoming too large, N - This prevents the carrier concentration accumulating in the type base layer 31 from becoming too low. Therefore, N - Since the electrical resistance of the base layer 31 can be prevented from becoming too high, the increase in conduction loss during the second period P2 can be suppressed.

[0051] Furthermore, as shown in Figure 1, in this embodiment, the distance G2 between the connecting electrode 43 and the second control electrode 39 is greater than the distance G1 between the connecting electrode 43 and the first control electrode 36. This makes it easier to enlarge the range of the second direction D2 of the hole emission region Rd shown in Figure 5. Therefore, in the second period P2, the amount of carriers discharged to the emitter electrode 21 can be suitably increased. Thus, N - The carrier concentration accumulated in the base layer 31 can be suitably reduced. Also, although not shown in the figure, when the distance G2 between the connecting electrode 43 and the second control electrode 39 is smaller than the distance G1 between the connecting electrode 43 and the first control electrode 36, the range of the hole emission region Rd in the second direction D2 can be reduced. Therefore, the amount of carriers emitted to the emitter electrode 21 in the second period P2 can be reduced. Thus, N - This prevents the carrier concentration accumulated in the base layer 31 from becoming too low. - Since the increase in the electrical resistance of the base layer 31 can be suppressed, the increase in conduction loss in the second period P2 can be suitably suppressed. In other words, in this embodiment, by appropriately adjusting the position of each connecting electrode 43 in the second direction D2, in the second period P2, N -The carrier concentration of the N-type base layer 31 can be adjusted. Thereby, while suppressing an increase in conduction loss in the second period P2, as will be described later, an increase in turn-off loss in the third period P3 can be suppressed.

[0052] As shown in FIG. 3, at time T3, the voltage control circuit 50 switches the first voltage Vg1 from the first high voltage Hg1 to the first low voltage Lg1. That is, the voltage control circuit 50 switches the first voltage Vg1 after a predetermined time has elapsed since switching the second voltage Vg2 at time T2. Also, the voltage control circuit 50 maintains the second voltage Vg2 at the second low voltage Lg2. At time T3, the semiconductor device 20 turns off for the second time. Thereby, as shown in FIG. 7, at time T3, the semiconductor device 20 is in an off state where no current flows from the collector electrode 23 to the emitter electrode 21.

[0053] At time T3, at the interface between the first insulating film 37 and the N - -type base layer 31 and at the interface between the second insulating film 40 and the N - -type base layer 31, a carrier accumulation layer 70 is formed. The holes accumulated in the N - -type base layer 31 are discharged to the emitter electrode 21 through the carrier accumulation layer 70 and each channel region Rc.

[0054] As shown in FIG. 3, the second turn-off continues until time T4, which is the time after a predetermined time has elapsed from time T3. In the following description, the period from time T3 to time T4 is referred to as the third period P3. In the third period P3, the semiconductor device 20 is in an off state. Also, in the third period P3, the holes accumulated in the N - -type base layer 31 are discharged to the emitter electrode 21. In the present embodiment, as described above, in the second period P2, by discharging a part of the holes accumulated in the N - -type base layer 31 to the emitter electrode 21, N -The carrier concentration in the base layer 31 is reduced. This reduces the amount of holes discharged to the emitter electrode 21 during the third period P3, thus shortening the time during which carriers are discharged to the emitter electrode 21. Therefore, the turn-off loss during the third period P3 can be effectively reduced.

[0055] At time T4, the control signal S switches from Ls to Hs, and the semiconductor device 20 turns ON. After this, the semiconductor device 20 repeatedly switches between ON state, first turn-off, and second turn-off.

[0056] According to this embodiment, the semiconductor device 20 includes an emitter electrode 21, i.e., a first electrode, and a collector electrode 23, i.e., a second electrode, which are spaced apart from each other in a first direction D1; a plurality of control electrodes 35, which are spaced apart along a second direction D2 and are positioned between the emitter electrode 21 and the collector electrode 23; a connecting electrode 43, which is electrically connected to the emitter electrode 21; a P-type, i.e., first conductivity type P-type base layer 29, i.e., a first semiconductor layer, which is electrically connected to the emitter electrode 21; a P-type floating layer 30, i.e., a second semiconductor layer, which is electrically insulated from the emitter electrode 21; and an N-type, i.e., second conductivity type N - It comprises a P-type base layer 31, i.e., a third semiconductor layer, and a P-type collector layer 33, i.e., a fourth semiconductor layer. P-type base layer 29, P-type floating layer 30, N - The P-type base layer 31 and the P-type collector layer 33 are each positioned between the emitter electrode 21 and the collector electrode 23. Each of the multiple regions sandwiched between adjacent control electrodes 35 in the second direction D2 is either a channel region Rc where the P-type base layer 29 is positioned, or a floating region Rf where the P-type floating layer 30 is positioned. The multiple control electrodes 35 include a plurality of first control electrodes 36 to which a first voltage Vg1 is applied, and a plurality of second control electrodes 39 to which a second voltage Vg2 is applied. The floating region Rf includes a first floating region Rf1 where at least one of the control electrodes 35 sandwiching the floating region Rf is a second control electrode 39, and a connecting electrode 43 is positioned in the first floating region Rf1. As described above, in the present embodiment, between the first period P1 in which the semiconductor device 20 is in the on state and the third period P3 in which the semiconductor device 20 is in the off state, a second period P2 can be provided in which the second voltage Vg2 applied to the second control electrode 39 is switched to the second low voltage Lg2 to perform the first turn-off. Therefore, in the second period P2, while current flows from the collector electrode 23 to the emitter electrode 21, a part of the holes accumulated in the N - type base layer 31 can be discharged to the emitter electrode 21. As a result, in the second period P2, while suppressing an excessive increase in the resistance of the N - type base layer 31, the carrier concentration of the N - type base layer 31 can be reduced. Therefore, the turn-off loss in the third period P3 can be reduced. However, when not provided with the connection electrode 43 as in the semiconductor device 920 of the above-described comparative example, the range of the second direction D2 of the hole discharge region Rd becomes large. Therefore, in the second period P2, the carrier concentration of the N - type base layer 31 becomes too low. As a result, the electrical resistance of the N - type base layer 31 increases, so that the conduction loss in the second period P2 increases. On the other hand, in the present embodiment, as described above, the connection electrode 43 is disposed in the first floating region Rf1. As a result, as described above, the range of the second direction D2 of the hole discharge region Rd can be preferably reduced, so that it is possible to suppress the carrier concentration of the N - type base layer 31 from becoming too low. Therefore, it is possible to preferably suppress an increase in the conduction loss in the second period P2. Further, in the present embodiment, as described above, in the second period P2, since the carrier concentration of the N - type base layer 31 can be reduced, the amount of holes discharged to the emitter electrode 21 in the third period P3 can be reduced. As a result, in the third period P3, the time for discharging carriers to the emitter electrode 21 can be preferably shortened. Therefore, the turn-off loss in the third period P3 can be preferably reduced. That is, in the semiconductor device 20 of the present embodiment, it is possible to preferably suppress an increase in the conduction loss in the second period P2 and preferably reduce the turn-off loss in the third period P3.

[0057] Furthermore, in this embodiment, the range of the hole emission region Rd in the second direction D2 can be appropriately adjusted by appropriately adjusting the position of each connecting electrode 43 in the second direction D2. This allows for the adjustment of the range of the hole emission region Rd in the second direction D2 during the second period P2. - The carrier concentration in the base layer 31 can be adjusted as appropriate. Therefore, the increase in conduction loss in the second period P2 can be more effectively suppressed, and the turn-off loss in the third period P3 can be more effectively reduced.

[0058] Furthermore, in this embodiment, the connecting electrode 43 is electrically connected to the emitter electrode 21. Therefore, the potential of the connecting electrode 43 can be stabilized to a potential near the emitter potential. As a result, the potential difference between the connecting electrode 43 and the collector electrode 23 can be stabilized in the second period P2, and thus the amount of holes discharged to the emitter electrode 21 can be stabilized. Therefore, in the second period P2, N - The carrier concentration in the base layer 31 can be adjusted with greater precision. Therefore, the increase in conduction loss in the second period P2 can be more effectively suppressed, and the turn-off loss in the third period P3 can be more effectively reduced.

[0059] According to this embodiment, the first floating region Rf1 is sandwiched between one first control electrode 36 and one second control electrode 39, and the distance G2 between the connecting electrode 43 and the second control electrode 39 is greater than the distance G1 between the connecting electrode 43 and the first control electrode 36. Therefore, as described above, it is easy to increase the range of the hole emission region Rd in the second direction D2. As a result, the amount of carriers discharged to the emitter electrode 21 can be suitably increased during the second period P2. Therefore, N - Since the carrier concentration in the base layer 31 can be suitably reduced, the turn-off loss in the third period P3 can be more suitably reduced.

[0060] According to this embodiment, the first floating region Rf1 is sandwiched between one first control electrode 36 and one second control electrode 39, and the distance G2 between the connecting electrode 43 and the second control electrode 39 may be smaller than the distance G1 between the connecting electrode 43 and the first control electrode 36. Therefore, as described above, the range of the second direction D2 of the hole emission region Rd can be easily reduced. As a result, the amount of carriers discharged to the emitter electrode 21 in the second period P2 can be reduced. Therefore, N - Since it is possible to suppress the carrier concentration in the base layer 31 from becoming too low, it is possible to more effectively suppress the increase in conduction loss in the second period P2.

[0061] According to this embodiment, the semiconductor device 20 includes a voltage control circuit 50 capable of controlling the first voltage Vg1 and the second voltage Vg2 at different timings. Therefore, as described above, at time T2, the first voltage Vg1 applied to the first control electrode 36 can be maintained at the first high voltage Hg1, while the second voltage Vg2 applied to the second control electrode 39 can be switched to the second low voltage Lg2. As a result, as described above, during the second period P2, a current can be passed from the collector electrode 23 to the emitter electrode 21, while a portion of the holes can be discharged to the emitter electrode 21. Therefore, during the second period P2, N - While suppressing an excessive increase in the resistance of the base layer 31, - The carrier concentration in the base layer 31 can be reduced. Therefore, the increase in conduction loss in the second period P2 can be effectively suppressed, and the turn-off loss in the third period P3 can be effectively reduced.

[0062] According to this embodiment, the voltage control circuit 50 switches the first voltage Vg1 after a predetermined time has elapsed since switching the second voltage Vg2. If the second period P2 is too short, the amount of carrier discharged to the emitter electrode 21 during the second period P2 will be small, which may prevent sufficient reduction of the turn-off loss during the third period P3. Also, if the second period P2 is too long, the on-resistance may increase. In this embodiment, the duration of the second period P2 can be set to a desired time. This allows for appropriate adjustment of the amount of carrier discharged to the emitter electrode 21 during the second period P2. Therefore, the increase in conduction loss during the second period P2 can be more effectively suppressed, and the turn-off loss during the third period P3 can be more effectively reduced.

[0063] According to this embodiment, the voltage control circuit 50 switches the first voltage Vg1 and the second voltage Vg2 to the first high voltage Hg1 and the second high voltage Hg2, respectively, then switches the second voltage Vg2 to the second low voltage Lg2, which is a voltage lower than the second high voltage Hg2, and after a predetermined time has elapsed since switching the second voltage Vg2 to the second low voltage Lg2, it switches the first voltage Vg1 to the first low voltage Lg1, which is a voltage lower than the first high voltage Hg1. Therefore, in this embodiment, the time of the second period P2 can be set to a desired time. This allows the amount of carrier discharged to the emitter electrode 21 to be adjusted appropriately during the second period P2. Therefore, it is possible to more effectively suppress the increase in conduction loss during the second period P2 and to more effectively reduce turn-off loss during the third period P3.

[0064] (Second Embodiment) Figure 8 is a schematic cross-sectional view showing the semiconductor device 220 of this embodiment. Figure 9 is a schematic cross-sectional view showing the carrier behavior of the semiconductor device 220 of this embodiment during the second period P2. The first control electrode 36 and the second control electrode 39 of this embodiment are arranged alternately along the second direction D2. In the following description, components that are the same as those in the first embodiment described above are denoted by the same reference numerals, and their descriptions are omitted.

[0065] As shown in Figure 8, in this embodiment, the plurality of control electrodes 35 includes a plurality of first control electrodes 36 and a plurality of second control electrodes 39. Each first control electrode 36 is spaced apart along the second direction D2. Each second control electrode 39 is spaced apart along the second direction D2. In this embodiment, each second control electrode 39 is positioned adjacent to the right side (+D2 side) of a different first control electrode 36. That is, in this embodiment, the first control electrodes 36 and the second control electrodes 39 are arranged alternately along the second direction D2.

[0066] In this embodiment, the channel region Rc is the region between each first control electrode 36 and the second control electrode 39 which is positioned adjacent to each first control electrode 36 on its right side (+D2 side). The channel region Rc is sandwiched between the first control electrode 36 and the second control electrode 39. In this embodiment, the floating region Rf is the region other than the channel region Rc among a plurality of regions sandwiched between adjacent control electrodes 35 which are positioned adjacent to each other in the second direction D2. In this embodiment, the floating region Rf includes the first floating region Rf1.

[0067] The first floating region Rf1 is a region in which at least one of the control electrodes 35 flanking the floating region Rf is a second control electrode 39. In this embodiment, the first floating region Rf1 is sandwiched between one first control electrode 36 and one second control electrode 39. In this embodiment, the channel region Rc and the first floating region Rf1 are alternately provided along the second direction D2. The other configurations of the semiconductor device 220 in this embodiment are the same as the other configurations of the semiconductor device 20 in the first embodiment described above.

[0068] In this embodiment, similar to the first embodiment described above, at time T2, the semiconductor device 220 is first turned off. In this embodiment, similar to the first embodiment described above, at time T2, the first control circuit 51 maintains the first voltage Vg1 at the first high voltage Hg1. The second control circuit 55 switches the second voltage Vg2 to the second low voltage Lg2. As a result, at time T2, as shown in Figure 9, the N220 is in contact with the first insulating film 37. + The state in which electrons move from the emitter electrode 21 to the collector electrode 23 is maintained via the P-type emitter layer 25 and the P-type base layer 29. In this embodiment, electrons move from the emitter electrode 21 to the collector electrode 23 in the portion of each channel region Rc on the first control electrode 36 side. This also maintains the state in which current flows from the collector electrode 23 to the emitter electrode 21.

[0069] Also, N - Holes accumulated in the base layer 31 are discharged to the emitter electrode 21 through each channel region Rc. More specifically, N - Holes accumulated in the first hole discharge region Rd1, which is the sum of the portion of the mold base layer 31 that overlaps with each second control electrode 39 when viewed from the first direction D1, and the portion of the first floating region Rf1 that overlaps with the portion to the left of the connecting electrode 43 (-D2 side), are discharged to the emitter electrode 21. In this embodiment, the first hole discharge region Rd1 is formed with gaps along the second direction D2. - Holes accumulated in the second hole emission region Rd2, which is the sum of the portion of the P-type base layer 31 that overlaps with the second control electrode 39 located on the far right (+D2 side) and the portion that overlaps with the P-type floating layer 30 located to the right of the second control electrode 39, are discharged to the emitter electrode 21. Some of the holes accumulated in the first hole emission region Rd1 and the second hole emission region Rd2 are discharged to the carrier accumulation layer 70, the P-type base layer 29, and P +The holes are discharged to the emitter electrode 21 via the P-type contact layer 27. In addition, other holes accumulated in the first hole discharge region Rd1 and the second hole discharge region Rd2 move to the P-type floating layer 30, and then to the carrier accumulation layer 70, the P-type base layer 29, and P + The holes are discharged to the emitter electrode 21 via the type contact layer 27. In this embodiment, the portion of each channel region Rc on the second control electrode 39 side moves toward the emitter electrode 21.

[0070] During the second period P2, the semiconductor device 220 is in an ON state in which current flows from the collector electrode 23 to the emitter electrode 21 through each channel region Rc. Also, during the second period P2, some of the holes accumulated in the first hole emission region Rd1 and the second hole emission region Rd2 are emitted to the emitter electrode 21, so N - The carrier concentration accumulated in the base layer 31 can be reduced. As a result, similar to the first embodiment described above, in this embodiment, in the second period P2, N - While suppressing an excessive increase in the resistance of the base layer 31, - The carrier concentration in the base layer 31 can be reduced. Therefore, the increase in conduction loss in the second period P2 can be effectively suppressed, and the turn-off loss in the third period P3 can be effectively reduced.

[0071] (Third embodiment) Figure 10 is a schematic cross-sectional view showing the semiconductor device 320 of this embodiment. Figure 11 is a schematic cross-sectional view showing the carrier behavior of the semiconductor device 320 of this embodiment during the second period P2. Multiple connection electrodes 43 are arranged in the first floating region Rf1 of this embodiment. In the following description, components that are the same as those in the first embodiment described above are denoted by the same reference numerals, and their descriptions are omitted.

[0072] As shown in Figure 10, in this embodiment, the plurality of control electrodes 35 includes a plurality of first control electrodes 36 and a plurality of second control electrodes 39. Each first control electrode 36 is spaced apart along the second direction D2. Each second control electrode 39 is spaced apart along the second direction D2. In this embodiment, the plurality of control electrodes 35 are arranged from left side (-D2 side) to right side (+D2 side) in the order of one first control electrode 36, two second control electrodes 39, two first control electrodes 36, and one second control electrode 39.

[0073] In this embodiment, the channel region Rc is the region sandwiched between the first control electrode 36 and the second control electrode 39. In this embodiment, the floating region Rf is the region other than the channel region Rc among a plurality of regions sandwiched between adjacent control electrodes 35 in the second direction D2. In this embodiment, the floating region Rf includes the first floating region Rf1 and the second floating region Rf2.

[0074] In this embodiment, the first floating region Rf1 is the region of the floating region Rf that is sandwiched between the two second control electrodes 39. The second floating region Rf2 is the region sandwiched between the two first control electrodes 36. In this embodiment, the floating region Rf includes one first floating region Rf1 and one second floating region Rf2.

[0075] The semiconductor device 320 includes a plurality of connection electrodes 43. Each connection electrode 43 is spaced apart from each other along a second direction D2. Each connection electrode 43 is located in the same first floating region Rf1. Therefore, in this embodiment, the first floating region Rf1 contains a plurality of connection electrodes 43 spaced apart from each other along the second direction D2. In this embodiment, two connection electrodes 43 are located in the first floating region Rf1. Three or more connection electrodes 43 may be located in the first floating region Rf1. No connection electrodes 43 are located in the second floating region Rf2. Other configurations of the semiconductor device 320 in this embodiment are the same as those of the semiconductor device 20 in the first embodiment described above. In this embodiment, two connection electrodes 43 are located in the first floating region Rf1, but one connection electrode may be located where the dimension in the second direction D2 is approximately twice the dimension in the second direction D2 of the connection electrode 43 in this embodiment.

[0076] In this embodiment, similar to the first embodiment described above, at time T2, the semiconductor device 320 is first turned off. In this embodiment, similar to the first embodiment described above, at time T2, the first control circuit 51 maintains the first voltage Vg1 at the first high voltage Hg1. The second control circuit 55 switches the second voltage Vg2 to the second low voltage Lg2. As a result, at time T2, as shown in Figure 11, the N2 that contacts the first insulating film 37 + The state in which electrons move from the emitter electrode 21 to the collector electrode 23 is maintained via the P-type emitter layer 25 and the P-type base layer 29. In this embodiment, electrons move from the emitter electrode 21 to the collector electrode 23 in the portion of each channel region Rc on the first control electrode 36 side. As a result, the state in which current flows from the collector electrode 23 to the emitter electrode 21 via each channel region Rc is also maintained.

[0077] Also, N - Holes accumulated in the base layer 31 are discharged to the emitter electrode 21 through each channel region Rc. More specifically, N -Holes accumulated in the first hole discharge region Rd1, which is the sum of the portion of the mold base layer 31 that overlaps with each second control electrode 39 when viewed from the first direction D1 and the portion of the first floating region Rf1 that overlaps with the portion between the connecting electrode 43 and the second control electrode 39, are discharged to the emitter electrode 21. In this embodiment, the first hole discharge region Rd1 is formed with gaps along the second direction D2. - Holes accumulated in the second hole emission region Rd2, which is the sum of the portion of the P-type base layer 31 that overlaps with the second control electrode 39 located on the far right (+D2 side) when viewed from the first direction D1, and the portion that overlaps with the P-type floating layer 30 located to the right of the second control electrode 39, are discharged to the emitter electrode 21. Some of the holes accumulated in the first hole emission region Rd1 and the second hole emission region Rd2 are discharged to the carrier storage layer 70, the P-type base layer 29, and P + The holes are discharged to the emitter electrode 21 via the P-type contact layer 27. In addition, other holes accumulated in the first hole discharge region Rd1 and the second hole discharge region Rd2 move to the P-type floating layer 30, and then to the carrier accumulation layer 70, the P-type base layer 29, and P + The holes are discharged to the emitter electrode 21 via the type contact layer 27. In this embodiment, the portion of each channel region Rc on the second control electrode 39 side moves toward the emitter electrode 21.

[0078] During the second period P2, the semiconductor device 320 is in an ON state in which current flows from the collector electrode 23 to the emitter electrode 21 through each channel region Rc. Also, during the second period P2, a portion of the holes accumulated in the first hole emission region Rd1 and the second hole emission region Rd2 are discharged to the emitter electrode 21, so N - The carrier concentration accumulated in the base layer 31 can be reduced. As a result, similar to the first embodiment described above, in this embodiment, in the second period P2, N - While suppressing an excessive increase in the resistance of the base layer 31, -The carrier concentration in the base layer 31 can be reduced. Therefore, the increase in conduction loss in the second period P2 can be effectively suppressed, and the turn-off loss in the third period P3 can be effectively reduced.

[0079] According to this embodiment, the first floating region Rf1 is sandwiched between two second control electrodes 39, and a plurality of connecting electrodes 43 are arranged in the first floating region Rf1, spaced apart from each other along the second direction D2. Since the P-type floating layer 30 is conductive, when there is one connecting electrode 43 arranged in the first floating region Rf1, N - In the base layer 31, carriers accumulated in the portion overlapping with the first floating region Rf1 when viewed from the first direction D1 are discharged to the emitter electrode 21. Therefore, in the second period P2, N - There is a risk that the amount of carriers discharged from the base layer 31 may become too large. In contrast, in this embodiment, since multiple connecting electrodes 43 are arranged in the first floating region Rf1, N - In the base layer 31, when viewed from the first direction D1, carriers are less likely to be discharged to the emitter electrode 21 from the portion that overlaps with the multiple connecting electrodes 43 and the portion that overlaps with the space between the multiple connecting electrodes 43. As a result, in the second period P2, N - This can suppress the amount of carriers discharged from the base layer 31 to the emitter electrode 21 from becoming too large. Therefore, in the second period P2, N - Since it is possible to suppress the carrier concentration in the base layer 31 from becoming too low, it is possible to more effectively suppress the increase in conduction loss in the second period P2.

[0080] According to at least one embodiment described above, a semiconductor device can be provided that reduces both conduction loss and turn-off loss by arranging connecting electrodes in the first floating region.

[0081] The implemented semiconductor device includes the following appended features. (Note 1) A first electrode and a second electrode are arranged spaced apart from each other in the first direction, A plurality of control electrodes are arranged between the first electrode and the second electrode, spaced apart along a second direction intersecting the first direction, A connecting electrode electrically connected to the aforementioned first electrode, A first semiconductor layer of a first conductivity type electrically connected to the first electrode, A second semiconductor layer of a first conductivity type, electrically insulated from the first electrode, A second electrode and a third semiconductor layer of second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, A fourth semiconductor layer of first conductivity type is disposed between the second electrode and the third semiconductor layer, Equipped with, Each of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer is disposed between the first electrode and the second electrode. Each of the multiple regions sandwiched between the control electrodes arranged adjacent to each other in the second direction is either a channel region where the first semiconductor layer is arranged, or a floating region where the second semiconductor layer is arranged. The plurality of control electrodes include a plurality of first control electrodes to which a first voltage is applied, and a plurality of second control electrodes to which a second voltage is applied. The floating region includes a first floating region in which at least one of the control electrodes flanking the floating region is the second control electrode. A semiconductor device in which the connecting electrodes are arranged in the first floating region. (Note 2) The first floating region is sandwiched between one of the first control electrodes and one of the second control electrodes. The semiconductor device according to Appendix 1, wherein the distance between the connecting electrode and the second control electrode is greater than the distance between the connecting electrode and the first control electrode. (Note 3) The first floating region is sandwiched between one of the first control electrodes and one of the second control electrodes. The semiconductor device according to Appendix 1, wherein the distance between the connecting electrode and the second control electrode is smaller than the distance between the connecting electrode and the first control electrode. (Note 4) The first floating region is sandwiched between the two second control electrodes, The semiconductor device according to Appendix 1, wherein a plurality of the connecting electrodes are arranged in the first floating region, spaced apart from each other along the second direction. (Note 5) A semiconductor device further comprising a voltage control circuit capable of controlling the first voltage and the second voltage at different timings. (Note 6) The semiconductor device described in Appendix 5, wherein the voltage control circuit switches the first voltage after a predetermined time has elapsed since switching the second voltage. (Note 7) The semiconductor device according to Appendix 5 or Appendix 6, wherein the voltage control circuit switches the first voltage and the second voltage, respectively, to a first high voltage and a second high voltage, respectively, then switches the second voltage to a second low voltage which is lower than the second high voltage, and after a predetermined time has elapsed since switching the second voltage to the second low voltage, switches the first voltage to a first low voltage which is lower than the first high voltage.

[0082] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0083] 20, 220, 320… Semiconductor equipment, 21… Emitter electrode (first electrode), 23… Collector electrode (second electrode), 29… P-type base layer (first semiconductor layer), 30… P-type floating layer (second semiconductor layer), 31… N- 33...P-type base layer (third semiconductor layer), 35...P-type collector layer (fourth semiconductor layer), 36...Control electrode, 39...First control electrode, 43...Connecting electrode, 50...Voltage control circuit, D1...First direction, D2...Second direction, G1...Spacing between connecting electrode and first control electrode, G2...Spacing between connecting electrode and second control electrode, Rc...Channel region, Rf...Floating region, Rf1...First floating region, Vg1...First voltage, Vg2...Second voltage

Claims

1. A first electrode and a second electrode are arranged spaced apart from each other in the first direction, A plurality of control electrodes are arranged between the first electrode and the second electrode, spaced apart along a second direction intersecting the first direction, A connecting electrode electrically connected to the aforementioned first electrode, A first semiconductor layer of a first conductivity type electrically connected to the first electrode, A second semiconductor layer of a first conductivity type, electrically insulated from the first electrode, A second electrode and a third semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second semiconductor layer, A fourth semiconductor layer of first conductivity type is disposed between the second electrode and the third semiconductor layer, Equipped with, Each of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer is disposed between the first electrode and the second electrode. Each of the multiple regions sandwiched between the control electrodes arranged adjacent to each other in the second direction is either a channel region where the first semiconductor layer is arranged, or a floating region where the second semiconductor layer is arranged. The plurality of control electrodes include a plurality of first control electrodes to which a first voltage is applied, and a plurality of second control electrodes to which a second voltage is applied. The floating region includes a first floating region in which at least one of the control electrodes flanking the floating region is the second control electrode. A semiconductor device in which the connecting electrodes are arranged in the first floating region.

2. The first floating region is sandwiched between one of the first control electrodes and one of the second control electrodes. The semiconductor device according to claim 1, wherein the distance between the connecting electrode and the second control electrode is greater than the distance between the connecting electrode and the first control electrode.

3. The first floating region is sandwiched between one of the first control electrodes and one of the second control electrodes. The semiconductor device according to claim 1, wherein the distance between the connecting electrode and the second control electrode is smaller than the distance between the connecting electrode and the first control electrode.

4. The first floating region is sandwiched between the two second control electrodes, The semiconductor device according to claim 1, wherein a plurality of the connecting electrodes are arranged in the first floating region, spaced apart from each other along the second direction.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a voltage control circuit capable of controlling the first voltage and the second voltage at different timings.

6. The semiconductor device according to claim 5, wherein the voltage control circuit switches the first voltage after a predetermined time has elapsed since switching the second voltage.

7. The semiconductor device according to claim 5, wherein the voltage control circuit switches the first voltage and the second voltage, respectively, to a first high voltage and a second high voltage, respectively, then switches the second voltage to a second low voltage which is lower than the second high voltage, and after a predetermined time has elapsed since switching the second voltage to the second low voltage, switches the first voltage to a first low voltage which is lower than the first high voltage.

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