Semiconductor memory

Abstract

To provide a semiconductor memory device that operates optimally. [Solution] The semiconductor memory device comprises a substrate, first to third layers spaced apart from the substrate, first and second semiconductor layers facing the first to third layers, a first electrode connected to the first layer, a second electrode whose outer surface is surrounded by the first layer and whose end is connected to the second layer, a third electrode whose outer surface is surrounded by the first and second layers and whose end is connected to the third layer, and a first insulating layer that divides a part of the first layer but does not divide the second and third layers. The first layer includes a first conductive layer facing the first semiconductor layer and connected to the first electrode, a second conductive layer facing the second semiconductor layer, and an intermediate layer formed continuously in the region between the second electrode and the third electrode and not electrically connected to either the first or second conductive layer. The second and third layers each include a third conductive layer formed continuously in the region between the first and second semiconductor layers and facing the first and second semiconductor layers.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, semiconductor layers facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layers. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (SiN) or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-026518 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that operates optimally. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a first layer spaced apart from the substrate in a first direction intersecting the surface of the substrate, a second layer provided on one side of the first direction relative to the first layer, a third layer provided on one side of the first direction relative to the second layer, a first semiconductor layer and a second semiconductor layer extending in the first direction and facing the first layer, the second layer, and the third layer, a first electrode extending in the first direction and connected to the first layer, a second electrode extending in the first direction, its outer periphery surrounded by the first layer and one end in the first direction connected to the second layer, a third electrode extending in the first direction, its outer periphery surrounded by the first and second layers and one end in the first direction connected to the third layer, and a first insulating layer extending in the first direction and in a second direction intersecting the first direction, dividing a part of the first layer but not dividing the second and third layers. The second and third electrodes are further from the first semiconductor layer than the first electrode in the second direction. The second semiconductor layer is further from the first semiconductor layer than the second and third electrodes in the second direction. The first layer includes a first conductive layer facing the first semiconductor layer and connected to the first electrode, a second conductive layer facing the second semiconductor layer, and an intermediate layer formed continuously in the region between the second and third electrodes and not electrically connected to either the first or second conductive layer. The second and third layers each include a third conductive layer formed continuously in the region between the first and second semiconductor layers and facing the first and second semiconductor layers, respectively. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic plan view of the semiconductor memory device. [Figure 3] This is a schematic enlarged view of the area indicated by A in Figure 2. [Figure 4] This is a schematic enlarged view of the memory hole region (RMH). [Figure 5] Figure 4 is a schematic cross-sectional view taken by cutting the structure along line DD' and viewing it in the direction of the arrow. [Figure 6] This is a schematic enlarged view of the area indicated by E in Figure 5. [Figure 7] This is a schematic cross-sectional view illustrating the structure of the part indicated by A2 in Figure 2. [Figure 8] A schematic cross-sectional view of the portion indicated by A in Figure 2. [Figure 9] This is a schematic cross-sectional view to illustrate the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 10] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 11] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 12] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 13] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating a semiconductor memory device manufacturing method 2 according to the first embodiment. [Figure 15] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 16] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 17] This is a schematic cross-sectional view to illustrate the semiconductor memory device manufacturing method 3 according to the first embodiment. [Figure 18] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 19] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 20] This is a schematic plan view showing a part of the configuration of Modification 1 of the First Embodiment. [Figure 21] This is a schematic plan view showing a part of the configuration of a modified example 2 of the first embodiment. [Figure 22] This is a schematic cross-sectional view showing a portion of the structure of the modified example. [Figure 23] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 24]This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 25] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 26] This is a schematic plan view illustrating the method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 27] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 28] This is a schematic plan view illustrating the manufacturing method. [Figure 29] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 30] This is a schematic plan view illustrating the manufacturing method. [Figure 31] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 32] This is a schematic plan view illustrating the manufacturing method. [Figure 33] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 34] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 35] This is a schematic plan view illustrating the manufacturing method. [Figure 36] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 37] This is a schematic plan view illustrating the manufacturing method. [Figure 38] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 39] This is a schematic plan view illustrating the manufacturing method. [Figure 40] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 41] This is a schematic plan view illustrating the manufacturing method. [Figure 42] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 43] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 44] This is a schematic plan view illustrating the manufacturing method. [Figure 45] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 46] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 47] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 48] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 49] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 50] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 51] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 52] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 53] This is a schematic cross-sectional view illustrating the method for manufacturing a semiconductor memory device according to the third embodiment. [Figure 54] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 55] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 56] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 57] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 58] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 59] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 60] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 61]This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 62] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 63] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 64] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 65] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 66] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 67] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 68] This is a schematic cross-sectional view to illustrate the manufacturing method. [Figure 69] This is a schematic cross-sectional view showing some of the components of a modified example of the third embodiment. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0012] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0013] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0014] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0015] [First Embodiment] [composition] [Circuit configuration of the memory die MD] Figure 1 is a schematic circuit diagram showing a part of the configuration of a memory die MD. As shown in Figure 1, the memory die MD comprises a memory cell array MCA and a peripheral circuit PC. The memory cell array MCA comprises a plurality of memory blocks BLK. Each of these memory blocks BLK comprises a plurality of string units SU. Each of these string units SU comprises a plurality of memory strings MS. One end of each of these memory strings MS is connected to the peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0016] A memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory transistors), and a source-side selection transistor STS. The drain-side selection transistor STD, the multiple memory cells MC, and the source-side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0017] A memory cell MC is a field-effect transistor. A memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are commonly connected to all memory string MS in one memory block BLK.

[0018] Selection transistors (STD, STS) are field-effect transistors. Each selection transistor (STD, STS) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage layer. Selection gate lines (SGD, SGS) are connected to the gate electrodes of each selection transistor (STD, STS). One drain-side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK.

[0019] [Memory die MD structure] Figure 2 is a schematic plan view of the memory die MD. Figure 3 is a schematic enlarged view of the part indicated by A in Figure 2. Figure 4 is the memory hole region R. MH This is a schematic enlarged view. Figure 5 is a schematic cross-sectional view of the structure shown in Figure 4, cut along line DD' and viewed in the direction of the arrow. Figure 6 is a schematic enlarged view of the part indicated by E in Figure 5. Figure 7 is a schematic cross-sectional view to illustrate the structure of the part indicated by A2 in Figure 2. Figure 8 is a schematic cross-sectional view of the part indicated by A in Figure 2.

[0020] For example, as shown in Figure 2, the memory die MD includes a semiconductor substrate 100. The semiconductor substrate 100 is a semiconductor substrate made of p-type silicon (Si) containing p-type impurities such as boron (B). The surface of the semiconductor substrate 100 is provided with an N-type well region containing an N-type impurity such as phosphorus (P), a p-type well region containing a p-type impurity such as boron (B), a semiconductor substrate region where neither the N-type well region nor the p-type well region is provided, and an insulating region.

[0021] Furthermore, the memory die MD has four memory cell array regions R aligned in the X and Y directions. MCA It includes the memory cell array region R. MCA These are two memory hole regions R aligned in the X direction. MH And these memory hole regions R MH Hookup region R provided between HU It also includes a memory cell array region R MCA Multiple memory blocks BLK are provided, aligned in the Y direction. Between two adjacent memory blocks BLK in the Y direction, an interblock structure ST, such as silicon oxide (SiO2), is provided, as shown in Figure 4.

[0022] The memory block BLK comprises multiple string units SU arranged in the Y direction. In Figures 3 and 4, five string units SU arranged in the Y direction are shown as string units SUa, SUb, SUc, SUd, and SUe, starting from the negative side in the Y direction. Between two adjacent string units SU in the Y direction, an inter-string unit insulating layer SHE, such as silicon oxide (SiO2), is provided.

[0023] The memory block BLK comprises a plurality of conductive layers 110 arranged in the Z direction, as shown in Figures 5 to 8, for example. An insulating layer 101, such as silicon oxide (SiO2), is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0024] The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction and the Y direction. As shown in, for example, FIG. 7, the conductive layer 110 includes two memory hole regions R arranged in the X direction MH , and a hook-up region R HU therebetween.

[0025] The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Further, the conductive layer 110 may include, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). Note that the conductive layer 110 functions as a gate electrode and a word line WL of the memory cell MC, or a gate electrode and a select gate line (SGD, SGS) of the select transistor (STD, STS).

[0026] The memory hole region R of the memory block BLK MH includes, as shown in, for example, FIG. 5, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120, respectively.

[0027] Among the plurality of conductive layers 110, one or more conductive layers 110 located at the uppermost layer may be referred to as the conductive layer 110 (SGD) in the following description (FIGS. 7 and 8). The conductive layer 110 (SGD) is a drain side select gate line SGD and a plurality of drain side select transistors STD connected thereto in a part (region R MH ) of the memory hole region R HU and the hook-up region R HU_S . In a part (region R MH ) of the memory hole region R HU and the hook-up region R HU_S , a string unit interlayer insulating layer SHE is provided between two adjacent conductive layers 110 (SGD) in the Y direction (FIG. 5), and the conductive layers 110 (SGD) in these regions are electrically independent for each string unit SU, respectively.

[0028] Furthermore, in the following description, multiple conductive layers 110 located below conductive layer 110 (SGD) may be referred to as conductive layer 110 (WL) (Figures 7 and 8). Conductive layer 110 (WL) functions as the gate electrode of the word line WL (Figure 1) and the multiple memory cells MC (Figure 1) connected thereto. Each of the multiple conductive layers 110 (WL) is electrically independent for each memory block BLK.

[0029] Furthermore, one or more conductive layers 110 located below conductive layer 110 (WL) may be referred to as conductive layer 110 (SGS) in the following description (Figure 8). Conductive layer 110 (SGS) functions as the gate electrode of the source-side selection gate line SGS (Figure 1) and the multiple source-side selection transistors STS connected thereto. Conductive layer 110 (SGS) is electrically independent for each memory block BLK.

[0030] The inter-string unit insulating layer SHE extends, for example, in the X and Z directions. The inter-string unit insulating layer SHE is provided along the extending direction of the inter-block structure ST, for example, as shown in Figures 3 and 4. The lower surface of the inter-string unit insulating layer SHE is provided between the bottom conductive layer 110 (SGD) and the top conductive layer 110 (WL), for example, as shown in Figure 5. The inter-string unit insulating layer SHE divides the conductive layer 110 (SGD) in the Y direction but does not divide the conductive layer 110 (WL).

[0031] Furthermore, among the multiple conductive layers 110, one or more dummy conductive layers 110(DM) may be provided between the bottom conductive layer 110(SGD) and the top conductive layer 110(WL) (Figures 5 to 8). The string unit insulating layer SHE may or may not divide the conductive layer 110(DM) in the Y direction.

[0032] The width of the conductive layer 110 (SGD) in the Y direction is smaller than the width of the conductive layer 110 (WL) in the Y direction. For example, in the examples shown in Figures 3 and 4, five conductive layers 110 (SGD) arranged in the Y direction and four string unit insulating layers SHE arranged in the Y direction are provided corresponding to one conductive layer 110 (WL). In the illustrated examples, the width of the conductive layer 110 (SGD) in the Y direction is smaller than 1 / 5 of the width of the conductive layer 110 (WL) in the Y direction.

[0033] A semiconductor layer 112 is provided below the conductive layer 110 (Figure 5). The semiconductor layer 112 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is provided between the semiconductor layer 112 and the conductive layer 110. The semiconductor layer 112 functions as part of the source wire SL.

[0034] The semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions, as shown in Figure 4, for example. The semiconductor layer 120 functions as the channel region of multiple memory cells (MC) and selection transistors (STD, STS). The semiconductor layer 120 is, for example, a semiconductor layer made of polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, as shown in Figure 5, for example, and an insulating layer 125 made of silicon oxide (SiO2) or the like is provided in the central part. The outer circumferential surfaces of the semiconductor layer 120 are each surrounded by conductive layers 110 and face the conductive layers 110.

[0035] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. In the example in Figure 5, the boundary line between the upper end of the semiconductor layer 120 and the lower end of the impurity region 121 is shown by a dashed line. The impurity region 121 is connected to the bit line BL via contacts Ch and Vy (Figure 4).

[0036] The lower end of the semiconductor layer 120 is connected to the semiconductor layer 112.

[0037] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110, as shown in Figure 6, for example. The tunnel insulating film 131 and the block insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a charge-storing film such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor layer 120, excluding the contact area between the semiconductor layer 120 and the semiconductor layer 112.

[0038] Figure 6 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0039] The interblock structure ST consists of two memory hole regions R aligned in the X direction, as shown in Figure 3, for example. MH , and the hookup region R between them HU It extends in the X direction over a certain distance. Furthermore, the interblock structure ST extends in the Z direction so as to divide the multiple insulating layers 101 and the multiple conductive layers 110 in the Y direction, as shown in Figure 5, for example. The positive and negative Y-direction sides of the conductive layer 110 (WL) are in contact with the interblock structure ST. The multiple conductive layers 110 are electrically insulated from the components in other memory blocks BLK via the interblock structure ST.

[0040] The interblock structure ST includes, for example, a conductive layer 141 extending in the Z and X directions, and an insulating layer 142 made of silicon oxide (SiO2) or the like, provided on the Y-direction side of the conductive layer 141, as shown in Figure 5. The conductive layer 141 is connected to, for example, a semiconductor layer 112. The conductive layer 141 may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions, for example, as part of the source wire SL (Figure 1).

[0041] Furthermore, the interblock structure ST may not have a conductive layer 141, and may be formed only by an insulating layer 142.

[0042] Hookup region R of memory block BLK HU For example, as shown in Figures 3 and 7, region R HU_S And, region R HU_W It is equipped with the following.

[0043] [Area R HU_S ] area R HU_S A portion of the conductive layer 110 is provided in the region R, for example, as shown in Figures 3, 7, and 8. HU_S Each string unit SU is provided with a contact electrode array CCSG (Figure 8). Furthermore, region R HU_S As shown in Figure 3, for example, a portion of the inter-string unit insulating layer SHE and an insulating layer SHE_V in contact with the X-direction end of the inter-string unit insulating layer SHE are provided in region R. HU_S For example, as shown in Figure 3, multiple support structures HR arranged in the X and Y directions may be provided.

[0044] area R HU_S The conductive layer 110 (SGD) is located in the memory hole region R MH It is provided in a continuous manner with the conductive layer 110 (SGD) and is electrically connected (Figures 7 and 8). Region R HU_S In this configuration, two adjacent conductive layers 110 (SGD) in the Y direction are separated in the X direction by the inter-string unit insulating layer SHE and are not electrically connected (Figure 3).

[0045] area R HU_S The width of the conductive layer 110 (SGD) in the Y direction is the width of the memory hole region R MH The width of the conductive layer 110 (SGD) in the Y direction may be different. Region R HU_SThe width of the conductive layer 110 (SGD) in the Y direction may be such that, as shown in Figure 3, for example, the width of the conductive layer 110 (SGD) closer to the interblock structure ST is larger, and the width of the conductive layer 110 (SGD) further from the interblock structure ST is smaller.

[0046] area R HU_S The conductive layer 110 (WL) is located in the memory hole region R MH It is provided continuously with the conductive layer 110 (WL) and is electrically connected (Figures 7 and 8). Region R HU_S The conductive layer 110 (WL) is not separated by the inter-string unit insulating layer SHE.

[0047] area R HU_S The insulating layer SHE between string units is located in the memory hole region R MH The insulating layer SHE between string units is basically provided in the same way as in region R. HU_S The insulating layer SHE between string units is located in the memory hole region R MH It is provided in conjunction with the insulating layer SHE between string units. For example, as shown in Figure 3, region R HU_S The width of the conductive layer 110 (SGD) in the Y direction is such that the memory hole region R MH When the width of the conductive layer 110 (SGD) in the Y direction is different, the memory hole region R MH From the region R HU_S In this regard, the string unit insulating layer SHE may include a portion that extends in the X direction and a portion that extends in a direction different from the X direction.

[0048] The insulating layer SHE_V is located in region R, as shown in Figures 3 and 8, for example. HU_S The conductive layer 110 (SGD) and region R HU_W The insulating layer SHE_V is provided between the conductive layer 110 (SGD) and the contact electrode CC. The insulating layer SHE_V extends, for example, in the Y and Z directions. Both ends of the insulating layer SHE_V in the Y direction are in contact with the interblock structures ST provided at both ends of the memory block BLK in the Y direction, for example, as shown in Figure 3.

[0049] The lower surface of the insulating layer SHE_V is located between the bottom conductive layer 110(SGD) and the top conductive layer 110(WL), as shown in Figure 8, for example. The insulating layer SHE_V is located in region R HU_S The conductive layer 110 (SGD) and region R HU_W The conductive layer 110 (SGD) and the insulating layer SHE_V are separated in the X direction, electrically separating them. The insulating layer SHE_V does not separate the conductive layer 110 (WL). The insulating layer SHE_V contains, for example, silicon oxide (SiO2).

[0050] The contact electrode array CCSG comprises multiple contact electrodes CCS arranged in the X direction, as shown in Figure 8, for example.

[0051] The contact electrode CCS is extended in the Z direction and connected at its lower end to one of a plurality of conductive layers 110 (SGD). The contact electrode CCS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). An insulating layer 170 such as silicon oxide (SiO2) is provided on the outer circumferential surface of the contact electrode CCS. The outer circumferential surface of the contact electrode CCS is surrounded by conductive layers 110 (SGD) via the insulating layer 170.

[0052] In the following explanation, the conductive layer 110 (SGD) that is m-th (where m is an integer greater than or equal to 1) from the top may be referred to as conductive layer 110(m-1). Also, among the multiple contact electrodes CCS, the one connected to conductive layer 110(m) may be referred to as contact electrode CCS(m).

[0053] Figure 8 shows region R HU_S In this, the memory hole region R MH Examples of contact electrodes CCS(0), CCS(1), CCS(4), and CCS(5) are shown, arranged in order from closest to furthest.

[0054] Furthermore, the contact electrodes CCS(m) provided on each of the string units SUa, SUb, SUc, SUd, and SUe, which are aligned in the Y direction, do not all have to be aligned in the Y direction; their positions in the X direction may differ (Figure 3).

[0055] The support structure HR extends in the Z direction and penetrates multiple conductive layers 110 aligned in the Z direction. The support structure HR includes, for example, silicon oxide (SiO2).

[0056] [Area R HU_W ] area R HU_W A portion of the conductive layer 110 is provided in the region R, for example, as shown in Figures 3, 7, and 8. HU_W For example, two contact electrode arrays CCG are provided in the Y direction. In Figure 3, these two contact electrode arrays CCG are shown as contact electrode array CCG(0) and CCG(1). Also, region R HU_W In the region R HU_S Similarly, multiple support structures HR arranged in the X and Y directions may be provided.

[0057] area R HU_W The conductive layer 110 (SGD) is located in the memory hole region R MH and region R HU_S The conductive layer 110 (SGD) is separated in the X direction by the insulating layer SHE_V, is not provided continuously, and is not electrically connected (Figures 7 and 8).

[0058] area R HU_W The conductive layer 110 (WL) is located in the memory hole region R MH and region R HU_S It is provided in continuous with the conductive layer 110 (WL) and is electrically connected to it (Figures 7 and 8).

[0059] The contact electrode array CCG comprises multiple contact electrodes CC arranged in the X direction, as shown in Figure 8, for example.

[0060] The contact electrode CC is extended in the Z direction and connected at its lower end to one of the conductive layers 110(WL). The contact electrode CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). An insulating layer 160 such as silicon oxide (SiO2) is provided on the outer circumferential surface of the contact electrode CC. The outer circumferential surface of the contact electrode CC is surrounded by the conductive layer 110(SGD) and the conductive layer 110(WL) via the insulating layer 160.

[0061] In the following explanation, the nth conductive layer 110 (where n is an integer greater than or equal to 1) from the top of the conductive layer 110 (WL) may be referred to as conductive layer 110(n-1). Also, among the multiple contact electrodes CC, the one connected to conductive layer 110(n) may be referred to as contact electrode CC(n).

[0062] Figure 8 shows region R HU_W In this, the memory hole region R MH This shows an example of contact electrodes CC(0), CC(2), CC(4), and CC(6) in the contact electrode array CCG(0), arranged in order from closest to furthest.

[0063] Furthermore, the contact electrodes CC(0), CC(2), CC(4), and CC(6) in the contact electrode array CCG(0) may be aligned in the Y direction with multiple contact electrodes CC(1), CC(3), CC(5), and CC(7) in the contact electrode array CCG(1).

[0064] [Layer structure of conductive layer 110 (SGD) and conductive layer 110 (WL)] The conductive layer 110 (SGD) has, for example, a memory hole region R on one side, as shown in Figure 7. MH A conductive layer 110I is provided opposite the semiconductor layer 120 and connected to the contact electrode CCS, and a hook-up region R HU The other memory hole region R via MHThe semiconductor layer 120 provided therein is opposed to a conductive layer 110II connected to a contact electrode CCS. Furthermore, an intermediate layer 110J is provided in the layer containing the conductive layer 110I and the conductive layer 110II, for example, as shown in Figure 7. The intermediate layer 110J is a layer continuously formed in the region between the contact electrodes CC, which are at different positions in the X direction, and is not electrically connected to either the conductive layer 110I or the conductive layer 110II.

[0065] The conductive layers 110I, 110II, and the intermediate layer 110J contain the same material.

[0066] The conductive layer 110 (WL) has a memory hole region R on one side, as shown in Figure 7, for example. MH A semiconductor layer 120 is provided therein, and a hookup region R HU The other memory hole region R via MH A semiconductor layer 120 provided on and a layer formed continuously in the region between them, and including a conductive layer 110III facing these semiconductor layers 120.

[0067] The conductive layer 110III contains the same material as conductive layers 110I, 110II, and the intermediate layer 110J.

[0068] The insulating layer SHE_V is provided between the conductive layer 110I and the intermediate layer 110J.

[0069] Next, a plurality of manufacturing methods for producing a semiconductor memory device according to the first embodiment will be described.

[0070] [Manufacturing method 1] Figures 9 to 13 are schematic cross-sectional views illustrating a semiconductor memory device manufacturing method 1 according to the first embodiment. In manufacturing method 1, contact electrodes CC and CCS are formed simultaneously.

[0071] In this manufacturing method, for example, as shown in Figure 9, a semiconductor layer 112 is formed on a substrate (not shown). Furthermore, multiple insulating layers 101 and multiple sacrificial layers 111 are alternately formed above the semiconductor layer 112. The sacrificial layers 111 include, for example, silicon nitride (SiN). This process is carried out, for example, by CVD (Chemical Vapor Deposition).

[0072] Next, as shown in Figure 9, for example, the memory hole region R MH Multiple semiconductor layers 120, etc., are formed. In this process, openings are formed that penetrate multiple insulating layers 101 and multiple sacrificial layers 111, and a gate insulating film 130 (Figure 6) and semiconductor layers 120, etc., are formed on the inner circumferential surface of these openings. This process is carried out, for example, by RIE (Reactive Ion Etching), CVD, etc.

[0073] Next, as shown in Figure 10, for example, a hard mask 104 made of amorphous silicon (α-Si) or the like is formed on the upper surface of the structure shown in Figure 9, and then multiple openings CCA and CCSA are formed. The multiple openings CCA and CCSA penetrate, for example, the hard mask 104, one or more insulating layers 101, and one or more sacrificial layers 111, exposing the upper surface of one of the insulating layers 101. As the shallowest opening CCSA (not shown), an opening that penetrates the hard mask 104 and has its lower end in the uppermost insulating layer 101 may be formed. In this process, the formation and patterning of the hard mask 104 and the removal of the insulating layer 101 and sacrificial layer 111 by RIE or the like are repeated multiple times until each opening reaches a predetermined depth.

[0074] Next, as shown in Figure 11, for example, the hard mask 104 is removed, and an insulating layer 180 containing the same material as insulating layers 160 and 170 is formed on the upper surface of the structure shown in Figure 10 and inside the openings CCA and CCSA. This process is carried out by, for example, CVD.

[0075] Next, as shown in Figure 12, for example, a portion of the insulating layer 180 on the upper surface of the structure shown in Figure 11, a portion of the insulating layer 180 at the bottom of the openings CCA and CCSA, and one layer of the insulating layer 101 closest to the bottom of each opening CCA and CCSA are removed to form insulating layers 160 and 170. This process is carried out, for example, by RIE.

[0076] Next, as shown in Figure 12, for example, a sacrificial layer 190 of amorphous silicon (α-Si) or the like is formed inside the opening CCA and CCSA. This process is carried out, for example, by CVD.

[0077] Next, a conductive layer 110 is formed, for example, as shown in Figure 13. In this step, for example, by a method such as RIE, openings are formed that penetrate multiple insulating layers 101 and multiple sacrificial layers 111 at positions corresponding to the interblock structure ST (Figure 3). Next, the multiple sacrificial layers 111 are removed by wet etching or the like through these openings. Then, multiple conductive layers 110 are formed by a method such as CVD.

[0078] Next, as shown in Figure 8, for example, the sacrificial layer 190 is removed to form contact electrodes CC and CCS. This process is carried out by, for example, wet etching, CVD, etc.

[0079] Next, for example, an inter-string unit insulating layer SHE and an insulating layer SHE_V are formed as shown in Figure 8. In this step, after forming openings that penetrate multiple insulating layers 101 and multiple conductive layers 110 at positions corresponding to the inter-string unit insulating layer SHE and insulating layer SHE_V, silicon oxide (SiO2) or the like is formed in the openings. This step is carried out by, for example, RIE, CVD, etc.

[0080] Subsequently, structures above the contact electrodes CC and CCS, such as the bit line BL, are formed to create the semiconductor memory device described with reference to Figures 1 to 8.

[0081] [Manufacturing method 2] Figures 14 to 16 are schematic cross-sectional views illustrating a semiconductor memory manufacturing method 2 according to the first embodiment. In manufacturing method 2, the contact electrode CCS is formed first, and then the contact electrode CC is formed.

[0082] In this manufacturing method, the same steps as those described up to the step shown in Figure 9 are performed.

[0083] Next, as shown in Figure 14, for example, multiple opening CCSAs are formed at positions corresponding to the contact electrode CCS. This step is performed in the same manner as described with reference to Figure 10.

[0084] Next, an insulating layer 170 is formed, for example, as shown in Figure 15. In this step, an insulating layer 180 is formed inside the opening CCSA, similar to the step shown in Figure 11, and then a portion of the insulating layer 180 at the bottom of the opening CCSA is removed. This step is performed, for example, by CVD, RIE, etc.

[0085] Next, multiple open CCAs are formed, for example, as shown in Figure 16. In this step, a hard mask 105 made of amorphous silicon (α-Si) or the like is formed on the upper surface of the structure shown in Figure 15 and inside the open CCAs, and the open CCAs are formed in the same manner as described with reference to Figure 10.

[0086] Next, the same process as described with reference to Figures 11 to 13 is performed on the opening CCSA to form an insulating layer 160 and a conductive layer 110, after which the contact electrodes CC and CCS are formed.

[0087] Next, for example, in the same manner as in manufacturing method 1, an insulating layer SHE and an insulating layer SHE_V are formed between string units.

[0088] Subsequently, structures above the contact electrodes CC and CCS, such as the bit line BL, are formed to create the semiconductor memory device described with reference to Figures 1 to 8.

[0089] [Manufacturing method 3] Figures 17 to 19 are schematic cross-sectional views illustrating a semiconductor memory manufacturing method 3 according to the first embodiment. In manufacturing method 3, the contact electrode CC is formed first, and then the contact electrode CCS is formed.

[0090] In this manufacturing method, the process described with reference to Figures 9 to 13 is performed in region R HU_W This process is performed only on the surface, and as shown in Figure 17, a semiconductor layer 120, multiple conductive layers 110, multiple contact electrodes CC, etc. are formed.

[0091] Next, as shown in Figure 18, for example, multiple opening CCSAb are formed. The multiple opening CCSAb penetrate one or more insulating layers 101 and one or more conductive layers 110, exposing the upper surface of one of the multiple conductive layers 110 (SGD). This step is performed, for example, by RIE.

[0092] Next, as shown in Figure 19, for example, an insulating layer containing the same material as the insulating layer 170 is formed inside the opening CCSAb, and a portion of the insulating layer at the bottom of the opening CCSAb is removed to form the insulating layer 170. This process is carried out by, for example, CVD, RIE, etc.

[0093] Next, a contact electrode CCS is formed on the open CCSAb. This process is carried out, for example, by CVD.

[0094] Next, for example, in the same manner as in manufacturing method 1, an insulating layer SHE and an insulating layer SHE_V are formed between string units.

[0095] Subsequently, structures above the contact electrodes CC and CCS, such as the bit line BL, are formed to create the semiconductor memory device described with reference to Figures 1 to 8.

[0096] [effect] As shown in Figures 3, 7, and 8, the semiconductor memory device according to this embodiment has region R HU_S Each string unit SU contains a conductive layer 110 (SGD) in region R HU_WThe conductive layer 110 (SGD) and the insulating layer SHE_V are electrically separated. In such a configuration, region R HU_S The multiple conductive layers 110 (SGD) are located in region R HU_W They do not conduct electricity to each other through the conductive layer 110 (SGD). Therefore, region R HU_S The conductive layer 110 (SGD) contained in each string unit SU is insulated from each other, making the string units SU electrically independent of each other, and thus providing a suitably operating semiconductor memory device.

[0097] Furthermore, according to manufacturing method 1, contact electrodes CC and CCS can be formed simultaneously, thus suppressing the increase in the number of manufacturing steps and enabling the provision of a semiconductor memory device that can be manufactured at low cost.

[0098] [Modification 1 of the First Embodiment] Next, with reference to Figure 20, a modified example 1 of the semiconductor memory device according to the first embodiment will be described. Figure 20 is a schematic plan view showing a part of the configuration of the semiconductor memory device according to this modified example.

[0099] In the semiconductor memory device according to this modified example, the insulating layer SHE_V (Figure 3) is not provided, and instead, the insulating layer SHE_V2 (Figure 20) is provided.

[0100] The insulating layer SHE_V2 is basically constructed in the same way as the insulating layer SHE_V (Figure 3). However, one end of the insulating layer SHE_V2 in the Y direction does not contact the interblock structure ST provided on one side of the memory block BLK in the Y direction. The other end of the insulating layer SHE_V2 in the Y direction does contact the interblock structure ST provided on the other side of the memory block BLK in the Y direction.

[0101] In this modified example, region R HU_S Of the five conductive layers 110(SGD), the first conductive layer 110(SGD) counting from the negative side in the Y direction in Figure 20, and region R HU_WThe conductive layers 110 (SGD) are electrically connected. On the other hand, the 2nd to 5th conductive layers 110 (SGD) counting from the negative side in the Y direction in Figure 20 and region R HU_S The conductive layer 110 (SGD) is electrically separated from the insulating layer SHE_V. Even with this configuration, region R HU_S The five conductive layers 110 (SGD) are located in region R HU_W They do not conduct electricity to each other through the conductive layer 110 (SGD). Therefore, even with a structure like this modified example, region R HU_S The five conductive layers 110 (SGD) are insulated from each other, allowing the string units SU to be electrically isolated from one another.

[0102] [Modification 2 of the First Embodiment] Next, a modified example 2 of the semiconductor memory device according to the first embodiment will be described with reference to Figures 21 and 22. Figure 21 is a schematic plan view showing a part of the configuration of the semiconductor memory device according to this modified example. Figure 22 shows a cross-section of the structure shown in Figure 21, cut along the FF' line and viewed along the direction of the arrow.

[0103] In the semiconductor memory device according to this modified example, the insulating layer SHE_V (Figure 3) is not provided, and instead, the insulating layer SHE_V3 (Figure 21) is provided.

[0104] The insulating layer SHE_V3 is basically constructed in the same way as the insulating layer SHE_V (Figure 3). However, the insulating layer SHE_V3 extends in the Y direction across the memory block BLK and the interblock structure ST provided on both sides of the memory block BLK in the Y direction. For example, as shown in Figure 22, at the intersection PT10 (Figure 22) of the interblock structure ST and the insulating layer SHE_V3, the upper surface of the conductive layer 141 included in the interblock structure ST is in contact with the lower surface of the insulating layer SHE_V3.

[0105] Furthermore, the upper surface of the conductive layer 141 at the intersection PT10 may be located between the lowest conductive layer 110 (SGD) and the uppermost conductive layer 110 (WL), as shown in Figure 22.

[0106] [Second Embodiment] Figure 23 is a schematic plan view showing a part of the configuration of the semiconductor memory device according to this embodiment. Figure 23 is a schematic enlarged view of the part indicated by A in Figure 2. Figures 24 and 25 are schematic cross-sectional views showing a part of the configuration of the semiconductor memory device according to this embodiment. Figure 25 is a schematic cross-sectional view taken by cutting the structure shown in Figure 23 along line GG' and viewing it in the direction of the arrow. In the following description, parts the same as in the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0107] The semiconductor memory device according to this embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to this embodiment (Figure 23) does not have an insulating layer SHE_V (Figure 3).

[0108] The semiconductor memory device according to this embodiment has region R HU_S In this embodiment, a contact electrode array CCSG_L (Figure 24) is provided instead of the contact electrode array CCSG (Figure 8). Furthermore, an insulating layer 210 is provided in the semiconductor memory device according to this embodiment.

[0109] A contact electrode array CCSG_L is provided for each string unit SU. The contact electrode array CCSG_L comprises multiple contact electrodes CCS_L arranged in the X direction, for example, as shown in Figure 24.

[0110] The contact electrode CCS_L is stretched in the Z direction and connected at its lower end to one of the multiple conductive layers 110 (SGD). The contact electrode CCS_L may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0111] In the following explanation, among the multiple contact electrodes CCS_L, the one connected to the conductive layer 110(m) may be referred to as contact electrode CCS_L(m).

[0112] In the example shown in Figure 24, region R HU_S In this, the memory hole region R MH Examples of contact electrodes CCS(0) and CCS(4) are shown, arranged in order from closest to furthest. Furthermore, among the multiple contact electrodes CCS_L, the one connected to the conductive layer 110(DM) is shown as contact electrode CCS_L(D).

[0113] For example, in the example shown in Figure 25, the contact electrodes CCS_L(m) provided on each of the string units SUa, SUb, SUc, SUd, and SUe, which are aligned in the Y direction, are all aligned in the Y direction. An inter-string unit insulating layer SHE is provided between the contact electrodes CCS_L(m) provided on each of two adjacent string units SU. The contact electrodes CCS_L(m) provided on each of two adjacent string units SU are insulated by the inter-string unit insulating layer SHE. At least one of the Y-direction sides of the contact electrode CCS_L is in contact with the inter-string unit insulating layer SHE, as shown in Figure 25, for example.

[0114] The insulating layer 210 is provided so as to surround the outer surface of the contact electrodes CCS_L(m) arranged in the Y direction, as shown in Figure 23, for example. The insulating layer 210 is located in region R HU_S The conductive layer 110 (SGD) and region R HU_W The conductive layer 110 (SGD) and the insulating layer 210 are separated in the X direction, electrically separating them. The insulating layer 210 does not separate the conductive layer 110 (WL). The insulating layer 210 contains, for example, silicon oxide (SiO2).

[0115] Furthermore, a portion of the insulating layer 210 is provided on both sides of the contact electrode CCS_L in the X direction, as shown in Figures 23 and 24. Both sides of the contact electrode CCS_L in the X direction are surrounded by the conductive layer 110 (SGD) via the insulating layer 210.

[0116] Furthermore, a portion of the insulating layer 210 is also provided on the side surface (Figures 23 and 25) in the Y direction of the contact electrode CCS_L located on the ST side of the interblock structure in the string units SUa and SUe, which are closest to the interblock structure ST.

[0117] [Manufacturing method] Figures 26 to 46 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0118] Figures 26, 28, 30, 32, 35, 37, 39, 41, and 44 show plan views corresponding to Figure 23. Furthermore, in Figures 26, 28, 30, and 32, the area P_ST corresponding to the inter-block structure ST is shown with a dotted line.

[0119] Figures 27, 29, 31, 33, 36, 38, 40, 42, 45, and 46 show cross-sections corresponding to Figure 24.

[0120] Figures 34 and 43 show cross-sections corresponding to Figure 25.

[0121] In this manufacturing method, for example, as shown in Figures 26 and 27, a semiconductor layer 112 is formed on a substrate (not shown). Furthermore, multiple insulating layers 101 and multiple sacrificial layers 111 are alternately formed above the semiconductor layer 112. This process is carried out, for example, by CVD.

[0122] Next, as shown in Figures 26 and 27, for example, the memory hole region R MH Multiple sacrificial layers 120S are formed. In this process, openings are formed that penetrate multiple insulating layers 101 and multiple sacrificial layers 111, and sacrificial layers 120S such as amorphous silicon (α-Si) are formed inside these openings. This process is carried out by, for example, RIE, CVD, etc.

[0123] Next, as shown in Figures 26 and 27, for example, the hook-up region R HUNext, a support structure HR_L is formed. In this step, openings are formed that penetrate multiple insulating layers 101 and multiple sacrificial layers 111, and an insulating layer containing silicon oxide (SiO2) or the like is formed inside these openings. This step is carried out by, for example, RIE, CVD, etc. Note that the step of forming the openings of the support structure HR_L may be carried out simultaneously with the step of forming the openings of the sacrificial layer 120S.

[0124] Next, as shown in Figures 28 and 29, for example, an insulating layer 102 made of silicon oxide (SiO2) or the like is formed on the upper surface of the structure shown in Figure 27, and multiple insulating layers 101 and multiple sacrificial layers 111 are formed alternately. This process is carried out by, for example, CVD.

[0125] Next, multiple openings CCA and CCS_LA are formed, for example, as shown in Figures 30 and 31. The openings CCS_LA extend in the Z direction, as shown in Figure 31, for example, penetrating one or more insulating layers 101 and one or more sacrificial layers 111, and exposing the upper surface of one of the insulating layers 101. The bottom surface of the shallowest opening CCSA may be located above the upper surface of the uppermost sacrificial layer 111. The openings CCS_LA are also provided as a line shape extending in the Y direction across the memory block BLK and a part of the region P_ST where the interblock structure ST is formed, as shown in Figure 30, for example. Multiple openings CCA and CCS_LA are formed in the same manner as described with reference to Figure 10, for example.

[0126] Next, as shown in Figures 32 to 34, for example, insulating layers 210' and 160 containing the same material as insulating layer 210, and a sacrificial layer 290 made of amorphous silicon (α-Si) are formed inside the multiple openings CCA and CCS_LA. In this process, insulating layers containing the same material as insulating layers 210 and 160 are formed inside the multiple openings CCA and CCS_LA, the bottom portions of the insulating layers that are attached to the multiple openings CCA and CCS_LA are removed to form insulating layers 210' and 160, and then the sacrificial layer 290 is formed inside the multiple openings CCA and CCS_LA. This process is carried out by, for example, CVD, RIE, etc.

[0127] Next, as shown in Figures 35 and 36, for example, a support structure HR, an insulating layer 210, and a sacrificial layer 291 are formed. In this step, an opening is formed above the support structure HR_L that penetrates multiple insulating layers 101 and multiple sacrificial layers 111, and an opening is formed in region P_ST that penetrates multiple insulating layers 101 and multiple sacrificial layers 111 to expose the semiconductor layer 112. When forming the opening in region P_ST, both sides of the insulating layer 210' in the Y direction are removed simultaneously, and the insulating layer 210 is formed. Next, an insulating layer containing silicon oxide (SiO2) or the like is formed inside the opening above the support structure HR_L to form the support structure HR, and a sacrificial layer 291 of amorphous silicon (α-Si) or the like is formed in the opening formed in region P_ST. This step is performed by, for example, RIE, CVD, etc.

[0128] Next, as shown in Figures 37 and 38, for example, an insulating layer 203 such as silicon oxide (SiO2) is formed on the upper surface of the structure shown in Figure 36. This step is carried out by, for example, CVD.

[0129] Next, as shown in Figures 37 and 38, for example, an opening is formed that penetrates the insulating layer 203 above the sacrificial layer 120S, the multiple insulating layers 101, and the multiple sacrificial layers 111 to expose the upper surface of the sacrificial layer 120S. After removing the sacrificial layer 120S through the opening, a gate insulating film 130 and a semiconductor layer 120 are formed inside the opening. This process is carried out by, for example, CVD, RIE, etc.

[0130] Next, as shown in Figure 39, for example, the sacrificial layer 291 is removed to form an opening STA. The opening STA is stretched in the Z direction, penetrating the multiple insulating layers 101 and the multiple sacrificial layers 111, and exposing the semiconductor layer 112. This process is carried out, for example, by wet etching.

[0131] Next, as shown in Figure 40, for example, the sacrificial layer 111 is removed through the opening STA to form the opening 111A. This step is performed, for example, by wet etching.

[0132] Next, a conductive layer 110 is formed via the opening STA, for example, as shown in Figures 41 and 42. Furthermore, an interblock structure ST is formed on the opening STA. This process is carried out by, for example, CVD, RIE, etc.

[0133] Next, as shown in Figures 41 to 43, for example, an inter-string unit insulating layer SHE is formed. In this step, openings are formed at positions corresponding to the inter-string unit insulating layer SHE, penetrating the insulating layer 203, multiple insulating layers 101, multiple conductive layers 110, and multiple sacrificial layers 290, and then silicon oxide (SiO2) or the like is formed in the openings. This step is carried out by, for example, RIE, CVD, etc.

[0134] Next, as shown in Figures 44 and 45, for example, an insulating layer 204 made of silicon oxide (SiO2) or the like is formed on the upper surface of the structure shown in Figure 42, and a portion of the insulating layers 203 and 204 above the sacrificial layer 290 is removed to form openings 290Ab and 291Ab. The openings 290Ab and 291Ab penetrate the insulating layers 203 and 204, exposing the upper surface of the sacrificial layer 290. This process is carried out, for example, by RIE.

[0135] Next, as shown in Figures 44 and 45, for example, the sacrificial layer 290 is removed through openings 290Ab and 291Ab to form openings 290A and 291A. This process is carried out, for example, by wet etching.

[0136] Next, as shown in Figure 46, for example, contact electrodes CCS_L and CC are formed in the openings 290A and 290Ab. This process is carried out by, for example, CVD.

[0137] Subsequently, structures above the contact electrodes CC and CCS_L, such as the bit line BL, are formed to create the semiconductor memory device described with reference to Figures 23 to 25.

[0138] [effect] As shown in Figures 23 and 24, the semiconductor memory device according to this embodiment has region R HU_S Each string unit SU contains a conductive layer 110 (SGD) in region RHU_W The conductive layer 110 (SGD) is electrically separated by the insulating layer 210. In such a configuration, in region R HU_S the plurality of conductive layers 110 (SGD) do not conduct with each other through the conductive layer 110 (SGD) in region R HU_W . Therefore, the conductive layers 110 (SGD) included in each string unit SU in region R HU_S can be insulated from each other, and the string units SU can be electrically independent of each other, enabling the provision of a semiconductor memory device that operates preferably.

[0139] Also, according to the manufacturing method according to the present embodiment, since a plurality of openings CCA, CCS_LA (FIG. 31) for forming the contact electrodes CC, CCS_L can be formed at once, an increase in the number of manufacturing steps can be suppressed, and a semiconductor memory device that can be manufactured at low cost can be provided.

[0140] [Third Embodiment] FIG. 47 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the third embodiment. FIGS. 48 to 52 are schematic cross-sectional views showing a partial configuration of the semiconductor memory device according to the present embodiment. FIG. 48 is a schematic cross-sectional view obtained by cutting the structure shown in FIG. 47 along the line P-P' and viewed along the direction of the arrow. FIG. 49 is a schematic cross-sectional view obtained by cutting the structure shown in FIG. 47 along the line A3-A3' and viewed along the direction of the arrow. FIG. 50 is a schematic cross-sectional view obtained by cutting the structure shown in FIG. 47 along the line B3-B3' and viewed along the direction of the arrow. FIG. 51 is a schematic cross-sectional view obtained by cutting the structure shown in FIG. 47 along the line C3-C3' and viewed along the direction of the arrow. FIG. 52 is a schematic cross-sectional view obtained by cutting the structure shown in FIG. 47 along the line D3-D3' and viewed along the direction of the arrow. In the following description, the same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0141] The semiconductor memory device according to the present embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device (FIG. 47) according to the present embodiment has regions R HU_S , R HU_W instead of regions RHU_S3 , R HU_W3 comprises. Further, in the semiconductor memory device according to the present embodiment, for example, six string units SU arranged in the Y direction are provided. In the example shown in FIG. 47, the six string units SU are shown as string units SUa, SUb, SUc, SUd, Sue, Suf from the negative side in the Y direction. Further, in the semiconductor memory device according to the present embodiment, in the region R HU_W3 , for example, three contact electrode columns CCG arranged in the Y direction are provided. In the example shown in FIG. 47, these three contact electrode columns CCG are shown as contact electrode columns CCG(0), CCG(1), CCG(2).

[0142] Region R HU_S3 , R HU_W3 (FIG. 47) is basically configured in the same manner as the region R HU_S , R HU_W (FIG. 3). However, in the semiconductor memory device according to the present embodiment, an insulating layer SHE_V (FIG. 7) is not provided in the region R HU_S3 (FIG. 48), and instead, a region P_In (FIGS. 47 and 48) is provided.

[0143] The region P_In is provided, for example, at both ends in the X direction of the region R HU_W3 as shown in FIGS. 47 and 48. In the region P_In, an insulating layer 111b is provided, for example, in a layer provided at the same height position as the conductive layer 110 (SGD) as shown in FIG. 48.

[0144] The insulating layer 111b is provided, for example, between the conductive layer 110 (SGD) provided in the region R HU_S3 and the conductive layer 110 (SGD) provided in the region R HU_W3 as shown in FIG. 48. The insulating layer 111b extends, for example, in the X direction and the Y direction. Both ends in the Y direction of the insulating layer 111b are in contact with the inter-block structure ST, for example, as shown in FIGS. 50 and 51. The insulating layer 111b is between the conductive layer 110 (SGD) in the region R HU_S3 and the conductive layer 110 (SGD) in the region R HU_W3The conductive layer 110 (SGD) and the insulating layer 111b are separated in the X direction, thereby electrically separating them. The insulating layer 111b contains a material similar to that of the sacrificial layer 111, such as silicon nitride (SiN).

[0145] Region R in the X direction of the insulating layer SHE between string units HU_W3 The side ends are located inside region P_In, as shown in Figure 47, for example.

[0146] area R HU_S3 In Figure 47, the string units SUa, SUb, SUc, SUd, SUe, and SUf are each provided with contact electrode rows CCSGa, CCSGb, CCSGc, CCSGd, CCSGe, and CCSGf, respectively.

[0147] The contact electrode arrays CCSGa to CCSGf are basically arranged in the same way as the contact electrode array CCSG (Figure 8), and include, for example, multiple contact electrodes CCS arranged in the X direction. However, as shown in Figure 47, for example, the contact electrode arrays CCSGa and CCSGf are arranged in the X direction, within the memory hole region R MH It is positioned closest to the memory hole region R. The contact electrode rows CCSGc and CCSGd are located in the X direction. MH It is located at the position furthest from the center. Contact electrode arrays CCSGb and CCSGe are located in the X direction between contact electrode arrays CCSGa and CCSGf and contact electrode arrays CCSGc and CCSGd.

[0148] area R HU_S3 In Figure 47, the width of the conductive layer 110 (SGD) in the Y direction in each string unit SUa to SUf is the memory hole region R MH The width of the conductive layer 110 (SGD) in the Y direction is different from that of the region R. HU_S3For example, as shown in Figures 47 and 49, in the portion where the contact electrode rows CCSGa to CCSGf are provided, the conductive layer 110 (SGD) in each string unit SUa to SUf is provided in such a way that the width in the Y direction is increased. The inter-string unit insulating layer SHE provided between each string unit SUa to SUf is provided along the Y-direction end of the conductive layer 110 (SGD) and includes, for example, a portion extending in the X direction and a portion extending in directions other than the X direction.

[0149] For example, as shown in Figure 49, in the portion where contact electrode rows CCSGa to CCSGf (contact electrode CCS) are provided, the conductive layer 110 (SGD) has a width D30 in the Y direction. The width D30 is greater than 1 / 6 of the width of the memory block BLK in the Y direction.

[0150] An insulating layer 310 is provided between the interblock structure ST and region P_In, for example, as shown in Figure 47. The insulating layer 310 is provided on a portion of both sides of the interblock structure ST on the Y-direction side, for example, as shown in Figures 50 and 51, and extends in the X and Z directions. The insulating layer 310 is provided between the insulating layer 111b and the interblock structure ST, but not between the conductive layer 110 and the interblock structure ST. The insulating layer 310 contains, for example, silicon oxide (SiO2).

[0151] The conductive layer 110 (SGD) includes, for example, a conductive layer 110I and a conductive layer 110II, as shown in Figure 48. Furthermore, an intermediate layer 110J is provided in the layer containing conductive layers 110I and 110II, as also shown in Figure 48. The intermediate layer 110J is a layer continuously formed in the region between contact electrodes CC, which are located at different positions in the X direction, and is not electrically connected to either conductive layer 110I or conductive layer 110II.

[0152] The conductive layers 110I, 110II, and the intermediate layer 110J contain the same material.

[0153] The insulating layer 111b is provided between the conductive layer 110I and the intermediate layer 110J, as shown in Figure 48, for example.

[0154] [Manufacturing method] Figures 53 to 68 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the second embodiment.

[0155] Figures 53, 55, 57, 59, 61, 63, 65, and 67 show cross-sections corresponding to Figure 49.

[0156] Figures 54, 56, 58, 60, 62, 64, 66, and 68 show cross-sections corresponding to Figure 50.

[0157] In this manufacturing method, the same steps as those described up to the step shown in Figure 9 are performed.

[0158] Next, as shown in Figures 53 and 54, for example, multiple openings CCA, CCSA, and multiple openings STAa are formed. The openings STAa extend in the Z direction, penetrating multiple insulating layers 101 and multiple sacrificial layers 111, and exposing the sacrificial layer 111 corresponding to the conductive layer 110 (DM). The openings STAa also extend in the X direction and are provided between adjacent regions P_In in the Y direction, in the portion corresponding to the interblock structure ST. The formation of the multiple openings CCA, CCSA, and STAa is carried out in the same manner as described with reference to Figure 10, for example.

[0159] Next, as shown in Figures 55 and 56, for example, an insulating layer 181 containing the same material as insulating layer 160, insulating layer 170, and insulating layer 310 is formed on the upper surface of the structure shown in Figures 53 and 54, and inside the openings CCA, CCSA, and STAa. This process is carried out, for example, by CVD.

[0160] Next, as shown in Figures 57 and 58, for example, a portion of the insulating layer 181 at the bottom of the openings CCA, CCSA, and STAa is removed, and insulating layers 160, 170, and insulating layer 310' containing the same material as insulating layer 310 are formed. This process is carried out, for example, by RIE.

[0161] Next, as shown in Figures 57 and 58, for example, a sacrificial layer 190 of amorphous silicon (α-Si) or the like is formed inside the openings CCA, CCSA, and STAa. This process is carried out, for example, by CVD.

[0162] Next, as shown in Figures 59 and 60, for example, an insulating layer 320 made of silicon oxide (SiO2) or the like is formed on the upper surface of the structure shown in Figures 57 and 58. Then, a resist or the like is formed and patterned on the upper surface of the insulating layer 320, and the portion of the insulating layer 320 above the part corresponding to the opening STAa is removed, and the sacrificial layer 190 above the part corresponding to the opening STAa is removed to form the opening STAa. This process is carried out by methods such as CVD, RIE, or wet etching.

[0163] Next, as shown in Figures 61 and 62, for example, an insulating layer 330 such as silicon oxide (SiO2) is formed on the upper surface of the structure shown in Figures 59 and 60, and inside the opening STAa. This process is carried out, for example, by CVD.

[0164] Next, as shown in Figures 63 and 64, for example, an opening STA is formed at a position corresponding to the interblock structure ST (Figures 49 and 50). In this step, a portion of the side surface of the insulating layer 310' on the interblock structure ST side in the Y direction is removed, and the insulating layer 310 is formed. This step is performed, for example, by RIE.

[0165] Next, as shown in Figures 65 and 66, for example, the multiple sacrificial layers 111 are removed by wet etching through the opening STA. In this step, the multiple sacrificial layers 111 provided between adjacent insulating layers 310 are not etched because they are not exposed to the opening STA, and remain as insulating layer 111b.

[0166] Next, as shown in Figures 65 and 66, for example, multiple conductive layers 110 are formed through the opening STA at positions corresponding to the removed sacrificial layer 111. This process is carried out, for example, by CVD.

[0167] Next, as shown in Figures 67 and 68, for example, an interblock structure ST is formed in the opening STA. This process is carried out by methods such as CVD or RIE.

[0168] Next, as shown in Figures 67 and 68, for example, a portion of the insulating layers 320 and 330 above the sacrificial layer 190 at the positions corresponding to the contact electrodes CC and CCS is removed to form an opening. After removing the sacrificial layer 190 through this opening, the contact electrodes CC and CCS are formed. This process is carried out by methods such as RIE, wet etching, or CVD.

[0169] Subsequently, structures above the contact electrodes CC and CCS, such as bit lines BL, are formed to create the semiconductor memory device according to this embodiment.

[0170] [effect] The semiconductor memory device according to this embodiment, as shown in Figure 48, has region R HU_S3 Each string unit SU contains a conductive layer 110 (SGD) in region R HU_W3 The conductive layer 110 (SGD) and the insulating layer 111b provided in region P_In are electrically separated. In such a configuration, region R HU_S3 The conductive layer 110 (SGD) is in region R HU_W3 They do not conduct electricity to each other through the conductive layer 110 (SGD). Therefore, region R HU_S3 The conductive layer 110 (SGD) contained in each string unit SU is insulated from each other, making the string units SU electrically independent of each other, and thus providing a suitably operating semiconductor memory device.

[0171] Furthermore, according to the manufacturing method of this embodiment, contact electrodes CC and CCS can be formed simultaneously, thus suppressing the increase in the number of manufacturing steps and enabling the provision of a semiconductor memory device that can be manufactured at low cost.

[0172] [Modified version of the third embodiment] Next, a modified example of the semiconductor memory device according to the third embodiment will be described with reference to Figure 69. Figure 69 is a schematic plan view showing a part of the configuration of the semiconductor memory device according to this modified example.

[0173] The semiconductor memory device related to this modified example has region R HU_S3 In this case, region P_In (Figure 48) is not provided, and instead region P_In2 (Figure 69) is provided.

[0174] Region P_In2 is, for example, as shown in Figure 69, region R HU_W3 It is provided throughout the entire area. In region P_In2, for example as shown in Figure 69, an insulating layer 111c is provided in a layer located at the same height as the conductive layer 110 (SGD).

[0175] The insulating layer 111c is, for example, shown in Figure 69, in one region R HU_S3 A conductive layer 110 (SGD) is provided in the region R HU_W3 The other adjacent region R HU_S3 It is provided between the conductive layer 110 (SGD) provided in and the insulating layer 111c. The insulating layer 111c extends, for example, in the X and Y directions. Both ends of the insulating layer 111c in the Y direction are in contact with the interblock structure ST, respectively. The insulating layer 111c is in region R HU_W3 Adjacent region R via HU_S3 Each conductive layer 110 (SGD) provided therein is separated in the X direction, thereby electrically separating them.

[0176] In this embodiment, the conductive layer 110 (SGD) includes, for example, a conductive layer 110I and a conductive layer 110II, as shown in Figure 69. Furthermore, an insulating layer 111c is provided on the layer including the conductive layer 110I and the conductive layer 110II, as shown in Figure 69. The insulating layer 111c is a layer continuously formed in the region between contact electrodes CC, which are located at different positions in the X direction, and is not electrically connected to either the conductive layer 110I or the conductive layer 110II. The insulating layer 111c includes, for example, a material similar to the sacrificial layer 111, such as silicon nitride (SiN).

[0177] [Other embodiments] The semiconductor memory devices according to the first to third embodiments have been described above. However, the configurations and manufacturing methods of the semiconductor memory devices according to the first to third embodiments are merely illustrative, and the specific configurations and manufacturing methods can be adjusted as appropriate.

[0178] Furthermore, for example, in the first to third embodiments, one end of the semiconductor layer 120 in the Z direction was connected to the semiconductor layer 112. However, one end of the semiconductor layer 120 in the Z direction may also be connected to the semiconductor substrate 100. Also, for example, in the first to third embodiments, the contact electrode CC was connected to the upper surface of the conductive layer 110. However, the contact electrode CC may be connected between the upper and lower surfaces of the conductive layer 110.

[0179] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0180] 100...Semiconductor substrate, 110...Conductive layer, 120...Semiconductor layer, CCG...Contact electrode array, CC...Contact electrode, CCSG...Contact electrode array, CCS...Contact electrode, SHE...Insulating layer between string units.

Claims

1. circuit board and A first layer is provided spaced apart from the substrate in a first direction intersecting the surface of the substrate, A second layer provided on one side of the first direction relative to the first layer, A third layer provided on one side of the second layer in the first direction, A first semiconductor layer and a second semiconductor layer extending in the first direction and facing the first layer, the second layer, and the third layer, A first electrode extending in the first direction and connected to the first layer, A second electrode extending in the first direction, with its outer surface surrounded by the first layer, and one end in the first direction connected to the second layer, A third electrode extending in the first direction, with its outer surface surrounded by the first and second layers, and one end in the first direction connected to the third layer, A first insulating layer extending in the first direction and in a second direction intersecting the first direction, dividing a portion of the first layer but not dividing the second and third layers. Equipped with, The second electrode and the third electrode are located further from the first semiconductor layer than the first electrode in the second direction. The second semiconductor layer is located further from the first semiconductor layer than the second electrode and the third electrode in the second direction. The first layer is, A first conductive layer facing the first semiconductor layer and connected to the first electrode, A second conductive layer facing the second semiconductor layer, An intermediate layer is formed continuously in the region between the second electrode and the third electrode, and is not electrically connected to either the first conductive layer or the second conductive layer. Includes, The second and third layers are each formed continuously in the region between the first and second semiconductor layers and include a third conductive layer facing the first and second semiconductor layers. Semiconductor memory device.

2. The intermediate layer contains the same material as the first conductive layer and the second conductive layer. The semiconductor memory device according to claim 1.

3. The aforementioned intermediate layer contains silicon nitride (SiN). The semiconductor memory device according to claim 1.

4. A second insulating layer is provided between the first conductive layer and the intermediate layer, and extends in a third direction intersecting the first and second directions. Equipped with, The second insulating layer is in contact with the first insulating layer. The semiconductor memory device according to claim 1.

5. The second insulating layer extends in the first direction, divides at least a portion of the first layer, and does not divide the second and third layers. The semiconductor memory device according to claim 4.

6. A third insulating layer and a fourth insulating layer extending in the first and second directions, and provided in contact with the first, second, and third layers on one and the other sides in the third direction. Equipped with, The second insulating layer is in contact with the third insulating layer and the fourth insulating layer. The semiconductor memory device according to claim 4.

7. A third insulating layer and a fourth insulating layer extending in the first and second directions, and provided in contact with the first, second, and third layers on one and the other sides in the third direction. Equipped with, The second insulating layer is in contact with the third insulating layer but not with the fourth insulating layer. The semiconductor memory device according to claim 4.

8. A fourth layer is provided between the first layer and the second layer, A fourth electrode extending in the first direction, with one end in the first direction connected to the fourth layer, and Equipped with, The first insulating layer divides a portion of the fourth layer in the third direction, The fourth electrode is in contact with the second insulating layer. The semiconductor memory device according to claim 4.

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