Memory system

Abstract

A memory system is provided that can reduce the computational load while ensuring the accuracy of the read voltage estimation. [Solution] The memory system comprises an input data acquisition unit, a quantization range determination unit, a parameter setting unit, an estimation unit, and a voltage setting unit. The input data acquisition unit acquires input data showing the relationship between the number of on-cells and multiple read voltages. The quantization range determination unit determines the quantization range of the read voltage shift value. The parameter setting unit sets the parameters of the quantization neural network. The estimation unit estimates the read voltage shift value from the input data using a quantization neural network with parameters set by the parameter setting unit. The voltage setting unit sets the read voltage used during the read operation of the semiconductor memory device based on the read voltage shift value.

Description

[Technical Field]

[0001] The embodiment relates to a memory system. [Background technology]

[0002] NAND flash memory is a well-known type of semiconductor memory device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-86292 [Non-patent literature]

[0004] [Non-Patent Document 1] Jacob, Benoit, et al. "Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference", 2018 IEEE / CVF Conference on Computer Vision and Pattern Recognition, pp. 2704-2713, doi:10.1109 / CVPR.2018.00286 [Overview of the project] [Problems that the invention aims to solve]

[0005] According to this embodiment, a memory system is provided that can reduce the computational load while ensuring the accuracy of the read voltage estimation. [Means for solving the problem]

[0006] The memory system of this embodiment comprises an input data acquisition unit, a quantization range determination unit, a parameter setting unit, an estimation unit, and a voltage setting unit. The input data acquisition unit acquires input data showing the relationship between the number of on-cells (the number of memory cells that become ON in the semiconductor memory device when data is read) and the multiple read voltages by causing the semiconductor memory device to read data using multiple read voltages. The quantization range determination unit determines the quantization range of the read voltage shift value to be estimated by the quantization neural network. The parameter setting unit sets the parameters of the quantization neural network based on the quantization range determined by the quantization range determination unit. The estimation unit estimates the read voltage shift value from the input data using the quantization neural network with the parameters set by the parameter setting unit. The voltage setting unit sets the read voltage to be used during the read operation of the semiconductor memory device based on the read voltage shift value. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing the schematic configuration of the memory system of the first embodiment. [Figure 2] A block diagram showing the schematic configuration of a semiconductor memory device according to the first embodiment. [Figure 3] A circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 4] A figure showing an example of the threshold voltage distribution of a memory cell in the first embodiment. [Figure 5] This figure shows an example of the relationship between the shift value of the readout voltage and its frequency of occurrence in the first embodiment. [Figure 6] This figure shows an example of a method for estimating the shift value of the readout voltage in the first embodiment. [Figure 7] A schematic diagram showing the configuration of the quantized neural network of the first embodiment. [Figure 8] A diagram showing the relationship between the stress conditions, basic calculation parameters, and quantization parameters of the first embodiment. [Figure 9]A diagram showing an example of the relationship between the shift value of the read voltage and its frequency of occurrence in the first embodiment. [Figure 10] A flowchart showing the procedure of the process related to the determination of the input data in the first embodiment. [Figure 11] A block diagram showing the functional configuration of the memory controller in the first embodiment. [Figure 12] A flowchart showing the procedure of the process executed by the memory controller in the first embodiment. [Figure 13] A flowchart showing the procedure of the process executed by the memory controller in the second embodiment. [Figure 14] A diagram showing an example of the relationship between the shift value of the read voltage and its frequency of occurrence in the second embodiment. [Figure 15] A diagram showing the relationship between the quantization range, basic operation parameters, and quantization parameters in the second embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. For ease of understanding the description, the same reference numerals are given to the same components in each drawing as much as possible, and redundant descriptions are omitted.

[0009] 1 First Embodiment The memory system of the first embodiment will be described. The semiconductor memory device used in the memory system of this embodiment is a non-volatile memory device configured as a NAND type flash memory.

[0010] 1.1 Configuration of Memory System First, the configuration of the memory system of this embodiment will be described.

[0011] As shown in Figure 1, the memory system 3 of this embodiment comprises a memory controller 1 and a semiconductor memory device 2. The semiconductor memory device 2 is a non-volatile memory device configured as a NAND flash memory. The memory system 3 is connectable to a host. The host is an electronic device such as a personal computer or a mobile terminal.

[0012] The memory controller 1 controls the writing of data to the semiconductor storage device 2 in accordance with write requests from the host. The memory controller 1 also controls the reading of data from the semiconductor storage device 2 in accordance with read requests from the host.

[0013] The following signals are transmitted and received between the memory controller 1 and the semiconductor storage device 2: chip enable signal / CE, ready busy signal R / B, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE,RE, write protect signal / WP, signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0014] The chip enable signal / CE is a signal to enable the semiconductor memory device 2. The ready-busy signal / RB is a signal to indicate whether the semiconductor memory device 2 is in a ready state or a busy state. "Ready state" means, for example, a state in which it is ready to accept commands from the outside. "Busy state" means a state in which it is not ready to accept commands from the outside. The command latch enable signal CLE is a signal that indicates that signal DQ<7:0> is a command. The address latch enable signal ALE is a signal that indicates that signal DQ<7:0> is an address. The write enable signal / WE is a signal to take the received signal into the semiconductor memory device 2 and is asserted by the memory controller 1 each time it receives a command, address, and data. The read enable signals / RE,RE are signals that the memory controller 1 uses to read data from the semiconductor memory device 2. Signal DQ<7:0> is the actual data transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes commands, addresses, and data. The data strobe signals DQS, / DQS are used to control the timing of the input and output of the signal DQ<7:0>.

[0015] The memory controller 1 includes RAM 11, ROM 12, processor 13, host interface 14, ECC circuit 15, and memory interface 16. These are connected to each other by an internal bus 17.

[0016] The host interface 14 outputs requests and user data (write data), etc., received from the host to the internal bus 17. The host interface 14 also sends user data read from the semiconductor memory device 2 and responses from the processor 13, etc., to the host.

[0017] The memory interface 16 controls the process of writing user data, etc., to the semiconductor storage device 2 and the process of reading data from the semiconductor storage device 2, based on instructions from the processor 13.

[0018] The processor 13 comprehensively controls the memory controller 1. The processor 13 is a CPU, MPU, etc. When the processor 13 receives a request from the host via the host interface 14, it performs control according to that request. For example, the processor 13 instructs the memory interface 16 to write user data and parity to the semiconductor storage device 2 according to a request from the host. The processor 13 also instructs the memory interface 16 to read user data and parity from the semiconductor storage device 2 according to a request from the host.

[0019] The processor 13 determines the storage area (memory area) on the semiconductor memory device 2 for the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 17. The processor 13 determines the memory area for data in page units (page data), which are the writing units. User data stored in one page of the semiconductor memory device 2 will also be referred to as "unit data" below. Unit data is generally encoded and stored in the semiconductor memory device 2 as a codeword. In this embodiment, encoding is not mandatory.

[0020] The processor 13 determines the memory area of ​​the semiconductor storage device 2 to which each unit data should be written. A physical address is assigned to the memory area of ​​the semiconductor storage device 2. The processor 13 manages the memory area to which the unit data should be written using the physical address. The processor 13 instructs the memory interface 16 to write the user data to the semiconductor storage device 2 by specifying the determined memory area (physical address). The processor 13 manages the correspondence between the logical address (logical address managed by the host) and the physical address of the user data. When the processor 13 receives a read request from the host that includes a logical address, it identifies the physical address corresponding to the logical address and instructs the memory interface 16 to read the user data by specifying the physical address.

[0021] The ECC circuit 15 encodes user data stored in the RAM 11 to generate a codeword. The ECC circuit 15 also decodes the codeword read from the semiconductor memory device 2.

[0022] RAM11 temporarily stores user data received from the host before storing it in the semiconductor memory device 2, and also temporarily stores data read from the semiconductor memory device 2 before sending it to the host. RAM11 is a general-purpose memory such as SRAM or DRAM.

[0023] ROM12 is a semiconductor memory from which data can be read. ROM12 stores various data necessary for the operation of, for example, the processor 13.

[0024] When a write request is received from the host, the memory system 3 in Figure 1 operates as follows: The processor 13 temporarily stores the data to be written in the RAM 11. The processor 13 reads the data stored in the RAM 11 and inputs it to the ECC circuit 15. The ECC circuit 15 encodes the input data and inputs the codeword to the memory interface 16. The memory interface 16 writes the input codeword to the semiconductor memory device 2.

[0025] When a read request is received from the host, the memory system 3 in Figure 1 operates as follows: The memory interface 16 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 15. The ECC circuit 15 decodes the input codeword and stores the decoded data in the RAM 11. The processor 13 transmits the data stored in the RAM 11 to the host via the host interface 14.

[0026] 1.2 Schematic Configuration of Semiconductor Memory Devices As shown in Figure 2, the semiconductor memory device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a register 24, a sequencer 25, a voltage generation circuit 26, a row decoder 27, a sense amplifier 28, a group of input / output pads 30, a group of logic control pads 31, and a group of power input terminals 32.

[0027] The memory cell array 21 is the part that stores data. The memory cell array 21 is composed of multiple memory cell transistors associated with multiple bit lines and multiple word lines.

[0028] The input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS, / DQS to and from the memory controller 1. The input / output circuit 22 also transfers the command and address within signal DQ<7:0> to register 24. Furthermore, the input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier 28.

[0029] The logic control circuit 23 receives the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE,RE, and write protect signal / WP from the memory controller 1. The logic control circuit 23 also forwards the ready busy signal / RB to the memory controller 1 to notify the external system of the state of the semiconductor memory device 2.

[0030] Register 24 temporarily holds various types of data. For example, register 24 holds commands that instruct write, read, and erase operations. These commands are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to register 24 for storage. Register 24 also holds the addresses corresponding to the above commands. These addresses are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to register 24 for storage. Furthermore, register 24 also holds status information indicating the operating state of the semiconductor memory device 2. This status information is updated by the sequencer 25 as needed, according to the operating state of the memory cell array 21, etc. The status information is output to the memory controller 1 from the input / output circuit 22 as a status signal in response to a request from the memory controller 1.

[0031] The sequencer 25 controls the operation of each part, including the memory cell array 21, based on control signals input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23.

[0032] The voltage generation circuit 26 is the part that generates the voltages necessary for the data writing, reading, and erasing operations in the memory cell array 21. These voltages include, for example, the voltages applied to multiple word lines and multiple bit lines of the memory cell array 21. The operation of the voltage generation circuit 26 is controlled by the sequencer 25.

[0033] The row decoder 27 is a circuit composed of a group of switches for applying voltage to multiple word lines of the memory cell array 21. The row decoder 27 receives a block address and a row address from the register 24, selects a block based on the block address, and selects a word line based on the row address. The row decoder 27 switches the open / closed state of the group of switches so that a voltage from the voltage generation circuit 26 is applied to the selected word line. The operation of the row decoder 27 is controlled by the sequencer 25.

[0034] The sense amplifier 28 is a circuit for adjusting the voltage applied to the bit lines of the memory cell array 21 and for reading the voltage from the bit lines and converting it into data. When reading data, the sense amplifier 28 acquires the data read from the memory cell transistors of the memory cell array 21 onto the bit lines and transfers the acquired read data to the input / output circuit 22. When writing data, the sense amplifier 28 transfers the data to be written to the memory cell transistors via the bit lines. The operation of the sense amplifier 28 is controlled by the sequencer 25.

[0035] The input / output pad group 30 is a section provided with multiple terminals (pads) for sending and receiving signals between the memory controller 1 and the input / output circuit 22. Each terminal is individually provided to correspond to the signal DQ<7:0> and the data strobe signals DQS, / DQS, respectively.

[0036] The logic control pad group 31 is a section provided with multiple terminals for sending and receiving various signals between the memory controller 1 and the logic control circuit 23. Each terminal is individually provided to correspond to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE,RE, write protect signal / WP, and ready busy signal / RB.

[0037] The power input terminal group 32 is a section provided with multiple terminals for receiving the voltages necessary for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltage Vcc, VccQ, Vpp, and the ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage supplied externally as the operating power supply, and is, for example, a voltage of about 2.5V. The power supply voltage Vcc is the voltage used to generate the internal power supply voltage Vdd of the semiconductor memory device 2, for example. The power supply voltage Vdd is, for example, a voltage of about 1.5V. The power supply voltage VccQ is a power supply voltage lower than the power supply voltage Vcc, for example, a voltage of 1.2V. The power supply voltage VccQ is the input / output power supply voltage used when sending and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12V.

[0038] 1.3 Circuit configuration of memory cell array Next, the circuit configuration of the memory cell array 21 will be described.

[0039] As shown in Figure 3, the memory cell array 21 is composed of multiple block blocks (BLKs). In Figure 3, only one of the block blocks is shown. The configuration of the other block blocks in the memory cell array 21 is the same as that shown in Figure 3.

[0040] As shown in Figure 3, block BLK contains, for example, four string units SU (SU0 to SU3). Each string unit SU contains multiple NAND strings NS. Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2. Hereafter, memory cell transistors MT (MT0 to MT7) will be abbreviated as "memory cell MT (MT0 to MT7)".

[0041] The memory cells MT are arranged to be connected in series between selection transistors ST1 and ST2. One end of memory cell MT7 is connected to the source of selection transistor ST1, and the other end of memory cell MT0 is connected to the drain of selection transistor ST2.

[0042] The gates of the selection transistors ST1 in each string unit SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The gates of the selection transistors ST2 are commonly connected to the same select gate line SGS among multiple string units SU within the same block BLK. The gates of the memory cells MT0 to MT7 within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. In other words, the word lines WL0 to WL7 and the select gate line SGS are common among multiple string units SU0 to SU3 within the same block BLK, whereas the select gate line SGD is provided individually for each string unit SU0 to SU3, even within the same block BLK.

[0043] The memory cell array 21 is provided with m bit lines BL(BL0, BL1, ..., BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS contained in one string unit SU. The drain of each selection transistor ST1 of the NAND string NS is connected to the corresponding bit line BL. The source of each selection transistor ST2 of the NAND string NS is connected to the source line SL. The source line SL is common to the sources of multiple selection transistors ST2 in block BLK.

[0044] Data stored in multiple memory cells MT within the same block BLK is erased collectively. On the other hand, data reading and writing are performed collectively on multiple memory cells MT connected to a single word line WL and belonging to a single string unit SU. Each memory cell can hold 3 bits of data consisting of a high-order bit, a middle bit, and a low-order bit. That is, the semiconductor memory device 2 according to this embodiment employs a TLC method to store 3 bits of data in one memory cell MT as the data writing method to the memory cells MT. Alternatively, an MLC method to store 2 bits of data in one memory cell MT may be employed as the data writing method to the memory cells MT. The number of bits of data stored in one memory cell MT is not particularly limited.

[0045] In the following explanation, a "page" refers to a set of 1-bit data stored in multiple memory cells MT connected to a single word line WL and belonging to a single string unit SU. In Figure 3, one of the sets of multiple memory cells MT described above is denoted with the code "MG".

[0046] In this embodiment, when 3 bits of data are stored in one memory cell MT, a set of multiple memory cells MT connected to a common word line WL within a single string unit SU can store data for 3 pages. Of these, the page consisting of the lower bit data will be referred to as the "lower page" below, and the data on the lower page will be referred to as the "lower page data" below. Similarly, the page consisting of the middle bit data will be referred to as the "middle page" below, and the data on the middle page will be referred to as the "middle page data" below. The page consisting of the upper bit data will be referred to as the "upper page" below, and the data on the upper page will be referred to as the "upper page data" below.

[0047] 1.4 Threshold voltage distribution of memory cells Figure 4 schematically shows the threshold voltage distribution of memory cells (MTs). The diagram in the middle of Figure 4 shows the correspondence between the threshold voltage of the memory cells (horizontal axis) and the number of memory cells (vertical axis).

[0048] In the case where the TLC method is adopted as in this embodiment, the multiple memory cells MT form eight threshold voltage distributions, as shown in the middle of Figure 4. These eight threshold voltage distributions (write levels) are referred to as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage. The table in the upper part of Figure 4 shows examples of 3-bit data assigned to each threshold voltage level.

[0049] Thus, the threshold voltage of the memory cell MT in this embodiment can take one of eight preset candidate levels, and data is assigned to each candidate level as described above.

[0050] Between adjacent threshold voltage distributions, a read voltage used in the read operation is set. The "read voltage" is the voltage applied to the word line WL connected to the memory cell MT to be read, i.e., the selected word line, during the read operation. In the read operation, data is determined based on the result of determining whether the threshold voltage of the memory cell MT to be read is higher than the applied read voltage. For example, as schematically shown in the lower part of Figure 4, the read voltage VrA, which determines whether the threshold voltage of the memory cell MT falls into the "ER" level or the "A" level, is set between the maximum threshold voltage in the "ER" level and the minimum threshold voltage in the "A" level. The other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as the read voltage VrA described above.

[0051] For voltages higher than the maximum threshold voltage of the highest threshold voltage distribution (e.g., "G" level), the read path voltage VPASS_READ is set. A memory cell MT with the read path voltage VPASS_READ applied to its gate turns on regardless of the data being stored.

[0052] When the data allocation described above is applied, the lower-order bit page data can be determined in the read operation by the read results using read voltages VrA and VrE. The middle-order bit page data can be determined by the read results using read voltages VrB, VrD, and VrF. The upper-order bit page data can be determined by the read results using read voltages VrC and VrG.

[0053] Such read voltages change due to the stress applied to the memory cell MT. Figure 5 shows the distribution of read voltage shift values ​​due to changes in stress conditions. The read voltage shift value is the difference between the optimal read voltage relative to the current threshold voltage distribution of the memory cell MT and the preset read voltage. Note that Figure 5 only shows the distribution of the shift value of one of the multiple read voltages shown in Figure 4 (for example, VrA).

[0054] For example, in an ideal situation where no strong stress is applied to the memory cell MT, the read voltage hardly changes. Therefore, in such a situation, the shift value of the read voltage exhibits a distribution Db as shown by the solid line in Figure 5. For convenience, the stress conditions under which the distribution Db shown by the solid line in Figure 5 is formed will be referred to as the ideal stress conditions below.

[0055] In contrast, when the same memory cell MT is subjected to stress from repeated data readouts, the read voltage shifts to the higher voltage side. Therefore, in such a situation, the shift value of the read voltage shows a distribution Dc that is shifted to the higher voltage side than the ideal solid line distribution, as shown by the dashed line in Figure 5. Such stress conditions are called read disturb conditions.

[0056] On the other hand, if the same memory cell MT is subjected to stress by being left in that state for a long period of time after data has been written to it, the read voltage shifts to the lower voltage side. Therefore, in such a situation, the shift value of the read voltage shows a distribution Da that is shifted to the lower voltage side than the ideal distribution shown by the dashed line in Figure 5. Such stress conditions are called data retention conditions.

[0057] In Figure 5, the distribution of the readout voltage shift values ​​corresponding to all stress conditions is shown by the dashed line Dd.

[0058] Thus, since the shift value of the read voltage changes depending on the stress conditions, it is necessary to change the read voltage as appropriate in such a memory system 3. In the memory system 3, for example, if the memory controller 1 is unable to read data from the semiconductor memory device 2 during a read operation, and is unable to recover the data through error correction, the memory controller 1 determines that the optimal read voltage may have changed and performs a read voltage estimation process. Alternatively, the memory controller 1 performs a process to estimate the shift value of the read voltage during the patrol process of the semiconductor memory device 2. The patrol process is a process that performs read operations periodically or irregularly in order to read data stored in the semiconductor memory device 2 with a small number of error bits. The patrol process includes an update patrol process that updates the read voltage used when reading data in order to reduce the number of errors contained in the data read from the memory cell MT under patrol. The process of estimating the shift value of the read voltage is used, for example, to update the read voltage of the memory cell MT during the update patrol process.

[0059] On the other hand, in the memory system 3 of this embodiment, a neural network is used to estimate the optimal read voltage of the memory cell MT. In this case, if the neural network calculations are performed using floating-point arithmetic, calculation accuracy can be ensured, but concerns arise regarding increased memory capacity, increased latency, and increased circuit size. Therefore, in the memory system 3 of this embodiment, a so-called quantized neural network, which performs calculations using integer arithmetic, is used to estimate the shift value of the read voltage. However, when using a quantized neural network, there is a trade-off relationship between the number of quantization bits and calculation accuracy.

[0060] For example, if the shift value of the read voltage changes depending on the stress condition as shown in Figure 5, then in order to estimate the shift value of the read voltage under all stress conditions, it is necessary to set the quantization range of the read voltage shift value to the range from "-ΔV17" to "ΔV17". In this case, if the quantization bit count of the quantization neural network is set to 3 bits, then, as shown in Pattern 1 in Figure 5, the shift value of the read voltage will be estimated with 3 bits in the range from "-ΔV17" to "ΔV17". In other words, the shift value of the read voltage will be estimated in 8 divisions in the range from "-ΔV17" to "ΔV17". Note that in Figure 5, the range that can be represented by 1 bit is represented by a square frame. If the shift value of the read voltage is estimated in this manner, for example, if the memory cell MT is subjected to the stress condition of DR, the shift value of the read voltage can only take the range from "-ΔV17" to "0", so in effect, the shift value of the read voltage can only be estimated with a precision of 2 bits. Therefore, there is a risk that the estimation accuracy of the read voltage shift value cannot be ensured.

[0061] Therefore, in the memory system 3 of this embodiment, the distribution of the read voltage shift value is determined to fall under one of the distributions Da to Dc shown in Figure 5, and the quantization range of the quantization neural network is changed according to the determination result. For example, if the memory system 3 determines that the read voltage shift value is distribution Da, the quantization range of the quantization neural network is set to the range from "-ΔV17" to "0" as shown in pattern 2 in Figure 5. This allows the read voltage shift value to be estimated with 3-bit accuracy even when the memory cell MT is subjected to DR stress. Also, if the memory system 3 determines that the read voltage shift value is distribution Dc, the quantization range of the quantization neural network is set to the range from "0" to "ΔV17" as shown in pattern 3 in Figure 5. This allows the read voltage shift value to be estimated with 3-bit accuracy even when the memory cell MT is subjected to RD stress. In this way, the memory system 3 of this embodiment maintains 3-bit calculation accuracy by changing the quantization range of the quantization neural network according to the stress condition.

[0062] 1.5 Principle of Estimating the Readout Voltage Shift Value Before explaining the configuration for realizing the estimation of the read voltage shift value as described above, we will first explain the principle of estimating the read voltage shift value.

[0063] The memory system 3 of this embodiment causes the semiconductor storage device 2 to read data using a plurality of different read voltages, and estimates the shift value of the read voltage using the on-cell number, which is the number of memory cells MT that become ON at that time.

[0064] Figure 6(A) is a graph showing two threshold voltage distributions corresponding to the "A" level and the "B" level as an example. Figure 6(B) is a graph showing the relationship between the readout voltage Vr and the number of on-cells b. Figures 6(A) and (B) illustrate the case where the optimal readout voltage corresponding to the "A" level and the "B" level, in other words, the readout voltage at which the overlap between the threshold voltage distribution belonging to the "A" level and the threshold voltage distribution belonging to the "B" level is minimized, transitions from nVrB to ΔVrB (<0).

[0065] As shown in Figure 6(B), when the read voltage Vr is gradually increased, the on-cell number b increases sharply at a voltage slightly higher than VS0mid, which is the mode of the “A” level. Here, the mode is the voltage at which the probability of the threshold voltage distribution is maximized in Figure 6(A). When the read voltage Vr is further increased, the rate of increase of the on-cell number b decreases. In this case, as shown in Figure 6(A), if the threshold voltage distribution belonging to the “A” level and the threshold voltage distribution belonging to the “B” level overlap, the rate of increase of the on-cell number b is greater than zero, so the on-cell number b increases slightly with increasing read voltage Vr. If the threshold voltage distribution belonging to the “A” level and the threshold voltage distribution belonging to the “B” level do not overlap, the rate of increase of the on-cell number b is zero, so the on-cell number b is maintained at a predetermined value even if the read voltage Vr increases. As the read voltage Vr increases further, the on-cell number b increases again, and the on-cell number b increases sharply at a voltage slightly higher than VS1mid, which is the mode of the "B" level.

[0066] From this change in the number of on-cells b, the readout voltage VrB at which the overlap of the threshold voltage distributions between the two levels is minimized, that is, the readout voltage VrB corresponding to the intersection of the threshold voltage distributions of the two states, can be estimated, for example, by the following procedure.

[0067] First, the on-cell number b4 corresponding to the default read voltage nVrB is obtained by performing a read operation using the default read voltage nVrB. The default read voltage nVrB is a default voltage that is pre-set to be used as the read voltage VrB shown in Figure 4. Next, the on-cell numbers b3, b2, b1, and b0 corresponding to "nVrB-ΔV", "nVrB-2×ΔV", "nVrB-3×ΔV", and "nVrB-4×ΔV" are obtained by performing a read operation while decreasing the read voltage from nVrB at predetermined voltage intervals of ΔV. Furthermore, the on-cell numbers b5, b6, b7, and b8 corresponding to "nVrB+ΔV", "nVrB+2×ΔV", "nVrB+3×ΔV", and "nVrB+4×ΔV" are obtained by increasing the read voltage from nVrB at predetermined voltage intervals of ΔV. In this way, the number of on-cells b0 to b8 before and after the default read voltage nVrB is obtained.

[0068] Next, the difference in on-cell count X is calculated from the acquired on-cell counts b0 to b8 based on the following formula f1. k The following calculation is performed. Note that in equation f1, k = 0, 1, 2, ..., 7.

[0069] X k =b k+1 -b k (f1) Figure 6(C) is a graph showing the relationship between the read voltage Vr and the differential on-cell number X. In Figure 6(C), the dashed lines L connect the differential on-cell numbers X0 to X7, respectively. From the graph shown in Figure 6(C), the optimal read voltage VrB corresponding to the "A" level and "B" level can be estimated. Specifically, the read voltage at which the dashed line L takes its minimum value in Figure 6(C) is considered to be the read voltage at which the overlap between the threshold voltage distribution belonging to the "A" level and the threshold voltage distribution belonging to the "B" level is smallest, and this read voltage can be set as the read voltage VrB corresponding to the "A" level and "B" level. In the following, the shift value of the optimal read voltage VrB from the default read voltage nVrB will be denoted as "ΔVr".

[0070] Up to this point, we have explained how to set the read voltage VrB corresponding to the "A" level and "B" level. However, by performing the same process for the other read voltages VrA, VrC to VrG, the other read voltages VrA, VrC to VrG can also be set to the optimal value in the same way.

[0071] 1.6 Configuration of a Quantized Neural Network Next, we will explain the construction of a quantized neural network using the principles described above.

[0072] In this embodiment, the part of the above principle that calculates the shift value ΔVr of the read voltage from the difference on-cell number X and the default read voltage nVr is performed by a quantized neural network.

[0073] As shown in Figure 7, the quantized neural network 500 has an input layer 510, a hidden layer 520, and an output layer 530.

[0074] The input layer 510 receives predetermined input data. The input layer 510 has a plurality of arithmetic units (also called neurons or neuron circuits) 511. The arithmetic units 511 may be dedicated devices or circuits, or their processing may be realized by a processor executing a program. The same configuration will be described as an arithmetic unit from here on. In the input layer 510, each arithmetic unit 511 performs arbitrary processing on the input data (for example, linear transformation or addition of auxiliary data) to transform it, and transmits the transformed data to the intermediate layer 520.

[0075] The intermediate layer 520 (520A, 520B) performs various arithmetic operations on the data from the input layer 510.

[0076] The intermediate layer 520 has a plurality of arithmetic units 521 (521A, 521B). In the intermediate layer 520, each arithmetic unit 521 performs arithmetic processing (e.g., sum-of-products operation) on the supplied data (hereinafter also referred to as interlayer input data for distinction) using predetermined parameters (e.g., weight w). For example, each arithmetic unit 521 performs sum-of-products operation on the supplied data using different parameters from each other.

[0077] The intermediate layer 520 may be hierarchical. In this case, the intermediate layer 520 includes at least two layers (a first intermediate layer 520A and a second intermediate layer 520B). The first intermediate layer 520A has a plurality of arithmetic units 521A, and the second intermediate layer 520B has a plurality of arithmetic units 521B.

[0078] Each arithmetic unit 521A of the first intermediate layer 520A performs a predetermined arithmetic operation on the interlayer input data, which is the processing result of the input layer 510. Each arithmetic unit 521A transmits the calculation result to each arithmetic unit 521B of the second intermediate layer 520B. Each arithmetic unit 521B of the second intermediate layer 520B performs a predetermined arithmetic operation on the interlayer input data, which is the calculation result of each arithmetic unit 521A. Each arithmetic unit 521B transmits the calculation result to the output layer 530.

[0079] Thus, when the hidden layer 520 has a hierarchical structure, the inference and learning / training capabilities of the quantized neural network 500 can be improved. The number of layers in the hidden layer 520 may be three or more, or it may be just one. A single hidden layer may be configured to include any combination of operations such as multiply-accumulate operations, pooling operations, normalization operations, and activation operations.

[0080] The output layer 530 receives the results of various calculation processes performed by each arithmetic unit 521 of the intermediate layer 520 and executes various processes.

[0081] The output layer 530 has a calculation unit 531. The calculation unit 531 outputs calculation result data by performing calculation processing on the interlayer input data, which is the calculation result of multiple calculation units 521B, using predetermined parameters.

[0082] In the following, the parameters used in the intermediate layer 520 and the output layer 530 will be referred to as the basic operation parameters Pb.

[0083] On the other hand, in general neural networks, various parameters and inter-layer input data are represented using 16-bit to 32-bit floating-point numbers. In contrast, the quantized neural network 500 of this embodiment reduces capacity, latency, and circuit size by representing various parameters and inter-layer input data using 1-bit to 8-bit integers. In this embodiment, the quantized neural network 500 will be explained using the example where the output layer 530 outputs calculation result data with 3-bit precision.

[0084] Furthermore, the quantized neural network 500 uses a quantization scale S and a zero point Z as parameters for adjusting the data output from the output layer 530. The quantization scale S is a parameter that indicates the resolution of the quantized value, and is a real number parameter used to adjust the scale between the real number r before quantization and the integer q after quantization. The zero point Z is the value that a value that was zero as a real number before quantization takes as an integer value after quantization, and is an offset used to adjust the integer q after quantization so that the real number r before quantization is represented as zero. The following equation f2 holds between the real number r before quantization, the integer q after quantization, the quantization scale S, and the zero point Z.

[0085] r=S(qZ) (f2) Since the quantization scale S and zeros Z used in the Quantized Neural Network 500 are well-known technical concepts, a detailed explanation will be omitted. Hereafter, the quantization scale S and zeros Z will also be referred to as the quantization parameter Pq.

[0086] In the quantized neural network 500 of this embodiment, the difference on-cell number X is input as input data.

[0087] The default read voltage nVr is one of the following: default read voltage nVrA corresponding to read voltage VrA, default read voltage nVrB corresponding to read voltage VrB, default read voltage nVrC corresponding to read voltage VrC, default read voltage nVrD corresponding to read voltage VrD, default read voltage nVrE corresponding to read voltage VrE, default read voltage nVrF corresponding to read voltage VrF, and default read voltage nVrG corresponding to read voltage VrG. The default read voltage nVr is pre-stored in the ROM 12 of the memory controller 1.

[0088] The differential on-cell number X is the differential on-cell number X corresponding to multiple read voltages before and after a predetermined read voltage nVr. For example, if data as shown in Figure 6(C) is obtained, the differential on-cell numbers X0 to X7 are input to the input layer 510.

[0089] Furthermore, in the quantized neural network 500 of this embodiment, the output layer 530 outputs a shift value ΔVr of the read voltage. For example, if data as shown in Figure 6(C) is obtained, the output layer 530 outputs a shift value ΔVrB of the read voltage.

[0090] On the other hand, in light of the fact that the distribution of the shift value of the readout voltage changes according to the stress conditions as shown in Figure 5, the quantized neural network 500 of this embodiment uses basic calculation parameters PbA, PbB, PbC and quantization parameters PqA, PqB, PqC according to the stress conditions, as shown in Figure 8.

[0091] Specifically, in the memory system 3 of this embodiment, training data for multiple inputs and outputs corresponding to ideal stress conditions, training data for multiple inputs and outputs corresponding to RD conditions, and training data for multiple inputs and outputs corresponding to DR conditions are prepared through experiments and other means for training the quantized neural network 500.

[0092] Based on this training data, we first set the quantization range corresponding to each stress condition, and then set the boundary conditions for each stress condition.

[0093] For example, by analyzing the output data contained in multiple training datasets corresponding to ideal stress conditions, the range of possible values ​​for the multiple output data, i.e., the range of possible values ​​for the readout voltage shift value ΔVr corresponding to the ideal stress conditions, can be determined, for example, as shown in Figure 9 as range RqB. By using this range RqB as the quantization range corresponding to the ideal stress conditions, the quantization parameters PqB, specifically the quantization scale SB and the zero point ZB, corresponding to the ideal stress conditions are set based on this quantization range RqB. For example, when estimating the quantization range RqB with 3-bit precision, the quantization scale SB is set to a voltage width that allows the quantization range RqB to be divided into 8 equal parts, as shown in Figure 9.

[0094] Furthermore, by training the quantized neural network 500 using training data for multiple inputs and outputs corresponding to ideal stress conditions, the basic computational parameter PbB corresponding to the ideal stress conditions is determined.

[0095] Based on the above, the quantization parameter PqB and the basic calculation parameter PbB corresponding to the ideal stress condition are obtained. Using a similar method, the quantization range RqA, quantization parameter PqA, and basic calculation parameter PbA corresponding to the DR condition, and the quantization range RqC, quantization parameter PqC, and basic calculation parameter PbC corresponding to the RD condition are obtained.

[0096] Figure 8 shows the correspondence between each stress condition and the quantization range shown in Figure 9.

[0097] On the other hand, in order to switch the basic calculation parameter Pb and the quantization parameter Pq according to the stress condition, it is necessary to determine which of the three stress conditions the actual input data corresponds to. For this purpose, in this embodiment, boundary conditions for determining which of the three stress conditions the input data corresponds to are set in advance by using the training data for each stress condition. The boundary conditions are set as shown in Figure 10, for example.

[0098] First, it is determined whether the actual input data satisfies the first condition (step S10). The first condition is a condition that allows it to be determined that the actual input data corresponds to the DR condition and does not correspond to any other stress conditions. As the first condition, for example, the condition shown in the following formula f3, which uses the number of difference on-cells X0 to X7 included in the input data, can be used.

[0099] X i >T A (f3) In equation f3, i is an integer satisfying "0 ≤ i ≤ 7". A The difference on-cell count X0 to X7 is set to a value that allows it to be determined that it corresponds to the DR condition and does not correspond to any other stress condition. A This is determined in advance by using training data for each stress condition. In this embodiment, the first condition is an example of a boundary condition.

[0100] If the actual input data satisfies the first condition (Step S10: YES), it is determined that the actual input data corresponds to the DR condition (Step S11).

[0101] When the actual input data does not satisfy the first condition (step S10: NO), it is determined whether the actual input data satisfies the second condition (step S12). The second condition is a condition that it is possible to determine that the differential on-cell numbers X0 to X7 are input data corresponding to the RD condition and not input data corresponding to other stress conditions. As the second condition, for example, a condition represented by the following formula f4 using the differential on-cell numbers X0 to X7 included in the input data can be used.

[0102] X j >T B (f4) In the formula f4, j is an integer satisfying "0 ≦ j ≦ 7". T B is set to a value that can determine that the differential on-cell numbers X0 to X7 correspond to the RD condition and do not correspond to other stress conditions. T B is obtained in advance by using the training data of each stress condition. In this embodiment, the second condition is an example of a boundary condition.

[0103] When the actual input data satisfies the second condition (step S12: YES), it is determined that the actual input data corresponds to the RD condition (step S13).

[0104] When the actual input data does not satisfy the second condition (step S12: NO), it is determined that the actual input data corresponds to the ideal stress condition (step S14).

[0105] In the quantized neural network 500 of this embodiment, based on the process shown in Figure 10, it is determined which of the three stress conditions the input data, including the difference on-cell number X, corresponds to, and then the quantization parameter Pq and the basic operation parameter Pb are selected based on that determination result. For example, if it is determined that the input data corresponds to the DR condition based on the process shown in Figure 10, the basic operation parameter PbA and the quantization parameter PqA shown in Figure 9 are selected. The quantized neural network 500 then uses these basic operation parameter PbA and quantization parameter PqA to calculate the shift value ΔVr of the readout voltage.

[0106] 1.7 Memory Controller Configuration Next, we will specifically describe the configuration of the memory controller 1 for setting the optimal read voltage of the memory cell MT using the quantized neural network 500 described above.

[0107] As shown in Figure 11, the memory controller 1 includes an input data acquisition unit 41, a quantization range determination unit 42, a parameter setting unit 43, an estimation unit 44, a voltage setting unit 45, and a quantization neural network 500. These functions are realized by any one of the hardware such as electronic circuits, firmware, and software of the memory controller 1, or a combination of two or more of them. For example, the quantization neural network 500 is stored in ROM 12. Furthermore, the functions of the input data acquisition unit 41, the quantization range determination unit 42, the parameter setting unit 43, the estimation unit 44, and the voltage setting unit 45 are realized by a computer-readable program stored in ROM 12 being loaded into RAM 11 and executed by processor 13. In this case, RAM 11 and ROM 12 are examples of storage media. Below, with reference to Figure 12, examples of the operation of the input data acquisition unit 41, the quantization range determination unit 42, the parameter setting unit 43, the estimation unit 44, and the voltage setting unit 45 will be described. Figure 12 is a flowchart showing the procedure for estimating the read voltage, which is performed by the memory controller 1 when data cannot be recovered by error correction or during patrol processing.

[0108] As shown in Figure 12, in the read voltage estimation process, first, the input data acquisition unit 41 acquires data showing the relationship between the read voltage Vr and the on-cell number b, as shown in Figure 6(B) (step S20). For example, the input data acquisition unit 41 sequentially acquires data for the on-cell number b corresponding to each read voltage Vr by increasing the read voltage Vr from the ground voltage Vss to the read path voltage VPASS_READ at intervals of a predetermined voltage ΔV.

[0109] Next, the input data acquisition unit 41 reads one of the multiple default read voltages nVr of the memory cell MT from the ROM 12 (step S21). Below, as an example, we will describe the case in which the input data acquisition unit 41 reads the default read voltage nVrB corresponding to the "A" level and the "B" level.

[0110] Next, the input data acquisition unit 41 acquires data on the number of on-cells corresponding to multiple read voltages near the default read voltage nVrB from the data acquired in step S20, based on the default read voltage nVrB read in step S21 (step S22). For example, as shown in Figure 6(B), the input data acquisition unit 41 acquires the number of on-cells b4 corresponding to the default read voltage nVrB, the number of on-cells b0 to b3 corresponding to multiple read voltages lower than the default read voltage nVrB, and the number of on-cells b5 to b8 corresponding to multiple read voltages higher than the default read voltage nVrB.

[0111] Next, the input data acquisition unit 41 calculates the difference on-cell numbers X0 to X7 from the multiple on-cell numbers b0 to b8 obtained in step S22 using the above formula f1, thereby acquiring data showing the relationship between the read voltage Vr and the difference on-cell numbers X0 to X7 as shown in Figure 6(C) (step S23).

[0112] Next, the input data acquisition unit 41 generates input data for the quantized neural network 500 from the data showing the relationship between the read voltage Vr and the difference on-cell numbers X0 to X7 acquired in step S23 (step S24).

[0113] Next, the quantization range determination unit 42 uses the actual input data generated in step S24 to perform the processing shown in Figure 10, thereby determining which of the three stress conditions the actual input data corresponds to (step S25). Below, as an example, the case where the actual input data corresponds to the DR condition will be described. If the actual input data corresponds to the DR condition, the quantization range determination unit 42 determines the quantization range of the shift value of the read voltage to the quantization range RqA corresponding to the DR condition shown in Figure 9 (step S26).

[0114] Next, the parameter setting unit 43 sets the parameters of the quantized neural network 500 based on the quantization range RqA of the shift value of the read voltage determined in step S26 (step S27). For example, if the quantization range of the shift value of the read voltage is determined to be the quantization range RqA corresponding to the DR condition in step S26, the parameter setting unit 43 decides to use the basic operation parameter PbA and the quantization parameter PqA as parameters of the quantized neural network 500.

[0115] Next, the estimation unit 44 estimates the shift value ΔVr of the readout voltage using the parameters determined in step S27 via a quantized neural network (step S28). For example, the estimation unit 44 inputs the input data generated in step S24 to the input layer 510 of the quantized neural network 500, using the basic calculation parameter PbA and quantization parameter PqA determined in step S27 as shown in Figure 12. As a result, the shift value ΔVr of the readout voltage is output from the output layer 530 of the quantized neural network 500.

[0116] Next, the voltage setting unit 45 sets the read voltage VrB to "nVrB + ΔVr" based on the shift value ΔVr of the read voltage output from the quantized neural network 500 and the default read voltage nVrB (step S29).

[0117] Next, the memory controller 1 determines whether there are any read voltages whose estimation is not yet complete (step S30). If there are read voltages whose estimation is not yet complete (step S30: YES), the process returns to step S21. As a result, steps S21 to S30 are repeatedly executed until the estimation of all read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG is complete.

[0118] Once the estimation of all read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG is complete, the memory controller 1 makes a negative decision in step S30 (step S30: NO) and terminates the process shown in Figure 12.

[0119] 1.8 Operation and Effects of the Memory System As described above, the memory system 3 comprises an input data acquisition unit 41, a quantization range determination unit 42, a parameter setting unit 43, an estimation unit 44, and a voltage setting unit 45. The input data acquisition unit 41 acquires input data showing the relationship between the number of on-cells b and multiple read voltages by causing the semiconductor memory device 2 to read data using multiple read voltages. The quantization range determination unit 42 determines the quantization range of the read voltage shift value to be estimated by the quantization neural network 500. The parameter setting unit 43 sets the parameters Pb and Pq of the quantization neural network 500 based on the quantization range determined by the quantization range determination unit 42. The estimation unit 44 estimates the read voltage shift value ΔVr from the input data using the quantization neural network 500 with the parameters Pb and Pq set by the parameter setting unit 43. The voltage setting unit 45 sets the read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG used during the read operation of the semiconductor memory device 2, based on the shift value ΔVr of the read voltage.

[0120] This configuration allows the quantized neural network 500 to perform calculations using integers, thereby reducing the computational load. As a result, it becomes possible to reduce parameter capacity, latency, and circuit size. Furthermore, since the quantization range of the readout voltage shift value is set to an appropriate range corresponding to the input data from the three ranges RqA, RqB, and RqC shown in Figure 9, the computational accuracy of the quantized neural network 500 can also be ensured. Consequently, it becomes possible to reduce the computational burden while ensuring the estimation accuracy of the readout voltage.

[0121] The parameters of the quantized neural network 500 include the basic operation parameter Pb and the quantization parameter Pq. The basic operation parameter Pb includes the weights w of the quantized neural network 500. The quantization parameter Pq includes the quantization scale S and zeros Z of the quantized neural network 500.

[0122] This configuration makes it possible to easily switch the quantization range of the quantized neural network 500 according to the input data.

[0123] The quantization range determination unit 42 determines the quantization range based on whether the input data satisfies predetermined boundary conditions. The quantization range determination unit 42 uses a plurality of boundary conditions as shown in the above equations f3 and f4.

[0124] With this configuration, the quantization range of the readout voltage shift value can be set to one of the three ranges RqA, RqB, and RqC shown in Figure 9.

[0125] 1.9 First Variation Next, a first modified example of the memory system 3 of the first embodiment will be described.

[0126] The boundary conditions used to determine which of the three stress conditions the actual input data corresponds to are not limited to those shown in equations f3 and f4 above; any arbitrary conditions can be used.

[0127] For example, you may use the following formula f5 instead of the above formula f3, and the following formula f6 instead of the above formula f4.

[0128] f0(X)≦0 (f5) f1(X)≦0 (f6) Furthermore, the "X" used in equations f5 and f6 is defined by the following equation f7.

[0129] X=(X0,X1,···.X7) Furthermore, the function f0 used in equation f5 can be obtained by calculating a function (kernel function) corresponding to an interface that can demarcate, for example, the region where input data corresponding to the DR condition exists and the region where input data corresponding to other conditions exists, using a support vector machine. Similarly, the function f0 used in equation f6 can be obtained by calculating a function corresponding to an interface that can demarcate, for example, the region where input data corresponding to the RD condition exists and the region where input data corresponding to the ideal stress condition exists, using a support vector machine.

[0130] Even with this configuration, it is possible to obtain the same or similar functions and effects as the memory system 3 of the first embodiment described above.

[0131] 1.10 Second variation Next, a second modified example of the memory system of the first embodiment will be described.

[0132] In the first embodiment described above, as shown in Figure 12, the number of difference on-cells X0 to X7 included in the actual input data was used to determine which of the three stress conditions the actual input data corresponds to, and then the quantization range of the readout voltage shift value was set based on that determination.

[0133] Alternatively, in this modified example, the quantization range determination unit 42 performs a process to determine the quantization range of the readout voltage shift value based on the calculated value of the first intermediate layer 520A of the quantized neural network 500, as the process of step S25 shown in Figure 12.

[0134] With this configuration, the quantization range of the readout voltage shift value can be determined based on the calculation results of the quantized neural network 500, thereby improving calculation accuracy.

[0135] 2. Second Embodiment Next, the memory system 3 of the second embodiment will be described. The following description will focus on the differences from the memory system 3 of the first embodiment.

[0136] 2.1 Memory Controller Configuration The memory controller 1 of this embodiment performs the read voltage estimation process in the procedure shown in Figure 13. In the process shown in Figure 13, the same reference numerals are used for processes that are the same as those shown in Figure 12, and redundant explanations are omitted.

[0137] As shown in Figure 13, in the memory controller 1 of this embodiment, after input data is generated by the input data acquisition unit 41 (step S24), the estimation unit 44 roughly estimates the shift value ΔVr of the read voltage using the input data (step S40).

[0138] Specifically, as shown in Figure 14, in this embodiment, four ranges RqD, RqE, RqF, RqG, and RqH are set as the quantization ranges of the memory cell MT. The quantization range RqH is set to include all regions where the shift value ΔVr of the read voltage may be distributed. The other quantization ranges RqD, RqE, RqF, and RqG are set to divide the quantization range RqH into four equal parts.

[0139] Furthermore, as shown in Figure 15, for each quantization range RqD, RqE, RqF, RqG, and RqH, the basic operation parameters PbD, PbE, PbF, PbG, and PbH, and the quantization parameters PqD, PqE, PqF, PqG, and PqH are set accordingly. The quantization parameters PqD, PqE, PqF, PqG, and PqH in this embodiment include bit count settings that allow specifying the number of bits in the output data of the quantized neural network 500. The bit count settings for each of the quantization parameters PqD, PqE, PqF, and PqG are set to 3 bits. The bit count setting for the quantization parameter PqH is set to 2 bits. In other words, in the memory system 3 of this embodiment, when any of the quantization ranges RqD, RqE, RqF, and RqG are used, the output data of the quantized neural network 500 has a precision of 3 bits. Furthermore, when using the quantization range RqH, the output data of the quantized neural network 500 has a precision of 2 bits.

[0140] In step S40, as shown in Figure 13, the estimation unit 44 inputs the input data generated in step S24 to the input layer 510 of the quantized neural network 500, using the basic calculation parameter PbH and the quantization parameter PqH. As a result, the output layer 530 of the quantized neural network 500 outputs an approximate shift value ΔVrA of the readout voltage with a 2-bit accuracy.

[0141] Next, the estimation unit 44 determines whether or not it is necessary to re-estimate the shift value ΔVr of the read voltage (step S41). For example, if the approximate shift value ΔVrA of the read voltage calculated in step S40 is within the range of either the quantization ranges RqD and RqE shown in Figure 14, the estimation unit 44 determines that it is necessary to re-estimate the shift value ΔVr of the read voltage (step S41: YES). In this case, the quantization range determination unit 42 determines the quantization range of the shift value of the read voltage based on the approximate shift value ΔVrA of the read voltage calculated in step S40 (step S42). For example, if the approximate shift value ΔVrA of the read voltage is within the range RqD shown in Figure 14, the quantization range of the shift value of the read voltage is set to RqD. After that, steps S27 and S28 are executed. As a result, when the quantization range of the memory cell MT is set to RqD, the shift value ΔVr of the read voltage is calculated with 3-bit precision, i.e., with higher precision, within the quantization range RqD shown in Figure 14. Thus, when the quantization range of the roughly estimated read voltage shift value is either RqD or RqE, the read voltage shift value ΔVr is re-estimated with 3-bit precision.

[0142] On the other hand, in the process of step S41, the quantization range determination unit 42 determines that if the approximate shift value ΔVrA of the read voltage is within the range of either the quantization ranges RqF and RqG shown in Figure 14, it is not necessary to re-estimate the shift value ΔVr of the read voltage (step S41: NO). In this case, steps S42, S27, and S28 are not executed. Therefore, the approximate value ΔVrA calculated in the process of step S40 is used as is as the shift value ΔVr of the read voltage. Consequently, if the quantization range of the roughly estimated shift value of the read voltage is either RqD or RqE, the shift value ΔVr of the read voltage is estimated with a precision of 2 bits.

[0143] If a negative judgment is made in step S41, or after step S28 is executed, steps S29 and S30 are executed.

[0144] 2.2 Operation and Effects of the Memory System The quantization range determination unit 42 of this embodiment determines the quantization range of the shift value of the read voltage to be estimated by the quantization neural network 500, using the approximate shift value ΔVrA of the read voltage roughly estimated using the quantization neural network 500.

[0145] This configuration allows for more precise determination of the quantization range of the read voltage shift value, thus enabling accurate setting of the read voltage of the memory cell MT.

[0146] 3 Other Embodiments This disclosure is not limited to the specific examples given above.

[0147] For example, the configuration of the quantized neural network 500 can be changed arbitrarily.

[0148] The configuration of the memory system 3 in each of the above embodiments is not limited to a memory system having NAND flash memory as a semiconductor memory device, but can be applied to any memory system having an SSD (Solid State Drive) or other semiconductor memory device.

[0149] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the claims of the invention and its equivalents. [Explanation of symbols]

[0150] 2: Semiconductor memory device, 3: Memory system, 11: RAM (storage medium), 12: ROM (storage medium), 13: Processor, 41: Input data acquisition unit, 42: Quantization range determination unit, 43: Parameter setting unit, 44: Estimation unit, 45: Voltage setting unit, 500: Quantization neural network.

Claims

1. An input data acquisition unit obtains input data indicating the relationship between the number of on-cells, which is the number of memory cells that become ON in the semiconductor memory device when data is read, and the multiple read voltages, by causing the semiconductor memory device to read data using multiple read voltages. A quantization range determination unit that determines the quantization range of the shift value of the readout voltage estimated by the quantized neural network, A parameter setting unit sets the parameters of the quantized neural network based on the quantization range determined by the quantization range determination unit, An estimation unit that estimates the shift value of the readout voltage from the input data using the quantized neural network that uses the parameters set by the parameter setting unit, The system includes a voltage setting unit that sets the read voltage used during the read operation of the semiconductor memory based on the shift value. Memory system.

2. The aforementioned parameters include the weights and quantization parameters of the quantized neural network. The memory system according to claim 1.

3. The quantization parameter includes a quantization scale that indicates the resolution of the value after quantization, and zeros that are integer values ​​taken after quantization from values ​​that were zero as real numbers before quantization. The memory system according to claim 2.

4. The quantization range determination unit determines the quantization range based on whether the input data satisfies predetermined boundary conditions. The memory system according to claim 1.

5. The quantization range determination unit uses a plurality of predetermined boundary conditions The memory system according to claim 4.

6. The quantization range determination unit sets the quantization range based on the input data. The memory system according to claim 1.

7. The quantization range determination unit sets the quantization range based on the calculation values ​​of the intermediate layer of the quantized neural network. The memory system according to claim 1.

8. The quantization range determination unit determines the quantization range of the shift value of the readout voltage to be estimated by the quantization neural network, using the shift value roughly estimated using the quantization neural network. The memory system according to claim 1.

9. A storage medium that stores a computer-readable program and a quantized neural network, A processor that executes the aforementioned program, The processor executes the program, By causing a semiconductor memory device to read data using multiple read voltages, input data is obtained that shows the relationship between the number of on-cells (the number of memory cells that become ON in the semiconductor memory device when data is read) and the multiple read voltages. The quantization range of the shift value of the readout voltage estimated by the quantized neural network is determined, The parameters of the quantized neural network are set based on the quantization range. The quantized neural network using the aforementioned parameters estimates the shift value of the readout voltage from the input data. Based on the shift value, the read voltage used during the read operation of the semiconductor memory is calculated. Memory system.

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