Method for forming contact holes, method for manufacturing semiconductor devices

Abstract

This makes it possible to improve the precision of contact hole formation. [Solution] A method for forming a contact hole, comprising the steps of: applying a first precursor to a substrate on which the gate electrode of a transistor is arranged, such that the amount applied to the upper part of the gate electrode is less than that applied to other parts, thereby forming a first film having a flat upper surface; and patterning the first film when forming the contact hole.

Description

Technical Field

[0001] The present invention relates to a method for forming a contact hole and a method for manufacturing a semiconductor device.

Background Art

[0002] The miniaturization of the manufacturing process of semiconductor devices is progressing. Patent Document 1 discloses a semiconductor device having a contact plug connected to a semiconductor layer element layer, a fine wiring pattern, and a metal junction.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When forming a contact plug, a contact hole is formed in an insulating layer at the position where the contact plug is to be arranged. In the step of forming this contact hole, there is a step of forming a photoresist on a surface with irregularities. At this time, due to the fine irregularities on the upper surface of the photoresist, it was difficult to form a fine resist pattern, and it was difficult to improve the formation accuracy of the contact hole.

Means for Solving the Problems

[0005] According to one disclosure of the present specification, in a method for forming a contact hole, a first precursor is applied on a substrate on which a gate electrode of a transistor is arranged so that the application amount on the upper part of the gate electrode is less than that of other parts, and a first film having a flat upper surface is formed; and a step of patterning the first film when forming the contact hole. There is provided a method for forming a contact hole, characterized by comprising these steps.

Effects of the Invention

[0006] According to the present invention, it is possible to improve the accuracy of contact hole formation. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic diagram showing the configuration of a planarization device. [Figure 2] A schematic diagram illustrating the flattening process. [Figure 3] A schematic diagram illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 4] A schematic diagram illustrating the manufacturing method of a semiconductor device according to the first embodiment. [Figure 5] A schematic diagram illustrating the manufacturing method of a semiconductor device according to the second embodiment. [Figure 6] A schematic diagram illustrating a semiconductor device according to the third embodiment. [Figure 7] A schematic diagram illustrating an application example of the semiconductor device according to the fourth embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings. Note that the embodiments described below do not limit the invention as defined in the claims. While multiple features are described in the embodiments, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, the same or similar configurations are given the same reference numeral, and redundant descriptions may be omitted.

[0009] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, terms indicating specific directions or positions (e.g., "up," "down," "right," "left," and other terms including these terms) will be used as needed. The use of these terms is for the purpose of facilitating the understanding of embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0010] In this specification, a plan view refers to a view taken from a direction perpendicular to the top surface of the semiconductor substrate. A cross-sectional view refers to a surface perpendicular to the top surface of the semiconductor substrate. If the top surface of the semiconductor substrate is rough when viewed microscopically, the plan view is defined based on the top surface of the semiconductor substrate as viewed macroscopically. The top surface of the semiconductor substrate is defined as the surface on which elements formed on the semiconductor substrate, such as the gate of a transistor, are provided, or the surface on which connections to contact plugs are located.

[0011] Furthermore, expressions such as "A or B," "at least one of A and B," "at least one of A and / or B," and "one or more of A and / or B" include all possible combinations of the enumerated items unless explicitly defined otherwise. That is, the above expressions are understood to disclose all cases where at least one A is included, where at least one B is included, and where at least one A and at least one B are included. This applies equally to combinations of three or more elements.

[0012] <First Embodiment> Figure 1 is a schematic diagram showing the configuration of the planarization apparatus 100 according to this embodiment. Directions are indicated in an XYZ coordinate system where the horizontal plane is the XY plane. Generally, the substrate 1, which is the object to be processed, is placed on the substrate stage 3 so that its surface is parallel to the horizontal plane (XY plane). Therefore, in the following, the directions that are orthogonal to each other in the plane along the surface of the substrate 1 will be referred to as the X axis and the Y axis, and the direction perpendicular to the X axis and the Y axis will be referred to as the Z axis. Also, in the following, the directions parallel to the X axis, Y axis and Z axis in the XYZ coordinate system will be referred to as the X direction, Y direction and Z direction, respectively, and the rotational directions around the X axis, Y axis and Z axis will be referred to as the θX direction, θY direction and θZ direction, respectively. The substrate 1 will be described later, but it is a material to which semiconductor processes can be applied, such as a semiconductor wafer, a semiconductor wafer with a wiring structure formed on it, a glass substrate with an element formed on it, or a metal substrate.

[0013] The underlying pattern on the substrate has an uneven profile resulting from the pattern formed in the previous process, and especially with the recent increase in the multilayer structure of memory elements, process substrates are now sometimes found to have steps of around 100 nm. Steps caused by gentle undulations across the entire substrate can be corrected by the focus tracking function of the scan exposure equipment used in the photoprocessing stage. However, fine-pitched irregularities that fit within the exposure slit area of ​​the exposure equipment may fall outside the exposure equipment's DOF ​​(Depth of Focus). Conventionally, methods such as SOC (Spin On Carbon) and CMP (Chemical Mechanical Polishing) have been used to smooth the underlying pattern of the substrate by forming or flattening a planarization layer. However, conventional techniques have the problem of not being able to obtain sufficient planarization performance. For example, manufacturing processes are evolving to new technology nodes such as 22 nm, 16 nm, 14 nm, and 10 nm. Even if a planarization layer that was practically sufficient was obtained at the previous node, that planarization layer may not be practical at the next node. For example, surface irregularities in the planarization layer that were acceptable in the previous node may not be acceptable in the next node. Furthermore, CMP is expensive and its applicability is limited, while the difference in substrate irregularities due to multi-layer construction is expected to increase further in the future.

[0014] To solve this problem, a planarization apparatus that uses imprint technology to planarize substrates is being investigated. The planarization apparatus brings a flat surface of a component, or a component without a pattern (a planar template), into contact with an uncured composition that has been supplied to the substrate in advance, thereby planarizing a localized area or the entire surface of the substrate. Subsequently, the composition is cured while in contact with the planar template, and the planar template is separated from the cured composition. This forms a planarized layer on the substrate. This planarization apparatus is not affected by the unevenness of the pattern surface of the substrate, unlike the planarization method using a commonly used SOC sacrificial film, and is therefore expected to improve the accuracy of planarization compared to existing methods.

[0015] The planarization apparatus 100 in Figure 1 can be realized by a molding apparatus that uses a plate 9, which is a pressing member, to form a composition on a substrate 1. The planarization apparatus 100 hardens the composition while the material on the substrate 1 and the plate 9 are in contact, and then separates the plate 9 from the hardened composition to form a planarized layer of material on the substrate 1.

[0016] Substrate 1 is a semiconductor, insulator, or metal substrate, and its shape can be circular, such as a silicon wafer or quartz wafer, or rectangular, such as a (mother) glass for an FPD (Flat Panel Display). The material of substrate 1 may be, but is not limited to, a single-crystal silicon wafer. The material of the substrate may be an elemental semiconductor or compound semiconductor such as silicon, germanium, diamond, silicon carbide, silicon germanium, gallium nitride, gallium arsenide, indium arsenide, or cadmium telluride. The material of substrate 1 may also be an inorganic insulator such as silicon oxide, silicon nitride, aluminum oxide, or aluminum nitride. The material of substrate 1 may also be an organic insulator such as polyimide, polyamide, or polycarbonate. Furthermore, substrate 1 may be aluminum, titanium-tungsten alloy, aluminum-silicon alloy, or aluminum-copper-silicon alloy. In short, substrate 1 may be composed of one or more materials arbitrarily selected from the materials listed above. The surface of the substrate 1 may have at least one film of a semiconductor, insulator, or metal formed on it, and its surface may be flat or have an uneven surface. Furthermore, a substrate may be used in which an adhesion layer is formed on the surface by surface treatment such as silane coupling treatment, silazane treatment, or deposition of an organic thin film to improve adhesion to the composition. The substrate 1 is typically circular with a diameter of 300 mm, but is not limited to this.

[0017] As the plate 9, it can be made of a light-transmissive material in consideration of the light irradiation process. The material of such a material is, for example, a light-transmissive inorganic material such as glass or quartz, or a light-transmissive organic material such as PMMA (Polymethyl methacrylate) or polycarbonate resin. The plate 9 may be a rigid plate or a flexible film. And the surface of the plate 9 in contact with the composition is flat. Note that the plate 9 preferably has a circular shape with a diameter larger than 300 mm and smaller than 500 mm, but is not limited thereto. Also, the thickness of the plate 9 is preferably 0.25 mm or more and less than 2 mm, but is not limited thereto. Note that when the composition is a thermosetting material rather than a photo-curable material, the plate 9 does not need to be transparent, and any material having the above characteristics may be used. <照合前>

[0018] The composition is a precursor that cures to become at least part of the planarizing film, and is a curable composition that can be cured by receiving light or heat energy. A curable composition that can be cured by receiving light or heat energy is a photo-curable composition that cures when irradiated with light, a thermosetting composition that cures when heated, or a photo-thermosetting composition that cures by receiving light and heat energy. Examples of the photo-curable composition include UV curable liquids. As the UV curable liquid, typically monomers such as acrylates and methacrylates can be used. The curable composition may be referred to as a moldable material. Hereinafter, the moldable material is also simply referred to as "material". ​​As shown in Fig. 1, the planarization apparatus 100 includes a substrate chuck 2, a substrate stage 3, a base platen 4, a support column 5, a top plate 6, a guide bar 7, a support column 8, a plate chuck 11, a head 12, and an alignment shelf 13. The planarization apparatus 100 further includes a pressure adjustment unit 15, a supply unit 17, a substrate transfer unit 18, an alignment scope 19, a light source 20, a stage drive unit 21, a plate transfer unit 22, a cleaning unit 23, an input unit 24, and a control unit 200. The substrate chuck 2 and the substrate stage 3 can hold and move the substrate 1. Also, the plate chuck 11 and the head 12 can hold and move the plate 9.

[0020] The substrate 1 is carried into the planarization apparatus 100 from the outside by a substrate transfer unit 18 including a transfer hand or the like and is held by the substrate chuck 2. The substrate stage 3 is supported by the base platen 4 and is driven in the X direction and the Y direction to position the substrate 1 held by the substrate chuck 2 at a predetermined position. The stage drive unit 21 includes, for example, a linear motor, an air cylinder, or the like, and drives the substrate stage 3 at least in the X direction and the Y direction, but may have a function of driving the substrate stage 3 in two or more axes (for example, six axes). Also, the stage drive unit 21 includes a rotation mechanism and can rotationally drive the substrate chuck 2 or the substrate stage 3 in the θZ direction.

[0021] The pressing member, plate 9, is brought in from outside the flattening device 100 by a plate transport unit 22, including a transport hand, and held by a plate chuck 11. The plate 9 has, for example, a circular or rectangular outer shape and has a first surface including a flat surface 10 that contacts the material placed on the substrate 1, and a second surface opposite to the first surface. In this embodiment, the flat surface 10 is the same size as the substrate 1 or larger than the substrate 1. The plate chuck 11 is supported by a head 12 and may have the function of correcting the position of the plate 9 in the θZ direction (tilt around the Z axis). Both the plate chuck 11 and the head 12 include an aperture that allows light (ultraviolet light) irradiated from the light source 20 through a collimator lens to pass through. The plate chuck 11 functions as a holding part that mechanically holds the plate 9. For example, the plate chuck 11 holds the plate 9 by pulling the second surface of the plate 9 upwards. The head 12 also mechanically holds the plate chuck 11. The plate chuck 11 and head 12 constitute a forming unit 50 that performs the process of forming a planarized film. The head 12 comprises a drive mechanism (not shown) for positioning the distance between the substrate 1 and the plate 9 when the plate 9 is brought into contact with and separated from the material on the substrate 1, and moves the plate 9 in the Z direction. The drive mechanism of the head 12 may be composed of an actuator such as a linear motor, an air cylinder, or a voice coil motor. A load cell may also be placed in the plate chuck 11 or the head 12 for measuring the pressing force (imprinting force) of the plate 9 against the material on the substrate. The plate deformation mechanism (plate deformation unit) first comprises a sealing member 14 that seals the spatial region A formed by the space inside the plate chuck 11 and the internal space surrounded by the plate 9. The plate deformation mechanism also comprises a pressure adjustment unit 15 installed outside the plate chuck 11 that adjusts the pressure in the spatial region A. The sealing member 14 is made of a light-transmitting flat plate member such as quartz glass, and is provided with a connection port (not shown) for a pipe 16 connected to the pressure adjustment unit 15. The pressure adjustment unit 15 can increase the amount by which the plate 9 deforms convexly toward the substrate side by increasing the pressure in the spatial region A.Furthermore, the pressure adjustment unit 15 can reduce the amount of convex deformation of the plate 9 by lowering the pressure in spatial region A. Support columns 5 that support the top plate 6 are arranged on the base plate 4. The guide bar 7 is suspended from the top plate 6, passes through the alignment shelf 13, and is fixed to the head 12. The alignment shelf 13 is suspended from the top plate 6 via support columns 8. The guide bar 7 passes through the alignment shelf 13. In addition, the alignment shelf 13 is equipped with a height measuring system (not shown) for measuring the height (flatness) of the substrate 1 held by the substrate chuck 2, for example, using an oblique incidence image misalignment method.

[0022] The alignment scope 19 includes an optical system and imaging system for observing a reference mark provided on the substrate stage 3 and an alignment mark provided on the plate 9. However, if no alignment mark is provided on the plate 9, the alignment scope 19 may not be necessary. The alignment scope 19 is used for alignment, measuring the relative position of the reference mark provided on the substrate stage 3 and the alignment mark provided on the plate 9, and correcting any misalignment.

[0023] The supply unit 17 includes a dispenser with nozzles that dispense uncured material onto the substrate 1, and supplies (coats) the material onto the substrate. The supply unit 17 employs, for example, a piezo jet system or a micro solenoid system, and can supply a minute volume of material of about 1 pL (picoliters) onto the substrate 1 while the substrate stage 3 is scanning. There is no limit to the number of nozzles in the supply unit 17; there may be one (single nozzle) or multiple (for example, 100 or more). Multiple nozzles may form a linear nozzle array of one or more rows. Dispensers of the type known as an inkjet head are particularly suitable because they can apply liquid material to the substrate as minute droplets. A piezo inkjet head, which is equipped with at least one piezoelectric energy generator at each nozzle, is particularly suitable because it can change the volume of the ejected droplets.

[0024] The cleaning unit 23 cleans the plate 9 while it is held in the plate chuck 11. In this embodiment, the cleaning unit 23 removes material adhering to the plate 9, particularly to the flat surface 10, by separating the plate 9 from the hardened material on the substrate. The cleaning unit 23 may, for example, wipe off the material adhering to the plate 9, or it may remove the material adhering to the plate 9 using UV irradiation, electrostatic discharge, wet cleaning, dry plasma cleaning, or the like.

[0025] The control unit 200 is composed of a computer device including a CPU and memory, and controls the entire planarization apparatus 100. The control unit 200 functions as a processing unit that comprehensively controls each part of the planarization apparatus 100 and performs the planarization process. Here, the planarization process is a process in which the flat surface 10 of the plate 9 is brought into contact with the material on the substrate, and the flat surface 10 is made to conform to the surface shape of the substrate 1, thereby flattening the material. Generally, the planarization process is performed on a lot basis, that is, for each of the multiple substrates included in the same lot.

[0026] Next, the planarization process will be explained with reference to Figure 2. First, the material IM is supplied to the substrate 1 on which the base pattern 1a is formed by the supply unit 17. Figure 2(a) shows the state after the material IM has been placed on the substrate 1 but before the plate 9 is brought into contact with it. Next, as shown in Figure 2(b), the material IM on the substrate 1 is brought into contact with the flat surface 10 of the plate 9. The plate 9 presses against the material IM, causing the material IM to spread across the entire surface of the substrate 1. Figure 2(b) shows the state where the entire flat surface 10 of the plate 9 is in contact with the material IM on the substrate 1, and the flat surface 10 of the plate 9 conforms to the surface shape of the substrate 1. Then, in the state shown in Figure 2(b), light is irradiated from the light source 20 through the plate 9 onto the material IM on the substrate 1, thereby hardening the material IM. After that, the plate 9 is separated from the hardened material IM on the substrate 1. This forms a layer of material IM of uniform thickness (planarization layer) across the entire surface of the substrate 1. Figure 2(c) shows the state in which a planarization layer made of material IM has been formed on the substrate 1. Hereafter, contact (adhesion) or separation between the flat surface 10 of the plate 9 and the material IM on the substrate 1 will be simply expressed as "contact (adhesion) or separation" between the plate 9 and the material IM on the substrate 1. Also below, the material IM in the state supplied to the substrate 1 will be referred to as a precursor, and the material IM after curing will be referred to as a film. The precursor corresponding to the first material IM1 may be referred to as the first precursor, and the film corresponding to the first material IM1 may be referred to as the first film. The precursor corresponding to the second material IM2 may be referred to as the second precursor, and the film corresponding to the second material IM2 may be referred to as the second film.

[0027] Next, a method for manufacturing articles (semiconductor devices, liquid crystal display devices, color filters, MEMS, etc.) using this planarization apparatus 100 will be described. This manufacturing method includes the steps of: planarizing a composition by bringing it into contact with a mold on a substrate (wafer, glass substrate, etc.) using the aforementioned planarization apparatus; curing the composition; and separating the composition from the mold. This forms a planarized film on the substrate. Then, the substrate on which the planarized film has been formed is subjected to processing such as patterning using a lithography apparatus, and the processed substrate is processed in other well-known processing steps to manufacture an article. Other well-known processes include etching, resist stripping, dicing, bonding, packaging, etc. According to this manufacturing method, articles of higher quality than conventional methods can be manufactured.

[0028] The following explanation will use semiconductor devices as an example of specific items. Figures 3(a) and 3(b) are schematic diagrams illustrating the manufacturing method of the semiconductor device of this embodiment, showing the process of forming contact holes. Semiconductor devices 300a and 300b have a semiconductor substrate 301 having a transistor source-drain region 302 and a transistor gate electrode 303. Surface P1 is the upper surface of the semiconductor substrate 301, and surface P2 is the lower surface of the semiconductor substrate 301. Furthermore, semiconductor device 300a in Figure 3(a) further has an insulating layer 304 and a first photoresist film 306. The insulating layer 304 and the first photoresist film 306 are arranged in this order on surface P1 of the semiconductor substrate 301. That is, the insulating layer 304 is arranged between the first photoresist film 306 and surface P1 of the semiconductor substrate 301. The insulating layer 304 can be formed from a single layer or multiple layers of any insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxide carbide, spin-on glass (SOG), or low dielectric material.

[0029] Figure 3(a) shows the state in which an insulating layer 304 has been formed on the semiconductor substrate 301, and a first photoresist film 306 for forming a photoresist pattern for contact holes has been formed. The first photoresist film 306 is formed covering the upper surface of the insulating layer 304. Here, protrusions may be formed on the upper surface of the insulating layer 304 in accordance with the gate electrode 303. Furthermore, protrusions may be formed on the upper surface of the first photoresist film 306 in accordance with the protrusions formed on the upper surface of the insulating layer 304. Thus, if the flatness of the upper surface of the first photoresist film 306 is low, imaging cannot be formed when the first photoresist film 306 is exposed, making it difficult to form a fine photoresist pattern. In particular, with short wavelengths such as EUV (Extreme Ultra Violet), the depth of focus of the exposure device becomes shallow, so the flatness and uniformity of the film thickness of the photoresist are important.

[0030] Therefore, in the embodiment of the present invention, as shown in Figure 3(b), a liquid precursor (material IM) of a material that can later become an etching mask is applied in predetermined amounts, with less applied to the upper part of the gate electrode 303 and more applied to the other parts. The liquid precursor may be an energy-curable resin precursor or a Spin On Carbon (SOC) precursor. Then, if necessary, the flat surface of the plate is pressed against the liquid to cure it. After curing, a photoresist film is formed. Because liquid is applied between the multiple gate electrodes 303 before the formation of the photoresist film, the surface of the photoresist film formed thereafter has even greater flatness than the state shown in Figure 3(a), and can be sufficiently exposed even when the depth of field is shallow. The thus exposed photoresist film is developed to form a resist pattern.

[0031] When applying the uncured material, an inkjet head is used that has a piezoelectric element as an ejection actuator mounted between a plurality of pre-formed gate electrodes 303. Specifically, droplets are injected N times per unit area (N is a natural number) onto the top of the gate electrodes 303, and N+1 or more times per unit area onto the flat surfaces of the semiconductor substrate 301 (between the plurality of gate electrodes 303). The number of droplets injected can be determined according to the formation pattern of the gate electrodes 303. Specifically, droplets are injected while changing the relative position between the ejection port and the substrate, according to a drawing map that determines the number (or amount) of droplets to be injected onto the substrate and their injection position on the upper surface, based on the pattern data of the resist mask for forming the gate electrodes 303.

[0032] Because the spaces between the multiple gate electrodes 303 are filled in this way, the surface of the resist film that is subsequently formed becomes flat. The liquid used here is preferably a composition that hardens upon receiving light energy (a precursor to the cured film).

[0033] On the other hand, a so-called positive-type resist is preferably used as the resist film, in which a portion becomes soluble in the developer solution upon receiving light energy. The apparatus for exposing the resist film is preferably an EUV exposure apparatus, which may have an numerical aperture (NA) of 0.33 or higher and 0.75 or lower. For example, the numerical aperture (NA) may be 0.55. Note that the numerical aperture (NA) may be a value greater than 0.55. Note that the numerical aperture (NA) may be a value greater than 0.75. Alternatively, an ArF immersion exposure apparatus, an ArF dry exposure apparatus, or a KrF exposure apparatus may be used.

[0034] Next, the manufacturing method for the semiconductor device of this embodiment will be described. Figure 4 is a schematic diagram illustrating the manufacturing method for the semiconductor device of the first embodiment. The manufacturing method shown in Figure 4 applies the planarization method described in Figures 1 and 2 to the manufacturing of the contact holes described in Figure 3.

[0035] Figure 4(a) shows that, similar to Figure 3(b), the first material IM1 of the cured film is applied after the process of forming the gate electrode 303. The amount of the first material IM1 applied is adjusted according to the shape of the surface P1 of the semiconductor substrate 301. Here, the amount of the first material IM1 applied on the top of the gate electrode 303 is less than the amount applied on the flat surface P1 around it (between the multiple gate electrode 303s). This can be controlled, for example, by changing the number of droplets of the precursor (liquid) of the first material IM1 ejected by an inkjet method, or by changing the size of the droplets.

[0036] Next, as shown in Figure 4(b), the plate 9 is brought into contact with the first material IM1 as needed to flatten the upper surface of the first material IM1. Then, light is shone onto the first material IM1 through the plate 9. The first material IM1 hardens when exposed to light. After that, the plate 9 is separated from the hardened first material IM1 on the semiconductor substrate 301. This planarization process forms a first film 305 having a highly flat upper surface. Here, the first material IM1 can be, for example, a precursor of an energy-curable resin or a precursor of SOC (Spin On Carbon), as described above.

[0037] As shown in Figure 4(c), a first photoresist film 306 is formed on the upper surface of the first film 305. Because it is formed on the highly flat first film 305, the flatness of the upper surface of the first photoresist film 306 is also increased. An arbitrary pattern is exposed to the first photoresist film 306. At this time, the exposure may be EUV exposure. When the first photoresist film 306 that has been EUV exposed is developed, the exposed portion becomes soluble in the developer, and a resist pattern is formed. In this way, as shown in Figure 4(d), a first resist pattern 307 is formed. The first resist pattern 307 has a first aperture 308. The first film 305 is exposed by the first aperture 308.

[0038] In the state shown in Figure 4(d), a portion of the first film 305 is removed to form a contact hole 309. The contact hole 309 is formed to penetrate the first film 305 and expose the gate electrode 303. By performing anisotropic etching on the first film 305 using a reactive ion etching apparatus with the first resist pattern 307 as a mask, a contact hole 309 communicating with the first opening 308 is formed. If the etching resistance of the first resist pattern 307 is high during this etching, the first resist pattern 307 may remain, as shown in Figure 4(e). In that case, the first resist pattern 307 is removed after the contact hole 309 is formed. In this way, a structure having a contact hole 309 can be formed.

[0039] However, if there is no significant difference in etching rates between the first resist pattern 307 and the first film 305, the first resist pattern 307 and the first film 305 in the areas where the contact holes 309 are formed will be sequentially removed during etching of the first film 305. Therefore, as shown in Figure 4(f), when the contact holes 309 are formed by etching, the first resist pattern 307 and the first film 305 in the areas where the contact holes 309 are formed will have disappeared, except for the residue. The residue of the first resist pattern 307 and the first film 305 can be removed as needed.

[0040] Subsequently, a conductive film is formed to fill the contact hole 309, and any excess conductive film is removed. This forms a conductive portion that fills the contact hole 309. Here, the conductor may consist of multiple layers of barrier metals such as transition metals like Ti or Ta, or transition metal compounds such as TiN or TaN, and a filling metal such as Cu. The filling process can be carried out using known methods such as film deposition by CVD, sputtering, or plating, and polishing of the conductor by CMP.

[0041] As described above, the flatness of the upper surface of the photoresist before exposure and the uniformity of the photoresist film thickness can be improved, thereby improving the accuracy of resist pattern formation. In other words, the accuracy of contact hole formation can be improved.

[0042] Here, for example, the flatness of the top surface of the photoresist required by EUV exposure is <10 nm. According to the planarization method of this embodiment, it is easy to satisfy the flatness of the top surface of the photoresist. Furthermore, in EUV exposure, this method is preferable when the numerical aperture NA is greater than 0.33, and especially greater than 0.55.

[0043] As described above, the method for forming contact holes according to this embodiment makes it possible to form contact holes with high precision.

[0044] <Second Embodiment> The manufacturing method for the semiconductor device of this embodiment will now be described. Figure 5 is a schematic diagram illustrating the manufacturing method for the semiconductor device of the second embodiment. The manufacturing method shown in Figure 5 involves forming contact holes in an insulating layer different from the first film, compared to the manufacturing method described in Figure 4. Hereafter, the same configuration and process as in Figure 4 will not be described in detail.

[0045] Figure 5(a) shows the application of the first material IM1 of the cured film after the process of forming an insulating layer 304 on the gate electrode 303. In Figure 5(a), as in Figure 3(a), a protrusion is formed on the upper surface of the insulating layer 304 in accordance with the gate electrode 303. That is, a portion of the insulating layer 304 positioned above the gate electrode 303 forms a protrusion. The amount of the first material IM1 applied is adjusted according to the shape of the upper surface of the insulating layer 304. Here, the amount of the first material IM1 applied to the upper part of the insulating layer 304 that forms the protrusion is less than that applied to the surrounding flat upper surface. This can be controlled, for example, by changing the number of droplets of the precursor (liquid) of the first material IM1 ejected by an inkjet method, or by changing the size of the droplets.

[0046] As shown in Figure 5(b), if necessary, the flat surface of the plate 9 is brought into contact with the first material IM1 to flatten the upper surface of the first material IM1. Then, light is shone onto the first material IM1 through the plate 9 to cure the first material IM1. This process is the same as in Figure 4(b). Furthermore, as shown in Figure 5(c), after the first material IM1 has been cured and the first film 305 has been formed, the plate 9 is removed.

[0047] After removing plate 9, a first photoresist film 306 is formed on the flattened upper surface of the first film 305, as shown in Figure 5(d). Then, a latent image is formed on the first photoresist film 306 by exposing it to an arbitrary pattern, which is then developed and post-baked.

[0048] Thus, as shown in Figure 5(e), the first resist pattern 307 is formed. The first resist pattern 307 has a first opening 308. In the state shown in Figure 5(e), a portion of the first film 305 is removed to form a second opening 310 in the first film 305. Using the first resist pattern 307 as a mask, anisotropic etching is performed on the first film 305 using a reactive ion etching apparatus to form a second opening 310 that communicates with the first opening 308. Here, if there is no significant difference in etching rates between the first resist pattern 307 and the first film 305, the first film 305 in the areas where the first resist pattern 307 and the second opening 310 are formed will be sequentially removed during etching of the first film 305. Therefore, as shown in Figure 5(f), when the second opening 310 is formed by etching, the first film 305 in the areas where the first resist pattern 307 and the second opening 310 are formed will have disappeared, except for the residue. The residues of the first resist pattern 307 and the first film 305 can be removed as needed.

[0049] However, if the first resist pattern 307 has high etching resistance, the first resist pattern 307 may remain. In that case, the first resist pattern 307 is removed after the second opening 310 is formed.

[0050] In the state shown in Figure 5(f), a portion of the insulating layer 304 is removed to form a contact hole 309. The contact hole 309 is formed to penetrate the insulating layer 304 and expose the gate electrode 303. By performing anisotropic etching on the insulating layer 304 using a reactive ion etching apparatus with the first film 305 as a mask, a contact hole 309 communicating with the second opening 310 is formed. If the etching resistance of the first film 305 is high during this etching, the first film 305 may remain, as shown in Figure 5(g). In that case, the first film 305 is removed after the contact hole 309 is formed. In this way, a structure having a contact hole 309 can be formed.

[0051] However, if there is no significant difference in etching rates between the first film 305 and the insulating layer 304, the insulating layer 304 will be sequentially removed during etching of the insulating layer 304, along with the first film 305 and the insulating layer 304 where the contact holes 309 are formed. Therefore, as shown in Figure 5(h), when the contact holes 309 are formed by etching, the insulating layer 304 in the areas where the first film 305 and contact holes 309 are formed will have disappeared, except for any residue. The residue of the first film 305 and insulating layer 304 can be removed as needed.

[0052] Subsequently, a conductor can be embedded in the contact hole 309, similar to the method described above, to form a conductor portion that fills the contact hole 309.

[0053] This method improves the flatness of the upper surface of the photoresist, thereby improving the accuracy of resist pattern formation. In other words, it improves the accuracy of contact hole formation. As described above, the method for forming contact holes in this embodiment makes it possible to form contact holes with high accuracy.

[0054] <Third Embodiment> The manufacturing method for the semiconductor device of this embodiment will now be described. Figure 6 is a schematic diagram illustrating the manufacturing method for the semiconductor device of the third embodiment. The manufacturing method shown in Figure 6 is different from the manufacturing method described in Figure 4 in that a via hole is formed above the contact hole. Hereafter, the same configuration and process as in Figure 4 will not be described in detail.

[0055] Figure 6(a) shows the state in which a conductor is embedded in the contact hole 309 formed in the first film 305, and a contact plug 311 is formed.

[0056] Next, as shown in Figure 6(b), the second material IM2 of the cured film is applied, and if necessary, the flat surface of the plate 9 is brought into contact with the second material IM2 to flatten the upper surface of the second material IM2. Then, light is irradiated onto the second material IM2 through the plate 9 to cure the second material IM2. After that, the plate 9 is pulled away from the cured second material IM2 on the first film 305. This flattening process forms a second film 312 having a highly flat upper surface. Here, the second material IM2 can be, for example, a precursor of an energy-curable resin or a precursor of SOC (Spin On Carbon), as described above.

[0057] After removing plate 9, a second photoresist film 313 is formed on the upper surface of the second film 312, as shown in Figure 6(c). Because it is formed on the highly flat second film 312, the flatness of the upper surface of the second photoresist film 313 is also increased. An arbitrary pattern is exposed to the second photoresist film 313. At this time, the exposure may be EUV exposure. When the EUV-exposed second photoresist film 313 is developed, the exposed portion becomes soluble in the developer, forming a resist pattern. In this way, a second resist pattern 314 is formed, as shown in Figure 6(d). The second resist pattern 314 has a third aperture 315. The second film 312 is exposed by the third aperture 315.

[0058] In the state shown in Figure 6(d), a portion of the second film 312 is removed to form via holes 316 in the second film 312. Using the second resist pattern 314 as a mask, anisotropic etching is performed on the second film 312 using a reactive ion etching apparatus to form via holes 316 that communicate with the third opening 315. Here, if there is no significant difference in etching rates between the second resist pattern 314 and the second film 312, the second film 312 in the areas where the second resist pattern 314 and via holes 316 are formed will be sequentially removed during etching. Therefore, as shown in Figure 6(e), when the via holes 316 are formed by etching, the second film 312 in the areas where the second resist pattern 314 and via holes 316 are formed will have disappeared, except for the residue. The residue of the second resist pattern 314 and the second film 312 can be removed as needed.

[0059] However, if the second resist pattern 314 has high etching resistance, it may remain. In that case, the second resist pattern 314 is removed after forming the via hole 316.

[0060] Subsequently, in the same manner as described above, a conductor can be embedded in the via hole 316 to form a conductor portion (via plug 317) that embeds the via hole 316.

[0061] As described above, the flatness of the upper surface of the photoresist before exposure and the uniformity of the photoresist film thickness can be improved, thereby improving the accuracy of resist pattern formation. In other words, the accuracy of contact hole formation can be improved. Furthermore, the accuracy of via hole formation can be improved.

[0062] Here, for example, the flatness of the top surface of the photoresist required by EUV exposure is <10 nm. According to the planarization method of this embodiment, it is easy to satisfy the flatness of the top surface of the photoresist. Furthermore, in EUV exposure, this method is preferable when the numerical aperture NA is greater than 0.33, and especially greater than 0.55.

[0063] As described above, the method for forming contact holes according to this embodiment makes it possible to form via holes with high precision.

[0064] This embodiment is not limited to a configuration in which via holes are formed above the contact holes formed in the first film. For example, it may be applied to the manufacturing method described in Figure 5, in which case via holes are formed above the contact holes formed in the insulating layer.

[0065] <Fourth Embodiment> This embodiment describes application examples using semiconductor devices manufactured by the manufacturing methods of the first to third embodiments. Let the semiconductor device 910 be, for example, a CMOS image sensor.

[0066] Figure 7(a) is a schematic diagram illustrating an application example, device 9191. Device 9191 has a semiconductor device 930. The semiconductor device 930 includes a semiconductor device 910 and a package 920 that houses the semiconductor device 910. The semiconductor device 910 may be manufactured by a manufacturing method of another embodiment. The package 920 may include a substrate on which the semiconductor device 910 is fixed and a lid, such as glass, facing the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the substrate and terminals provided on the semiconductor device 910.

[0067] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, shutter, or mirror, and includes an optical system that directs light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0068] The processing unit 960 processes the signals output from the semiconductor device 930. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0069] The mechanical device 990 has movable parts or propulsion parts such as motors and engines. The device 9191 displays signals output from the semiconductor device 930 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, it is preferable that the device 9191 further includes a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the semiconductor device 930. The mechanical device 990 may be controlled based on signals output from the semiconductor device 930.

[0070] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the semiconductor device 930 for vibration damping.

[0071] Furthermore, the device 9191 may be a transport device such as a vehicle, ship, or aircraft. The mechanical device 990 in the transport device may be used as a mobile device. The device 9191 as a transport device is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (operation) through its imaging function. The processing device 960 for assisting and / or automating driving (operation) can perform processing to operate the mechanical device 990 as a mobile device based on information obtained from the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring instrument such as a distance sensor, an analytical instrument such as an electron microscope, an office machine such as a copier, or an industrial machine such as a robot.

[0072] According to the embodiments described above, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. Increasing value here means at least one of the following: addition of functions, improvement of performance, improvement of characteristics, improvement of reliability, improvement of manufacturing yield, reduction of environmental impact, cost reduction, miniaturization, and weight reduction.

[0073] Therefore, by using the semiconductor device 930 according to this embodiment in the device 9191, the value of the device can also be improved. For example, by mounting the semiconductor device 930 on a transport device, excellent performance can be obtained when taking external images of the transport device or measuring the external environment. Therefore, when manufacturing and selling transport devices, deciding to mount the semiconductor device according to this embodiment on the transport device is advantageous in improving the performance of the transport device itself. In particular, the semiconductor device 930 is suitable for transport devices that use information obtained from the semiconductor device to assist in driving and / or perform automated driving.

[0074] Next, as another application example, we will describe a mobile device. Figure 7(b) shows an example of a photoelectric conversion system for an in-vehicle camera. The photoelectric conversion system 80 has a semiconductor device 800. The semiconductor device 800 is, for example, a photoelectric conversion device (imaging device). The photoelectric conversion system 80 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the semiconductor device 800, and a parallax acquisition unit 802 that calculates parallax (phase difference of parallax image) from the plurality of image data acquired by the photoelectric conversion system 80. Here, the photoelectric conversion system 80 may include an optical system (not shown) that guides light to the semiconductor device 800, such as a lens, shutter, or mirror. Also, a plurality of photoelectric conversion units that are substantially conjugate to the pupil of the optical system may be arranged in pixels of the semiconductor device 800. For example, a plurality of photoelectric conversion units substantially conjugate to the pupil may be arranged corresponding to one microlens. Multiple photoelectric conversion units receive light beams that have passed through different positions in the pupil of the optical system, and the semiconductor device 800 outputs image data corresponding to the light beams that have passed through different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The photoelectric conversion system 80 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 804 may use any of this distance information to determine the possibility of collision. Note that the distance information may be acquired by ToF (Time of Flight). The distance information acquisition means may be implemented by specially designed hardware or by a software module. Furthermore, it may be implemented using FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits), or a combination thereof.

[0075] The photoelectric conversion system 80 is connected to the vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 80 is also connected to the control ECU 820, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 804. The photoelectric conversion system 80 is also connected to the warning device 830, which issues a warning to the driver based on the judgment result of the collision judgment unit 804. For example, if the collision judgment result of the collision judgment unit 804 indicates a high probability of collision, the control ECU 820 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 830 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0076] In this embodiment, the photoelectric conversion system 80 images the area around the vehicle, for example, in front of or behind it. Figure 7(c) shows the photoelectric conversion system 80 when imaging the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 80 or the semiconductor device 800. This configuration can further improve the accuracy of distance measurement.

[0077] The above example describes control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or control systems that automatically stay within their lanes. Furthermore, the photoelectric conversion system 80 can be applied not only to vehicles such as automobiles, but also to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. This mobile body mainly includes a drive force generation unit that generates the driving force used for the movement of the mobile body, and one or both of a rotating body mainly used for the movement of the mobile body. The drive force generation unit may be an engine, motor, etc. The rotating body may be a tire, wheel, ship's screw, propeller, etc. In addition, it can be applied not only to mobile bodies, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0078] The equipment of this embodiment may be transportation equipment such as vehicles, ships, or aircraft. Mechanical devices in transportation equipment can be used as mobile devices. Equipment as transportation equipment is suitable for transporting semiconductor devices or for assisting and / or automating driving (piloting) through imaging functions. The processing device for assisting and / or automating driving (piloting) can perform processing to operate the mechanical device as a mobile device based on information obtained from the semiconductor device.

[0079] In this embodiment, a photoelectric conversion device was used as an example of a semiconductor device, but other semiconductor devices may be used, or both may be used.

[0080] As described above, the present invention makes it possible to improve the accuracy of contact hole formation.

[0081] Furthermore, the disclosure of this embodiment includes the following methods.

[0082] (Method 1) A method for forming a contact hole, comprising the steps of: applying a first precursor to a substrate on which the gate electrode of a transistor is placed, such that the amount applied to the upper part of the gate electrode is less than that applied to other parts, thereby forming a first film having a flat upper surface; and patterning the first film when forming the contact hole.

[0083] (Method 2) The method for forming a contact hole according to Method 1, characterized in that, in the step of forming the first film, the upper surface of the first precursor is flattened and hardened to have a flat upper surface.

[0084] (Method 3) The method for forming a contact hole according to method 1 or 2, characterized in that the contact hole is formed in the first film.

[0085] (Method 4) A method for forming a contact hole according to any one of methods 1 to 3, further comprising the steps of: applying a second precursor to the first film on which the contact hole is formed to form a second film having a flat upper surface; and patterning the second film when forming via holes in the second film.

[0086] (Method 5) A method for forming a contact hole according to any one of methods 1 to 4, further comprising the steps of: forming a photoresist film on the first film and performing EUV exposure to form a resist pattern; and etching the first film using the resist pattern as a mask to form the contact hole in the first film.

[0087] (Method 6) The method for forming a contact hole according to any one of methods 1 to 5, characterized in that the EUV exposure has a numerical aperture NA greater than 0.55.

[0088] (Method 7) A method for forming a contact hole according to any one of methods 1 to 6, further comprising the step of forming an insulating layer on the substrate, wherein in the step of forming the first film, the first film is formed on the insulating layer.

[0089] (Method 8) The method for forming a contact hole according to any one of methods 1 to 7, characterized in that the contact hole is formed in the insulating layer.

[0090] (Method 9) A method for forming a contact hole according to any one of methods 1 to 8, further comprising the steps of: applying a second precursor to the insulating layer on which the contact hole is formed to form a second film having a flat upper surface; and patterning the second film when forming via holes in the second film.

[0091] (Method 10) A method for forming a contact hole according to any one of methods 1 to 9, further comprising the steps of: forming a photoresist film on the first film and performing EUV exposure to form a resist pattern; etching the first film using the resist pattern as a mask; and etching the insulating layer to form the contact hole in the insulating layer.

[0092] (Method 11) The method for forming a contact hole according to any one of methods 1 to 10, characterized in that the EUV exposure has a numerical aperture NA greater than 0.55.

[0093] (Method 12) A method for forming a contact hole according to any one of methods 1 to 11, characterized in that, in the step of forming the second film, the upper surface of the second precursor is flattened and hardened to have a flat upper surface.

[0094] (Method 13) A method for forming a contact hole according to any one of methods 1 to 12, further comprising the steps of forming a photoresist film on the second film and performing EUV exposure to form a resist pattern, and etching the second film using the resist pattern as a mask.

[0095] (Method 14) A method for forming a contact hole according to any one of methods 1 to 13, characterized in that the contact hole is formed such that the gate electrode is exposed.

[0096] (Method 15) A method for forming a contact hole according to any one of methods 1 to 14, characterized in that, in the step of forming the first film, the first precursor is applied such that the amount applied to the upper part of the gate electrode is less than the amount applied to the upper part of the region between the plurality of gate electrodes.

[0097] (Method 16) A method for manufacturing a semiconductor device, comprising the steps of: applying a first precursor to a substrate on which the gate electrode of a transistor is arranged, such that the amount applied to the upper part of the gate electrode is less than that applied to other parts, thereby forming a first film having a flat upper surface; and forming contact holes by patterning the first film.

[0098] (Method 17) A method for manufacturing a semiconductor device according to method 16, characterized in that, in the step of forming the first film, the upper surface of the first precursor is flattened and cured to have a flat upper surface.

[0099] (Method 18) A method for manufacturing a semiconductor device according to method 16 or 17, characterized in that the contact holes are formed in the first film.

[0100] (Method 19) A method for manufacturing a semiconductor device according to any one of the methods 16 to 18, further comprising the step of forming an insulating layer on the substrate, wherein in the step of forming the first film, the first film is formed on the insulating layer.

[0101] (Method 20) A method for manufacturing a semiconductor device according to any one of methods 16 to 19, characterized in that the contact holes are formed in the insulating layer. [Explanation of Symbols]

[0102] 301 Semiconductor substrate 303 Post Office 305 First membrane 309 Contact Hole

Claims

1. In a method for forming contact holes, A step of forming a first film having a flat top surface by applying a first precursor to a substrate on which the gate electrode of a transistor is arranged, such that the amount applied to the upper part of the gate electrode is less than that applied to other parts, A method for forming a contact hole, characterized by comprising the step of patterning the first film when forming the contact hole.

2. The method for forming a contact hole according to claim 1, characterized in that, in the step of forming the first film, the upper surface of the first precursor is flattened and hardened to have a flat upper surface.

3. The method for forming a contact hole according to claim 1, characterized in that the contact hole is formed in the first film.

4. The steps include applying a second precursor onto the first film on which the contact holes are formed to form a second film having a flat upper surface, The method for forming a contact hole according to claim 3, further comprising the step of patterning the second film when forming a via hole in the second film.

5. The process involves forming a photoresist film on the first film and performing EUV exposure to form a resist pattern. The method for forming a contact hole according to claim 3, further comprising the steps of etching the first film using the resist pattern as a mask to form the contact hole in the first film.

6. The method for forming a contact hole according to claim 5, characterized in that the EUV exposure has a numerical aperture (NA) greater than 0.

55.

7. The process further includes the step of forming an insulating layer on the substrate, The method for forming a contact hole according to claim 1, characterized in that the first film is formed on the insulating layer in the step of forming the first film.

8. The method for forming a contact hole according to claim 7, characterized in that the contact hole is formed in the insulating layer.

9. The steps include: applying a second precursor onto the insulating layer on which the contact holes are formed to form a second film having a flat upper surface; The method for forming a contact hole according to claim 8, further comprising the step of patterning the second film when forming a via hole in the second film.

10. The process involves forming a photoresist film on the first film and performing EUV exposure to form a resist pattern. A step of etching the first film using the resist pattern as a mask, The method for forming a contact hole according to claim 8, further comprising the step of etching the insulating layer to form the contact hole in the insulating layer.

11. The method for forming a contact hole according to claim 10, characterized in that the EUV exposure has a numerical aperture NA greater than 0.

55.

12. The method for forming a contact hole according to claim 4 or 9, characterized in that, in the step of forming the second film, the upper surface of the second precursor is flattened and cured to have a flat upper surface.

13. The process involves forming a photoresist film on the second film and performing EUV exposure to form a resist pattern. The method for forming a contact hole according to claim 4 or 9, further comprising the step of etching the second film using the resist pattern as a mask.

14. The method for forming a contact hole according to claim 1, characterized in that the contact hole is formed such that the gate electrode is exposed.

15. The method for forming a contact hole according to claim 1, characterized in that, in the step of forming the first film, the first precursor is applied such that the amount applied to the upper part of the gate electrode is less than the amount applied to the upper part of the region between the plurality of gate electrodes.

16. A step of forming a first film having a flat top surface by applying a first precursor to a substrate on which the gate electrode of a transistor is arranged, such that the amount applied to the upper part of the gate electrode is less than that applied to other parts, A method for manufacturing a semiconductor device, comprising the step of forming contact holes by patterning the first film.

17. The method for manufacturing a semiconductor device according to claim 16, characterized in that, in the step of forming the first film, the upper surface of the first precursor is flattened and cured to have a flat upper surface.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, characterized in that the contact holes are formed in the first film.

19. The process further includes the step of forming an insulating layer on the substrate, A method for manufacturing a semiconductor device according to claim 16 or 17, characterized in that the first film is formed on the insulating layer in the step of forming the first film.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that the contact holes are formed in the insulating layer.

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