Semiconductor devices, inverter circuits, drive systems, vehicles, and elevators.

Abstract

Provide a semiconductor device in which the amount of harmful defects in the gate insulating layer is reduced. 【Solution means】The semiconductor device of the embodiment includes a silicon carbide layer, a gate electrode, and a silicon oxide layer provided between the silicon carbide layer and the gate electrode, which contains one element selected from the group consisting of hydrogen, deuterium, and fluorine, boron, and carbon, and is provided between the silicon carbide layer and the silicon oxide layer. The concentration of boron is 1×10 20 cm -3 or more, and includes a region where the concentration distribution of boron in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region. The first concentration of boron at a first position 5 nm away from the peak toward the silicon oxide layer side is 1×10 18 cm -3 or more, the second concentration of carbon at the first position is 1×10 18 cm -3 or more, the third concentration of the element at the first position is 1×10 18 cm -3 or more, the second concentration is 80% or more and 120% or less of the first concentration, and the third concentration is 80% or more and 120% or less of the first concentration.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices, inverter circuits, drive devices, vehicles, and elevators. [Background technology]

[0002] Silicon carbide (SiC) is a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has superior physical properties, with a band gap approximately three times larger, a breakdown field strength approximately ten times greater, and a thermal conductivity approximately three times greater. By utilizing these properties, it is possible to realize semiconductor devices that are low-loss and capable of high-temperature operation.

[0003] For example, when forming a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) using silicon carbide, problems arise such as a decrease in carrier mobility and fluctuations in the threshold voltage. One factor causing the decrease in carrier mobility and fluctuations in the threshold voltage is thought to be harmful defects present in the gate insulating layer. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] D. Okamoto et al. “Improved Channel Mobility in 4H-SiC MOSFETs by Boron Passivation”, IEEE ELECTRON DEVICE LETTERS, VOL.35, No.12 (2014). [Overview of the project] [Problems that the invention aims to solve]

[0005] The problem that this invention aims to solve is to provide a semiconductor device in which the amount of harmful defects in the gate insulating layer is reduced. [Means for solving the problem]

[0006] The semiconductor device of the embodiment includes a silicon carbide layer, a gate electrode, a silicon oxide layer provided between the silicon carbide layer and the gate electrode, containing one element selected from the group consisting of hydrogen (H), deuterium (D), and fluorine (F), boron (B), and carbon (C), and a boron concentration of 1 × 10⁻¹⁶ between the silicon carbide layer and the silicon oxide layer. 20 cm -3 The above region is provided, and the concentration distribution of boron in the silicon carbide layer, the silicon oxide layer, and the region has a first peak in the region, and the first concentration of boron at a first position 5 nm away from the first peak on the side of the silicon oxide layer is 1 × 10⁻¹⁰ 18 cm -3 Thus, the second concentration of carbon at the first position is 1 × 10⁻⁶ 18 cm -3 The above is true, and the third concentration of the element at the first position is 1 × 10⁻⁶ 18 cm -3 The above conditions apply, where the second concentration is 80% to 120% of the first concentration, and the third concentration is 80% to 120% of the first concentration. [Brief explanation of the drawing]

[0007] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A diagram showing the crystal structure of a SiC semiconductor. [Figure 3] A diagram showing the elemental concentration distribution of the semiconductor device according to the first embodiment. [Figure 4] A schematic diagram showing the bonding state of boron atoms in the semiconductor device of the first embodiment. [Figure 5] Diagram illustrating the gate insulating layer of a semiconductor device according to the first embodiment. [Figure 6] Diagram illustrating the gate insulating layer of a semiconductor device according to the first embodiment. [Figure 7] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 8]Explanation diagram of the operation and effects of the semiconductor device according to the first embodiment. [Figure 9] Explanation diagram of the operation and effects of the semiconductor device according to the first embodiment. [Figure 10] Diagram showing the element concentration distribution of the semiconductor device according to the modified example of the first embodiment. [Figure 11] Schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 12] Diagram showing the element concentration distribution of the semiconductor device according to the second embodiment. [Figure 13] Schematic diagram of the drive device according to the third embodiment. [Figure 14] Schematic diagram of the vehicle according to the fourth embodiment. [Figure 15] Schematic diagram of the vehicle according to the fifth embodiment. [Figure 16] Schematic diagram of the elevator according to the sixth embodiment.

Embodiments for Carrying Out the Invention

[0008] [[ID=P31]] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0009] Also, in the following description, when there is notation of n + , n, n - and, p + , p, p - , it represents the relative high and low of the impurity concentration in each conductivity type. That is, n + indicates that the n-type impurity concentration is relatively higher than that of n, and n - indicates that the n-type impurity concentration is relatively lower than that of n. Also, p + indicates that the p-type impurity concentration is relatively higher than that of p, and p - indicates that the p-type impurity concentration is relatively lower than that of p. Note that the n + type and n - type are simply referred to as the n-type, and the p + type and p -The type is sometimes simply referred to as p-type. Unless otherwise specified, the impurity concentration in each region is represented by, for example, the value of the impurity concentration in the central part of each region.

[0010] Impurity concentrations can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Furthermore, the relative levels of impurity concentrations can be determined, for example, from the carrier concentrations obtained by Scanning Capacitance Microscopy (SCM). Additionally, the width and depth of impurity regions can be determined, for example, by SIMS. Furthermore, the width and depth of impurity regions can be determined, for example, from SCM images.

[0011] The concentrations of silicon atoms, carbon atoms, boron atoms, oxygen atoms, hydrogen atoms, deuterium atoms, or fluorine atoms in the silicon carbide layer or gate insulating layer can be measured by SIMS.

[0012] In this specification, impurity concentrations and the concentrations of each element are expressed in terms of atomic concentrations.

[0013] The depth of the trench, the thickness of the insulating layer, etc., can be measured, for example, on images from SIMS or a Transmission Electron Microscope (TEM).

[0014] The bonding states of silicon atoms, carbon atoms, boron atoms, oxygen atoms, hydrogen atoms, deuterium, or fluorine atoms in the silicon carbide layer or gate insulating layer can be identified, for example, by using X-ray photoelectron spectroscopy (XPS) or Fourier transform infrared spectroscopy (FT-IR). Furthermore, the concentrations of each bonding state and their relative magnitudes can be determined, for example, by using X-ray photoelectron spectroscopy or Fourier transform infrared spectroscopy.

[0015] (First embodiment) The semiconductor device of the first embodiment comprises a silicon carbide layer, a gate electrode, a silicon oxide layer provided between the silicon carbide layer and the gate electrode and containing one element selected from the group consisting of hydrogen (H), deuterium (D), and fluorine (F), boron (B), and carbon (C), and a boron concentration of 1 × 10⁻¹⁶ between the silicon carbide layer and the silicon oxide layer. 20 cm -3 The above region comprises a silicon carbide layer, a silicon oxide layer, and a boron concentration distribution within the region, with a first peak in the region, and the first boron concentration at a first position 5 nm away from the first peak on the silicon oxide layer side is 1 × 10⁻⁶ 18 cm -3 Therefore, the second concentration of carbon at the first position is 1 × 10⁻⁶ 18 cm -3 Therefore, the third concentration of the element at the first position is 1 × 10⁻⁶ 18 cm -3 The above conditions apply, with the second concentration being between 80% and 120% of the first concentration, and the third concentration being between 80% and 120% of the first concentration.

[0016] Figure 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. The semiconductor device is a MOSFET 100. The MOSFET 100 is a Double Implantation MOSFET (DIMOSFET) in which the p-well and source region are formed by ion implantation. The MOSFET 100 is also an n-channel type MOSFET that uses electrons as carriers.

[0017] The MOSFET 100 comprises a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40 (region).

[0018] The silicon carbide layer 10 comprises a drain region 12, a drift region 14, a p-well region 16, a source region 18, and a p-well contact region 20.

[0019] The silicon carbide layer 10 is, for example, a single crystal of 4H-SiC. The silicon carbide layer 10 is located between the source electrode 34 and the drain electrode 36.

[0020] Figure 2 shows the crystal structure of a SiC semiconductor. A typical crystal structure of a SiC semiconductor is a hexagonal system, such as 4H-SiC. One of the planes (vertical faces of the hexagonal prism) whose normal axis is the c-axis along the axial direction of the hexagonal prism is the (0001) plane. The plane equivalent to the (0001) plane is called the silicon plane (Si plane) and is denoted as the {0001} plane. Silicon atoms (Si) are arranged on the outermost surface of the silicon plane.

[0021] The other plane (the vertex face of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (000-1) plane. The plane equivalent to the (000-1) plane is called the carbon plane (C plane) and is denoted as the {000-1} plane. Carbon atoms (C) are arranged on the outermost surface of the carbon plane.

[0022] On the other hand, the side faces (prismatic faces) of the hexagonal prism are the m faces, or {1-100} faces, which are equivalent to the (1-100) faces. Also, the faces passing through a pair of non-adjacent edges are the a faces, or {11-20} faces, which are equivalent to the (11-20) faces. Both silicon atoms (Si) and carbon atoms (C) are arranged on the outermost surfaces of the m faces and a faces.

[0023] The following explanation will use the example where the surface of the silicon carbide layer 10 is inclined at an angle of 0 to 8 degrees relative to the silicon surface, and the back surface is inclined at an angle of 0 to 8 degrees relative to the carbon surface. The surface of the silicon carbide layer 10 has an off-angle of 0 to 8 degrees relative to the silicon surface.

[0024] The drain region 12 is n + This is a type of SiC. The drain region 12 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 12 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0025] The drift region 14 is located above the drain region 12. The drift region 14 is n - It is a type of SiC. The drift region 14 contains, for example, nitrogen as an n-type impurity.

[0026] The n-type impurity concentration in the drift region 14 is lower than the n-type impurity concentration in the drain region 12. The n-type impurity concentration in the drift region 14 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 2 x 10 16 cm -3 The following applies: The drift region 14 is, for example, an epitaxial growth layer of SiC formed by epitaxial growth on the drain region 12.

[0027] The thickness of the drift region 14 is, for example, between 5 μm and 100 μm.

[0028] The p-well region 16 is provided on a portion of the surface of the drift region 14. The p-well region 16 is p-type SiC. The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the p-well region 16 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 20 cm -3 The following applies:

[0029] The depth of the p-well region 16 is, for example, between 0.4 μm and 0.8 μm. The p-well region 16 functions as the channel region of the MOSFET 100.

[0030] The source region 18 is provided on a part of the surface of the p-well region 16. The source region 18 is n + This is a type of SiC. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration in the source region 18 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 It is less than or equal to cm.

[0031] The depth of the source region 18 is shallower than the depth of the p-well region 16. For example, the depth of the source region 18 is between 0.2 μm and 0.4 μm.

[0032] The p-well contact region 20 is provided on a part of the surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is p + It is a type of SiC.

[0033] The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The concentration of p-type impurities in the p-well contact region 20 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 22 cm -3 The following applies:

[0034] The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. For example, the depth of the p-well contact region 20 is between 0.2 μm and 0.4 μm.

[0035] The gate insulating layer 28 is provided between the silicon carbide layer 10 and the gate electrode 30. The gate insulating layer 28 is provided between the drift region 14 and the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided on top of the drift region 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift region 14 and the p-well region 16.

[0036] The gate insulating layer 28 is silicon oxide. For example, the gate insulating layer 28 is silicon dioxide. The gate insulating layer 28 is an example of a silicon oxide layer.

[0037] The gate insulating layer 28 contains one element selected from the group consisting of hydrogen (H), deuterium (D), and fluorine (F), as well as boron (B) and carbon (C). Below, we will explain using hydrogen (H) as one of the elements.

[0038] The thickness of the gate insulating layer 28 is, for example, 30 nm to 100 nm. The gate insulating layer 28 functions as the gate insulating layer of the MOSFET 100. The thickness of the gate insulating layer 28 is, for example, 40 nm to 50 nm.

[0039] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the p-well region 16 and the gate insulating layer 28. The interface termination region 40 contains boron (B) as a termination element that terminates the dangling bond of the silicon carbide layer 10. The interface termination region 40 is an example of a region.

[0040] The boron concentration in the interface termination region 40 is 1 × 10⁻⁶ 20 cm -3 That's all.

[0041] Figure 3 shows the elemental concentration distribution of the semiconductor device according to the first embodiment. Figure 3 shows the elemental concentration distribution in the gate insulating layer 28, the interface termination region 40, and the silicon carbide layer 10.

[0042] Figure 3 shows the concentration distributions of boron (B), carbon (C), and hydrogen (H). In Figure 3, the solid line shows the concentration distribution of boron, the dotted line shows the concentration distribution of carbon, and the dashed line shows the concentration distribution of hydrogen.

[0043] The boron concentration distribution has a first peak in the interface termination region 40. The boron concentration at the first peak is, for example, 1 × 10⁻⁶ 20 cm -3 The above 1 x 10 22 cm -3 The following applies: The full width at half maximum for the first peak of the boron concentration distribution is, for example, less than 1 nm. Boron is segregated at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0044] The hydrogen concentration in the interface termination region 40 is, for example, lower than the boron concentration in the interface termination region 40. 20 cm -3 The following applies:

[0045] Figure 4 is a schematic diagram showing the bonding state of boron atoms in the semiconductor device of the first embodiment. Figure 4 shows the bonding state of boron atoms in the interface termination region 40. Figure 4 shows the case where a boron atom is bonded to three carbon atoms.

[0046] The interface termination region 40 contains a three-coordinate boron atom. The interface termination region 40 contains a boron atom bonded to three carbon atoms.

[0047] The three-coordinate boron atoms present in the interface termination region 40 terminate the dangling bonds on the surface of the silicon carbide layer 10. The boron atoms replace the silicon atoms on the outermost surface of the silicon carbide layer 10.

[0048] As shown in Figure 3, for example, the first boron concentration (C1 in Figure 3) at a first position 5 nm away from the first peak of the boron concentration distribution on the gate insulating layer 28 side is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies. Also, for example, the second concentration of carbon at the first position (C2 in Figure 3) is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies. Also, for example, the third concentration of hydrogen at the first position (C3 in Figure 3) is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0049] For example, the first concentration C1 is 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 20 cm -3 The following is true, and the second concentration C2 is 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 20 cm -3 The following applies, and the third concentration C3 is 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 20cm -3 is as follows.

[0050] The second concentration C2 is 80% or more and 120% or less of the first concentration C1. Also, the third concentration C3 is 80% or more and 120% or less of the first concentration C1.

[0051] For example, the second concentration C2 is 90% or more and 110% or less of the first concentration C1. Also, for example, the third concentration C3 is 90% or more and 110% or less of the first concentration C1.

[0052] As shown in FIG. 3, for example, the fourth concentration of boron (C4 in FIG. 3) at the second position 15 nm away from the first peak of the boron concentration distribution toward the gate insulating layer 28 is 1×10 17 cm -3 or more and 1×10 20 cm -3 or less. Also, for example, the fifth concentration of carbon (C5 in FIG. 3) at the second position is 1×10 17 cm -3 or more and 1×10 20 cm -3 or less. Also, for example, the sixth concentration of hydrogen (C6 in FIG. 3) at the second position is 1×10 17 cm -3 or more and 1×10<00​​​​​​​​​​​​​​The semiconductor device manufacturing method of the first embodiment, described later, allows for good matching of the concentration distributions of boron, carbon, and hydrogen. If precise concentration measurements below the measurement limit of SIMS are required, it is effective to use methods such as HAXPES measurement (Hard X-ray photoelectron spectroscopy).

[0056] Figure 5 is an explanatory diagram of the gate insulating layer of the semiconductor device according to the first embodiment. Figure 5 shows a composite composed of carbon atoms, oxygen atoms, boron atoms, and hydrogen atoms contained in the gate insulating layer 28. Hereinafter, the composite composed of carbon atoms, oxygen atoms, boron atoms, and hydrogen atoms shown in Figure 5 will be referred to as the COBH composite.

[0057] As shown in Figure 5, in the COBH complex, carbon atoms, oxygen atoms, boron atoms, and hydrogen atoms are in close proximity within the silicon oxide, forming a complex. In the COBH complex, carbon atoms are bonded to oxygen atoms, boron atoms to oxygen atoms, and boron atoms to hydrogen atoms.

[0058] In the COBH complex, carbon atoms and boron atoms each substitute for silicon atoms in silicon oxide. In other words, in the COBH complex, carbon atoms and boron atoms each reside at the silicon sites of silicon dioxide. In the COBH complex, an oxygen atom is present between the carbon atom and the boron atom. The oxygen atom between the carbon atom and the boron atom is not covalently bonded to the boron atom. The carbon atom and oxygen atom, the boron atom and oxygen atom, and the boron atom and hydrogen atom are each bonded by single bonds. The carbon atoms constituting the COBH complex are 4-coordinate. The boron atoms constituting the COBH complex are 4-coordinate.

[0059] In COBH complexes, for example, four-coordinate carbon atoms are positively charged. Also, in COBH complexes, for example, four-coordinate boron atoms are negatively charged.

[0060] The gate insulating layer 28 contains a COBH composite, and therefore contains boron atoms bonded to three oxygen atoms and one hydrogen atom.

[0061] For example, most of the carbon atoms, boron atoms, and hydrogen atoms located in a region more than 5 nm away from the peak of the boron concentration distribution on the gate insulating layer 28 side constitute the COBH composite. Therefore, as shown in Figure 3, for example, the distributions of carbon atoms, boron atoms, and hydrogen atoms overlap in the region more than 5 nm away from the peak of the boron concentration distribution on the gate insulating layer 28 side.

[0062] For example, the amount of COBH composite in the gate insulating layer 28 decreases as you move away from the peak of the boron concentration distribution. Therefore, as shown in Figure 3, the concentrations of carbon, boron, and hydrogen in the gate insulating layer 28 decrease as you move away from the peak of the boron concentration distribution.

[0063] Furthermore, since most of the hydrogen atoms in the gate insulating layer 28 constitute the COBH composite, the amount of hydrogen atoms that bond with boron atoms in the gate insulating layer 28 is greater than the amount of hydrogen atoms that bond with silicon atoms.

[0064] Figure 6 is an explanatory diagram of the gate insulating layer of the semiconductor device according to the first embodiment. Figure 6 shows a composite composed of carbon atoms, oxygen atoms, and boron atoms that may be included in the gate insulating layer 28. Hereinafter, the composite composed of carbon atoms, oxygen atoms, and boron atoms shown in Figure 6 will be referred to as the COB composite. Note that the COB composite may not be included in the gate insulating layer 28.

[0065] As shown in Figure 6, in the COB composite, carbon atoms, oxygen atoms, and boron atoms are in close proximity within the silicon oxide, forming a complex. In the COB composite, carbon atoms are bonded to oxygen atoms, and oxygen atoms are bonded to boron atoms.

[0066] In COB complexes, carbon atoms and boron atoms each substitute for silicon atoms in silicon oxide. In other words, in COB complexes, carbon atoms and boron atoms each reside at the silicon sites of silicon dioxide. In COB complexes, oxygen atoms are present between carbon atoms and boron atoms. Carbon atoms and oxygen atoms, and oxygen atoms and boron atoms, are bonded by single bonds. The carbon atoms constituting the COB complex are 4-coordinate. The boron atoms constituting the COB complex are 4-coordinate. The boron atoms constituting the COB complex are bonded to 4 oxygen atoms.

[0067] In COB complexes, for example, four-coordinate carbon atoms are uncharged. Similarly, in COB complexes, for example, four-coordinate boron atoms are uncharged.

[0068] If the gate insulating layer 28 contains a COB composite, the amount of COBH composite in the gate insulating layer 28 is greater than the amount of COB composite. Therefore, the amount of boron atoms bonded to 3 oxygen atoms and 1 hydrogen atom in the gate insulating layer 28 is greater than the amount of boron atoms bonded to 4 oxygen atoms. The amount of boron atoms bonded to 3 oxygen atoms and 1 hydrogen atom in the gate insulating layer 28 is, for example, 10 times or more the amount of boron atoms bonded to 4 oxygen atoms.

[0069] The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 has the gate insulating layer 28 sandwiched between it and the silicon carbide layer 10. The gate electrode 30 has the gate insulating layer 28 sandwiched between it and the drift region 14. The gate electrode 30 has the gate insulating layer 28 sandwiched between it and the p-well region 16.

[0070] The gate electrode 30 is, for example, polycrystalline silicon containing n-type or p-type impurities.

[0071] The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0072] The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16.

[0073] The source electrode 34 is composed of, for example, a stack of a barrier metal layer of Ni (nickel) and a metal layer of aluminum on the barrier metal layer. The barrier metal layer of nickel and the silicon carbide layer may react to form nickel silicide (such as NiSi, Ni2Si). The barrier metal layer of nickel and the metal layer of aluminum may react to form an alloy.

[0074] The drain electrode 36 is provided on the side opposite to the source electrode 34 of the silicon carbide layer 10, that is, on the back side. The drain electrode 36 is, for example, nickel. Nickel may react with the drain region 12 to form nickel silicide (such as NiSi, Ni2Si).

[0075] In the first embodiment, the n-type impurity is, for example, nitrogen or phosphorus. It is also possible to apply arsenic (As) or antimony (Sb) as the n-type impurity.

[0076] Also, in the first embodiment, the p-type impurity is, for example, aluminum. It is also possible to apply boron (B), gallium (Ga), or indium (In) as the p-type impurity. <�

[0077] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0078] [[ID=2}} First, the silicon carbide layer 10 is prepared. The silicon carbide layer 10 includes an n- + type drain region 12 and an n- - type drift region 14. The drift region 14 is formed, for example, by epitaxial growth on the drain region 12.

[0079] [[ID=}}{ The drain region 12 contains nitrogen as an n-type impurity. The concentration of n-type impurities in the drain region 12 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0080] The drift region 14 contains nitrogen as an n-type impurity. The concentration of n-type impurities in the drift region 14 is, for example, 1 × 10⁻⁶. 15 cm -3 The above 2 x 10 16 cm -3 The following applies: The thickness of the drift region 14 is, for example, between 5 μm and 100 μm.

[0081] First, a first mask material is formed by patterning using photolithography and etching. Then, using the first mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14. The p-well region 16 is formed by ion implantation.

[0082] Next, a second mask material is formed by patterning using photolithography and etching. Then, using the second mask material as an ion implantation mask, phosphorus, an n-type impurity, is ion-implanted into the drift region 14 to form the source region 18.

[0083] Next, a third mask material is formed by patterning using photolithography and etching. Using the third mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14 to form the p-well contact region 20.

[0084] Next, a polycrystalline silicon film containing boron is formed on the silicon carbide layer 10. The thickness of the polycrystalline silicon film is, for example, between 5 nm and 50 nm.

[0085] Polycrystalline silicon films are formed, for example, by vapor phase growth. Polycrystalline silicon films are formed, for example, by the Chemical Vapor Deposition (CVD) method.

[0086] Next, a first heat treatment is performed. The first heat treatment is carried out in an oxidizing atmosphere. For example, oxygen gas (O2) diluted with nitrogen gas (N2) is supplied to a reactor containing the silicon carbide layer 10 to perform the heat treatment. The temperature of the first heat treatment is between 900°C and 1300°C.

[0087] The first heat treatment oxidizes the polycrystalline silicon film, forming a silicon oxide film containing boron. The thickness of the silicon oxide film containing boron is, for example, between 10 nm and 100 nm. The silicon oxide film containing boron becomes the gate insulating layer 28.

[0088] The first heat treatment forms an interface termination region 40 at the interface between the silicon carbide layer 10 and the silicon oxide film.

[0089] The first heat treatment oxidizes the surface of the silicon carbide layer 10, and the excess carbon diffuses into the silicon oxide film.

[0090] Next, a second heat treatment is performed. The second heat treatment is carried out in an atmosphere containing 20% ​​to 60% hydrogen gas (H2). The hydrogen gas (H2) is diluted with, for example, nitrogen gas (N2) or argon gas (Ar).

[0091] For example, a reaction furnace containing a silicon carbide layer 10 is subjected to heat treatment by supplying hydrogen gas (H2) diluted with nitrogen gas (N2). The temperature of the second heat treatment is between 600°C and 900°C.

[0092] The second heat treatment process forms a COBH composite within the boron-containing silicon oxide film.

[0093] Next, a gate electrode 30 is formed on the gate insulating layer 28. The gate electrode 30 is, for example, polycrystalline silicon containing n-type or p-type impurities.

[0094] Furthermore, after the second heat treatment and before forming the gate electrode 30, a silicon oxide film may be formed on the gate insulating layer 28 by CVD, for example.

[0095] Next, an interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0096] Next, the source electrode 34 is formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed, for example, by sputtering nickel (Ni) and aluminum (Al).

[0097] Next, the drain electrode 36 is formed. The drain electrode 36 is formed on the back side of the silicon carbide layer 10. The drain electrode 36 is formed, for example, by nickel sputtering.

[0098] The MOSFET 100 shown in Figure 1 is manufactured using the above manufacturing method.

[0099] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0100] When forming a MOSFET using silicon carbide, there is a problem of reduced carrier mobility. One factor contributing to this reduced carrier mobility is thought to be the interface state between the silicon carbide layer and the gate insulating layer. This interface state is thought to be caused by dangling bonds present on the surface of the silicon carbide layer.

[0101] The MOSFET 100 of the first embodiment includes an interface termination region 40 in which boron is segregated between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 reduces dangling bonds. Therefore, a MOSFET 100 is realized in which the decrease in carrier mobility is suppressed.

[0102] Furthermore, when silicon carbide is used to form MOSFETs, problems arise such as a decrease in carrier mobility and fluctuations in the threshold voltage. Additionally, problems such as increased leakage current in the gate insulating layer and reduced reliability of the gate insulating layer are also present. One factor contributing to these problems is believed to be the presence of harmful defects within the gate insulating layer.

[0103] The harmful defects present in the gate insulating layer are thought to be, for example, oxygen vacancies in silicon oxide or defects caused by carbon contained in silicon oxide. These defects in the gate insulating layer are thought to cause the above-mentioned problems by forming trap levels within the gate insulating layer.

[0104] In the first embodiment, the MOSFET 100 has a reduced amount of harmful defects in the gate insulating layer 28. Therefore, a decrease in carrier mobility, fluctuations in threshold voltage, an increase in leakage current of the gate insulating layer, or a decrease in the reliability of the gate insulating layer, all caused by harmful defects, are suppressed. These will be described in detail below.

[0105] Figures 7(a), 7(b), and 7(c) are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. Figures 7(a), 7(b), and 7(c) are band diagrams of silicon dioxide. Figures 7(a), 7(b), and 7(c) each show the upper valence band (VBE) and lower conduction band (CBE) of silicon dioxide.

[0106] Figure 7(a) shows the case where carbon defects are present in the gate insulating layer of silicon dioxide, Figure 7(b) shows the case where a COB composite is present in the gate insulating layer of silicon dioxide, and Figure 7(c) shows the case where a COBH composite is present in the gate insulating layer of silicon dioxide.

[0107] Numerous carbon defects are formed in the gate insulating layer due to carbon released into the gate insulating layer as the silicon carbide layer is oxidized. As shown in Figure 7(a), the presence of carbon defects in the gate insulating layer creates a trap state within the gate insulating layer. Carbon defects include, for example, double-bonded carbon atoms or carbon atoms double-bonded to oxygen atoms.

[0108] When boron (B) is included in the gate insulating layer, carbon released into the gate insulating layer combines with boron to form a COB composite. Therefore, the formation of carbon defects in the gate insulating layer is suppressed. By suppressing the formation of carbon defects, the deterioration of the reliability of the gate insulating layer is suppressed.

[0109] However, when a COB composite is formed, for example, fluctuations in the threshold voltage when AC stress is applied to the gate insulating layer, and negative bias temperature instability (NBTI) may occur.

[0110] As shown in Figure 7(b), when a COB composite is formed, a trap level is formed near the upper valence band (VBE). It is thought that holes are trapped in the trap level near the upper valence band, causing fluctuations in the threshold voltage during AC stress and resulting in NBTI.

[0111] In the first embodiment, the MOSFET 100 includes a COBH composite in its gate insulating layer. As shown in Figure 7(c), no trap levels are formed within the gate insulating layer in the COBH composite. In the first embodiment, the COB composite in the gate insulating layer is converted to a COBH composite. Therefore, in the MOSFET 100, fluctuations in the threshold voltage and NBTI during AC stress are suppressed. Thus, the reliability of the MOSFET 100 is improved.

[0112] Figure 8 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 8 is a diagram showing the transient structure when the COB composite is converted to a COBH composite.

[0113] When hydrogen gas is introduced into the gate insulating layer containing the COB complex shown in Figure 6, the carbon atoms transiently form double bonds with oxygen atoms, the boron atoms become 3-coordinate, and a state is formed in which hydrogen atoms exist between the lattice, as shown in Figure 8. Subsequently, the COBH complex shown in Figure 5 is formed, which is energetically more stable than the structure in Figure 8.

[0114] Figures 9(a), 9(b), and 9(c) are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. Figures 9(a), 9(b), and 9(c) are band diagrams of silicon dioxide. Figures 9(a), 9(b), and 9(c) show the upper valence band (VBE) and lower conduction band (CBE) of silicon dioxide, respectively. Figures 9(a), 9(b), and 9(c) are explanatory diagrams illustrating the state change when a COB composite is converted to a COBH composite.

[0115] Figures 9(a), 9(b), and 9(c) are based on the inventor's first-principles calculations.

[0116] When hydrogen gas is introduced into the gate insulating layer containing the COB composite shown in Figure 9(a), the carbon atoms transiently form double bonds with oxygen atoms, the boron atoms become 3-coordinate, and a state is formed where hydrogen atoms exist between the lattice, as shown in Figure 9(b). Electrons are supplied from the double bond between the carbon and oxygen atoms in the state shown in Figure 9(b) to the boron atoms, and the boron atoms become 4-coordinate boron atoms bonded to 3 oxygen atoms and 1 hydrogen atom, thus stabilizing. In other words, the COBH composite shown in Figure 9(c) is formed and stabilized.

[0117] In the first embodiment of the MOSFET 100, the majority of carbon atoms, boron atoms, and hydrogen atoms contained in the gate insulating layer 28 are fixed as COBH complexes, which are defects harmless to the characteristics of the MOSFET 100. In other words, the amount of carbon defects and COB complexes, which are defects harmful to the characteristics of the MOSFET 100, is extremely small in the gate insulating layer 28 of the MOSFET 100. In the MOSFET 100, by reducing the amount of harmful defects in the gate insulating layer 28, a decrease in carrier mobility and fluctuations in threshold voltage can be suppressed.

[0118] In the first embodiment, the MOSFET 100 exhibits a threshold voltage fluctuation of less than 0.1V when an AC stress of -5MV / cm to 5MV / cm is applied between the silicon carbide layer 10 and the gate electrode 30 for 100 hours at room temperature and 1MHz.

[0119] (modified version) In a modified semiconductor device of the first embodiment, the fourth concentration of boron at a second position 15 nm away from the first peak on the silicon oxide layer side is 1 × 10⁻⁶ 17 cm -3 It is less than , and the fifth concentration of carbon at the second position is 1 × 10⁻⁶. 17 cm -3 It is less than 10⁻⁶, and the sixth concentration of the element at the second position is 1 × 10⁻⁶. 17 cm -3 It differs from the semiconductor device of the first embodiment in that it is less than [a certain value].

[0120] Figure 10 shows the elemental concentration distribution of a semiconductor device of a modified example of the first embodiment. Figure 3 shows the elemental concentration distribution in the gate insulating layer 28, the interface termination region 40, and the silicon carbide layer 10.

[0121] Figure 10 shows the concentration distributions of boron (B), carbon (C), and hydrogen (H). In Figure 10, the solid line shows the concentration distribution of boron, the dotted line shows the concentration distribution of carbon, and the dashed line shows the concentration distribution of hydrogen.

[0122] As shown in Figure 10, for example, the fourth boron concentration (C4 in Figure 10) at the second position, 15 nm away from the first peak of the boron concentration distribution on the gate insulating layer 28 side, is 1 × 10⁻⁶. 17 cm -3 It is less than . Also, for example, the fifth concentration of carbon at the second position (C5 in Figure 10) is 1 × 10⁻⁶. 17 cm -3 It is less than . Also, for example, the sixth concentration of hydrogen at the second position (C6 in Figure 10) is 1 × 10⁻⁶. 17 cm -3 It is less than.

[0123] For example, in the manufacturing method of the first embodiment, by additionally forming a silicon oxide film on top of the silicon oxide film containing boron after the second heat treatment, a MOSFET having the elemental concentration distribution shown in Figure 10 can be manufactured.

[0124] As described above, according to the first embodiment and its modifications, a method for manufacturing a semiconductor device is realized that reduces the amount of harmful defects in the gate insulating layer.

[0125] (Second embodiment) The semiconductor device of the second embodiment differs from the first embodiment in that it is a trench-gate type MOSFET with a gate electrode located in a trench. Furthermore, the surface of the silicon carbide layer facing the gate electrode differs from the first embodiment in that it is inclined at an angle of 0 to 8 degrees with respect to the {1-100} plane, or at an angle of 0 to 8 degrees with respect to the {11-20} plane. Some descriptions that overlap with the first embodiment will be omitted below.

[0126] Figure 11 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a MOSFET 200. The MOSFET 200 is a trench-gate type MOSFET with a gate electrode in a trench. The MOSFET 200 is also an n-channel type MOSFET that uses electrons as carriers.

[0127] The MOSFET200 comprises a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40 (region), and a trench 50.

[0128] The silicon carbide layer 10 comprises a drain region 12, a drift region 14, a p-well region 16, a source region 18, and a p-well contact region 20.

[0129] The trench 50 penetrates the source region 18 and the p-well region 16, reaching the drift region 14. The bottom of the trench 50 is located in the drift region 14.

[0130] A gate insulating layer 28 and a gate electrode 30 are provided within the trench 50. The side surface of the trench 50 is, for example, a surface having an off-angle of 0 to 8 degrees with respect to the m-plane, or a surface having an off-angle of 0 to 8 degrees with respect to the a-plane.

[0131] On the side surface of the trench 50, the surface of the silicon carbide layer 10 facing the gate electrode 30 is, for example, a surface inclined at 0 to 8 degrees with respect to the {1-100} plane, or a surface inclined at 0 to 8 degrees with respect to the {11-20} plane.

[0132] Figure 12 shows the elemental concentration distribution of a semiconductor device according to the second embodiment. Figure 12 shows the elemental concentration distribution in the gate insulating layer 28, the interface termination region 40, and the silicon carbide layer 10 on the side surface of the trench 50.

[0133] Figure 12 shows the concentration distributions of boron (B), carbon (C), and hydrogen (H). In Figure 12, the solid line shows the concentration distribution of boron, the dotted line shows the concentration distribution of carbon, and the dashed line shows the concentration distribution of hydrogen.

[0134] The boron concentration distribution has a first peak in the interface termination region 40. The boron concentration at the first peak is, for example, 1 × 10⁻⁶ 20 cm -3 The above 1 x 10 22 cm -3The following applies: The full width at half maximum for the first peak of the boron concentration distribution is, for example, less than 1 nm. Boron is segregated at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0135] The hydrogen concentration distribution has a second peak in the interface termination region 40. The hydrogen concentration at the second peak is, for example, 1 × 10⁻⁶. 20 cm -3 The above 2 x 10 22 cm -3 The following applies: The full width at half maximum for the second peak of the hydrogen concentration distribution is, for example, less than 1 nm. Hydrogen is segregated at the interface between the silicon carbide layer 10 and the gate insulating layer 28. Note that the hydrogen atoms present in the interface termination region 40 are bonded to carbon atoms.

[0136] The hydrogen concentration at the second peak in the interface termination region 40 is, for example, higher than the boron concentration at the first peak in the interface termination region 40.

[0137] According to the MOSFET 200 of the second embodiment, similar to the MOSFET 100 of the first embodiment, the amount of harmful defects in the gate insulating layer 28 is reduced, and a decrease in carrier mobility and fluctuations in the threshold voltage can be suppressed.

[0138] When forming a trench-gate MOSFET using silicon carbide, a problem arises in that threshold voltage fluctuations occur due to AC stress. One factor is thought to be the interface state between the silicon carbide layer and the gate insulating layer. These interface states are thought to be generated particularly by dangling bonds of carbon present on the inner surface of the trench. When AC stress is applied, charges injected into the interface between the silicon carbide layer and the gate insulating layer are trapped in these interface states, causing threshold voltage fluctuations.

[0139] For example, if the inner surface of a trench is an m-plane or an a-plane, unlike the Si-plane, dangling bonds of carbon atoms exist at its outermost surface.

[0140] In the manufacturing method of the MOSFET 200 of the second embodiment, a second heat treatment is performed in an atmosphere containing hydrogen gas (H2). By performing the second heat treatment, the dangling bonds of carbon atoms are terminated with hydrogen atoms. In the MOSFET 200 of the second embodiment, a peak in the hydrogen concentration distribution exists in the interface termination region 40 because the dangling bonds of carbon atoms are terminated with hydrogen atoms. In the MOSFET 200, the dangling bonds of carbon atoms on the surface of the silicon carbide layer are reduced, and threshold voltage fluctuations due to AC stress in the MOSFET 200 can be suppressed.

[0141] As described above, according to the second embodiment, a semiconductor device is realized in which the amount of harmful defects in the gate insulating layer is reduced.

[0142] (Third embodiment) The inverter circuit and drive device of the third embodiment is an inverter circuit and drive device comprising the semiconductor device of the first embodiment.

[0143] Figure 13 is a schematic diagram of the drive unit of the third embodiment. The drive unit 700 comprises a motor 140 and an inverter circuit 150.

[0144] The inverter circuit 150 consists of three semiconductor modules 150a, 150b, and 150c, each using a MOSFET 100 from the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0145] According to the third embodiment, the characteristics of the inverter circuit 150 and the drive unit 700 are improved by providing a MOSFET 100 with improved characteristics.

[0146] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0147] Figure 14 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 800 of the fourth embodiment is a railway vehicle. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0148] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 800.

[0149] According to the fourth embodiment, the characteristics of the vehicle 800 are improved by providing a MOSFET 100 with improved characteristics.

[0150] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0151] Figure 15 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 900 of the fifth embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0152] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0153] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 900.

[0154] According to the fifth embodiment, the characteristics of the vehicle 900 are improved by providing a MOSFET 100 with improved characteristics.

[0155] (Sixth embodiment) The elevator of the sixth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0156] Figure 16 is a schematic diagram of an elevator according to the sixth embodiment. The elevator 1000 of the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoisting machine 616, a motor 140, and an inverter circuit 150.

[0157] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0158] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the hoisting machine 616, causing the cage 610 to rise and fall.

[0159] According to the sixth embodiment, the characteristics of the elevator 1000 are improved by providing a MOSFET 100 with improved characteristics.

[0160] In the first and second embodiments described above, the case of silicon carbide with a 4H-SiC crystal structure was used as an example. However, the present invention can also be applied to silicon carbide with other crystal structures such as 6H-SiC and 3C-SiC.

[0161] Furthermore, the present invention can also be applied to n-channel type IGBTs (Insulated Gate Bipolar Transistors).

[0162] Furthermore, the present invention can be applied not only to n-channel type MOSFETs or IGBTs, but also to p-channel type MOSFETs or IGBTs.

[0163] Furthermore, although the third to sixth embodiments described the application of the semiconductor device of the present invention to vehicles and elevators as examples, it is also possible to apply the semiconductor device of the present invention to, for example, a power conditioner for a solar power generation system.

[0164] In the first or second embodiment, hydrogen (H) was used as an example of one element selected from the group consisting of hydrogen (H), deuterium (D), and fluorine (F). However, it is clear from the inventor's first-principles calculations that the same actions and effects as those of hydrogen (H) can be obtained in the case of deuterium (D) and fluorine (F).

[0165] When COB is treated with hydrogen molecules (deuterium molecules), a COBH structure (COBD) is formed, and it becomes significantly more stable. The inventor's first-principles calculations showed that the stabilization energy is very large, at 7.8 eV per hydrogen (deuterium) atom constituting the hydrogen (deuterium) molecule. Since hydrogen and deuterium have the same electronic state, their stabilization energies are equivalent. COB + 1 / 2·H2(D2) = COBH + 7.8eV

[0166] Similarly, when COB is treated with fluorine molecules, a COBF structure is formed, which significantly stabilizes it. The inventor's first-principles calculations showed that the energy gain is even greater, at 10.5 eV per fluorine atom constituting the fluorine molecule. COB + 1 / 2·F² = COBF + 10.5eV

[0167] In other words, the COB structure can be energetically stabilized by hydrogen treatment with hydrogen molecules (H2), deuterium treatment with deuterium (D2) molecules, and fluorine treatment with fluorine (F2) molecules. Once stabilized, it will not decompose again and form traps during device operation.

[0168] In the third to sixth embodiments, the case where the semiconductor device of the first embodiment is applied was described as an example, but it is also possible to apply, for example, the semiconductor device of the second embodiment.

[0169] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0170] 10. Silicon carbide layer 28 Gate insulating layer (silicon oxide layer) 30 Postal Codes 40 Interface termination area (area) 100 MOSFETs (Semiconductor Devices) 200 MOSFETs (Semiconductor Equipment) 700 Drive unit 800 vehicles 900 vehicles 1000 Elevators C1 First concentration C2 Second concentration C3 Third concentration C4 Fourth concentration C5 Fifth concentration C6 The sixth concentration

Claims

1. A silicon carbide layer, Terminal gate and, A silicon oxide layer is provided between the silicon carbide layer and the gate electrode, and the silicon oxide layer contains one element selected from the group consisting of hydrogen (H), deuterium (D), and fluorine (F), boron (B), and carbon (C). It is provided between the silicon carbide layer and the silicon oxide layer, and the boron concentration is 1 × 10 ２０ cm －３ The above areas and, The concentration distribution of boron in the silicon carbide layer, the silicon oxide layer, and the region has a first peak in the region. The first concentration of boron at a first position 5 nm away from the first peak on the silicon oxide layer side is 1 × 10⁻¹⁶ １８ cm －３ That's all. The second concentration of carbon at the first position is 1 × 10⁻⁶ １８ cm －３ That's all. The third concentration of the element at the first position is 1 × 10 １８ cm －３ That's all. The second concentration is 80% or more and 120% or less of the first concentration. A semiconductor device wherein the third concentration is 80% or more and 120% or less of the first concentration.

2. The fourth concentration of boron at a second position 15 nm away from the first peak toward the silicon oxide layer side is 1×10 １７ cm －３ or more, The fifth concentration of carbon at the second position is 1 × 10⁻⁶ １７ cm －３ That's all. The sixth concentration of the element at the second position is 1 × 10 １７ cm －３ That's all. The fifth concentration is 80% or more and 120% or less of the fourth concentration. The semiconductor device according to claim 1, wherein the sixth concentration is 80% or more and 120% or less of the fourth concentration.

3. The fourth concentration of boron at the second position, 15 nm away from the first peak on the silicon oxide layer side, is 1 × 10⁻⁶. １７ cm －３ It is less than, The fifth concentration of carbon at the second position is 1 × 10⁻⁶ １７ cm －３ It is less than, The sixth concentration of the element at the second position is 1 × 10 １７ cm －３ A semiconductor device according to claim 1, which is less than [amount missing].

4. The surface of the silicon carbide layer facing the gate electrode is a surface inclined at an angle of 0 to 8 degrees with respect to the {0001} plane, and the concentration of the element in the region is 1 × 10 ２０ cm －３ The semiconductor device according to claim 1, which is as follows:

5. The semiconductor device according to claim 1, wherein the surface of the silicon carbide layer facing the gate electrode is a surface inclined at 0 to 8 degrees with respect to the {1-100} plane, or a surface inclined at 0 to 8 degrees with respect to the {11-20} plane, and the concentration distribution of the element in the region has a second peak in the region.

6. The semiconductor device according to claim 5, wherein the concentration of the element in the second peak is higher than the concentration of boron in the first peak.

7. The semiconductor device according to claim 1, wherein the silicon oxide layer comprises three oxygen atoms and one boron atom bonded to the aforementioned element.

8. The semiconductor device according to claim 7, wherein, if the silicon oxide layer contains boron atoms bonded with four oxygen atoms, the amount of boron atoms bonded with three oxygen atoms and one of the elements in the silicon oxide layer is greater than the amount of boron atoms bonded with four oxygen atoms.

9. The semiconductor device according to claim 8, wherein in the silicon oxide layer, the amount of boron atoms bonded to three oxygen atoms and one of the aforementioned elements is 10 times or more the amount of boron atoms bonded to four oxygen atoms.

10. The semiconductor device according to claim 1, wherein the region includes a boron atom bonded to three carbon atoms.

11. A silicon carbide layer, Terminal gate and, A silicon oxide layer is provided between the silicon carbide layer and the gate electrode, and the silicon oxide layer contains one element selected from the group consisting of hydrogen (H), deuterium (D), and fluorine (F), boron (B), and carbon (C). It is provided between the silicon carbide layer and the silicon oxide layer, and the boron concentration is 1 × 10 ２０ cm －３ The above areas and, The silicon oxide layer comprises three oxygen atoms and one boron atom bonded to the aforementioned element, wherein the semiconductor device is provided.

12. The concentrations of boron, carbon, and the elements in the silicon oxide layer are 1 × 10 １８ cm －３ The semiconductor device according to claim 11.

13. The semiconductor device according to claim 11, wherein, if the silicon oxide layer contains boron atoms bonded with four oxygen atoms, the amount of boron atoms bonded with three oxygen atoms and one of the elements in the silicon oxide layer is greater than the amount of boron atoms bonded with four oxygen atoms.

14. The semiconductor device according to claim 13, wherein in the silicon oxide layer, the amount of boron atoms bonded with three oxygen atoms and one of the aforementioned elements is 10 times or more the amount of boron atoms bonded with four oxygen atoms.

15. The semiconductor device according to claim 11, wherein the region includes a boron atom bonded to three carbon atoms.

16. The semiconductor device according to claim 1 or claim 11, wherein when an AC stress of -5 MV / cm to 5 MV / cm at 1 MHz is applied between the silicon carbide layer and the gate electrode for 100 hours, the threshold voltage fluctuation is less than 0.1 V.

17. An inverter circuit comprising a semiconductor device according to claim 1 or claim 11.

18. A drive device comprising a semiconductor device according to claim 1 or claim 11.

19. A vehicle comprising the semiconductor device according to claim 1 or claim 11.

20. An elevator comprising the semiconductor device according to claim 1 or claim 11.

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