Semiconductor devices, memory systems, and information processing systems

Abstract

To provide semiconductor devices, memory systems, and information processing systems that can improve operational reliability. [Solution] A memory system according to one embodiment comprises a first semiconductor device and a controller. The first semiconductor device includes a first chip having a first temperature sensor. The controller includes a comparison circuit that compares a first measured temperature of the first temperature sensor with first temperature data and outputs a first comparison result, compares the first measured temperature with second temperature data and outputs a second comparison result, and a detection circuit that detects a malfunction of the first temperature sensor based on the first and second comparison results and outputs a first detection result. The first chip switches a first operating temperature based on the first detection result.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, memory systems, and information processing systems.

Background Art

[0002] An information processing system including a host device and a memory system is known. The memory system includes a semiconductor device and a memory controller that controls the semiconductor device. As the semiconductor device, a NAND type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are a semiconductor device, a memory system, and an information processing system capable of improving operation reliability.

Means for Solving the Problems

[0005] The memory system according to the embodiment comprises a first semiconductor device and a controller. The first semiconductor device includes a first chip. The first chip has a first temperature sensor. The controller includes a comparison circuit and a detection circuit. The comparison circuit compares a first measured temperature measured by the first temperature sensor with first temperature data and outputs the comparison result as a first comparison result. It also compares the first measured temperature with second temperature data and outputs the comparison result as a second comparison result. The detection circuit detects a malfunction of the first temperature sensor based on the first and second comparison results and outputs the detection result as a first detection result. The first chip switches the first operating temperature based on the first detection result. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the configuration of an information processing system according to the first embodiment. [Figure 2] A block diagram showing an example of the hardware configuration of a host device included in the information processing system according to the first embodiment. [Figure 3] A block diagram showing an example of the configuration of a memory system included in the information processing system according to the first embodiment. [Figure 4] A block diagram showing an example of the configuration of a NAND flash memory in a memory system included in the information processing system according to the first embodiment. [Figure 5] A circuit diagram showing an example of the circuit configuration of a memory cell array in a NAND flash memory included in the information processing system according to the first embodiment. [Figure 6] A cross-sectional view showing an example of the cross-sectional structure of a memory system included in the information processing system according to the first embodiment. [Figure 7] A circuit diagram showing an example of the configuration of a temperature sensor in a NAND flash memory included in the information processing system according to the first embodiment. [Figure 8] A diagram illustrating an example of the configuration of a comparison circuit within a memory controller included in the information processing system according to the first embodiment. [Figure 9]A circuit diagram showing an example of the configuration of a detection circuit in a memory controller included in the information processing system according to the first embodiment. [Figure 10] A diagram illustrating an example of the configuration of a generation circuit within a memory controller included in the information processing system according to the first embodiment. [Figure 11] A flowchart showing an example of the faulty temperature sensor detection operation in the information processing system according to the first embodiment. [Figure 12] A diagram illustrating an example of the faulty temperature sensor detection operation in the information processing system according to the first embodiment. [Figure 13] A diagram showing an example of temperature sensor data and threshold values ​​for each NAND flash memory in the information processing system according to the first embodiment. [Figure 14] A diagram illustrating an example of the operation of a comparison circuit within a memory controller included in the information processing system according to the first embodiment. [Figure 15] A diagram illustrating an example of the operation of a detection circuit within a memory controller included in the information processing system according to the first embodiment. [Figure 16] A diagram illustrating an example of the operation of a generation circuit within a memory controller included in the information processing system according to the first embodiment. [Figure 17] A diagram illustrating an example of the operation of a temperature sensor in a NAND flash memory included in the information processing system according to the first embodiment. [Figure 18] A diagram illustrating an example of the operation of a temperature sensor in a NAND flash memory included in the information processing system according to the first embodiment. [Figure 19] This figure illustrates an example of the configuration of a comparison circuit within a memory controller included in an information processing system according to a first modified example of the first embodiment. [Figure 20] This figure illustrates an example of the configuration of a generation circuit within a memory controller included in an information processing system according to a first modified example of the first embodiment. [Figure 21] This figure illustrates an example of faulty temperature sensor detection operation in an information processing system according to a first modified example of the first embodiment. [Figure 22]A diagram for explaining an example of the configuration of a comparison circuit in a memory controller included in an information processing system according to a second modification of the first embodiment. [Figure 23] A diagram for explaining an example of the configuration of a generation circuit in a memory controller included in an information processing system according to a second modification of the first embodiment. [Figure 24] A diagram for explaining an example of a defective temperature sensor detection operation in an information processing system according to a second modification of the first embodiment. [Figure 25] A diagram for explaining an example of the configuration of a generation circuit in a memory controller included in an information processing system according to a third modification of the first embodiment. [Figure 26] A diagram for explaining an example of a defective temperature sensor detection operation in an information processing system according to a third modification of the first embodiment. [Figure 27] A block diagram showing an example of the functional configuration of a host device included in an information processing system according to the second embodiment. [Figure 28] A block diagram showing an example of the configuration of a memory system included in an information processing system according to the second embodiment. [Figure 29] A diagram for explaining an example of a defective temperature sensor detection operation in an information processing system according to the second embodiment. [Figure 30] A block diagram showing an example of the configuration of a memory system included in an information processing system according to the third embodiment. [Figure 31] A plan view showing an example of the planar configuration of a memory system included in an information processing system according to the third embodiment. [Figure 32] A cross-sectional view showing an example of the cross-sectional structure of a package of a memory system included in an information processing system according to the third embodiment. [Figure 33] A block diagram showing an example of the configuration of a NAND-type flash memory in a memory system included in an information processing system according to the fourth embodiment. [Figure 34] A circuit diagram showing an example of the configuration of a temperature sensor in a NAND-type flash memory included in an information processing system according to the fourth embodiment.

Embodiments for Carrying Out the Invention

[0007] The embodiments will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. When elements with similar configurations need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] 1. First Embodiment 1.1 Configuration 1.1.1 Configuration of the Information Processing System The configuration of the information processing system according to the first embodiment will be described using Figure 1. Figure 1 is a block diagram showing an example of the configuration of the information processing system according to the first embodiment. As shown in Figure 1, the information processing system 1 includes a host device (hereinafter referred to as "host") 2 and a memory system 3. The host 2 and the memory system 3 are connected via a host bus HB. The memory system 3 includes a semiconductor device 30 and a memory controller 50. The semiconductor device 30 includes one or more chip CPs. The semiconductor device 30 and the memory controller 50 are connected via a memory bus MB. The memory controller 50 controls the semiconductor device 30.

[0009] In this embodiment, we will explain using the case where the semiconductor device 30 is a non-volatile memory and the chip CP is a NAND flash memory as an example. Hereafter, the semiconductor device 30 will be referred to as "non-volatile memory 30" and the chip CP will be referred to as "NAND chip CP".

[0010] Host 2 is a device that controls memory system 3. Host 2 may be, for example, a personal computer, a server system, a mobile device, an in-vehicle device, or a digital camera.

[0011] Memory system 3 is a device that stores data. Examples of memory system 3 include SSDs (solid state drives), UFS (Universal Flash Storage) devices, USB (Universal Serial Bus) memory, MMC (Multi-Media Cards), or SD cards. TM It is a card. The memory system 3 performs processing based on request signals received from the host 2 or spontaneous processing requests. The memory system 3 includes a non-volatile memory 30 and a memory controller 50.

[0012] The non-volatile memory 30 is a device that stores data in a non-volatile manner. The non-volatile memory 30 is connected to the memory controller 50 via a memory bus MB. The non-volatile memory 30 stores data received from the memory controller 50 via the memory bus MB in a non-volatile manner, for example.

[0013] The memory controller 50 is a device that controls the non-volatile memory 30. The memory controller 50 is, for example, a System On a Chip (SoC). The memory controller 50 is connected to the host 2 via the host bus HB. The memory controller 50 receives request signals and information from the host 2 via the host bus HB. The memory controller 50 also transmits information to the host 2 via the host bus HB.

[0014] The type of host bus HB depends on the application applied to memory system 3. If memory system 3 is an SSD, the host bus HB could be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TMThe Peripheral Component Interconnect Express (C) standard interface is used. If memory system 3 is a UFS device, the M-PHY standard interface is used as the host bus HB. If memory system 3 is a USB memory device, the USB standard interface is used as the host bus HB. If memory system 3 is an MMC, the eMMC (Embedded Multi Media Card) standard interface is used as the host bus HB. If memory system 3 is an SD TM If it is a card, the host bus HB is SD TM A standard interface is used.

[0015] The memory controller 50 controls the non-volatile memory 30 via the memory bus MB based on a request signal received from the host 2 or a spontaneous processing request. The memory controller 50, for example, transmits and receives data, as well as commands and addresses, to and from the non-volatile memory 30. The memory bus MB, for example, transmits and receives signals according to a NAND interface.

[0016] 1.1.2 Host Configuration The configuration of host 2 will be explained using Figure 2. Figure 2 is a block diagram showing an example of the hardware configuration of host 2 included in the information processing system 1 according to the first embodiment. As shown in Figure 2, host 2 includes, for example, a CPU (Central Processing Unit) 21, ROM (Read Only Memory) 23, RAM (Random Access Memory) 24, and a communication interface (I / F) circuit 25.

[0017] The CPU 21 is a processor configured to execute various programs related to the control of the host 2. The CPU 21 includes a temperature sensor 22. The temperature sensor 22 measures the temperature of the CPU 21. The temperature sensor 22 is a temperature measurement circuit implemented within the host 2, for example, using a bandgap reference circuit. Another example of the temperature sensor 22 is a thermocouple. Hereinafter, the temperature data measured by the temperature sensor 22 will be referred to as "temperature sensor data TempH". The CPU 21 transmits request signals and information via the communication interface circuit 25. The ROM 23 is a non-volatile memory configured to store the control programs of the host 2. The RAM 24 is a volatile memory used as the work area of ​​the CPU 21. The RAM 24 is, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory). The communication interface circuit 25 is an interface circuit used for communication with the memory system 3.

[0018] 1.1.3 Memory System Configuration The configuration of memory system 3 will be explained using Figure 3. Figure 3 is a block diagram showing an example of the configuration of memory system 3.

[0019] 1.1.3.1 Configuration of Non-Volatile Memory The internal structure of the non-volatile memory 30 will now be described. As shown in Figure 3, the non-volatile memory 30 includes, for example, (N+1) NAND chips CP (where N is an integer greater than or equal to 2). Hereafter, the (N+1) NAND chips CP will be denoted as CP0, CP1, ..., CPN, respectively. When NAND chips CP0 to CPN are not distinguished, they will simply be referred to as NAND chips CP.

[0020] The NAND chip CP is a device that stores data nonvolatilously. The NAND chip CP includes multiple memory cell transistors. Each of the multiple memory cell transistors stores data nonvolatilously. The NAND chip CP performs write, read, and erase operations based on commands and addresses received from the memory controller 50. In a write operation, the NAND chip CP stores the data received from the memory controller 50 nonvolatilously in the multiple memory cell transistors. In a read operation, the NAND chip CP outputs the data read from the multiple memory cell transistors to the memory controller 50.

[0021] (N+1) NAND chip CPs can each operate independently. Each NAND chip CP is connected to the memory controller 50 via a memory bus MB. The number of memory bus MBs and the number of NAND chip CPs connected to each memory bus MB are arbitrary. Communication between the memory controller 50 and the NAND chip CPs conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0022] 1.1.3.1.1 NAND Chip Configuration The configuration of the NAND chip CP will be explained using Figure 4. Figure 4 is a block diagram showing an example of the configuration of a NAND chip CP. Figure 4 shows the configuration of one NAND chip CP included in the non-volatile memory 30. Other NAND chip CPs included in the non-volatile memory 30 have a similar configuration to that in Figure 4. Figure 4 also shows the memory controller 50.

[0023] As shown in Figure 4, the NAND chip CP includes an input / output circuit 31, a logic control circuit 32, a ready / busy circuit 33, a register set 34, a temperature sensor 35, a sequencer 40, a memory cell array 41, a voltage generation circuit 42, a raw decoder module 43, and a sense amplifier module 44.

[0024] The input / output circuit 31 is a circuit that transmits and receives signals and information to and from the memory controller 50. The input / output circuit 31 transmits and receives input / output signals DQ (for example, 8-bit signals DQ0 to DQ7), as well as data strobe signals DQS and DQSn (inverted signals of signal DQS) to and from the memory controller 50.

[0025] The signal DQ includes, for example, the command CMD, address ADD, status information STS, data DAT, replacement temperature data (hereinafter also referred to as "input temperature") TempR, and the switching signal SigS. The replacement temperature data TempR is temperature data to replace the temperature sensor data (hereinafter also referred to as "measured temperature") Temp measured by the temperature sensor 35. The switching signal SigS is a signal to switch whether to use the internal data of the temperature sensor 35 (temperature sensor data Temp) or the external data of the temperature sensor 35 (replacement temperature data TempR) as the temperature data used by the NAND chip CP. The replacement temperature data TempR and the switching signal SigS are used, for example, by the temperature sensor 35.

[0026] Signals DQS and DQSn are signals used to control the timing of sending and receiving signal DQ. For example, when writing data, signals DQS and DQSn are transmitted from the memory controller 50 to the NAND chip CP along with signal DQ containing the data to be written. The NAND chip CP receives signal DQ containing the data to be written in synchronization with signals DQS and DQSn. Similarly, when reading data, signals DQS and DQSn are transmitted from the NAND chip CP to the memory controller 50 along with signal DQ containing the data to be read. The memory controller 50 receives signal DQ containing the data to be read in synchronization with signals DQS and DQSn.

[0027] The input / output circuit 31 may also receive signals DQS and DQSn from the memory controller 50 via the logic control circuit 32.

[0028] Furthermore, the input / output circuit 31 transmits the command CMD in signal DQ to the command register 34a, which will be described later. The input / output circuit 31 transmits the address ADD in signal DQ to the address register 34b, which will be described later. The input / output circuit 31 receives the status information STS from the status register 34c, which will be described later. The input / output circuit 31 transmits the replacement temperature data TempR and the switching signal SigS in signal DQ to the first feature register 34d, which will be described later. The input / output circuit 31 transmits and receives the data DAT in signal DQ to and from the sense amplifier module 44.

[0029] The logic control circuit 32 is a circuit that controls the input / output circuit 31 and the sequencer 40 based on control signals. The logic control circuit 32 receives control signals from the memory controller 50. Examples of such control signals include the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REn. Signal CEn is a signal for enabling the NAND chip CP. Signal CLE is a signal that indicates that the signal DQ received by the NAND chip CP is the command CMD. Signal ALE is a signal that indicates that the signal DQ received by the NAND chip CP is the address ADD. Signal WEn is a signal that commands the NAND chip CP to input signal DQ. Signal REn is a signal that commands the NAND chip CP to output signal DQ. The NAND chip CP generates signals DQS and DQSn based on signal REn. The NAND chip CP outputs signal DQ to the memory controller 50 based on the generated signals DQS and DQSn. The logic control circuit 32 controls the input / output circuit 31 and the sequencer 40 based on the received control signal.

[0030] The ready / busy circuit 33 is a circuit that informs the memory controller 50 of the operating status of the sequencer 40. Based on the operating status of the sequencer 40, the ready / busy circuit 33 sends a ready / busy signal RBn to the memory controller 50. Signal RBn is a signal that indicates whether the NAND chip CP is in a ready state or a busy state. For example, when the NAND chip CP is in a busy state, the signal RBn is at a "low" level. The ready state is when the NAND chip CP is able to accept commands from the memory controller 50. The busy state is when the NAND chip CP is unable to accept commands from the memory controller 50.

[0031] The register set 34 is a set of multiple circuits, each of which temporarily stores information. The register set 34 includes a command register 34a, an address register 34b, a status register 34c, a first feature register 34d, and a second feature register 34e.

[0032] Command register 34a is a circuit that stores command CMDs. Command CMDs include, for example, instructions that cause the sequencer 40 to perform read operations, write operations, and erase operations.

[0033] Address register 34b is a circuit that stores address ADD. Address ADD includes, for example, the row address RA (including the block address and page address) and the column address CA. The block address, page address, and column address CA are used, for example, for selecting the block BLK, word line, and bit line, respectively. For example, address register 34b transfers the row address RA to the row decoder module 43. Address register 34b transfers the column address CA to the sense amplifier module 44.

[0034] The status register 34c is a circuit that stores status information STS, for example, during read, write, and erase operations. The status information STS is used to notify the memory controller 50 whether or not the operation has been completed successfully.

[0035] The first feature register 34d is a circuit that stores various setting information input from outside the NAND chip CP. Such setting information includes, for example, replacement temperature data TempR and switching signal SigS.

[0036] The second feature register 34e is a circuit that stores various setting information used internally by the NAND chip CP. Such setting information includes, for example, operating temperature data (hereinafter also referred to as "operating temperature") TempU. The operating temperature data TempU is temperature data used by the NAND chip CP. The operating temperature data TempU is used, for example, by the voltage generation circuit 42.

[0037] The temperature sensor 35 measures the temperature of the NAND chip CP. The temperature sensor 35 is a temperature measurement circuit implemented within the semiconductor device 30, for example, by applying a bandgap reference circuit. Another example of the temperature sensor 35 is a thermocouple. For example, the temperature sensor 35 measures the temperature of the memory cell array 41 within the NAND chip CP. The temperature sensor 35 transmits the measured temperature as temperature sensor data Temp to the sequencer 40. Note that the temperature sensor 35 does not have to directly measure the temperature of the memory cell array 41. For example, the temperature sensor 35 may measure the temperature of a location other than the memory cell array 41 within the NAND chip CP. The temperature sensor 35 also obtains replacement temperature data TempR and a switching signal SigS from the first feature register 34d. Based on the switching signal SigS, the temperature sensor 35 selects either the temperature sensor data Temp or the replacement temperature data TempR and transmits the selected temperature data as the used temperature data TempU to the second feature register 34e. Thus, the temperature sensor 35 can switch between the measured temperature and the temperature input from an external source and output it as operating temperature data TempU. Details of the temperature sensor 35 will be described later.

[0038] The sequencer 40 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 40 controls the operation of the entire NAND chip CP. For example, the sequencer 40 controls the ready / busy circuit 33, the voltage generation circuit 42, the raw decoder module 43, and the sense amplifier module 44 based on the command CMD stored in the command register 34a. For example, the sequencer 40 performs read, write, and erase operations. The sequencer 40 also stores the temperature sensor data Temp acquired from the temperature sensor 35 as status information STS in the status register 34c and outputs it to the memory controller 50 via the input / output circuit 31. Note that the temperature sensor data Temp may be output to the memory controller 50 as information other than status information STS, rather than as status information STS. Furthermore, the sequencer 40 stores the replacement temperature data TempR and the switching signal SigS received from the memory controller 50 in the first feature register 34d.

[0039] The memory cell array 41 includes multiple blocks BLK0 to BLKi (where i is an integer greater than or equal to 1). Hereafter, if blocks BLK0 to BLKi are not distinguished, they will simply be referred to as block BLK. A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased collectively. For example, a block BLK is used as the unit of data erasure operation. The memory cell array 41 is provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. Details of the memory cell array 41 will be described later.

[0040] The voltage generation circuit 42 is a circuit that generates voltages used in various operations. The voltage generation circuit 42 obtains the operating temperature data TempU from the second feature register 34e. The voltage generation circuit 42 generates a voltage based on the operating temperature data TempU. The voltage generation circuit 42 supplies the generated voltage to, for example, the memory cell array 41, the row decoder module 43, and the sense amplifier module 44.

[0041] The row decoder module 43 is a circuit that selects one block BLK in the memory cell array 41 based on the row address RA. The row decoder module 43 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0042] The sense amplifier module 44 is a circuit that determines the data stored in the memory cell transistor. In a read operation, the sense amplifier module 44 determines the data stored in the memory cell transistor based on the voltage of the bit line (by applying a voltage to the bit line and determining whether or not current flows through the bit line). The sense amplifier module 44 transfers the determination result as read data DAT to the input / output circuit 31. In a write operation, the sense amplifier module 44 applies a voltage to the bit line based on the write data DAT received from the input / output circuit 31.

[0043] 1.1.3.1.2 Circuit configuration of memory cell array The circuit configuration of the memory cell array 41 will be explained using Figure 5. Figure 5 is a circuit diagram showing an example of the circuit configuration of the memory cell array 41. Figure 5 shows the circuit configuration of a block BLK included in the memory cell array 41 as an example of the circuit configuration of the memory cell array 41. Other block BLKs included in the memory cell array 41 have a configuration similar to that of Figure 5.

[0044] As shown in Figure 5, block BLK includes, for example, four string units SU0 to SU3. Hereinafter, if string units SU0 to SU3 are not distinguished, they will simply be referred to as string unit SU. String unit SU is a collection of multiple NAND strings NS that are selected collectively, for example, in a write or read operation. String unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Hereinafter, if bit lines BL0 to BLm are not distinguished, they will simply be referred to as bit line BL. NAND string NS is a collection of multiple memory cell transistors connected in series. Each NAND string NS includes, for example, memory cell transistors MC0 to MC7, as well as selection transistors ST1 and ST2. Hereinafter, if memory cell transistors MC0 to MC7 are not distinguished, they will simply be referred to as memory cell transistors MC. Memory cell transistors MC store data non-volatilely. Memory cell transistors MC include a control gate and a charge storage layer. Selection transistors ST1 and ST2 are switching elements. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0045] In the NAND string NS, the memory cell transistors MC0 to MC7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the series-connected memory cell transistors MC0 to MC7. The drain of the selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC7. The source of the selection transistor ST2 is connected to the source line SL.

[0046] Within the same block BLK, the control gates of memory cell transistors MC0 to MC7 are commonly connected to word lines WL0 to WL7, respectively. Hereafter, when word lines WL0 to WL7 are not distinguished, they will simply be referred to as word line WL. The gates of each selection transistor ST1 within string units SU0 to SU3 are commonly connected to selection gate lines SGD0 to SGD3, respectively. Hereafter, when selection gate lines SGD0 to SGD3 are not distinguished, they will simply be referred to as selection gate line SGD. The gates of selection transistor ST2 included in the same block BLK are commonly connected to selection gate line SGS.

[0047] In the circuit configuration of the memory cell array 41 described above, the bit line BL is shared, for example, by multiple NAND strings NS to which the same column address CA is assigned in multiple string units SU. The source line SL is shared, for example, between multiple blocks BLK.

[0048] A collection of multiple memory cell transistors MC connected to a common word line WL within a string unit SU is referred to, for example, as a cell unit CU. A block BLK contains multiple cell unit CUs. The data stored in a cell unit CU, each containing multiple memory cell transistors MC that store 1 bit of data according to a threshold voltage, corresponds to one page of data. A cell unit CU may store two or more pages of data, depending on the number of bits of data stored by the memory cell transistors MC.

[0049] Note that the circuit configuration of the memory cell array 41 is not limited to the configuration described above. For example, the number of string units SU included in block BLK, and the number of memory cell transistors MC and selection transistors ST1 and ST2 included in NAND string NS, may be any number.

[0050] 1.1.3.2 Memory Controller Configuration The internal configuration of the memory controller 50 will be explained again using Figure 3. As shown in Figure 3, the memory controller 50 includes, for example, a host interface (I / F) circuit 51, a CPU 52, a ROM 53, a RAM 54, a temperature sensor 55, a comparison circuit 56, a detection circuit 57, a generation circuit 61, and a memory interface (I / F) circuit 62.

[0051] The host interface circuit 51 is responsible for communication between the memory controller 50 and the host 2. The host interface circuit 51 is connected to the host 2 via the host bus HB.

[0052] The CPU 52 is the control circuit for the memory controller 50. The CPU 52 controls the operation of the entire memory controller 50 by executing the program (firmware) stored in the ROM 53. For example, when the CPU 52 receives a write request from the host 2, it controls the write operation based on that request. The same applies to read and erase operations. The CPU 52 also performs a faulty temperature sensor detection operation. The faulty temperature sensor detection operation detects a fault in the temperature sensor 35 of each NAND chip CP and rewrites the temperature sensor data Temp of the NAND chip in which the faulty temperature sensor 35 was detected. The faulty temperature sensor detection operation includes, for example, temperature sensor data acquisition processing, comparison processing, detection processing, replacement temperature data generation processing, and temperature information setting processing. Details of the faulty temperature sensor detection operation will be described later.

[0053] ROM53 is a non-volatile memory. ROM53 is, for example, an EEPROM. TM It is (Electrically Erasable Programmable Read-Only Memory). ROM53 stores programs such as firmware.

[0054] RAM54 is volatile memory. RAM54 is, for example, SRAM. RAM54 is used as the work area for CPU52. RAM54 stores firmware for managing non-volatile memory 30, and various management information.

[0055] The temperature sensor 55 measures the temperature of the memory controller 50. The temperature sensor 55 is a temperature measurement circuit implemented within the memory controller 50, for example, by applying a bandgap reference circuit. Another example of the temperature sensor 55 is a thermocouple. For example, the temperature sensor 55 measures the temperature of the CPU 52 within the memory controller 50. Note that the temperature sensor 55 does not have to directly measure the temperature of the CPU 52. For example, the temperature sensor 55 may measure the temperature of a part of the memory controller 50 other than the CPU 52. Hereinafter, the temperature data measured by the temperature sensor 55 will be referred to as "temperature sensor data TempC".

[0056] The comparison circuit 56 is a circuit that performs comparison processing. Details of the comparison circuit 56 will be described later.

[0057] The detection circuit 57 is a circuit that performs detection processing. Details of the detection circuit 57 will be described later.

[0058] The generation circuit 61 is a circuit that performs the process of generating replacement temperature data. Details of the generation circuit 61 will be described later.

[0059] The memory interface circuit 62 is responsible for communication between the memory controller 50 and the non-volatile memory 30. The memory interface circuit 62 is connected to the non-volatile memory 30 via the memory bus MB. For example, the memory interface circuit 62 controls the transfer of data, commands, and addresses between the memory controller 50 and the non-volatile memory 30.

[0060] 1.1.4 Structure of the memory system The structure of the memory system 3 will be explained using Figure 6. Figure 6 is a cross-sectional view showing an example of the structure of the memory system 3. In Figure 6, the memory bus MB is not shown.

[0061] As shown in Figure 6, a memory controller 50 is provided on the substrate 70. On the memory controller 50, (N+1) NAND chips CP are stacked in the order of NAND chips CP0, CP1, CP2, CP3, ..., CPN from the substrate 70 side.

[0062] In the memory system 3 having the structure described above, each NAND chip CP in the non-volatile memory 30 is in contact with one or two other NAND chips. Therefore, the temperature sensor data Temp of the temperature sensor 35 of each NAND chip CP shows a similar value.

[0063] 1.1.5 Temperature Sensor Configuration The configuration of the temperature sensor 35 of the NAND chip CP will be explained using Figure 7. Figure 7 is a circuit diagram showing an example of the configuration of the temperature sensor 35. As shown in Figure 7, the temperature sensor 35 includes a temperature sensor element 36, a first register 37, a second register 38, and a multiplexer (MUX) 39.

[0064] The temperature sensor element 36 measures the temperature. The temperature sensor element 36 transmits the measured temperature sensor data Temp to the first register 37.

[0065] The first register 37 is a circuit that temporarily stores the temperature sensor data Temp measured by the temperature sensor element 36. The first register 37 receives the temperature sensor data Temp from the temperature sensor element 36. The first register 37 stores the received temperature sensor data Temp. The first register 37 outputs the stored temperature sensor data Temp to the outside of the temperature sensor 35 and also transmits it to the MUX 39. The temperature sensor data Temp output to the outside of the temperature sensor 35 is transmitted to the sequencer 40.

[0066] The second register 38 is a circuit that temporarily stores the replacement temperature data TempR set in the first feature register 34d. The second register 38 receives the replacement temperature data TempR from the first feature register 34d. The second register 38 stores the received replacement temperature data TempR. The second register 38 sends the stored replacement temperature data TempR to the MUX 39.

[0067] MUX39 is a circuit that, based on the switching signal SigS set in the first feature register 34d, selects and outputs either the temperature sensor data Temp stored in the first register 37 or the replacement temperature data TempR stored in the second register 38.

[0068] MUX39 receives a switching signal SigS from the first feature register 34d. For example, the switching signal SigS is either "0" or "1". In this specification, "0" is defined as a value indicating that the temperature sensor data Temp will not be replaced (the temperature sensor 35 is not faulty (state)), and "1" is defined as a value indicating that the temperature sensor data Temp will be replaced (the temperature sensor 35 is faulty (state)). However, the value of the switching signal SigS does not have to be defined in this way. MUX39 receives the temperature sensor data Temp from the first register 37. MUX39 receives the replacement temperature data TempR from the second register 38. Based on the switching signal SigS, MUX39 outputs the selected temperature data as the used temperature data TempU to the outside of the temperature sensor 35. If the switching signal SigS is "0", MUX39 outputs the temperature sensor data Temp as the used temperature data TempU. On the other hand, when the switching signal SigS is "1", MUX39 outputs the replacement temperature data TempR as the used temperature data TempU. In this way, the NAND chip CP (temperature sensor 35) switches the used temperature data TempU based on the switching signal SigS. The used temperature data TempU output to the outside of the temperature sensor 35 is sent to the second feature register 34e.

[0069] Note that the temperature sensor 35 does not necessarily have to include the first register 37 and the second register 38. In this case, for example, the temperature sensor data Temp measured by the temperature sensor element 36 is output to the outside of the temperature sensor 35 and also transmitted to the MUX 39. The replacement temperature data TempR input from outside the temperature sensor 35 is transmitted to the MUX 39.

[0070] 1.1.6 Configuration of the comparator circuit The configuration of the comparison circuit 56 of the memory controller 50 will be explained using Figure 8. Figure 8 is a diagram illustrating an example of the configuration of the comparison circuit 56.

[0071] As shown in Figure 8, the comparison circuit 56 receives temperature sensor data Temp from each of the NAND chips CP0 to CPN. The temperature sensor data Temp includes temperature sensor data Temp0 to TempN. The temperature sensor data Temp0 to TempN correspond to the NAND chips CP0 to CPN, respectively.

[0072] The comparison circuit 56 compares the temperature sensor data Temp for each NAND chip CP with that NAND chip CP and one adjacent NAND chip CP. Here, "one adjacent NAND chip CP" means one NAND chip CP that is physically adjacent to that NAND chip CP, and is defined, for example, as follows.

[0073] In this embodiment, as shown in Figure 6, since NAND chip CP1 is provided on top of NAND chip CP0, one NAND chip CP adjacent to NAND chip CP0 is defined as NAND chip CP1. Since NAND chip CP2 is provided on top of NAND chip CP1, one NAND chip CP adjacent to NAND chip CP1 is defined as NAND chip CP2. Since NAND chip CP3 is provided on top of NAND chip CP2, one NAND chip CP adjacent to NAND chip CP2 is defined as NAND chip CP3. The same definitions are continued for subsequent chips. Note that since no other NAND chip CP is provided on top of NAND chip CPN, one NAND chip CP adjacent to NAND chip CPN is defined as NAND chip CP0.

[0074] Based on the above definitions, as shown in Figure 8, the comparison circuit 56 performs comparisons between Temp0 and Temp1, Temp1 and Temp2, Temp2 and Temp3, Temp3 and Temp4, ..., and TempN and Temp0. In this way, the comparison circuit 56 compares Temp0 and Temp1, and Temp0 and TempN for the NAND chip CP0. The comparison circuit 56 performs comparisons for other NAND chips CP in the same manner.

[0075] The comparison circuit 56 calculates the absolute value of the difference between the two compared devices and outputs the calculated value (comparison result) as comparison result ResA. Comparison result ResA contains (N+1) comparison results ResA0 to ResAN. Comparison results ResA0 to ResAN correspond to the absolute value of the difference between Temp0 and Temp1, the absolute value of the difference between Temp1 and Temp2, the absolute value of the difference between Temp2 and Temp3, the absolute value of the difference between Temp3 and Temp4, ..., the absolute value of the difference between TempN and Temp0, respectively. Comparison result ResA output from the comparison circuit 56 is transmitted to the detection circuit 57.

[0076] 1.1.7 Configuration of the detection circuit The configuration of the detection circuit 57 of the memory controller 50 will be explained using Figure 9. Figure 9 is a circuit diagram showing an example of the configuration of the detection circuit 57. As shown in Figure 9, the detection circuit 57 includes a determination circuit 58, an OR circuit 59, and a plurality of AND circuits 60-0 to 60-N.

[0077] The determination circuit 58 receives (N+1) comparison results ResA0 to ResAN from the comparison circuit 56.

[0078] The determination circuit 58 determines whether each comparison result ResA is smaller than the threshold X. If the comparison result ResA is smaller than the threshold X, the determination circuit 58 determines "Pass," meaning that no failure of the temperature sensor 35 has occurred in either of the two NAND chips CP from which the comparison result ResA was calculated. On the other hand, if the comparison result ResA is greater than or equal to the threshold X, the determination circuit 58 determines "Fail," meaning that a failure of the temperature sensor 35 has occurred in either of the two NAND chips CP from which the comparison result ResA was calculated. This is because, as described above, the temperature sensor data Temp of each NAND chip CP in the non-volatile memory 30 shows similar values, so if a particular comparison result ResA is relatively larger than other comparison results ResA, it is considered highly likely that a failure of the temperature sensor 35 has occurred in either of the two NAND chips CP from which that particular comparison result ResA was calculated.

[0079] The threshold X is a predetermined temperature. For example, the threshold X is determined by testing the product before shipment, collecting the variation in temperature sensor data Temp when each NAND chip CP is operating normally within the temperature range guaranteed by the product, and then using the collected data to determine the threshold X.

[0080] The determination circuit 58 outputs the result of the determination (Pass / Fail) as determination result ResB. Determination result ResB contains (N+1) determination results ResB0 to ResBN. Determination results ResB0 to ResBN correspond to the determination results for ResA0, ResA1, ResA2, ResA3, ..., ResAN, respectively. For example, determination result ResB is either "0" or "1". In this specification, "0" is defined as the value indicating "Pass" and "1" as the value indicating "Fail". However, the value of determination result ResB does not have to be defined in this way.

[0081] The OR circuit 59 receives (N+1) judgment results ResB0 to ResBN from the judgment circuit 58. The OR circuit 59 performs an OR operation on the (N+1) judgment results ResB0 to ResBN that it has received. The OR circuit 59 outputs the result of the OR operation (Pass / Fail) as the detection result ResC. If the detection result ResC is "0", it indicates that there is no NAND chip CP with a faulty temperature sensor 35 in the non-volatile memory 30. On the other hand, if the detection result ResC is "1", it indicates that there is a NAND chip CP with a faulty temperature sensor 35 in the non-volatile memory 30. The detection result ResC output from the OR circuit 59 is sent to the host 2.

[0082] The AND gate 60-0 receives the judgment results ResBN and ResB0 from the judgment circuit 58. The AND gate 60-1 receives the judgment results ResB0 and ResB1 from the judgment circuit 58. The AND gate 60-2 receives the judgment results ResB1 and ResB2 from the judgment circuit 58. The AND gate 60-3 receives the judgment results ResB2 and ResB3 from the judgment circuit 58. The same applies to AND gates 60-4 to 60-(N-1). The AND gate 60-N receives the judgment results ResB(N-1) and ResBN from the judgment circuit 58.

[0083] Each of the AND circuits 60-0 to 60-N performs an AND operation on the two input judgment results ResB. Each of the AND circuits 60-0 to 60-N outputs the result of the AND operation (Pass / Fail) as the detection result ResD. The detection result ResD contains (N+1) detection results ResD0 to ResDN. The detection results ResD0 to ResDN correspond to the AND operation results of AND circuits 60-0, 60-1, 60-2, 60-3, ..., and 60-N, respectively. Furthermore, the detection results ResD0 to ResDN correspond to NAND chips CP0 to CPN, respectively. If the detection result ResD is "0", it indicates that no failure has occurred in the temperature sensor 35 in the corresponding NAND chip CP. On the other hand, if the detection result ResD is "1", it indicates that a failure has occurred in the temperature sensor 35 of the corresponding NAND chip CP. In this way, AND circuit 60-0 detects a failure in the temperature sensor 35 of the NAND chip CP0 based on the judgment results ResB0 and ResBN. The other AND circuits 60-1 to 60-N similarly detect a failure in the temperature sensor 35 of the corresponding NAND chip CP. The detection results ResD0 to ResDN output from each of the AND circuits 60-0 to 60-N are transmitted to the corresponding NAND chip CP as a switching signal SigS.

[0084] 1.1.8 Configuration of the Generating Circuit The configuration of the generation circuit 61 of the memory controller 50 will be explained using Figure 10. Figure 10 is a diagram illustrating an example of the configuration of the generation circuit 61.

[0085] As shown in Figure 10, the generation circuit 61 receives temperature sensor data Temp from each of the NAND chips CP0 to CPN. The temperature sensor data Temp contains (N+1) temperature sensor data Temp0 to TempN. The temperature sensor data Temp0 to TempN correspond to the NAND chips CP0 to CPN, respectively.

[0086] The generation circuit 61 calculates the average value of the two adjacent NAND chip CPs for each NAND chip CP. Here, "the two adjacent NAND chip CPs" refers to the two NAND chip CPs that are physically adjacent to the NAND chip CP, and is defined, for example, as follows.

[0087] In this embodiment, as shown in Figure 6, NAND chip CP1 is provided between NAND chips CP0 and CP2, so the two NAND chips CP adjacent to NAND chip CP1 are defined as NAND chip CP0 and NAND chip CP2. Since NAND chip CP2 is provided between NAND chips CP1 and CP3, the two NAND chips CP adjacent to NAND chip CP2 are defined as NAND chip CP1 and NAND chip CP3. The same definitions are applied to subsequent steps. Note that since no other NAND chips CP are provided below NAND chip 0, the two NAND chips CP adjacent to NAND chip 0 are defined as NAND chip CPN and NAND chip CP1. Since no other NAND chips CP are provided above NAND chip CPN, the two NAND chips CP adjacent to NAND chip CPN are defined as NAND chip CP(N-1) and NAND chip CP0.

[0088] Based on the above definitions, as shown in Figure 10, the generation circuit 61 calculates the average values ​​of TempN and Temp1, Temp0 and Temp2, Temp1 and Temp3, Temp2 and Temp4, ..., and the average value of Temp(N-1) and Temp0, respectively.

[0089] The generation circuit 61 outputs the calculated average value as replacement temperature data TempR. The replacement temperature data TempR contains (N+1) replacement temperature data TempR0 to TempRN. The replacement temperature data TempR0 to TempRN correspond to the average value of TempN and Temp1, the average value of Temp0 and Temp2, the average value of Temp1 and Temp3, the average value of Temp2 and Temp4, ..., the average value of Temp(N-1) and Temp0, respectively. Furthermore, the replacement temperature data TempR0 to TempRN correspond to NAND chips CP0 to CPN, respectively. In this way, the generation circuit 61 generates the corresponding replacement temperature data TempR0 for NAND chip CP0 based on TempN and Temp1. The generation circuit 61 similarly generates the corresponding replacement temperature data TempR for the other NAND chips CP. The replacement temperature data TempR0 to TempRN output from the generation circuit 61 are transmitted to the corresponding NAND chips CP, respectively.

[0090] 1.2 Operation The faulty temperature sensor detection operation of the information processing system 1 according to the first embodiment will be explained using Figures 11 and 12. Figure 11 is a flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1 according to the first embodiment. Figure 12 is a diagram illustrating an example of the faulty temperature sensor detection operation in the information processing system 1 according to the first embodiment.

[0091] First, the memory controller 50 executes a temperature sensor data acquisition process at predetermined time intervals (S101). Specifically, for example, the CPU 52 issues a command set to read status information STS (hereinafter referred to as "first command set CMDS1") and transmits the first command set CMDS1 to each NAND chip CP in the non-volatile memory 30. The first command set CMDS1 includes the command CMD and the address ADD. Each NAND chip CP receives the first command set CMDS1 from the memory controller 50. The sequencer 40 of each NAND chip CP acquires temperature sensor data Temp from the temperature sensor 35 based on the command CMD in the first command set CMDS1 and transmits the temperature sensor data Temp as status information STS to the memory controller 50. The CPU 52 receives the temperature sensor data Temp from each NAND chip CP and transmits the temperature sensor data Temp to the comparison circuit 56 and the generation circuit 61. As a result, as shown in Figure 12, the comparison circuit 56 and the generation circuit 61 receive the temperature sensor data Temp from each NAND chip CP. The predetermined time interval is, for example, one that can track temperature fluctuations in the NAND chip CP. Such a time interval is, for example, one second, but is not limited to one second.

[0092] Next, the comparison circuit 56 performs a comparison process (S102). For example, the comparison circuit 56 compares the temperature sensor data Temp as described above and transmits the comparison result ResA to the detection circuit 57, as shown in Figure 12.

[0093] Next, the detection circuit 57 performs detection processing (S103). For example, the detection circuit 57 detects a malfunction in the temperature sensor 35 as described above and sends the detection result ResC to the host 2, as shown in Figure 12. The detection circuit 57 also sends the detection result ResD to the CPU 52.

[0094] Next, the generation circuit 61 performs the replacement temperature data generation process (S104). For example, the generation circuit 61 generates the replacement temperature data TempR as described above. The generation circuit 61 also sends the replacement temperature data TempR to the CPU 52.

[0095] Next, the memory controller 50 executes temperature information setting processing (S105). Specifically, for example, the CPU 52 issues a command set for setting various information (hereinafter referred to as "second command set CMDS2") and transmits the second command set CMDS2 to each NAND chip CP in the non-volatile memory 30. The second command set CMDS2 includes the command CMD, address ADD, replacement temperature data TempR, and switching signal SigS. As a result, as shown in Figure 12, the detection circuit 57 transmits the switching signal SigS to each NAND chip CP, and the generation circuit 61 transmits the replacement temperature data TempR to each NAND chip CP. Each NAND chip CP receives the second command set CMDS2 from the memory controller 50. The sequencer 40 of each NAND chip CP stores the replacement temperature data TempR and the switching signal SigS in the first feature register 34d of each NAND chip CP based on the command CMD in the second command set CMDS2.

[0096] The following describes the faulty temperature sensor detection operation, using the example of a case where the non-volatile memory 30 includes four NAND chips CP0 to CP3, and a failure occurs in the temperature sensor 35 in NAND chip CP1.

[0097] Figure 13 shows an example of temperature sensor data Temp and threshold X for each NAND chip in the information processing system 1 according to the first embodiment. As shown in Figure 13, the temperature sensor data Temp for NAND chips CP0, CP2, and CP3, where no failure of the temperature sensor 35 has occurred, is approximately the same temperature. Assume that the temperature sensor data Temp0 for NAND chip CP0 is 25°C. Assume that the temperature sensor data Temp2 for NAND chip CP2 is 23°C. Assume that the temperature sensor data Temp3 for NAND chip CP3 is 24°C. Assume that the temperature sensor data Temp1 for NAND chip CP1, where a failure of the temperature sensor 35 has occurred, is 50°C. Temp1 is a higher temperature than Temp0, Temp2, and Temp3. Assume that the threshold X is 10°C.

[0098] First, the comparison process will be explained using Figure 14. Figure 14 is a diagram illustrating an example of the operation of the comparison circuit 56. After the temperature sensor data acquisition process is executed, as shown in Figure 14, the comparison circuit 56 receives temperature sensor data Temp0 to Temp3 from NAND chips CP0 to CP3, respectively. The comparison circuit 56 compares Temp0 (25°C) and Temp1 (50°C) and outputs the absolute value of the difference between Temp0 and Temp1 (=25°C) as the comparison result ResA0. The comparison circuit 56 compares Temp1 (50°C) and Temp2 (23°C) and outputs the absolute value of the difference between Temp1 and Temp2 (=27°C) as the comparison result ResA1. The comparison circuit 56 compares Temp2 (23°C) and Temp3 (24°C) and outputs the absolute value of the difference between Temp2 and Temp3 (=1°C) as the comparison result ResA2. The comparison circuit 56 compares Temp3 (24°C) and Temp0 (25°C) and outputs the absolute value of the difference between Temp3 and Temp0 (=1°C) as the comparison result ResA3. The comparison results ResA0 to ResA3 are sent to the detection circuit 57.

[0099] Next, the detection process will be explained using Figure 15. Figure 15 is a diagram illustrating an example of the operation of the detection circuit 57.

[0100] As shown in Figure 15, the detection circuit 57 receives comparison results ResA0 to ResA3 from the comparison circuit 56. The judgment circuit 58 determines whether ResA0 (25°C) is less than the threshold X (10°C) and outputs the result of the determination (=Fail) as judgment result ResB0. The judgment circuit 58 determines whether ResA1 (27°C) is less than the threshold X (10°C) and outputs the result of the determination (=Fail) as judgment result ResB1. The judgment circuit 58 determines whether ResA2 (1°C) is less than the threshold X (10°C) and outputs the result of the determination (=Pass) as judgment result ResB2. The judgment circuit 58 determines whether ResA3 (1°C) is less than the threshold X (10°C) and outputs the result of the determination (=Pass) as judgment result ResB3.

[0101] The OR circuit 59 receives the judgment results ResB0 to ResB3 from the judgment circuit 58. The OR circuit 59 performs the OR operation and outputs the result of the OR operation (=Fail) as the detection result ResC. The detection result ResC is sent to the host 2.

[0102] The AND circuit 60-0 receives the judgment results ResB3 and ResB0 from the judgment circuit 58. The AND circuit 60-0 performs an AND operation and outputs the result of the AND operation (=Pass) as the detection result ResD0. The AND circuit 60-1 receives the judgment results ResB0 and ResB1 from the judgment circuit 58. The AND circuit 60-1 performs an AND operation and outputs the result of the AND operation (=Fail) as the detection result ResD1. The AND circuit 60-2 receives the judgment results ResB1 and ResB2 from the judgment circuit 58. The AND circuit 60-2 performs an AND operation and outputs the result of the AND operation (=Pass) as the detection result ResD2. The AND circuit 60-3 receives the judgment results ResB2 and ResB3 from the judgment circuit 58. The AND circuit 60-3 performs an AND operation and outputs the result of the AND operation (=Pass) as the detection result ResD3. The detection results ResD0 to ResD3, i.e., the switching signals SigS0 to SigS3, are transmitted to the NAND chips CP0 to CP3, respectively, via the CPU 52.

[0103] Next, the process for generating replacement temperature data will be explained using Figure 16. Figure 16 is a diagram illustrating an example of the operation of the generation circuit 61. As shown in Figure 16, the generation circuit 61 receives temperature sensor data Temp0 to Temp3 from NAND chips CP0 to CP3, respectively. The generation circuit 61 calculates the average of Temp3 (24°C) and Temp1 (50°C) and outputs the average value (=37°C) as replacement temperature data TempR0. The generation circuit 61 calculates the average of Temp0 (25°C) and Temp2 (23°C) and outputs the average value (=24°C) as replacement temperature data TempR1. The generation circuit 61 calculates the average of Temp1 (50°C) and Temp3 (24°C) and outputs the average value (=37°C) as replacement temperature data TempR2. The generation circuit 61 calculates the average of Temp2 (23°C) and Temp0 (25°C) and outputs the average value (=24°C) as replacement temperature data TempR3. The replacement temperature data TempR0 to TempR3 are transmitted to the NAND chips CP0 to CP3, respectively, via the CPU 52.

[0104] After the replacement temperature data generation process is executed, the temperature information setting process is performed, and the replacement temperature data TempR and the switching signal SigS are stored in the first feature register 34d of each of the NAND chips CP0 to CP3.

[0105] Figures 17 and 18 illustrate an example of the operation of the temperature sensor 35.

[0106] After the temperature information setting process is executed, as shown in Figure 17, the temperature sensor 35 of the NAND chip CP1 receives a switching signal SigS1 (Fail("1")) from the first feature register 34d. The second register 38 of the temperature sensor 35 of the NAND chip CP1 receives replacement temperature data TempR1 (24°C) from the first feature register 34d. The first register 37 of the temperature sensor 35 of the NAND chip CP1 outputs the temperature data (50°C) stored in the first register 37 as temperature sensor data Temp1. Based on the switching signal SigS1, the MUX 39 of the temperature sensor 35 of the NAND chip CP1 outputs the temperature data (24°C) stored in the second register 38 as the usable temperature data TempU1.

[0107] After the temperature information setting process is executed, as shown in Figure 18, the temperature sensor 35 of the NAND chip CP0 receives a switching signal SigS0 (Pass("0")) from the first feature register 34d. The second register 38 of the temperature sensor 35 of the NAND chip CP0 receives replacement temperature data TempR0 (37°C) from the first feature register 34d. The first register 37 of the temperature sensor 35 of the NAND chip CP0 outputs the temperature data (25°C) stored in the first register 37 as temperature sensor data Temp0. Based on the switching signal SigS0, the MUX 39 of the temperature sensor 35 of the NAND chip CP0 outputs the temperature data (25°C) stored in the first register 37 as the used temperature data TempU0.

[0108] 1.3 Effects of the First Embodiment In NAND chips, electrons flow more easily into the memory cell transistor channels as the NAND chip temperature increases. Therefore, when writing data, the voltage applied to the word line decreases as the temperature increases under the same writing conditions. Similarly, when reading data, the voltage applied to the word line required for current to flow through the bit line decreases. Based on these temperature characteristics of NAND chips, NAND chips control the word line voltage during writing and reading by referring to temperature sensor data obtained from a temperature sensor mounted on the NAND chip.

[0109] However, even if the voltage of the word line is controlled as described above, if there is a defect in the temperature sensor and there is a discrepancy between the actual temperature of the NAND chip and the temperature sensor data measured by the NAND chip's temperature sensor, the data may not be written or read correctly.

[0110] In the memory system 3 according to this embodiment, each NAND chip CP in the non-volatile memory 30 includes a first feature register 34d, a second feature register 34e, and a temperature sensor 35. The first feature register 34d stores a switching signal SigS and replacement temperature data TempR input from an external source. Based on the switching signal SigS, the temperature sensor 35 switches between the measured temperature sensor data Temp and the replacement temperature data TempR input from an external source and outputs it as the used temperature data TempU. The second feature register 34e stores the used temperature data TempU output from the temperature sensor 35. In this way, each NAND chip CP can rewrite the used temperature data TempU.

[0111] Furthermore, in the memory system 3 according to this embodiment, the memory controller 50 includes a comparison circuit 56, a detection circuit 57, and a generation circuit 61. The comparison circuit 56 compares the temperature sensor data Temp of each NAND chip CP (hereinafter also referred to as "target NAND chip") with one adjacent NAND chip CP and outputs the absolute value of the difference between the two as the comparison result ResA. The detection circuit 57 determines whether the comparison result ResA is smaller than the threshold X for each comparison result ResA and outputs the AND operation result of the two determination results ResB related to the target NAND chip CP as the detection result ResD (switching signal SigS). The generation circuit 61 outputs the average value of the NAND chip CP and two adjacent NAND chip CPs as replacement temperature data TempR for each NAND chip CP. As described above, the temperature sensor data Temp of each NAND chip CP is approximately the same in the non-volatile memory 30. Therefore, the failure of the temperature sensor 35 can be properly detected, and replacement temperature data TempR that is close to the actual temperature of the NAND chip CP can be created. Furthermore, if the comparison process, detection process, and replacement temperature data generation process are performed using three NAND chip CPs that are physically adjacent (located close to each other), the failure of the temperature sensor 35 can be detected more accurately, and replacement temperature data TempR that is closer to the actual temperature of the NAND chip CP can be created. The switching signal SigS and the replacement temperature data TempR are transmitted from the memory controller 50 to the corresponding NAND chip CP and stored in the first feature register 34d of the corresponding NAND chip CP.

[0112] As a result, the temperature sensor 35 can rewrite the operating temperature data TempU used in the defective NAND chip CP to more appropriate temperature data. The voltage generation circuit 42 controls the voltage of the word line during writing and reading based on the operating temperature data TempU stored in the second feature register 34e. This improves the accuracy of data writing and reading. Therefore, the semiconductor device 30, memory system 3, and information processing system 1 according to this embodiment can improve operational reliability.

[0113] Furthermore, the host 2 or memory controller 50 employs a technology called thermal throttling, which reduces heat generation by limiting the memory's operating speed when the temperature rises.

[0114] However, if a faulty temperature sensor causes it to output a temperature higher than the actual temperature, thermal throttling may be performed unnecessarily, potentially slowing down memory operation. Conversely, if a faulty temperature sensor causes it to output a temperature lower than the actual temperature, thermal throttling may not be performed when needed.

[0115] In the memory system 3 according to this embodiment, the detection circuit 57 outputs the OR result of all judgment results ResB as the detection result ResC. The detection result ResC is transmitted from the memory controller 50 to the host 2. This allows the memory controller 50 and the host 2 to detect whether or not there is a defect in the temperature sensor 35 of the NAND chip CP in the non-volatile memory 30. Therefore, according to the semiconductor device 30, memory system 3, and information processing system 1 according to this embodiment, thermal throttling can be properly implemented.

[0116] 1.4 First Variation The configuration of the information processing system 1A according to the first modified example of the first embodiment will now be described. In the information processing system 1A according to this modified example, the configuration of the non-volatile memory 30A, and the configuration of the comparison circuit 56A and generation circuit 61A of the memory controller 50A differ from those of the first embodiment. The following will focus on the differences from the first embodiment.

[0117] 1.4.1 Configuration of Non-Volatile Memory The non-volatile memory 30A includes one NAND chip CP0. The configuration of the NAND chip CP0 is the same as shown in Figure 4 in the first embodiment.

[0118] 1.4.2 Configuration of the comparator circuit The configuration of the comparator circuit 56A will be explained using Figure 19. Figure 19 is a diagram illustrating an example of the configuration of the comparator circuit 56A.

[0119] As shown in Figure 19, the comparison circuit 56A receives temperature sensor data Temp0 from the NAND chip CP0, temperature sensor data TempC from the temperature sensor 55, and temperature sensor data TempH from the temperature sensor 22 of the host 2.

[0120] The comparison circuit 56A performs a comparison between Temp0 and TempC, a comparison between TempC and TempH, and a comparison between TempH and Temp0, in the same manner as in the first embodiment.

[0121] The comparison circuit 56A calculates the absolute difference between Temp0 and TempC, the absolute difference between TempC and TempH, and the absolute difference between TempH and Temp0, in the same manner as in the first embodiment, and outputs the calculated values ​​as comparison results ResA0 to ResA2, respectively. The comparison results ResA0 to ResA2 output from the comparison circuit 56A are transmitted to the detection circuit 57.

[0122] 1.4.3 Configuration of the Generating Circuit The configuration of the generation circuit 61A will be explained using Figure 20. Figure 20 is a diagram illustrating an example of the configuration of the generation circuit 61A.

[0123] As shown in Figure 20, the generation circuit 61A receives temperature sensor data Temp0 from the NAND chip CP0, temperature sensor data TempC from the temperature sensor 55, and temperature sensor data TempH from the temperature sensor 22 of the host 2.

[0124] The generation circuit 61A calculates the average values ​​of TempH and TempC, the average values ​​of Temp0 and TempH, and the average values ​​of TempC and Temp0, in the same manner as in the first embodiment, and outputs the calculated values ​​as replacement temperature data TempR0 to TempR2, respectively. The replacement temperature data TempR0 output from the generation circuit 61A is transmitted to the NAND chip CP0.

[0125] 1.4.4 Operation The faulty temperature sensor detection operation of the information processing system 1A will be explained using Figure 21. Figure 21 is a diagram illustrating an example of the faulty temperature sensor detection operation in the information processing system 1A. The flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1A is the same as that shown in Figure 11 in the first embodiment.

[0126] In S101, the memory controller 50A executes temperature sensor data acquisition processing at predetermined time intervals (for example, 1 second). Specifically, for example, the CPU 52 acquires temperature sensor data Temp0 from the NAND chip CP0 in the same manner as in the first embodiment. The CPU 52 also acquires temperature sensor data TempC from the temperature sensor 55 and temperature sensor data TempH from the temperature sensor 22 of the host 2. The CPU 52 transmits the temperature sensor data Temp0, TempC, and TempH to the comparison circuit 56A and the generation circuit 61A. As a result, as shown in Figure 21, the comparison circuit 56A and the generation circuit 61A receive temperature sensor data Temp0 from the NAND chip CP0, temperature sensor data TempC from the temperature sensor 55, and temperature sensor data TempH from the host 2.

[0127] In S105, the memory controller 50A performs temperature information setting processing. Specifically, for example, the CPU 52 transmits the switching signal SigS0 received from the detection circuit 57 and the replacement temperature data TempR0 received from the generation circuit 61A to the NAND chip CP0, in the same manner as in the first embodiment. As a result, as shown in Figure 21, the detection circuit 57 transmits the switching signal SigS0 to the NAND chip CP0, and the generation circuit 61A transmits the replacement temperature data TempR0 to the NAND chip CP0. The sequencer 40 of the NAND chip CP0 stores the replacement temperature data TempR0 and the switching signal SigS0 in the first feature register 34d of the NAND chip CP0, in the same manner as in the first embodiment.

[0128] S102 to S104 are the same as in the first embodiment.

[0129] 1.4.5 Effects of the first modified example In the modified memory system 3A, the comparison circuit 56A outputs the absolute value of the difference between the temperature sensor data Temp0 of the NAND chip CP0 and the temperature sensor data TempC of the temperature sensor 55, the absolute value of the difference between TempC and the temperature sensor data TempH of the temperature sensor 22, and the absolute value of the difference between TempH and Temp0 as the comparison result ResA. For each comparison result ResA, the detection circuit 57 determines whether the comparison result ResA is smaller than the threshold X, and outputs the AND operation result of the two determination results ResB related to the NAND chip CP0 as the detection result ResD0 (switching signal SigS0). The generation circuit 61A outputs the average value of TempC and TempH as the replacement temperature data TempR0. As described above, this modified version provides the same effects as the first embodiment.

[0130] 1.5 Second Variation The configuration of the information processing system 1B according to the second modification of the first embodiment will now be described. In the information processing system 1B according to this modification, the configuration of the non-volatile memory 30B, and the configuration of the comparison circuit 56B and generation circuit 61B of the memory controller 50B differ from those of the first embodiment. The following will focus on the differences from the first embodiment.

[0131] 1.5.1 Configuration of Non-Volatile Memory The non-volatile memory 30B includes two NAND chips CP0 and CP1. The configuration of each of the NAND chips CP0 and CP1 is the same as that shown in Figure 4 of the first embodiment.

[0132] 1.5.2 Configuration of the comparator circuit The configuration of the comparator circuit 56B will be explained using Figure 22. Figure 22 is a diagram illustrating an example of the configuration of the comparator circuit 56B.

[0133] As shown in Figure 22, the comparison circuit 56B receives temperature sensor data Temp0 from NAND chip CP0, temperature sensor data Temp1 from NAND chip CP1, and temperature sensor data TempC from temperature sensor 55.

[0134] The comparison circuit 56B performs a comparison between Temp0 and Temp1, a comparison between Temp1 and TempC, and a comparison between TempC and Temp0, in the same manner as in the first embodiment.

[0135] The comparison circuit 56B calculates the absolute difference between Temp0 and Temp1, the absolute difference between Temp1 and TempC, and the absolute difference between TempC and Temp0, in the same manner as in the first embodiment, and outputs the calculated values ​​as comparison results ResA0 to ResA2, respectively. The comparison results ResA0 to ResA2 output from the comparison circuit 56B are transmitted to the detection circuit 57.

[0136] 1.5.3 Configuration of the Generating Circuit The configuration of the generation circuit 61B will be explained using Figure 23. Figure 23 is a diagram illustrating an example of the configuration of the generation circuit 61B.

[0137] As shown in Figure 23, the generation circuit 61B receives temperature sensor data Temp0 from NAND chip CP0, temperature sensor data Temp1 from NAND chip CP1, and temperature sensor data TempC from temperature sensor 55.

[0138] The generation circuit 61B calculates the average value of TempC and Temp1, the average value of Temp0 and TempC, and the average value of Temp1 and Temp0, in the same manner as in the first embodiment, and outputs the calculated values ​​as replacement temperature data TempR0 to TempR2, respectively. The replacement temperature data TempR0 output from the generation circuit 61B is transmitted to the NAND chip CP0. The replacement temperature data TempR1 output from the generation circuit 61B is transmitted to the NAND chip CP1.

[0139] 1.5.4 Operation The faulty temperature sensor detection operation of the information processing system 1B will be explained using Figure 24. Figure 24 is a diagram illustrating an example of the faulty temperature sensor detection operation in the information processing system 1B. The flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1B is the same as that shown in Figure 11 in the first embodiment.

[0140] In S101, the memory controller 50B executes a temperature sensor data acquisition process at predetermined time intervals (for example, 1 second). Specifically, for example, the CPU 52 acquires temperature sensor data Temp0 and Temp1 from NAND chips CP0 and CP1, respectively, in the same manner as in the first embodiment. The CPU 52 also acquires temperature sensor data TempC from temperature sensor 55. The CPU 52 transmits the temperature sensor data Temp0, Temp1, and TempC to the comparison circuit 56B and the generation circuit 61B. As a result, as shown in Figure 24, the comparison circuit 56B and the generation circuit 61B receive temperature sensor data Temp0 and Temp1 from NAND chips CP0 and CP1, respectively, and temperature sensor data TempC from temperature sensor 55.

[0141] In S105, the memory controller 50B executes temperature information setting processing. Specifically, for example, the CPU 52 transmits the switching signals SigS0 and SigS1 received from the detection circuit 57, and the replacement temperature data TempR0 and TempR1 received from the generation circuit 61B, respectively, to the NAND chips CP0 and CP1, respectively, in the same manner as in the first embodiment. As a result, as shown in Figure 24, the detection circuit 57 transmits the switching signals SigS0 and SigS1 to the NAND chips CP0 and CP1, respectively, and the generation circuit 61B transmits the replacement temperature data TempR0 and TempR1 to the NAND chips CP0 and CP1, respectively. The sequencer 40 of the NAND chip CP0 stores the replacement temperature data TempR0 and the switching signal SigS0 in the first feature register 34d of the NAND chip CP0, in the same manner as in the first embodiment. The sequencer 40 of the NAND chip CP1 stores the replacement temperature data TempR1 and the switching signal SigS1 in the first feature register 34d of the NAND chip CP1, in the same manner as in the first embodiment.

[0142] S102 to S104 are the same as in the first embodiment.

[0143] 1.5.5 Effects of the second modified example In the modified memory system 3B, the comparison circuit 56B outputs the absolute value of the difference between the temperature sensor data Temp0 of the NAND chip CP0 and the temperature sensor data Temp1 of the NAND chip CP1, the absolute value of the difference between Temp1 and the temperature sensor data TempC of the temperature sensor 55, and the absolute value of the difference between TempC and Temp0 as comparison result ResA. For each comparison result ResA, the detection circuit 57 determines whether the comparison result ResA is smaller than the threshold X. The detection circuit 57 outputs the AND operation result of the two determination results ResB for the NAND chip CP0 and the AND operation result of the two determination results ResB for the NAND chip CP1 as detection results ResD0 and D1 (switching signals SigS0 and SigS1), respectively. The generation circuit 61B outputs the average value of TempC and Temp1 as replacement temperature data TempR0, and the average value of Temp0 and TempC as replacement temperature data TempR1. As described above, this modified version provides the same effects as the first embodiment.

[0144] 1.6 Third Variation The configuration of the information processing system 1C according to the third modification of the first embodiment will now be described. In the information processing system 1C according to this modification, the configuration of the generation circuit 61C of the memory controller 50C differs from that of the first embodiment. The following will focus on the differences from the first embodiment.

[0145] 1.6.1 Configuration of the Generating Circuit The configuration of the generation circuit 61C will be explained using Figure 25. Figure 25 is a diagram illustrating an example of the configuration of the generation circuit 61C.

[0146] As shown in Figure 25, the generation circuit 61C receives temperature sensor data TempC from the temperature sensor 55.

[0147] The generation circuit 61C outputs (generates) the temperature sensor data TempC as replacement temperature data TempR0 to TempRN. The replacement temperature data TempR0 to TempRN output from the generation circuit 61C are transmitted to the corresponding NAND chip CP.

[0148] 1.6.2 Operation The faulty temperature sensor detection operation of the information processing system 1C will be explained using Figure 26. Figure 26 is a diagram illustrating an example of the faulty temperature sensor detection operation in the information processing system 1C. The flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1C is the same as that shown in Figure 11 in the first embodiment.

[0149] In S101, the memory controller 50C executes temperature sensor data acquisition processing at predetermined time intervals (for example, 1 second). Specifically, for example, the CPU 52 acquires temperature sensor data Temp from each NAND chip CP in the same manner as in the first embodiment. The CPU 52 also acquires temperature sensor data TempC from the temperature sensor 55. The CPU 52 transmits the temperature sensor data Temp to the comparison circuit 56 and the temperature sensor data TempC to the generation circuit 61C. As a result, as shown in Figure 26, the comparison circuit 56 receives temperature sensor data Temp from each NAND chip CP, and the generation circuit 61C receives temperature sensor data TempC from the temperature sensor 55.

[0150] S102 to S105 are the same as in the first embodiment.

[0151] 1.6.3 Effects of the Third Modified Example In the memory system 3C according to this modified example, the generation circuit 61C outputs the temperature sensor data TempC from the temperature sensor 55 as replacement temperature data TempR. As a result, this modified example achieves the same effects as the first embodiment.

[0152] 2. Second Embodiment The configuration of the information processing system 1D according to the second embodiment will now be described. In the information processing system 1D according to the second embodiment, the configuration of the host 2D and the configuration of the memory controller 50D differ from those of the first embodiment. The following description will focus on the differences from the first embodiment.

[0153] 2.1 Host Configuration The hardware configuration of the host 2D is the same as that shown in Figure 2 of the first embodiment. The CPU 21 performs, for example, temperature sensor data acquisition processing, comparison processing, detection processing, replacement temperature data generation processing, and temperature information setting processing. The ROM 23 stores, for example, a program that causes the CPU 21 to perform temperature sensor data acquisition processing, comparison processing, detection processing, replacement temperature data generation processing, and temperature information setting processing.

[0154] The functional configuration of host 2D will be explained using Figure 27. Figure 27 is a block diagram showing an example of the functional configuration of host 2D. As shown in Figure 27, host 2D includes an acquisition unit 201, a comparison unit 202, a detection unit 203, a generation unit 204, and a setting unit 205. The acquisition unit 201, comparison unit 202, detection unit 203, generation unit 204, and setting unit 205 are functional blocks corresponding to the CPU 21. That is, the CPU 21 functions as the acquisition unit 201, comparison unit 202, detection unit 203, generation unit 204, and setting unit 205. Note that in Figure 27, the functional blocks corresponding to the temperature sensor 22, ROM 23, RAM 24, and communication interface circuit 25 are omitted from the illustration.

[0155] The acquisition unit 201 performs temperature sensor data acquisition processing. The temperature sensor data acquisition processing involves requesting the memory controller 50C to acquire temperature sensor data Temp and acquiring the temperature sensor data Temp from each NAND chip CP in the non-volatile memory 30. The acquisition unit 201 sends a signal ReqA to the memory controller 50D requesting the acquisition of temperature sensor data Temp and receives the temperature sensor data Temp from each NAND chip CP from the memory controller 50. The acquisition unit 201 transmits the temperature sensor data Temp to the comparison unit 202 and the generation unit 204.

[0156] The comparison unit 202 performs a comparison process. The comparison process is the same as the process performed by the comparison circuit 56 shown in the first embodiment. The comparison unit 202 receives temperature sensor data Temp from the acquisition unit 201. The comparison unit 202 performs a comparison process based on the temperature sensor data Temp and transmits the comparison result ResA to the detection unit 203.

[0157] The detection unit 203 performs detection processing. The detection processing is the same as the processing performed by the detection circuit 57 shown in the first embodiment. The detection unit 203 receives the comparison result ResA from the comparison unit 202. Based on the comparison result ResA, the detection unit 203 performs detection processing, outputs the detection result ResC, and transmits the detection result ResD, i.e., the switching signal SigS, to the setting unit 205.

[0158] The generation unit 204 performs replacement temperature data generation processing. The replacement temperature data generation processing is the same as the processing performed by the generation circuit 61 shown in the first embodiment. The generation unit 204 receives temperature sensor data Temp from the acquisition unit 201. Based on the temperature sensor data Temp, the generation unit 204 performs replacement temperature data generation processing and transmits the replacement temperature data TempR to the setting unit 205.

[0159] The setting unit 205 performs temperature information setting processing. The temperature information setting processing is the process of requesting the memory controller 50C to set temperature information and setting the temperature information in each NAND chip CP in the non-volatile memory 30. The setting unit 205 receives a switching signal SigS from the detection unit 203. The setting unit 205 receives replacement temperature data TempR from the generation unit 204. The setting unit 205 transmits a signal ReqB requesting the setting of temperature information, a switching signal SigS, and replacement temperature data TempR to the memory controller 50D.

[0160] 2.2 Memory Controller Configuration The internal configuration of the memory controller 50D will be explained using Figure 28. Figure 28 is a block diagram showing an example of the configuration of the memory system 3D. As shown in Figure 28, the memory controller 50D includes, for example, a host interface circuit 51, a CPU 52, a ROM 53, a RAM 54, a temperature sensor 55, and a memory interface circuit 62. The comparison circuit 56, detection circuit 57, and generation circuit 61 shown in the first embodiment have been eliminated from the memory controller 50D.

[0161] 2.3 Operation The faulty temperature sensor detection operation of the information processing system 1D will be explained using Figure 29. Figure 29 is a diagram illustrating an example of the faulty temperature sensor detection operation in the information processing system 1D. The flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1D is the same as that shown in Figure 11 in the first embodiment.

[0162] In S101, the host 2D executes the temperature sensor data acquisition process at predetermined time intervals (for example, 1 second). Specifically, as shown in Figure 29, for example, the acquisition unit 201 sends a signal ReqA to the memory controller 50D requesting the acquisition of temperature sensor data Temp. When the memory controller 50D receives the request signal ReqA, the CPU 52 acquires temperature sensor data Temp from each NAND chip CP in the same manner as in the first embodiment. The CPU 52 transmits the temperature sensor data Temp from each NAND chip CP to the host 2D. The acquisition unit 201 receives the temperature sensor data Temp from each NAND chip CP from the memory controller 50D and transmits the temperature sensor data Temp to the comparison unit 202 and the generation unit 204. As a result, the comparison unit 202 and the generation unit 204 receive the temperature sensor data Temp from each NAND chip CP.

[0163] In S102, the comparison unit 202 performs the comparison process in the same manner as in the first embodiment and transmits the comparison result ResA to the detection unit 203, as shown in Figure 29.

[0164] In S103, the detection unit 203 performs detection processing in the same manner as in the first embodiment and outputs the detection result ResC as shown in Figure 29. The detection unit 203 also transmits the detection result ResD, i.e., the switching signal SigS, to the setting unit 205.

[0165] In S104, the generation unit 204 performs replacement temperature data generation processing in the same manner as in the first embodiment, and transmits the replacement temperature data TempR to the setting unit 205, as shown in Figure 29.

[0166] In S105, the host 2D executes temperature information setting processing. Specifically, for example, as shown in Figure 29, the setting unit 205 sends a signal ReqB requesting the setting of temperature information, a switching signal SigS, and replacement temperature data TempR to the memory controller 50D. When the memory controller 50D receives the request signal ReqB, the switching signal SigS, and the replacement temperature data TempR, the CPU 52 sends the switching signal SigS and the replacement temperature data TempR to each NAND chip CP in the same manner as in the first embodiment. As a result, the detection unit 203 sends the switching signal SigS to each NAND chip CP, and the generation unit 204 sends the replacement temperature data TempR to each NAND chip CP. The sequencer 40 of each NAND chip CP stores the replacement temperature data TempR and the switching signal SigS in the first feature register 34d of each NAND chip CP in the same manner as in the first embodiment.

[0167] 2.4 Effects of the Second Embodiment According to the second embodiment, the same effects as the first embodiment are achieved.

[0168] Furthermore, according to this embodiment, each process of the faulty temperature sensor detection operation can be implemented in software on the host 2. This eliminates the need to implement the comparison circuit 56, detection circuit 57, and generation circuit 61 on the memory controller 50. Therefore, according to this embodiment, the physical size of the memory system 3D chip can be made relatively small.

[0169] The first, second, and third variations of the first embodiment can also be applied to the second embodiment.

[0170] 3. Third Embodiment The configuration of the information processing system 1E according to the third embodiment will now be described. In the information processing system 1E according to the third embodiment, the configuration of the memory system 3E differs from that of the first embodiment. The following description will focus on the differences from the first embodiment.

[0171] 3.1 Memory System Configuration The configuration of the memory system 3E will be explained using Figure 30. Figure 30 is a block diagram showing an example of the configuration of the memory system 3E. As shown in Figure 30, the memory system 3E includes multiple packages PKG0 to PKGk (where k is an integer of 1 or more). Hereafter, if packages PKG0 to PKGk are not distinguished, they will simply be referred to as package PKG. Package PKG includes the non-volatile memory 30 and the interface (I / F) chip 80.

[0172] The configuration of the non-volatile memory 30 is the same as that shown in Figure 3 of the first embodiment.

[0173] The interface chip 80 is a device that manages communication between the memory controller 50 and the non-volatile memory 30. The interface chip 80 is connected to the non-volatile memory 30 via a bus. The interface chip 80 is connected to the memory controller 50 via the memory bus MB.

[0174] The memory controller 50 is, for example, an SSD controller. The configuration of the memory controller 50 is the same as shown in Figure 3 in the first embodiment. The memory controller 50 controls the non-volatile memory 30 in each package PKG via the memory bus MB based on a request signal received from the host 2 or a spontaneous processing request.

[0175] The comparison circuit 56, detection circuit 57, and generation circuit 61 may be implemented on the interface chip 80 instead of the memory controller 50.

[0176] 3.2 Structure of the Memory System The structure of the memory system 3E will be described using Figures 31 and 32. Figure 31 is a plan view showing an example of the structure of the memory system 3E. Figure 32 is a cross-sectional view showing an example of the structure of the package PKG of the memory system 3E. In Figures 31 and 32, the memory bus MB and the bus connecting the interface chip 80 and the non-volatile memory 30 are not shown.

[0177] As shown in Figure 31, multiple packages (PKG) and a memory controller (50) are provided on the substrate (70). To the right of the memory controller (50) are multiple packages (PKG) including packages PKG0 to PKG3. Packages PKG0 to PKG3 are spaced apart from each other in the vertical direction. To the left of the memory controller (50) are multiple packages (PKG) including packages PKG4 to PKG7. Packages PKG4 to PKG7 are spaced apart from each other in the vertical direction.

[0178] As shown in Figure 32, an interface chip 80 is provided on the substrate 70. On the interface chip 80, (N+1) NAND chips CP are stacked in the order of NAND chips CP0, CP1, CP2, CP3, ..., CPN from the substrate 70 side.

[0179] In the memory system 3E having the structure described above, each NAND chip CP in the non-volatile memory 30 is in contact with one or two other NAND chips. Therefore, the temperature sensor data Temp of the temperature sensor 35 of each NAND chip CP in the non-volatile memory 30 will show a similar value. Also, packages PKG0 to PKG3 are relatively close to each other. Similarly, packages PKG4 to PKG7 are also relatively close to each other. Therefore, it is highly likely that the temperature sensor data Temp of the temperature sensor 35 of each NAND chip CP in the non-volatile memory 30 will be similar between packages PKG0 to PKG3. It is also highly likely that the temperature sensor data Temp of the temperature sensor 35 of each NAND chip CP in the non-volatile memory 30 will be similar between packages PKG4 to PKG7.

[0180] On the other hand, packages PKG0 to PKG3 (hereinafter referred to as the "first package group") and packages PKG4 to PKG7 (hereinafter referred to as the "second package group") are physically far apart from each other. Therefore, there is a high possibility that the temperature sensor data Temp of the temperature sensor 35 of each NAND chip CP in the non-volatile memory 30 will differ significantly between the first package group and the second package group.

[0181] 3.3 Operation The faulty temperature sensor detection operation of the information processing system 1E will be described. The flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1E is the same as Figure 11 shown in the first embodiment.

[0182] As described above, the temperature sensor data Temp of each NAND chip CP's temperature sensor 35 is approximately the same in the non-volatile memory 30. Therefore, in this embodiment, the memory controller 50 performs a faulty temperature sensor detection operation for each package PKG of the non-volatile memory 30, in the same manner as in the first embodiment.

[0183] 3.4 Effects of the Third Embodiment According to the third embodiment, the same effects as the first embodiment are achieved.

[0184] Furthermore, in the memory system 3E according to this embodiment, the memory controller 50 performs a faulty temperature sensor detection operation for each package PKG with respect to the non-volatile memory 30, in the same manner as in the first embodiment. The memory controller 50 does not perform a faulty temperature sensor detection operation with respect to other package PKGs. Therefore, according to this embodiment, the faulty temperature sensor detection operation can be performed more effectively.

[0185] As mentioned above, the temperature sensor data Temp of the temperature sensor 35 of each NAND chip CP in the non-volatile memory 30 is likely to be similar between packages PKG0 to PKG3 and between packages PKG4 to PKG7. Therefore, between packages PKG0 to PKG3, the faulty temperature sensor detection operation may be performed using three corresponding NAND chip CPs. For example, the faulty temperature sensor detection operation may be performed using the temperature sensor data Temp of the corresponding NAND chip CP in package PKG0, the temperature sensor data Temp of the corresponding NAND chip CP in package PKG1, and the temperature sensor data Temp of the corresponding NAND chip CP in package PKG2. Corresponding NAND chip CPs refer to, for example, NAND chip CPs with the same subscript (number). The faulty temperature sensor detection operation may also be performed in the same manner between packages PKG4 to PKG7.

[0186] The first, second, and third modifications of the first embodiment can also be applied to the third embodiment.

[0187] 4. Fourth Embodiment The configuration of the information processing system 1F according to the fourth embodiment will now be described. In the information processing system 1F according to the fourth embodiment, the configuration of the temperature sensor 35F of the NAND chip CP and the sequencer 40F differs from that of the first embodiment. The following will focus on the differences from the first embodiment.

[0188] 4.1 NAND Chip Configuration The configuration of the NAND chip CP will be explained using Figure 33. Figure 33 is a block diagram showing an example of the configuration of a NAND chip CP. Figure 33 shows the configuration of one NAND chip CP included in the non-volatile memory 30. Other NAND chip CPs included in the non-volatile memory 30 have a similar configuration to that shown in Figure 33. Figure 33 also shows the memory controller 50.

[0189] As shown in Figure 33, the temperature sensor 35F measures the temperature of the NAND chip CP. The temperature sensor 35F is a temperature measurement circuit implemented within the semiconductor device 30, for example, by applying a bandgap reference circuit. Another example of the temperature sensor 35F is a thermocouple. For example, the temperature sensor 35F measures the temperature of the memory cell array 41 within the NAND chip CP. The temperature sensor 35F transmits the measured temperature as temperature sensor data Temp to the sequencer 40F. Note that the temperature sensor 35F does not have to directly measure the temperature of the memory cell array 41. For example, the temperature sensor 35F may measure the temperature of a location other than the memory cell array 41 within the NAND chip CP. Details of the temperature sensor 35F will be described later.

[0190] The sequencer 40F controls the operation of the entire NAND chip CP, similar to the first embodiment. For example, the sequencer 40F controls the ready / busy circuit 33, the voltage generation circuit 42, the raw decoder module 43, and the sense amplifier module 44 based on the command CMD stored in the command register 34a. For example, the sequencer 40F performs read, write, and erase operations. The sequencer 40F also stores the temperature sensor data Temp acquired from the temperature sensor 35F as status information STS in the status register 34c and outputs it to the memory controller 50 via the input / output circuit 31. Note that the temperature sensor data Temp may be output to the memory controller 50 as information other than status information STS, rather than as status information STS. Furthermore, the sequencer 40F stores the replacement temperature data TempR and the switching signal SigS received from the memory controller 50 in the first feature register 34d.

[0191] Furthermore, the PLC 40F acquires replacement temperature data TempR and a switching signal SigS from the first feature register 34d. Based on the switching signal SigS, the PLC 40F selects either the temperature sensor data Temp acquired from the temperature sensor 35F or the replacement temperature data TempR, and transmits the selected temperature data as the used temperature data TempU to the second feature register 34e. In other words, the NAND chip CP (PLC 40F) switches the used temperature data TempU based on the switching signal SigS. In this way, the PLC 40F can switch between the temperature measured by the temperature sensor 35F and the temperature input from an external source and output them as the used temperature data TempU.

[0192] 4.2 Temperature Sensor Configuration The configuration of the temperature sensor 35F of the NAND chip CP will be explained using Figure 34. Figure 34 is a circuit diagram showing an example of the configuration of the temperature sensor 35F. As shown in Figure 34, the temperature sensor 35F includes a temperature sensor element 36.

[0193] The temperature sensor element 36 measures the temperature. The temperature sensor element 36 outputs the measured temperature sensor data Temp to the outside of the temperature sensor 35F. The temperature sensor data Temp output to the outside of the temperature sensor 35F is transmitted to the sequencer 40F.

[0194] 4.3 Operation The faulty temperature sensor detection operation of the information processing system 1F will be described. The flowchart showing an example of the faulty temperature sensor detection operation in the information processing system 1F is the same as Figure 11 shown in the first embodiment.

[0195] In this embodiment, the memory controller 50 performs a faulty temperature sensor detection operation on the non-volatile memory 30 in the same manner as in the first embodiment.

[0196] 4.4 Effects of the Fourth Embodiment In the memory system 3F according to this embodiment, the temperature sensor 35F measures the temperature and transmits the measured temperature sensor data Temp to the sequencer 40F. Based on the switching signal SigS, the sequencer 40F switches between the temperature sensor data Temp obtained from the temperature sensor 35F and the replacement temperature data TempR input from an external source and outputs it as the used temperature data TempU. The used temperature data TempU output from the sequencer 40F is stored in the second feature register 34e. In this way, the used temperature data TempU can be rewritten in each NAND chip CP. As described above, this embodiment provides the same effects as the first embodiment.

[0197] The first, second, and third modifications of the first embodiment can also be applied to the fourth embodiment. Furthermore, the non-volatile memory 30 of the fourth embodiment can also be applied to the third embodiment.

[0198] 5. Others As described above, the memory system (3) according to the embodiment comprises a first semiconductor device (30) and a controller (50). The first semiconductor device (30) includes a first chip (CP0). The first chip (CP0) has a first temperature sensor (35). The controller (50) includes a comparison circuit (56) and a detection circuit (57). The comparison circuit (56) compares a first measured temperature (Temp0) measured by the first temperature sensor (35) with first temperature data (Temp1), outputs the result of the comparison as a first comparison result (ResA0), and compares the first measured temperature (Temp0) with second temperature data (Temp2), outputs the result of the comparison as a second comparison result (ResA2). The detection circuit (57) detects a malfunction in the first temperature sensor (35) based on the first comparison result (ResA0) and the second comparison result (ResA2), and outputs the detection result as the first detection result (ResD0=SigS0). The first chip (CP0) switches the first operating temperature (TempU0) based on the first detection result (ResD0=SigS0).

[0199] It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible.

[0200] Furthermore, the flowchart described in the above embodiment allows for rearranging the order of processing as much as possible.

[0201] In the above embodiment, the case where the semiconductor device 30 is a non-volatile memory was used as an example, but the semiconductor device 30 is not limited to a non-volatile memory. That is, the chip CP included in the semiconductor device 30 is not limited to NAND flash memory, but may be DRAM or SRAM. Furthermore, the chip CP included in the semiconductor device 30 may be other types of memory or other devices.

[0202] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0203] 1, 1A, 1B, 1C, 1D, 1E, 1F... Information processing system, 2, 2D... Host, 3, 3D, 3E, 3F... Memory system, 21... CPU, 22... Temperature sensor, 23... ROM, 24... RAM, 25... Communication interface circuit, 30, 30A, 30B... Semiconductor device, 31... Input / output circuit, 32... Logic control circuit, 33... Ready / busy circuit, 34... Register set, 34a... Command register, 34b... Address register, 34c... Status register, 34d... First feature register, 34e... Second feature register, 35, 35F... Temperature sensor, 36... Temperature sensor element, 37... First register, 38... Second register, 39... Multiplexer 40, 40F…Sequencer, 41…Memory cell array, 42…Voltage generation circuit, 43…Raw decoder module, 44…Sense amplifier module, 50, 50A, 50B, 50C, 50D…Memory controller, 51…Host interface circuit, 52…CPU, 53…ROM, 54…RAM, 55…Temperature sensor, 56, 56A, 56B…Comparison circuit, 57…Detection circuit, 58…Decision circuit, 59…OR circuit, 60-0~60-N…AND circuit, 61, 61A, 61B, 61C…Generation circuit, 62…Memory interface circuit, 70…Board, 80…Interface chip, 201…Acquisition unit, 202…Comparison unit, 203…Detection unit, 204…Generation unit, 205…Setting unit

Claims

1. A first semiconductor device including a first chip having a first temperature sensor, A comparison circuit that compares the first measured temperature measured by the first temperature sensor with the first temperature data, outputs the result of the comparison as the first comparison result, compares the first measured temperature with the second temperature data, and outputs the result of the comparison as the second comparison result, A detection circuit that detects a malfunction in the first temperature sensor based on the first and second comparison results and outputs the detection result as the first detection result. Including controllers and Equipped with, The first chip switches the first operating temperature based on the first detection result. Memory system.

2. The aforementioned controller, A generation circuit that generates a first input temperature corresponding to the first temperature sensor based on the first temperature data and the second temperature data. It further includes, If the first detection result indicates that the first temperature sensor is in a first state, the first chip uses the first measured temperature as the first operating temperature. If the first detection result indicates that the first temperature sensor is in a second state different from the first state, the first chip uses the first input temperature as the first operating temperature. The memory system according to claim 1.

3. The first semiconductor device is A second chip having a second temperature sensor A third chip having a third temperature sensor It further includes, The first temperature data is the temperature measured by the second temperature sensor. The aforementioned second temperature data is the temperature measured by the aforementioned third temperature sensor. The memory system according to claim 1.

4. The aforementioned comparison circuit is The absolute value of the difference between the first measured temperature and the first temperature data is output as the first comparison result. The absolute value of the difference between the first measured temperature and the second temperature data is output as the second comparison result. The memory system according to claim 1.

5. The first semiconductor device is A second chip having a second temperature sensor A third chip having a third temperature sensor It further includes, The first temperature data is the temperature measured by the second temperature sensor. The aforementioned second temperature data is the temperature measured by the aforementioned third temperature sensor. The first chip is physically adjacent to the second chip and the third chip. The memory system according to claim 4.

6. The aforementioned detection circuit is A determination circuit that determines whether the first comparison result is smaller than a first threshold and outputs the result of the determination as the first determination result, determines whether the second comparison result is smaller than the first threshold and outputs the result of the determination as the second determination result, An AND circuit performs an AND operation on the first determination result and the second determination result, and transmits the result of the AND operation to the first chip as the first detection result. including, The memory system according to claim 4.

7. If the first comparison result is smaller than the first threshold, the determination circuit outputs the first value as the first determination result. If the first comparison result is greater than or equal to the first threshold, the determination circuit outputs the second value as the first determination result. If the second comparison result is smaller than the first threshold, the determination circuit outputs the third value as the second determination result. If the second comparison result is greater than or equal to the first threshold, the determination circuit outputs the fourth value as the second determination result. If the first determination result is the first value and the second determination result is the third value, the AND circuit outputs a fifth value as the first detection result indicating that the first temperature sensor is in a first state. If the first determination result is the first value and the second determination result is the fourth value, if the first determination result is the second value and the second determination result is the third value, or if the first determination result is the second value and the second determination result is the fourth value, the AND circuit outputs a sixth value as the first detection result, indicating that the first temperature sensor is in a second state different from the first state. The memory system according to claim 6.

8. The aforementioned detection circuit is An OR circuit performs an OR operation on the first and second determination results and outputs the result of the OR operation as a second detection result. This also includes, The memory system according to claim 6.

9. The aforementioned generation circuit is The average value of the first temperature data and the second temperature data is output as the first input temperature. The memory system according to claim 2.

10. The first semiconductor device is A second chip having a second temperature sensor A third chip having a third temperature sensor It further includes, The first temperature data is the temperature measured by the second temperature sensor. The aforementioned second temperature data is the temperature measured by the aforementioned third temperature sensor. The first chip is physically adjacent to the second chip and the third chip. The memory system according to claim 9.

11. The aforementioned controller, Second temperature sensor, A generation circuit that generates the second measured temperature measured by the second temperature sensor as the first input temperature corresponding to the first temperature sensor. It further includes, If the first detection result indicates that the first temperature sensor is in a first state, the first chip uses the first measured temperature as the first operating temperature. If the first detection result indicates that the first temperature sensor is in a second state different from the first state, the first chip uses the first input temperature as the first operating temperature. The memory system according to claim 1.

12. The first semiconductor device is Second chip having a second temperature sensor It further includes, The aforementioned controller, Third temperature sensor It further includes, The first temperature data is the temperature measured by the second temperature sensor. The aforementioned second temperature data is the temperature measured by the aforementioned third temperature sensor. The memory system according to claim 1.

13. A second semiconductor device including a second chip having a second temperature sensor. Furthermore, The comparison circuit compares the second measured temperature measured by the second temperature sensor with the third temperature data, outputs the result of the comparison as the third comparison result, compares the second measured temperature with the fourth temperature data, outputs the result of the comparison as the fourth comparison result, The detection circuit detects a malfunction in the second temperature sensor based on the third and fourth comparison results, and outputs the detection result as the second detection result. The second chip switches the second operating temperature based on the second detection result. The memory system according to claim 1.

14. The aforementioned controller, A generation circuit that generates a second input temperature corresponding to the second temperature sensor based on the third temperature data and the fourth temperature data. It further includes, If the second detection result indicates that the second temperature sensor is in the first state, the second chip uses the second measured temperature as the second operating temperature. If the second detection result indicates that the second temperature sensor is in a second state different from the first state, the second chip uses the second input temperature as the second operating temperature. The memory system according to claim 13.

15. The memory system according to claim 1, Host and, Equipped with, The aforementioned controller, Second temperature sensor It further includes, The aforementioned host, Third temperature sensor Includes, The first temperature data is the temperature measured by the second temperature sensor. The aforementioned second temperature data is the temperature measured by the aforementioned third temperature sensor. Information processing system.

16. A first semiconductor device including a first chip having a first temperature sensor, A controller that controls the first semiconductor device and A memory system including, A comparison unit compares the first measured temperature measured by the first temperature sensor with the first temperature data, outputs the result of the comparison as the first comparison result, compares the first measured temperature with the second temperature data, and outputs the result of the comparison as the second comparison result. A detection unit detects a malfunction in the first temperature sensor based on the first and second comparison results, and outputs the detection result as the first detection result. including hosts and Equipped with, The first chip switches the first operating temperature based on the first detection result. Information processing system.

17. The aforementioned host, A generation unit generates a first input temperature corresponding to the first temperature sensor based on the first temperature data and the second temperature data. It further includes, If the first detection result indicates that the first temperature sensor is in a first state, the first chip uses the first measured temperature as the first operating temperature. If the first detection result indicates that the first temperature sensor is in a second state different from the first state, the first chip uses the first input temperature as the first operating temperature. The information processing system according to claim 16.

18. First chip having a first temperature sensor Equipped with, The first chip switches a first operating temperature based on a first signal input from an external source. Semiconductor devices.

19. The first temperature sensor is A first register that stores the measured temperature, A second register that stores the temperature input from an external source, A multiplexer that receives the first measured temperature stored in the first register and the first input temperature stored in the second register, and switches between the first measured temperature and the first input temperature based on the first signal to output the first operating temperature. including, The semiconductor device according to claim 18.

20. The first chip is A third register that stores the first signal and the first input temperature, The fourth register that stores the first operating temperature and This also includes, The semiconductor device according to claim 19.

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