Semiconductor memory

Abstract

To provide a semiconductor memory device that can be suitably manufactured. [Solution] The semiconductor memory device comprises a first chip and a second chip bonded together via a plurality of bonding electrodes, and the first chip and the second chip are provided with an edge seal region (R) that surrounds the memory area. ES The second chip has an edge seal area (R ES The memory area is provided with a plurality of spaced-apart edge seals surrounding the periphery of the memory area, a first wiring layer, and a second wiring layer, wherein the first wiring layer is provided at a position that overlaps with a plurality of first edge seals, excluding the outermost one when viewed from a first direction, and is electrically connected to the plurality of first edge seals, and comprises a plurality of second conductive layers provided at a position that overlaps with the outermost second edge seal when viewed from a first direction, and is not electrically connected to the second edge seal, and is spaced apart from the second edge seal.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, semiconductor layers facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layers. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (SiN) or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-026518 [Patent Document 2] Japanese Patent Publication No. 2015-041743 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that can be suitably manufactured. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises a first chip and a second chip bonded together via a plurality of bonding electrodes, the first chip and the second chip each comprising a memory region including a memory cell array or peripheral circuits connected to a memory cell array, and an edge seal region provided to surround the memory region, the first chip comprising a semiconductor substrate and a plurality of first conductive layers provided in the edge seal region and each connected to the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate, the second chip comprising a plurality of edge seals in the edge seal region each extending along the first direction and provided to surround the memory region when viewed from the first direction, spaced apart from the inner circumference to the outer circumference of the edge seal region, a first wiring layer provided on the second chip side relative to the plurality of edge seals, and a first wiring layer The first wiring layer is provided on the second chip side and comprises a second wiring layer having a plurality of wirings including tungsten (W). The first wiring layer is provided in the edge seal region and is provided in a position that overlaps with a plurality of first edge seals, excluding the outermost one when viewed from the first direction, when viewed from the first direction, and comprises a plurality of second conductive layers electrically connected to the plurality of first edge seals. The second wiring layer is provided in the edge seal region and is provided in a position that overlaps with a plurality of first edge seals when viewed from the first direction, and comprises a plurality of third conductive layers connected to the plurality of first edge seals. The fourth conductive layer is provided in the edge seal region and is provided on the outermost side of the plurality of third conductive layers when viewed from the first direction, and is not electrically connected to the outermost second edge seal when viewed from the first direction, and is spaced apart from the second edge seal. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 3] This is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 4] This is a schematic bottom view showing an enlarged portion of Figure 2. [Figure 5]This is a schematic plan view showing an example of the configuration of a chip CP. [Figure 6] This is a schematic plan view showing an enlarged portion of Figure 5. [Figure 7] This is a schematic cross-sectional view showing a portion of the configuration of a memory die (MD). [Figure 8] This is a schematic cross-sectional view showing an enlarged portion of Figure 7. [Figure 9] This is a schematic cross-sectional view showing an enlarged portion of Figure 8. [Figure 10] This is a schematic cross-sectional view showing an example of the configuration of the edge seal region and kerf region according to the first embodiment. [Figure 11] This is a schematic bottom view illustrating the method for manufacturing a semiconductor memory device according to the first embodiment. [Figure 12] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 13] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 14] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 15] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 16] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 17] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 20] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 21] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 22] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 23] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 24] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 25] This is a schematic plan view illustrating the manufacturing method. [Figure 26] This is a schematic perspective view illustrating the manufacturing method. [Figure 27] This is a schematic perspective view illustrating the manufacturing method. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 29] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic plan view showing the arrangement of multiple edge seals in the edge seal region and the arrangement of the wiring layer M1 according to Example 1 of the first embodiment. [Figure 32] This is a schematic plan view showing an enlarged portion of Figure 31. [Figure 33] This is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the edge seal ES6 when cut along the dotted line EE' in Figure 31. [Figure 34] This is a schematic plan view showing the arrangement of multiple edge seals in the edge seal region and the arrangement of the wiring layer M1 according to Embodiment 2 of the first embodiment. [Figure 35] This is a schematic plan view showing an enlarged portion of Figure 34. [Figure 36] This is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the edge seal ES6 when cut along the dotted line of FF' in Figure 34. [Figure 37] This is a schematic plan view showing the arrangement of multiple edge seals in the edge seal region and the arrangement of the wiring layer M1 according to Embodiment 3 of the first embodiment. [Figure 38] This is a schematic plan view showing an enlarged portion of Figure 37. [Figure 39]This is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the edge seal ES6 when cut along the dotted line GG' in Figure 37. [Figure 40] This is a schematic plan view showing the arrangement of multiple edge seals in the edge seal region and the arrangement of the wiring layer M1 according to Embodiment 4 of the first embodiment. [Figure 41] This is a schematic plan view showing an enlarged portion of Figure 40. [Figure 42] This is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the edge seal ES6 when cut along the dotted line HH' in Figure 40. [Figure 43] This is a schematic plan view showing the arrangement of multiple edge seals in the edge seal region and the arrangement of the wiring layer M1 according to Example 5 of the first embodiment. [Figure 44] This is a schematic plan view showing an enlarged portion of Figure 43. [Figure 45] This is a schematic cross-sectional view showing the structure of the edge seal ES6 and the conductive layer below the edge seal ES6 according to another embodiment. [Figure 46] This is a schematic cross-sectional view showing the structure of the edge seal ES6 and the conductive layer below the edge seal ES6 according to another embodiment. [Figure 47] This is a schematic cross-sectional view showing the structure of the edge seal ES6 and the conductive layer below the edge seal ES6 according to another embodiment. [Figure 48] This is a schematic cross-sectional view showing the structure of the edge seal ES6 and the conductive layer below the edge seal ES6 according to another embodiment. [Figure 49] This is a schematic plan view showing the arrangement of multiple edge seals in the edge seal region according to another embodiment, and the arrangement of wiring layers M0 and M1. [Figure 50] This is a schematic cross-sectional view showing the structure of the wiring layers M0 and M1 located below the edge seal ES6 when cut along the dotted line II' in Figure 49. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die after dicing, or to a wafer before dicing. In the former case, it may also refer to a memory die after packaging, or to a memory die before packaging. In the latter case, it may refer to a wafer before lamination, or to a wafer after lamination.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the surface of the substrate is referred to as the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, when expressions such as "upper" and "lower" are used in this specification, for example, among two chips or two wafers included in a memory die or wafer, the one with external pad electrodes that can be connected to bonding wires may be referred to as the upper side, and the one without such external pad electrodes may be referred to as the lower side. In addition, when referring to a configuration included in a memory die or wafer, for example, the direction away from the semiconductor substrate included in the lower wafer along the Z direction may be referred to as the upper side, and the direction approaching the semiconductor substrate included in the lower wafer along the Z direction may be referred to as the lower side. Also, when referring to a certain configuration as the lower surface or lower end, it means the surface or end on the semiconductor substrate side included in the lower wafer of that configuration, and when referring to the upper surface or upper end, it means the surface or end on the opposite side from the semiconductor substrate included in the lower wafer of that configuration. Furthermore, a surface that intersects the X direction or Y direction may be referred to as a side, etc.

[0015] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0016] [First Embodiment] [Memory die MD structure] FIG. 1 is a schematic exploded perspective view showing a configuration example of a semiconductor memory device according to the present embodiment. As shown in FIG. 1, the memory die MD includes a chip C on the memory cell array side P and a chip C on the peripheral circuit side P and.

[0017] On the upper surface of the chip C M a plurality of external pad electrodes P that can be connected to bonding wires (not shown) X are provided. Also, on the lower surface of the chip C M a plurality of bonding electrodes P I1 are provided. Also, on the upper surface of the chip C P a plurality of bonding electrodes P I2 are provided. Hereinafter, for the chip C <00​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​ Note that in the example in Figure 1, chip C M The corners a1, a2, a3, and a4 are, respectively, chip C P These correspond to corners b1, b2, b3, and b4.

[0020] Figures 2 and 3 show chip C M This is a schematic bottom view showing an example of the configuration. Figure 3 shows the bonded electrode P I1 Some components, such as those shown, have been omitted. Figure 4 is a schematic bottom view showing an enlarged portion of Figure 2. Figure 5 shows chip C P This is a schematic plan view showing an example of the configuration. Figure 6 is a schematic plan view showing an enlarged portion of Figure 5. Figure 7 is a schematic cross-sectional view showing a part of the configuration of the memory die MD. Figure 8 is a schematic cross-sectional view showing an enlarged portion of Figure 7. Figure 9 is a schematic cross-sectional view showing an enlarged portion of Figure 8. Although Figure 9 shows a YZ cross-section, a similar structure to that in Figure 9 can be observed when observing cross-sections other than the YZ cross-section along the central axis of the semiconductor layer 120 (for example, an XZ cross-section).

[0021] [Chip C M [Structure] Chip C M For example, as shown in Figure 2, there are four memory plane regions R aligned in the X and Y directions. MP It is equipped with chip C. M This consists of four memory plane regions R MP A peripheral region R located on one end in the Y direction P It is equipped with the surrounding area R P This consists of multiple input / output regions R aligned in the X direction. IO It is equipped with chip C. M These four memory plane regions R MP and multiple input / output regions R IO Edge seal region R surrounding ES A feature is provided. Also, as shown in Figure 4, the edge seal region R ES Outside of it is the calf region R K A feature is provided. Furthermore, the calf region R KEven after dicing, some may remain, but not all of them. In the following explanation, the edge seal region R ES The inner region (four memory plane regions R) MP and surrounding region R P The region including the memory region R M It is sometimes called that.

[0022] Chip C M For example, as shown in Figure 7, the base structure L SB and the base structure L SB Memory cell array layer L located below MCA1 ,L MCA2 and memory cell array layer L MCA1 ,L MCA2 It comprises a plurality of wiring layers CH, M0, M1, MB located below it, and a memory cell array layer L MCA1 ,L MCA2 Each of these consists of multiple word line layers L aligned in the Z direction. WL It includes multiple word line layers L aligned in the Z direction. WL An insulating layer 111 made of silicon oxide (SiO2) or the like is provided between them.

[0023] [Chip C M Substrate structure L SB [Structure] For example, as shown in Figure 7, the base structure L SB The memory cell array layer L MCA1 It comprises a conductive layer 100 provided on the upper surface, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back wiring layer MA.

[0024] The conductive layer 100 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may contain a metal such as tungsten (W), or it may contain a silicide such as tungsten silicide (WSi).

[0025] The conductive layer 100 functions as part of the source lines of the NAND flash memory. The conductive layer 100 consists of four memory plane regions R aligned in the X and Y directions. MP Four are provided corresponding to (Figure 2). Memory plane area R MP Regions VZ that do not include the conductive layer 100 are provided at the ends in the X and Y directions.

[0026] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0027] The back wiring layer MA includes multiple wirings ma. These multiple wirings ma may include, for example, aluminum (Al).

[0028] Some of the multiple wirings ma function as part of the source lines of the NAND flash memory. These wirings ma are aligned in the X and Y directions across four memory plane regions R. MP There are four of these, corresponding to (Figure 2). Each of these wirings ma is electrically connected to the conductive layer 100.

[0029] Furthermore, some of the multiple wirings ma are external pad electrodes P X This function is achieved by connecting multiple input / output regions R aligned in the X direction. IO Multiple connections are provided corresponding to (Figure 2). This wiring ma is located in the memory cell array layer L in region VZ that does not include the conductive layer 100. MCA1 ,L MCA2 It is connected to the via contact electrode CC inside. In addition, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0030] The insulating layer 102 is a passivation layer that includes, for example, a resin material such as polyimide in its upper layer.

[0031] [Chip C M Memory cell array layer L MCA1 ,L MCA2 Memory plane region R MP [Structure in] For example, as shown in Figure 3, the memory cell array layer L MCA1 ,L MCA2 Multiple memory blocks BLK are provided, aligned in the Y direction. As shown in Figure 7, an interblock structure ST is provided between two adjacent memory blocks BLK in the Y direction.

[0032] The memory block BLK consists of multiple word line layers L, as shown in Figure 8, for example. WL The device comprises a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0033] The conductive layer 110 has a substantially plate-like shape that is stretched in the X direction. The conductive layer 110 may also contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, the conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B).

[0034] Furthermore, one or more of the conductive layers 110 located at the top of the multiple conductive layers 110 function as the select gate line of the NAND flash memory and the gate electrodes of the multiple select transistors connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0035] Furthermore, the multiple conductive layers 110 located below this function as the word lines of the NAND flash memory and the gate electrodes of the multiple memory cells (memory transistors) connected thereto. Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0036] One or more conductive layers 110 located below this also function as select gate lines of the NAND flash memory and gate electrodes of a plurality of select transistors connected thereto. These plurality of conductive layers 110 have a smaller width in the Y direction than other conductive layers 110. An insulating layer SHE such as silicon oxide (SiO2) is provided between two adjacent conductive layers 110 in the Y direction.

[0037] The semiconductor layers 120 are arranged in a predetermined pattern in the X and Y directions. The semiconductor layers 120 function as memory cells of the NAND flash memory and channel regions of select transistors. The semiconductor layers 120 include, for example, polycrystalline silicon (Si) or the like. The semiconductor layers 120 have a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the central portion.

[0038] The semiconductor layer 120 is the semiconductor region 120 included in the memory cell array layer L MCA1 and the semiconductor region 120 included in the memory cell array layer L L and is provided with. Further, the semiconductor layer 120 includes a semiconductor region 120 connected to the lower end of the semiconductor region 120 MCA2 and the semiconductor region 120 included in the memory cell array layer L U and a semiconductor region 120 connected to the upper end of the semiconductor region 120 L and an impurity region 122 connected to the upper end of the semiconductor region 120 U and an impurity region 121 connected to the lower end of the semiconductor region 120 J and is provided with. L and an impurity region 122 connected to the upper end of the semiconductor region 120 U and an impurity region 121 connected to the lower end of the semiconductor region 120

[0039] The semiconductor region 120 L has a substantially cylindrical shape extending in the Z direction. The outer peripheral surfaces of the semiconductor regions 120 L are respectively surrounded by a plurality of conductive layers 110 included in the memory cell array layer L MCA1 and face these plurality of conductive layers 110. Incidentally, the radial width W L of the upper end portion of the semiconductor region 120 120LL is smaller than the radial width W L of the lower end portion of the semiconductor region 120 120LU

[0040] Semiconductor field 120 U It has a substantially cylindrical shape that extends in the Z direction. Semiconductor region 120 U The outer surfaces are each the memory cell array layer L MCA2 It is surrounded by multiple conductive layers 110 and faces these multiple conductive layers 110. U The radial width W of the upper end 120UL Semiconductor area 120 U The radial width W of the lower end 120UU and the above width W 120LU It is smaller than that.

[0041] Semiconductor field 120 J These are memory cell array layer L MCA1 The memory cell array layer L is located below the multiple conductive layers 110 included in the MCA2 It is located above the multiple conductive layers 110 included in the semiconductor region 120. J Radial width W 120J The above width W 120LU ,W 120UU It is larger than that.

[0042] The impurity region 122 is connected to the conductive layer 100. In the example in Figure 8, the semiconductor region 120 L The boundary between the sample and the impurity region 122 is indicated by a dashed line. The impurity region 122 contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0043] The impurity region 121 contains, for example, N-type impurities such as phosphorus (P). In the example in Figure 8, the semiconductor region 120 U The boundary line between the impurity region 121 and the surrounding area is indicated by a dashed line. The impurity region 121 is connected to the bit line BL via wiring ch and wiring Vy (Figure 7).

[0044] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 laminated between the semiconductor layer 120 and the conductive layer 110, as shown in Figure 9, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2). The charge storage film 132 includes, for example, a charge-storing film such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 100. Furthermore, as shown in Figure 8, an insulating layer 126 made of silicon oxide (SiO2) or the like is provided between the gate insulating film 130 and the conductive layer 100.

[0045] Figure 9 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0046] The interblock structure ST includes, for example, a conductive layer 141 extending in the Z and X directions, and an insulating layer 142 provided on the side surface of the conductive layer 141, as shown in Figure 8. The conductive layer 141 is connected to the conductive layer 100. The conductive layer 141 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions, for example, as part of the source line of the NAND flash memory.

[0047] [Chip C M Memory cell array layer L MCA1 ,L MCA2 The surrounding region R P [Structure in] Surrounding region R P For example, as shown in Figure 7, the external pad electrode P X In response, multiple via contact electrodes CC are provided. These multiple via contact electrodes CC have an external pad electrode P at their upper end. XIt is connected to the wiring ma which functions as

[0048] [Chip C M [Structure of wiring layers CH, M0, M1, MB] For example, as shown in Figure 7, multiple wirings included in wiring layers CH, M0, M1, MB are, for example, in the memory cell array layer L MCA1 ,L MCA2 Configuration and chip C P It is electrically connected to at least one of the internal components.

[0049] The wiring layer CH includes multiple wirings, namely multiple wirings ch. These multiple wirings ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The wirings ch are provided corresponding to multiple semiconductor layers 120 and are connected to the lower ends of the multiple semiconductor layers 120.

[0050] The wiring layer M0 includes multiple wirings m0. These multiple wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Some of the multiple wirings m0 function as bit lines BL. The bit lines BL are, for example, aligned in the X direction and extended in the Y direction.

[0051] The wiring layer M1 includes a plurality of wirings m1, as shown in Figure 7, for example. These plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0052] The wiring layer MB consists of multiple bonded electrodes P I1 This includes multiple bonded electrodes P. I1 For example, a barrier conductive film p such as titanium nitride (TiN) I1B and metal films such as copper (Cu) p I1M It may also contain a multilayer film, etc.

[0053] Furthermore, as shown in Figure 4, the edge seal region R ESIn this configuration, wiring layers CH, M0, and M1 have line-and-space patterns p that extend along the four sides of the memory die MD. M1 It is also acceptable for a line and space pattern p to be formed in the wiring layer MB. M1 At least a part of it may be formed.

[0054] [Chip C P [Structure] Chip C P For example, as shown in Figure 5, the memory plane region R MP Corresponding to this, there are four peripheral circuit regions R aligned in the X and Y directions. PC It is equipped with chip C. P This is the surrounding region R P Circuit region R located in the region opposite to C It includes the following: Circuit region R C This consists of multiple input / output regions R aligned in the X direction. IO It is equipped with chip C. P These four peripheral circuit regions R PC and input / output region R IO Edge seal region R surrounding ES A feature is provided. Also, as shown in Figure 6, the edge seal region R ES Outside of it is the calf region R K A chip C is provided. M Similarly, chip C P In the calf region R K Some of it may remain after dicing, but not all of it. Tip C M Similarly, chip C P However, in the following explanation, the edge seal region R ES The inner region (four peripheral circuit regions R) PC and circuit region R C The region including the memory region R M It is sometimes called that.

[0055] Also, chip C PAs shown in Figure 7, for example, the device comprises a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, and wiring layers D0, D1, D2, D3, D4, DB provided above the electrode layer GC.

[0056] [Chip C P [Structure of semiconductor substrate 200] The semiconductor substrate 200 contains, for example, p-type silicon (Si) containing p-type impurities such as boron (B). The surface of the semiconductor substrate 200 is provided with, for example, an N-type well region 200N containing an N-type impurity such as phosphorus (P), a p-type well region 200P containing a p-type impurity such as boron (B), a semiconductor substrate region 200S where the N-type well region 200N and the p-type well region 200P are not provided, and an insulating region 200I. The N-type well region 200N, the p-type well region 200P, and the semiconductor substrate region 200S each function as part of a plurality of transistors Tr and a plurality of capacitors etc. that constitute a peripheral circuit.

[0057] Furthermore, as shown in Figure 6, the edge seal region R ES In this configuration, the surface of the semiconductor substrate 200 has a line-and-space pattern p extending along the four sides of the memory die MD, formed by the semiconductor substrate region 200S and the insulating region 200I. P1 It is acceptable if a structure is formed.

[0058] [Chip C P [Structure of the electrode layer GC] For example, as shown in Figure 7, an electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200 in the Z direction. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are each connected to a via contact electrode CS.

[0059] The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S of the semiconductor substrate 200 function as channel regions for multiple transistors Tr that constitute the peripheral circuit, and as one electrode of multiple capacitors, respectively.

[0060] The multiple electrodes gc contained in the electrode layer GC each function as the gate electrode of multiple transistors Tr that constitute the peripheral circuit, and as the other electrode of multiple capacitors, etc.

[0061] The via contact electrode CS extends in the Z direction and is connected at its lower end to the semiconductor substrate 200 or the upper surface of electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0062] Furthermore, the electrode layer GC also has the pattern p explained with reference to Figure 6. P1 It is acceptable if a structure is formed.

[0063] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4, DB] For example, as shown in Figure 7, the multiple wirings included in D0, D1, D2, D3, D4, DB are, for example, in the memory cell array layer L MCA1 ,L MCA2 Configuration and chip C P It is electrically connected to at least one of the internal components.

[0064] Each wiring layer D0, D1, and D2 contains multiple wirings d0, d1, and d2, respectively. These multiple wirings d0, d1, and d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0065] Each wiring layer D3 and D4 contains multiple wirings d3 and d4, respectively. These multiple wirings d3 and d4 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0066] The wiring layer DB consists of multiple bonded electrodes P I2This includes multiple bonded electrodes P. I1 For example, a barrier conductive film p such as titanium nitride (TiN) I2B and metal films such as copper (Cu) p I2M It may also contain a multilayer film, etc.

[0067] Here, the bonded electrode P I1 and bonded electrode P I2 and a metal film such as copper (Cu) p I1M ,p I2M Using this method, the metal film p I1M and metal film p I2M The two become integrated, making it difficult to confirm their boundaries. However, the bonded electrode P may be misaligned during bonding. I1 and bonded electrode P I2 Distortion of the shape when the two are bonded together, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the misalignment (occurrence of discontinuities on the side). Also, bonded electrode P I1 and bonded electrode P I2 When formed by a damascene process, each side has a tapered shape. Therefore, the bonded electrode P I1 and bonded electrode P I2 The cross-sectional shape along the Z-direction at the point where the two are bonded together is not a straight line, but rather a non-rectangular shape. Furthermore, the bonded electrode P I1 and bonded electrode P I2 When these are bonded together, the barrier metal covers the bottom, sides, and top surfaces of each Cu component forming them. In contrast, in a typical Cu wiring layer, an insulating layer (such as SiN or SiCN) with an oxidation prevention function for Cu is provided on the top surface of the Cu, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0068] Furthermore, the wiring layers D0, D1, D2, D3, and D4 also have the pattern p explained in Figure 6. P1 It is also acceptable for a pattern p, as explained with reference to Figure 6, to be formed in the wiring layer DB. P1 At least a part of it may be formed.

[0069] [Edge seal area R ES Structures such as Figure 10 shows the edge seal region R according to the first embodiment. ES and calf region R K This is a schematic cross-sectional view showing an example of its configuration.

[0070] Edge seal area R ES Memory cell array layer L MCA1 ,L MCA2 Multiple edge seals ES1 to ES6 are provided.

[0071] Edge seals ES1 to ES6 each extend along the Z direction, and in the XY plane viewed from the Z direction, they form a memory region R M A ring-shaped structure is provided in the outer region, and the edge seal region R ES They are spaced apart from the inner circumference to the outer circumference. The edge seals ES1 to ES6 are formed simultaneously with the interblock structure ST described with reference to Figure 8, and like the interblock structure ST, they include, for example, a conductive layer such as tungsten and an insulating layer provided on the side surface of this conductive layer. The edge seals ES1 to ES6 play a role in preventing cracks that occur when the wafer is diced to cut out individual semiconductor chips, and in preventing contaminants such as impurity ions from entering from the outside. The edge seals ES1 to ES6 are located in the memory area R M Although it is provided to completely surround the memory region R, it may also be provided to only a part of it. However, at least one of the edge seals ES2 and ES3 is located in the memory region R. M It is provided to completely surround it. The edge seals ES1 to ES6 are also sometimes referred to as guard rings, seal rings, or crack stoppers.

[0072] Edge seal ES1 is the innermost of the edge seals ES1 to ES6 when viewed from the Z direction (edge ​​seal region R). ES This is an edge seal located on the memory area side. The edge seal ES1 is connected to wiring ch, m0, m1, but the bonding electrode P of the wiring layer MB is connected to it. I1It is not connected to the edge seal ES1. Specifically, as shown in Figure 10, the edge seal ES1 is connected to the wiring ch at a position where it overlaps when viewed from the Z direction, and is electrically connected to the wirings Vy, m0, V1, m1 at a position where it overlaps when viewed from the Z direction. However, the edge seal ES1 and the bonded electrode P I1 It is not electrically connected to it. Also, below the edge seal ES1 is the bonding electrode P. I1 It is not provided.

[0073] The edge seals ES2 and ES3 are located outside the edge seal ES1 when viewed from the Z direction. In the example shown in Figure 10, the edge seal ES3 is located outside the edge seal ES2 when viewed from the Z direction. The edge seals ES2 and ES3 are connected to wiring layers CH, M0, M1, and MB. Specifically, as shown in Figure 10, the edge seals ES2 and ES3 are connected to wiring ch at overlapping positions when viewed from the Z direction, and to wiring Vy, m0, V1, m1, VB, and the bonded electrode P at overlapping positions when viewed from the Z direction. I1 It is electrically connected to edge seals ES2 and ES3, and further bonded to electrode P I2 and chip C P It is electrically connected to the multiple wires d0, d1, d2, d3, d4 above. Also, the edge seals ES2, ES3 are connected to the wire ma of the back wiring layer MA. As a result, the edge seals ES2, ES3 are connected to the chip C M The charge accumulated during the manufacturing process of chip C M The semiconductor substrate on which the seals are formed can release (discharge) the static electricity. In addition, the edge seals ES2 and ES3 allow impurities such as hydrogen to enter the memory area R from the outside. M This can prevent intrusion.

[0074] The edge seal ES5 is located outside the edge seal ES3 when viewed from the Z direction. The edge seal ES5 is connected to wiring ch, m0, m1, but to the bonding electrode P of the wiring layer MB. I1They are not connected. Specifically, as shown in Figure 10, the edge seal ES5 is connected to the wiring ch at a position where it overlaps when viewed from the Z direction, and is electrically connected to the wirings Vy, m0, V1, m1 at a position where it overlaps when viewed from the Z direction. However, the edge seal ES5 and the bonded electrode P I1 It is not electrically connected to the memory area R. The edge seal ES5 prevents impurities such as hydrogen from entering the memory area from the outside. M It can prevent intrusion into the kerf region R of the outer edge of the chip during the dicing process. K Cracks or peeling resulting from this cause memory area R M This can suppress its propagation.

[0075] Edge seal ES6 is the outermost edge seal region (R) among edge seals ES1 to ES6 when viewed from the Z direction. ES The most calf area within R K It is provided on the side of ( ). The edge seal ES6 is connected to wiring ch but not to wiring m1. Specifically, below the edge seal ES6, there are no wiring layers M0 and MB, and wiring m1 of wiring layer M1 is provided, spaced apart from the edge seal ES6 and not electrically connected.

[0076] [Manufacturing method] Next, the manufacturing method of the memory die MD will be described with reference to Figures 11 to 30. Figures 11 and 25 are schematic bottom views illustrating the manufacturing method. Figures 12 to 24 are schematic cross-sectional views illustrating the manufacturing method. Figures 26 and 27 are schematic perspective views illustrating the manufacturing method. Note that Figures 12 to 24 show cross-sections corresponding to Figure 10.

[0077] When manufacturing the memory die MD according to this embodiment, chip C M Wafer W corresponding to M , and chip C P Wafer W corresponding to P These two wafers W are manufactured (see Figure 26) M ,W PAfter bonding the materials together (see Figure 27) and forming the back wiring layer MA (Figure 7), the material is divided into individual pieces by dicing.

[0078] [WaferW M [Manufacturing method] Figure 11 shows wafer W M This shows the surface of the semiconductor substrate 150 corresponding to R. As shown in Figure 11, the surface of the semiconductor substrate 150 has multiple memory regions R M And these multiple memory regions R M Calf region R provided between K And, multiple memory regions R are provided. M After dicing, it becomes the memory die MD. Note that the kerf region R K The internal configuration is not used for voltage input / output to the memory cell array, nor for input / output of data signals or other signals to the memory cell array.

[0079] Wafer W M In the manufacturing process, for example, as shown in Figure 12, an insulating layer 112 made of silicon oxide (SiO2) or the like is formed on the surface of the semiconductor substrate 150. Next, a semiconductor layer 100A made of silicon or the like is formed on the surface of the insulating layer 112. This process is carried out by, for example, CVD (Chemical Vapor Deposition) or thermal oxidation. These processes are carried out by, for example, CVD or thermal oxidation.

[0080] Next, as shown in Figure 13, for example, the edge seal region R is formed by a method such as CVD (Chemical Vapor Deposition). ES and calf region R K Multiple insulating layers 111 and multiple sacrificial layers 110A are alternately formed on the semiconductor layer 100A. Also, the edge seal region R ES A resist 162 is formed in a portion of the region excluding the rest.

[0081] Next, the sacrificial layer 110A and the insulating layer 111 are removed once each, and by repeating the removal of a portion of the resist 162, a stepped structure is formed for connecting the conductive layer 110 (as explained with reference to Figure 8, etc.) and a contact electrode (not shown). In the example of Figure 14, the kerf region R K and edge seal region R ES A stepped structure is also formed at the boundary between the two. These processes are carried out, for example, by methods such as wet etching or dry etching.

[0082] Next, as shown in Figure 15, for example, the kerf region R K On the surface of the structure shown in Figure 14, there is an edge seal region R ES and calf region R K Next, an insulating layer 113 is formed. Then, multiple insulating layers 111 and multiple sacrificial layers 110A are formed alternately. These steps are carried out by methods such as CVD. Also, the edge seal region R ES A resist 163 is formed in a portion of the region excluding the rest.

[0083] Next, the sacrificial layer 110A and the insulating layer 111 are removed once each, and this process is repeated to remove a portion of the resist 163, thereby forming the stepped structure described above. In the example shown in Figure 16, the kerf region R K and edge seal region R ES A stepped structure is also formed at the boundary between the two. These processes are carried out, for example, by methods such as wet etching or dry etching.

[0084] Next, as shown in Figure 17, for example, an insulating layer 113 made of silicon oxide (SiO2) or the like is formed on the surface of the structure shown in Figure 16. This step is carried out by, for example, CVD.

[0085] Next, as shown in Figure 18, for example, a resist 164 is formed with openings in the regions corresponding to the edge seals ES1 to ES6 (Figure 10), and the insulating layer 113 at the positions corresponding to the edge seals ES1 to ES6 is removed to form grooves EST1 to EST6. The grooves EST1 to EST6 extend in the Z and X directions, penetrate the insulating layer 113, and expose the surface of the semiconductor layer 100A. This process is carried out by a method such as RIE (Reactive Ion Etching). In addition, the grooves EST1 to EST6 are located in the memory plane region R (not shown in the figure). MP and calf region R K The grooves that form the interblock structure ST (Figure 7) are formed simultaneously. Although not shown in the illustration, in this process the kerf region R K Grooves are also formed there.

[0086] Next, as shown in Figure 19, for example, the sacrificial layer 110A is removed through the grooves formed in the process described with reference to Figure 18, and the conductive layer 110 is formed. This replaces the sacrificial layer 110A with the conductive layer 110. The process of removing the sacrificial layer 110A is carried out by a method such as wet etching, and the process of forming the conductive layer 110 is carried out by a method such as CVD. Subsequently, the interblock structure ST (Figure 7) is formed in the grooves, and the edge seals ES1 to ES6 are formed in the grooves EST1 to EST6. This process is carried out by a method such as CVD and RIE.

[0087] Next, as shown in Figures 20 and 21, for example, wiring channels are formed by a damascene process.

[0088] For example, as shown in Figure 20, through holes are formed at positions corresponding to wiring ch, exposing one end of edge seals ES1 to ES6, and conductive layer chB is formed inside these through holes and on the surface of the insulating layer 113. The through holes are formed by methods such as RIE. The conductive layer chB is formed by methods such as CVD.

[0089] Next, as shown in Figure 21, for example, a portion of the conductive layer chB is removed to form multiple wiring channels. This process is carried out by methods such as CMP (Chemical Mechanical Polishing).

[0090] Next, as shown in Figure 22, for example, a wiring layer M0 is formed by a damascene process. In this process, wiring Vy and wiring m0 are formed on wiring ch formed on edge seals ES1 to ES5 using PVD (Physical Vapor Deposition) or the like. On the other hand, wiring Vy and wiring m0 are not formed on wiring ch formed on edge seal ES6.

[0091] Next, as shown in Figure 23, for example, a wiring layer M1 is formed by a damascene process. In this process, wiring V1 and wiring m1 are formed on wiring m0 formed above edge seals ES1 to ES5 (in the -Z direction in the figure) using PVD or the like. On the other hand, wiring V1 is not formed above edge seal ES6 (in the -Z direction in the figure), and only wiring m1 is formed. The wiring layer M1 above edge seal ES6 is formed in a floating state, separated from edge seal ES6.

[0092] Next, as shown in Figure 24, for example, a wiring layer MB is formed by a damascene process. In this process, wiring VB is formed on wiring m1 formed above edge seals ES2~ES3 using PVD or the like. Furthermore, a bonding electrode P is formed on wiring VB formed above edge seals ES2 and ES3. I1 This is formed using PVD or the like. On the other hand, above the edge seals ES1, ES5, and ES6, the bonding electrode P I1 It does not form.

[0093] [WaferW P [Manufacturing method] Figure 25 shows wafer W P This shows the surface of the semiconductor substrate 250 corresponding to the above. As shown in Figure 25, the surface of the semiconductor substrate 250 also has multiple memory regions R, similar to the surface of the semiconductor substrate 150. M And these multiple memory regions RM Calf region R provided between K And, is provided. Wafer W P Each of the above components is formed by a thin-film deposition process such as CVD, a patterning process such as photolithography, and a processing process such as etching and CMP.

[0094] [WaferW M ,W P [Processes after lamination] Wafer W M ,W P After manufacturing, as shown in Figure 26, for example, wafer W M The surface and wafer W P The surface of and are placed facing each other. Also, as shown in Figures 27 and 28, for example, wafer W M ,W P The wafers are bonded together. In this bonding process, for example, wafer W M wafer W P By pressing toward the wafer W M wafer W P It is then brought into close contact with the bonded electrode P and subjected to heat treatment, etc. This results in the bonded electrode P I1 and bonded electrode P I2 via wafer W M is wafer W P It is bonded to it.

[0095] Next, wafer W M The semiconductor substrate 150 and the insulating layer 112 are removed.

[0096] Next, the back wiring layer MA and the like are formed to create the base structure L as described with reference to Figure 10. SB It forms.

[0097] Specifically, as shown in Figure 29, for example, a portion of the semiconductor layer 100A is removed to form contact holes corresponding to the positions of edge seals ES1 to ES6. This step is performed by a method such as RIE. Next, an insulating layer 101 is formed. This step is performed by a method such as CVD. Next, the insulating layer 101 is removed at the contact holes corresponding to the positions of edge seals ES1 to ES6. This exposes the edge seals ES1 to ES6. This step is performed by a method such as RIE. Next, a metal layer is formed on the upper surface of the insulating layer 101, the X and Y side surfaces of the insulating layer 101 (including the inner circumferential surface of the contact holes), and the upper surface of the insulating layer 103 by a method such as CVD, and a portion of the formed metal layer is removed by a method such as RIE to form wiring ma. This step is performed by a method such as RIE.

[0098] Next, as shown in Figure 30, for example, an insulating layer 102 is formed on the upper surface of the insulating layer 101, the upper surface of the wiring ma, and the sides of the wiring ma in the X and Y directions (including the inner circumferential surface inside the contact hole). This process is carried out by a method such as CVD.

[0099] Subsequently, the calf region R K A wafer W is bonded along the dicing line DL provided inside. M ,W P This disconnects each memory die region R. MD The configurations provided in each of these areas constitute the memory die MD. Furthermore, the calf region R K A portion of this is the kerf region R, as explained with reference to Figure 10. K It may become part of the memory die MD.

[0100] [Effects of the First Embodiment] In the first embodiment, as shown in Figure 10, etc., chip C P and chip C M This is the memory region R M An edge seal region R is provided to surround it. ES And the edge seal area R ESCalf region R located on the outside K It includes the following: edge seal area R ES Each of these extends along the Z direction, and when viewed from the Z direction, it forms a memory region R M An edge seal region R is provided to surround the periphery. ES Multiple edge seals ES1 to ES6 are provided, spaced apart from the inner circumference to the outer circumference. Edge seals ES1 to ES5 are connected to the wiring m0 of wiring layer M0 and the wiring m1 of wiring layer M1. On the other hand, below the outermost edge seal ES6, there is wiring m1 of wiring layer M1 that is not electrically connected to edge seal ES6 and is spaced apart from edge seal ES6 in the Z direction.

[0101] Here, as described above, at least one of the edge seals ES2 and ES3 is in the memory region R M It is provided to completely surround the perimeter. Furthermore, edge seals ES2 and ES3 are provided for wiring layers CH, M0, M1, MB, and chip C. P Through multiple wiring layers D0~D4,DB within the substrate structure L SB It is connected to the region from the bottom surface to the top surface of the semiconductor substrate 200. As a result, the edge seals ES2 and ES3 are connected to the chip C M The charge accumulated during the manufacturing process of chip C M The static electricity can be released (discharged) through the semiconductor substrate on which the seals are formed. In addition, the edge seals ES2 and ES3 can suppress the intrusion of impurities such as hydrogen into the memory area from the outside.

[0102] Furthermore, edge seal ES1 is provided on the inner circumference side of edge seals ES2 and ES3, and edge seals ES5 and ES6 are provided on the outer circumference side. This makes it possible to precisely open the areas corresponding to edge seals ES2 and ES3 in the process described with reference to Figure 18, and to suitably manufacture edge seals ES2 and ES3.

[0103] In the process described with reference to Figure 27, wafer W M ,W P It is desirable that the insulating layer 113 is exposed at a certain percentage or more on the surface of the wafer W.M ,W P This is because, during bonding, the insulating layers 113 of each are connected to each other. For this reason, edge seals ES1, ES5, and ES6 are bonded to the bonding electrode P I1 It is not connected to wafer W. M ,W P In order to suitably bond the wafer W M ,W P It is desirable that the surface be flat.

[0104] Here, as explained with reference to Figure 23, the wiring layer M1 is formed by a damascene process. As described above, in the damascene process, an opening is formed in the insulating layer, a conductive layer is formed on the opening and the upper surface of the insulating layer, and then the conductive layer formed on the upper surface of the insulating layer is removed by a planarization means such as CMP, leaving the conductive layer in the opening. Here, when performing a planarization means such as CMP, if the density (coverage rate) of the conductive layer in the opening is not constant, wafer W M ,W P The surface may become uneven.

[0105] In particular, in this embodiment, the wiring m0 within the wiring layer M0 contains copper, and the wiring m1 within the wiring layer M1 contains tungsten. Furthermore, the tungsten corresponding to the wiring m1 is formed by PVD. This is because, due to the presence of copper in the wiring m0, it is difficult to use high-temperature processes. In such cases, the aforementioned problem of unevenness is particularly likely to occur due to the film quality of the formed tungsten.

[0106] Therefore, in this embodiment, wiring m1 of the wiring layer M1 is provided below the outermost edge seal ES6. As a result, compared to the case where wiring m1 of the wiring layer M1 is not provided below the edge seal ES6, the coverage of the wiring layer M1 below the edge seal ES6 becomes less sparse, so the chip C M Edge seal region R ES The difference in coverage between this area and other areas can be reduced. Therefore, compared to the case where wiring m1 of wiring layer M1 is not provided below edge seal ES6, the edge seal area R ESBy reducing the step difference between this area and the rest of the wafer W M ,W P By improving the precision of the bonding process, it is possible to improve the yield of semiconductor memory devices.

[0107] However, the edge seal ES6 has an edge seal area R ES Among the edge seals ES1 to ES6, it is provided on the outermost periphery. Therefore, in the process described with reference to Figure 20, for example, when forming the edge seal ES6, materials such as tungsten and silicon oxide may not be suitably embedded inside the groove EST6, and a recess may be formed. Therefore, if all the wirings ch, m0, and m1 in the wiring layers CH, M0, and M1 are formed above the edge seal ES6 (in the -Z direction), the wafer W will be affected by this recess. M There is a risk that unevenness may form on the surface.

[0108] Therefore, in the first embodiment, the wiring ch,m0 in the wiring layer CH,M0 is omitted below the edge seal ES6 (in the -Z direction). With this method, it is possible to flatten the surface side (negative side in the Z direction) of the edge seal ES6 by the insulating layer 113, etc., between the formation of the edge seal ES6 and the formation of the wiring m1 in the wiring layer M1.

[0109] [Example 1] In the first embodiment, as shown in Figure 10, for example, it was explained that the width in the Y direction of the wiring m1 of the floating wiring layer M1 provided below the edge seal ES6 is approximately the same as the width in the Y direction of the edge seal ES6, but the embodiment is not limited to this. Hereinafter, as Examples 1 to 4 of the first embodiment, the case in which the width in the Y direction of the floating wiring layer M1 provided below the edge seal ES6 is greater than the width in the Y direction of the edge seal ES6 will be described.

[0110] Figure 31 shows the edge seal region R according to Example 1 of the first embodiment. ESThis is a schematic plan view showing the arrangement of multiple edge seals ES1 to ES6 and the arrangement of the wiring layer M1. Figure 32 is a schematic plan view showing an enlarged portion of Figure 31. In Figure 32, a portion of area c in Figure 31 is shown in enlargement. Figure 33 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the edge seal ES6 when cut along the dotted line EE' in Figure 31. Components identical to those in Figure 10 are denoted by the same reference numerals, and redundant explanations are omitted.

[0111] Edge seal area R ES Alternatively, as shown in Figure 31, a dummy pattern of multiple island-shaped wiring layers M1 arranged in the X and Y directions may be formed. Figure 31 illustrates a dummy pattern of multiple wiring layers M1 arranged at a predetermined pitch in the X and Y directions.

[0112] Also, the edge seal area R ES As shown in Figure 31, the edge seals ES1 to ES6 are located in the memory region R (not shown). M It is provided in a ring shape surrounding the periphery. In addition, the wiring layer M1 is positioned so as to overlap with the edge seals ES1 to ES5 when viewed from the Z direction.

[0113] The edge seals ES1 to ES5 are located near the center of the wiring layer M1 when viewed from the Z direction. As shown in Figures 31 and 32, the width of the wiring layer M1 that overlaps with the edge seals ES1 to ES5 when viewed from the Z direction is approximately equal to or greater than the width of the edge seals ES1 to ES5. On the other hand, as shown in Figures 31 and 32, the edge seal ES6 is located at one end of the wiring layer M1, which is wider than the edge seal ES6 when viewed from the Z direction. The width in the Y direction of the wiring m1a of the floating wiring layer M1 located below the edge seal ES6 is greater than the width of the edge seal ES6 in the Y direction, as shown in Figure 33. Note that, as shown in Figure 33, the edge seal ES6 may partially overlap with one end of the wiring layer M1 when viewed from the Z direction, but it may also be positioned so as not to overlap with the wiring layer M1.

[0114] As a result, in Example 1, the wiring layer M1 below the edge seal ES6 can be provided, taking into account the machining accuracy (machining variation) of the edge seal ES6.

[0115] Furthermore, by making the width of the wiring layer M1 below the edge seal ES6 in the Y direction greater than the width of the edge seal ES6 in the Y direction, the coverage of the wiring layer M1 in the Z direction of the edge seal ES6 can be improved. This allows the chip C M Edge seal region R ES and calf region R K The difference in coverage between the end and the wiring layer M1 can be reduced.

[0116] Note that in Figures 31 and 32, when the edge seal ES6 is viewed from the Z direction, a wiring layer M1 larger than the width of the edge seal ES6 is visible, but this is not limited to this. Wiring layer M0 or wiring layer V1 may also be visible. In this case, when viewed from the Z direction, for example, as shown in Figure 33, wiring layer M0, wiring layer V1, or wiring layers M0 and V1 are arranged between the edge seal ES6 and wiring layer M1.

[0117] [Example 2] Figure 34 shows the edge seal region R according to Example 2 of the first embodiment. ES This is a schematic plan view showing the arrangement of edge seals ES1 to ES6 and the arrangement of wiring layer M1. Figure 35 is a schematic plan view showing an enlarged portion of Figure 34. In Figure 35, a portion of area d in Figure 34 is shown in enlargement. Figure 36 is a schematic cross-sectional view showing the structure of wiring layer M1 located below edge seal ES6 when cut along the dotted line FF' in Figure 34. Components identical to those in Figures 31 to 33 are denoted by the same reference numerals, and redundant explanations are omitted.

[0118] Edge seal area R ES As shown in Figure 34, the edge seals ES1 to ES6 are located in the memory region R (not shown). M It is provided in a ring shape surrounding the periphery, and the wiring layer M1 is positioned so as to overlap with the edge seals ES1 to ES6 when viewed from the Z direction.

[0119] The edge seal ES6 is located near the center of the wiring layer M1 when viewed from the Z direction, as shown in Figures 35 and 36, for example. When viewed from the Z direction, the width of the wiring m1b of the wiring layer M1 that overlaps with the edge seal ES6 is greater than the width of the edge seal ES6.

[0120] In this way, by making the width of the wiring layer M1 below the edge seal ES6 in the Y direction larger than the width of the edge seal ES6 in the Y direction, the coverage of the wiring layer M1 in the Z direction of the edge seal ES6 can be improved. As a result, chip C M Edge seal region R ES and calf region R K The difference in coverage between the end and the wiring layer M1 can be reduced.

[0121] Note that in Figures 34 and 35, the wiring layer M1 is visible when the edge seal ES6 is viewed from the Z direction, but this is not the only option. The wiring layer M0 or wiring layer V1 may also be visible. In this case, when viewed from the Z direction, for example, as shown in Figure 36, the wiring layer M0, the wiring layer V1, or the wiring layers M0 and V1 are arranged between the edge seal ES6 and the wiring layer M1.

[0122] [Example 3] Figure 37 shows the edge seal region R according to Example 3 of the first embodiment. ES This is a schematic plan view showing the arrangement of multiple edge seals ES1 to ES6 and the arrangement of the wiring layer M1. Figure 38 is a schematic plan view showing an enlarged portion of Figure 37. In Figure 38, a portion of area e in Figure 37 is shown in enlargement. Figure 39 is a schematic cross-sectional view showing the structure of the wiring layer M1 located below the edge seal ES6 when cut along the dotted line GG' in Figure 37. Components identical to those in Figures 31 to 33 are denoted by the same reference numerals, and redundant explanations are omitted.

[0123] Edge seal area R ES As shown in Figure 37, the edge seals ES1 to ES6 are located in the memory region R (not shown). MIt is provided in a ring shape surrounding the periphery, and the wiring layer M1 is positioned so as to overlap with the edge seals ES1 to ES5 when viewed from the Z direction.

[0124] The wiring layer M1, located below the edge seal ES6 (in the -Z direction), is positioned near both sides of the edge seal ES6, as shown in Figures 37 to 39. Furthermore, as shown in Figure 39, for example, there are multiple wiring layers M1 located below the edge seal ES6 when viewed from the Z direction. The sum of the Y-direction widths of the multiple wirings m1c in the floating wiring layer M1 is greater than the Y-direction width of the edge seal ES6. Note that, as shown in Figure 39, the multiple wirings m1c may partially overlap the edge seal ES6 when viewed from the Z direction, but they may also be arranged so as not to overlap the edge seal ES6.

[0125] This allows the total width of the wiring layer M1 located below the edge seal ES6 in the Y direction to be made larger than that of the edge seal ES6, even when the size of the wiring layer M1 located below the edge seal ES6 in the Y direction cannot be made as large as in Examples 1 and 2. Therefore, the coverage of the wiring layer M1 in the Z direction of the edge seal ES6 can be improved, so that the chip C M Edge seal region R ES and calf region R K The difference in coverage between the end and the wiring layer M1 can be reduced.

[0126] Note that in Figures 37 and 38, the wiring layer M1 is visible when the edge seal ES6 is viewed from the Z direction, but this is not the only option. The wiring layer M0 or wiring layer V1 may also be visible. In this case, when viewed from the Z direction, for example, the wiring layer M0, the wiring layer V1, or the wiring layers M0 and V1 are arranged between the edge seal ES6 and the wiring layer M1 as shown in Figure 39.

[0127] [Example 4] Embodiments 1 and 1 to 3 describe a case where the floating wiring layer M1, located below the edge seal ES6, is provided in a linear manner when viewed from the Z direction, but the invention is not limited to this case. Embodiment 4 below describes a case where the floating wiring layer M1 is provided in a meandering manner when viewed from the Z direction.

[0128] Figure 40 shows the edge seal region R according to Example 4 of the first embodiment. ES This is a schematic plan view showing the arrangement of multiple edge seals ES1 to ES6 and the arrangement of the wiring layer M1. Figure 41 is a schematic plan view showing an enlarged portion of Figure 40. In Figure 41, a portion of area f of Figure 40 is shown in enlargement. Figure 42 is a schematic cross-sectional view showing the structure of the wiring layer M1 provided below the edge seal ES6 when cut along the dotted line HH' in Figure 40. Components identical to those in Figures 31 to 33 are denoted by the same reference numerals, and redundant explanations are omitted.

[0129] Edge seal area R ES As shown in Figure 40, the edge seals ES1 to ES6 are located in the memory region R (not shown). M It is provided in a ring shape surrounding the periphery. In addition, the wiring layer M1 is positioned so as to overlap with the edge seals ES1 to ES5 when viewed from the Z direction.

[0130] The wiring layer M1 provided below the edge seal ES6 (in the -Z direction) partially overlaps with the edge seal ES6 and is meandering when viewed from the Z direction, as shown in Figures 40 and 41. More specifically, as shown in Figure 41, the wiring layer M1 (and its wiring m1d) provided below the edge seal ES6 (in the -Z direction) has multiple sub-regions that are at a predetermined angle with the edge seal ES6 when viewed from the Z direction. These sub-regions partially overlap with the edge seal ES6 when viewed from the Z direction. The predetermined angle is approximately 15 to 75 degrees and is appropriately determined to improve the coverage of the wiring layer M1 provided below the edge seal ES6 (in the -Z direction) when viewed from the Z direction.

[0131] Furthermore, as shown in Figure 42, for example, when viewed from the Z direction, the Y-direction width of the wiring m1d of the wiring layer M1 located below the edge seal ES6 is greater than the Y-direction width of the edge seal ES6.

[0132] Thus, in Example 4, the wiring layer M1 below the edge seal ES6 can be provided so as to partially overlap with the edge seal ES6 and meander when viewed from the Z direction. This makes it possible to improve the coverage of the wiring layer M1 in the Z direction of the edge seal ES6, even when the size of the wiring layer M1 located below the edge seal ES6 in the Y direction cannot be made as large as in Examples 1 and 2, so that the chip C M Edge seal region R ES and calf region R K The difference in coverage between the end and the wiring layer M1 can be reduced.

[0133] Note that in Figures 40 and 41, the wiring layer M1 is visible when the edge seal ES6 is viewed from the Z direction, but this is not the only option. The wiring layer M0 or wiring layer V1 may also be visible. In this case, when viewed from the Z direction, for example, the wiring layer M0, the wiring layer V1, or the wiring layers M0 and V1 are arranged between the edge seal ES6 and the wiring layer M1 as shown in Figure 42.

[0134] [Example 5] Embodiment 1 and Embodiments 1 to 4 describe a case where the floating wiring layer M1, located below the edge seal ES6, is provided in a continuous manner when viewed from the Z direction, but the invention is not limited to this case. Embodiment 5 below describes a case where the floating wiring layer M1 is provided in a discontinuous manner when viewed from the Z direction.

[0135] Figure 43 shows the edge seal region R according to Example 5 of the first embodiment. ESThis is a schematic plan view showing the arrangement of a plurality of edge seals ES1 to ES6 and the arrangement of the wiring layer M1. FIG. 44 is a schematic plan view showing an enlarged part of FIG. 43. Note that a schematic cross-sectional view showing the structure of the wiring layer M1 provided below the edge seal ES6 is the same as that in FIG. 36, so the description thereof is omitted. Also, the same components as those in FIGS. 31 and 32 are denoted by the same reference numerals, and redundant descriptions are omitted.

[0136] Edge seal region R ES In this case, as shown in FIG. 43, the edge seals ES1 to ES6 are provided in a ring shape so as to surround the periphery of a memory region R (not shown). M Also, the wiring layer M1 is arranged so as to overlap with the edge seals ES1 to ES5 when viewed from the Z direction.

[0137] The wiring layer M1 provided below the edge seal ES6 (in the -Z direction) partially overlaps with the edge seal ES6 and has a discontinuous portion when viewed from the Z direction, as shown in FIGS. 43 and 44, by way of example. More specifically, as shown in FIG. 44, for example, the wiring layer M1 provided below the edge seal ES6 (in the -Z direction) is a single wiring composed of a plurality of separated partial regions when viewed from the Z direction. These plurality of partial regions at least partially overlap with the edge seal ES6 when viewed from the Z direction. Note that the distance between adjacent partial regions in the X direction (the distance of the discontinuous portion) may be a predetermined ratio of the length of the partial region in the X direction (the wiring length).

[0138] Also, as shown in FIG. 44, for example, the width of the wiring layer M1 provided below the edge seal ES6 in the Y direction is larger than the width of the edge seal ES6 in the Y direction when viewed from the Z direction.

[0139] Thus, in Example 5, the wiring layer M1 below the edge seal ES6 can be provided so as to partially overlap with the edge seal ES6 and have a discontinuous portion when viewed from the Z direction. Thereby, the coverage rate of the wiring layer M1 in the Z direction of the edge seal ES6 can be improved as compared with the case where the wiring layer M1 is not provided below the edge seal ES6, so that the chip C MEdge seal region R ES and calf region R K The difference in coverage between the end and the wiring layer M1 can be reduced.

[0140] Furthermore, since the wiring layer M1 below the edge seal ES6 is provided to have discontinuous portions, the kerf region R on the outer edge of the chip during the dicing process K This prevents cracks or peeling arising from the edge seal ES6 from propagating along the entire wiring layer M1 beneath it.

[0141] Furthermore, the wiring layer M1 provided below the edge seal ES6 is not limited to a single wiring consisting of multiple spaced sub-regions when viewed from the Z direction, but may also consist of multiple wirings, as described in Example 3.

[0142] Note that in Figures 43 and 44, the wiring layer M1 is visible when the edge seal ES6 is viewed from the Z direction, but this is not the only option. The wiring layer M0 or wiring layer V1 may also be visible.

[0143] [Other embodiments] The semiconductor memory devices according to the first embodiment and Examples 1 to 5 have been described above. However, the above semiconductor memory devices are merely examples, and the specific configurations can be adjusted as appropriate.

[0144] Figures 45 to 48 are schematic cross-sectional views showing the structure of the edge seal ES6 and the conductive layer below the edge seal ES6 according to other embodiments.

[0145] For example, the edge seal ES6 according to the first embodiment, etc., was described as being connected to the wiring ch at a position that overlaps when viewed from the Z direction, as shown in Figure 10, and having wiring m1 of wiring layer M1 spaced apart from the edge seal ES6 and not electrically connected, below the edge seal ES6. However, it is not limited to this. It is sufficient if wiring layer M0 is not provided and wiring m1d of wiring layer M1 spaced apart from the edge seal ES6 is provided.

[0146] Specifically, for example, as shown in Figure 45, the edge seal ES6 may be connected to wiring ch at a position where it overlaps when viewed from the Z direction, wiring ch may be connected to wiring Vy, and wiring m1d of wiring layer M1 may be provided below the edge seal ES6, spaced apart from the edge seal ES6 and not electrically connected to it.

[0147] Furthermore, as shown in Figure 46, for example, the edge seal ES6 is connected to the wiring ch at a position where it overlaps when viewed from the Z direction, and below the edge seal ES6, there is a wiring m1d of the wiring layer M1 that is spaced apart from the edge seal ES6 and not electrically connected to it, and the wiring m1d may be connected to the wiring V1.

[0148] Furthermore, for example, as shown in Figure 47, the edge seal ES6 is connected to wiring ch at a position that overlaps when viewed from the Z direction, wiring ch is connected to wiring Vy, and wiring m1d of wiring layer M1 is provided below the edge seal ES6, spaced apart from the edge seal ES6 and not electrically connected, and wiring m1d may be connected to wiring V1.

[0149] Furthermore, if the wiring m1d of wiring layer M1 is spaced apart from the edge seal ES6 and not electrically connected to the edge seal ES6, then wiring m0d of wiring layer M0 may be provided. Specifically, for example, as shown in Figure 48, the edge seal ES6 is connected to the wiring ch at a position where it overlaps when viewed from the Z direction, and below the edge seal ES6, wiring m1d of wiring layer M1 is provided, spaced apart from the edge seal ES6 and not electrically connected to it, and wiring m1d is connected to wiring V1, and wiring V1 is connected to wiring m0d of wiring layer M0. The wiring m0d of wiring layer M0 is provided at a position where it overlaps with the wiring ch when viewed from the Z direction, but it is spaced apart from the wiring ch and not electrically connected to the wiring ch.

[0150] Next, we will describe a structure in which the wiring m1d of the wiring layer M1 located below the edge seal ES6 may be electrically connected to the edge seal ES6. In this case, the wiring layer M0 can be positioned so as to overlap the wiring layer M1 when viewed from the Z direction.

[0151] Figure 49 shows the edge seal region R according to another embodiment. ES Figure 50 is a schematic plan view showing the arrangement of edge seals ES1 to ES6 and wiring layers M0 and M1. Figure 50 is a schematic cross-sectional view showing the structure of wiring layers M0 and M1 located below edge seal ES6 when cut along the dotted line II' in Figure 49.

[0152] Edge seal area R ES As shown in Figure 49, the edge seals ES1 to ES6 are located in the memory region R (not shown). M It is provided in a ring shape surrounding the periphery. In addition, the wiring layers M0 and M1 may be positioned in positions where they overlap with the edge seals ES1 to ES5 and positions where they do not overlap when viewed from the Z direction.

[0153] The wiring layer M1, located below the edge seal ES6 (in the -Z direction), may be positioned, for example, as shown in Figure 50, at a location that partially overlaps with the edge seal ES6 and at a location that does not overlap with the edge seal ES6 when viewed from the Z direction.

[0154] Specifically, wiring m1d of wiring layer M1 may be placed in positions that partially overlap with edge seal ES6, and wiring m1d' of wiring layer M1 may be placed in positions that do not overlap with edge seal ES6. These are spaced apart.

[0155] When viewed from the Z direction, wiring m0d of wiring layer M0 may be provided so as to overlap with wiring m1d of wiring layer M1, which is located in a position that partially overlaps with edge seal ES6, and wiring m1d and wiring m0d may be electrically connected. Similarly, when viewed from the Z direction, wiring m0d of wiring layer M0 may be provided so as to overlap with wiring m1d' of wiring layer M1, which is located in a position that does not overlap with edge seal ES6, and wiring m1d' and wiring m0d may be electrically connected via wiring V1.

[0156] In such a case, for example, as shown in FIG. 50, the edge seal ES6 is electrically connected to the wirings ch, VY, m0d, V1, and m1d at overlapping positions when viewed from the Z direction, and the edge seal ES6 is not electrically connected to the wirings m0d, V1, and m1d at non-overlapping positions when viewed from the Z direction.

[0157] In addition, for example, as shown in FIG. 49, below the edge seal ES6 (in the -Z direction), the wiring layers M0 and M1 provided at positions overlapping and non-overlapping with the edge seal ES6 are each a single wiring composed of a plurality of separated partial regions when viewed from the Z direction.

[0158] Thus, the edge seal ES6 is provided on the outermost peripheral side among the edge seals ES1 to ES6 in the edge seal region R ES However, as described above, below the edge seal ES6, at a position not overlapping with the edge seal ES6 and on the outer peripheral side of the edge seal ES6, by providing the wiring layers M0 and M1 without electrically connecting to the edge seal ES6 and omitting the wirings ch and VY, it becomes unnecessary to omit the wirings ch and m0 in the wiring layers CH and M0 below the edge seal ES6.

[0159] In addition, although it has been described that below the edge seal ES6 (in the -Z direction), the wiring layer M1 is provided at a position not overlapping with the edge seal ES6 and the wiring layer M0 is provided at an overlapping position in the Z direction, it is not limited to this, and the wiring layer M0 may not be provided.

[0160] [Others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0161] W M ,W P ...wafer, R ES ...edge seal area, R MD ...device area, R K ,R kerf ...Kerf region, DL...Dicing line, ES1, ES2, ES3, ES5, ES6...Edge seal, M0, M1, MB...Wiring layer, 200...Semiconductor substrate, GC...Electrode layer, 110...Conductive layer, 120...Semiconductor layer, 130...Gate insulating film

Claims

1. It comprises a first chip and a second chip bonded together via multiple bonding electrodes, The first chip and the second chip are A memory area including a memory cell array or peripheral circuits connected to the memory cell array, An edge seal region is provided so as to surround the memory region, Equipped with, The first chip is Semiconductor substrate and A plurality of first conductive layers are provided in the edge seal region and each connects to the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate. Equipped with, The second chip is In the edge seal region, each of the following edge seals extends along the first direction and is provided so as to surround the memory region when viewed from the first direction, and is spaced apart from the inner circumference to the outer circumference of the edge seal region, With respect to the plurality of edge seals, the first wiring layer provided on the second chip side, A second wiring layer provided on the second chip side relative to the first wiring layer, comprising a plurality of wirings including tungsten (W) Equipped with, The first wiring layer is provided in the edge seal region and is provided at a position that overlaps with a plurality of first edge seals, excluding the outermost periphery when viewed from the first direction, when viewed from the first direction, and comprises a plurality of second conductive layers that are electrically connected to the plurality of first edge seals. The aforementioned second wiring layer is A plurality of third conductive layers are provided in the edge seal region, positioned to overlap with the plurality of first edge seals when viewed from the first direction, and connected to the plurality of first edge seals, A fourth conductive layer is provided in the edge seal region, located on the outer periphery of the plurality of third conductive layers when viewed from the first direction, and is not electrically connected to the outermost second edge seal of the plurality of edge seals when viewed from the first direction, and is spaced apart from the second edge seal. A semiconductor memory device equipped with the following features.

2. One of the plurality of first edge seals is electrically connected to one of the plurality of bonded electrodes via one of the plurality of second conductive layers and one of the plurality of third conductive layers. One of the plurality of first edge seals is not electrically connected to any of the plurality of bonded electrodes. The semiconductor memory device according to claim 1.

3. The fourth conductive layer includes a portion that overlaps with the second edge seal when viewed from the first direction. The semiconductor memory device according to claim 1.

4. The fourth conductive layer includes a portion that does not overlap with the second edge seal when viewed from the first direction. The semiconductor memory device according to claim 1.

5. The second edge seal includes a first extended portion that extends in a second direction intersecting the first direction, The fourth conductive layer includes a second extended portion that extends in the second direction, The width of the second extension in the third direction intersecting the first and second directions is greater than the width of the first extension in the second direction. The semiconductor memory device according to claim 1.

6. The second wiring layer further comprises a fifth conductive layer, The fifth conductive layer is provided in the edge seal region, is located on the outer circumference of the second edge seal when viewed from the first direction, is not electrically connected to the second edge seal, and is spaced apart from the second edge seal. The fourth conductive layer is provided on the inner circumference side of the second edge seal when viewed from the first direction. The semiconductor memory device according to claim 1.

7. The fourth conductive layer and the fifth conductive layer are such that, when viewed from the first direction, they do not overlap with the second edge seal. The semiconductor memory device according to claim 6.

8. The fourth conductive layer, when viewed from the first direction, partially overlaps with the second edge seal and is meandering. The semiconductor memory device according to claim 1.

9. The fourth conductive layer has a plurality of partial regions that, when viewed from the first direction, have a predetermined angle with respect to the second edge seal, The aforementioned plurality of sub-regions partially overlap with the second edge seal when viewed from the first direction. The semiconductor memory device according to claim 8.

10. The fourth conductive layer is a wiring consisting of multiple spaced-apart subregions when viewed from the first direction, The plurality of sub-regions, when viewed from the first direction, overlap at least partially with the second edge seal. The semiconductor memory device according to claim 8.

11. It comprises a first chip and a second chip bonded together via multiple bonding electrodes, The first chip and the second chip are A memory area including a memory cell array or peripheral circuits connected to the memory cell array, An edge seal region is provided so as to surround the memory region, Equipped with, The first chip is Semiconductor substrate and A plurality of first conductive layers are provided in the edge seal region and each connects to the semiconductor substrate in a first direction intersecting the surface of the semiconductor substrate. Equipped with, The second chip is In the edge seal region, each of the following edge seals extends along the first direction and is provided so as to surround the memory region when viewed from the first direction, and is spaced apart from the inner circumference to the outer circumference of the edge seal region, With respect to the plurality of edge seals, the first wiring layer provided on the second chip side, A second wiring layer provided on the second chip side relative to the first wiring layer, comprising a plurality of wirings including tungsten (W) Equipped with, The first wiring layer is provided in the edge seal region and is provided in a position that overlaps with the plurality of edge seals when viewed from the first direction, and comprises a plurality of second conductive layers that are electrically connected to the plurality of edge seals. The aforementioned second wiring layer is A plurality of third conductive layers are provided in the edge seal region, positioned to overlap with the plurality of edge seals when viewed from the first direction, and connected to the plurality of edge seals, A fourth conductive layer is provided in the edge seal region, and is located on the outer and inner sides of the third conductive layer, which is positioned to overlap with the outermost first edge seal when viewed from the first direction among the plurality of edge seals. The fourth conductive layer is spaced apart from the third conductive layer, is not electrically connected to the first edge seal, and is spaced apart from the first edge seal. A semiconductor memory device equipped with the following features.

12. The first wiring layer is provided in the edge seal region and is provided spaced apart from the second conductive layer on both the outer and inner sides of the second conductive layer, which is located in a position overlapping with the first edge seal when viewed from the first direction, and is not electrically connected to the first edge seal, and includes a fifth conductive layer spaced apart from the first edge seal. The semiconductor memory device according to claim 11.

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