Semiconductor equipment

Abstract

To provide a semiconductor device that can suppress the generation of leakage current. [Solution] The semiconductor device according to the embodiment comprises a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second insulating layer, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, and a second electrode. The third semiconductor region is provided on the second semiconductor region. The third semiconductor region includes a first portion in contact with the second semiconductor region, and a second portion provided on the first portion, having a shorter length in a second direction than the first portion, and in contact with the second insulating layer. The ratio of the second distance from the top surface of the first portion to the top end of the gate electrode to the first distance in a first direction from the top surface of the first portion to the bottom end of the gate electrode is 0.05 or more and 0.22 or less. The second electrode includes a contact portion in contact with a part of the second semiconductor region and the first portion in a second direction. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the second insulating layer.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used in applications such as power conversion. There is a need for technologies that can suppress the generation of leakage current in these semiconductor devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5894383 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that the embodiments of the present invention aim to solve is to provide a semiconductor device that can suppress the generation of leakage current. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second insulating layer, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode. The gate electrode is provided on the first semiconductor region via the first insulating layer. The second insulating layer is provided on the gate electrode. The second semiconductor region is provided on the first semiconductor region and faces the gate electrode via the first insulating layer in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The third semiconductor region includes a first portion in contact with the second semiconductor region, and a second portion provided on the first portion, having a shorter length in the second direction than the first portion, and in contact with the second insulating layer. The ratio of the second distance from the top surface of the first portion to the upper end of the gate electrode to the first distance in the first direction from the top surface of the first portion to the lower end of the gate electrode is 0.05 or more and 0.22 or less. The second electrode includes a contact portion that is in contact with a part of the second semiconductor region and the first portion in the second direction. The second electrode is provided on the second semiconductor region, the third semiconductor region, and the second insulating layer. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is an enlarged cross-sectional view of a portion of Figure 1. [Figure 3] Figures 3(a) and 3(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] Figures 4(a) and 4(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] Figures 5(a) and 5(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6]Figures 6(a) and 6(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] Figure 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] Figures 8(a) and 8(b) show the results of observations of a portion of a semiconductor device, a reference example, using a transmission electron microscope. [Figure 9] Figure 9 shows experimental results illustrating the leakage current in a semiconductor device. [Figure 10] Figure 10 is a table showing the experimental results. [Modes for carrying out the invention]

[0007] The embodiments of the present invention will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes of the parts, etc., are not necessarily the same as those of reality. Furthermore, even when representing the same part, the dimensions and ratios may be represented differently in the drawings. In this specification and each drawing, elements similar to those already described are denoted by the same reference numerals, and detailed explanations are omitted as appropriate. In the following description and drawings, n + , n - and p + The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0008] Figure 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. The semiconductor device 100 according to the embodiment is a MOSFET. As shown in FIG. 1, the semiconductor device 100 includes an n - -type (first conductivity type) drift region 1 (first semiconductor region), a p-type (second conductivity type) base region 2 (second semiconductor region), an n + -type source region 3 (third semiconductor region), a p + -type contact region 4 (fourth semiconductor region), an n + -type drain region 5, a gate electrode 10, a first insulating layer 11, a second insulating layer 12, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode). In FIG. 1, the source electrode 22 is shown transparently with a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 21 toward the n - -type drift region 1 is defined as the Z direction (first direction). Two directions perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). Also, for the sake of explanation, the direction from the drain electrode 21 toward the n - -type drift region 1 is referred to as "up", and the opposite direction is referred to as "down". These directions are independent of the direction of gravity based on the relative positional relationship between the drain electrode 21 and the n - -type drift region 1.

[0010] The drain electrode 21 is provided on the lower surface of the semiconductor device 100. The n + -type drain region 5 is provided above the drain electrode 21 and is electrically connected to the drain electrode 21. The n - -type drift region 1 is provided above the n + -type drain region 5. The n - -type drift region 1 is electrically connected to the drain electrode 21 through the n + -type drain region 5. The n-type impurity concentration in the n - -type drift region 1 is lower than the n-type impurity concentration in the n + -type drain region 5.

[0011] The gate electrode 10 is an n -It is provided on the shaped drift region 1 via a first insulating layer 11. Multiple gate electrodes 10 are provided in the X direction, and these gate electrodes 10 are spaced apart from each other.

[0012] A p-shaped base region 2 is provided between adjacent gate electrodes 10. The p-shaped base region 2 is n - It is located above the p-shaped drift region 1. The p-shaped base region 2 and the gate electrode 10 are arranged alternately in the X direction. The gate electrode 10 faces the p-shaped base region 2 in the X direction via the first insulating layer 11.

[0013] n + The p-shaped source region 3 is provided on the p-shaped base region 2. The gate electrode 10 has n in the X direction. - Part of the shape drift region 1 and n + A portion of the source region 3 may be facing the first insulating layer 11.

[0014] The source electrode 22 is provided on a plurality of gate electrodes 10, each with a second insulating layer 12 in between. The source electrode 22 is located on the upper surface of the semiconductor device 100, and has a p-type base region 2 and n + It is electrically connected to the source region 3. The source electrode 22 is electrically isolated from the gate electrode 10 by the second insulating layer 12.

[0015] The source electrode 22 includes a contact portion 22a. The contact portion 22a extends downward and in the X direction is part of the p-shaped base region 2 and n + It is in contact with the shape source region 3. + The p-shaped contact region 4 is provided between the p-shaped base region 2 and the contact portion 22a. + The concentration of p-type impurities in the contact region 4 is higher than the concentration of p-type impurities in the p-type base region 2.

[0016] For example, p-type base region 2, n + Shape source region 3, p +Each of the p-shaped contact region 4, gate electrode 10, and contact portion 22a extends in the Y direction. A pair of n-shaped base regions 2 are located on one p-shaped base region 2. + Shape source region 3, one p + A p-shaped contact region 4 and one contact portion 22a are provided. p-shaped base region 2, n + Shape source region 3, p + Multiple contact regions 4, gate electrodes 10, and contact portions 22a are provided in the X direction, and these are arranged in a stripe pattern.

[0017] The operation of the semiconductor device 100 will be explained. With a positive voltage applied to the drain electrode 21 relative to the source electrode 22, a voltage above a threshold is applied to the gate electrode 10. As a result, a channel (inversion layer) is formed in the p-type base region 2. Electrons pass through the channel from the source electrode 22 to n - The current flows into the p-type drift region 1, and the semiconductor device 100 turns on. Subsequently, when the voltage applied to the gate electrode 10 falls below a threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 turns off.

[0018] An example of the materials used for each component is described below. - Shape drift region 1, p-shaped base region 2, n + Shape source region 3, p + Shaped contact area 4, and n +The drain region 5 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as a p-type impurity. The gate electrode 10 contains a conductive material such as polysilicon. The first insulating layer 11 and the second insulating layer 12 contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21 and source electrode 22 contain metals such as titanium, gold, silver, tin, tungsten, or aluminum. The specific materials and compositions of the drain electrode 21 and source electrode 22 can be arbitrarily selected, as long as the drain electrode 21 and source electrode 22 can make ohmic contact with the semiconductor region.

[0019] The preferred range of impurity concentration for each semiconductor region is as follows: n - The n-type impurity concentration in the shape drift region 1 is 1.0 × 10⁻⁶. 16 atom / cm 3 The above 1.0 × 10 18 atom / cm 3 The following is true: The concentration of p-type impurities in the p-type base region 2 is 1.0 × 10⁻⁶. 17 atom / cm 3 The above 1.0 × 10 19 atom / cm 3 The following is the case: n + The n-type impurity concentration in the source region 3 is 5.0 × 10⁻⁶. 18 atom / cm 3 The above 5.0 x 10 20 atom / cm 3 The following is p + The p-type impurity concentration in contact region 4 is 5.0 × 10⁻⁶. 18 atom / cm 3 The above 5.0 x 10 20 atom / cm 3 The following is the case: n + The n-type impurity concentration in the drain region 5 is 1.0 × 10⁻⁶. 19 atom / cm 3 The above 1.0 × 10 21 atom / cm 3 The following applies:

[0020] Figure 2 is an enlarged cross-sectional view of a portion of Figure 1. As shown in Figure 2, n + The p-shaped source region 3 includes a first portion 3a and a second portion 3b. The first portion 3a is the portion in contact with the p-shaped base region 2. In the X direction, the first portion 3a is located between the gate electrode 10 and the contact portion 22a, and between the second insulating layer 12 and the contact portion 22a. The second portion 3b is located above the first portion 3a and is in contact with the second insulating layer 12.

[0021] The width W2 of the second part 3b is narrower than the width W1 of the first part 3a. "Width" is the length in the X direction. The first part 3a has an upper surface S1. The upper surface S1 is in contact with the source electrode 22 in the Z direction. The second part 3b has an inclined surface S2. The inclined surface S2 is in contact with the source electrode 22 and is inclined with respect to the Z direction.

[0022] In the semiconductor device 100 according to this embodiment, the ratio of the second distance D2 to the first distance D1 is 0.05 or more and 0.22 or less. The first distance D1 is the distance in the Z direction from the upper surface S1 to the lower end E1 of the gate electrode 10. The second distance D2 is the distance in the Z direction from the upper surface S1 to the upper end E2 of the gate electrode 10.

[0023] Other specific dimensional relationships are as follows: The width W2 of the second part 3b is 0.5 times or less the width W1 of the first part 3a, and decreases towards the Z direction. The width W2 may be 0.4 times or less the width W1, or 0.3 times or less the width W1. The width W1 is measured at the height of the upper end E2. "Height" is the position in the Z direction. The width W2 is measured at the height of the boundary between the upper surface S1 and the inclined surface S2.

[0024] The inclination of the upper surface S1 with respect to the X direction is between 0 degrees and 15 degrees. The inclination of the inclined surface S2 with respect to the X direction is greater than 15 degrees and 85 degrees or less. The inclination of at least a portion of the inclined surface S2 with respect to the X direction is 60 degrees or more.

[0025] The length L2 of the second part 3b in the Z direction is shorter than the length L1 of the first part 3a in the Z direction. Length L2 may be 0.5 times or less of length L1, and may also be 0.3 times or less of length L1. The ratio of the third distance D3 to the first distance D1 is 0.05 or more and 0.25 or less. The third distance D3 is the distance in the Z direction from the top surface S1 to the top surface S3 of the second insulating layer 12.

[0026] The length of the gate electrode 10 in the Z direction is between 550 nm and 890 nm. This length corresponds to the distance in the Z direction from the lower end E1 to the upper end E2. The first distance D1 is between 600 nm and 1000 nm. The second distance D2 is between 30 nm and 220 nm. The third distance D3 is between 50 nm and 250 nm.

[0027] The pitch P of the multiple gate electrodes 10 is between 450 nm and 650 nm. The pitch P corresponds to the distance between the center of the first gate electrode 10a in the X direction and the center of the second gate electrode 10b in the X direction. The first gate electrode 10a is one of the multiple gate electrodes 10. The second gate electrode 10b is another of the multiple gate electrodes 10 and is adjacent to the first gate electrode 10a in the X direction.

[0028] For example, the concentration of n-type impurities in the second part 3b is lower than that in the first part 3a. Therefore, the electrical resistivity of the second part 3b is higher than that of the first part 3a. Alternatively, the concentration of n-type impurities in the second part 3b may be the same as that in the first part 3a.

[0029] Figures 3(a), 3(b), 4(a), 4(b), 5(a), 5(b), 6(a), 6(b), and 7 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. First, n + Semiconductor layer 5x and n - A semiconductor substrate containing a shaped semiconductor layer 1x is prepared. - The semiconductor layer 1x is n +It is provided on a shaped semiconductor layer 5x. By photolithography and reactive ion etching (RIE), as shown in Figure 3(a), n - Multiple apertures OP1 are formed on the upper surface of a shaped semiconductor layer 1x. The multiple apertures OP1 are separated from each other in the X direction, and each aperture OP1 extends in the Y direction.

[0030] Due to thermal oxidation, n - An insulating layer 11x is formed along the surface of a semiconductor layer 1x. A conductive layer is formed on the insulating layer 11x by chemical vapor deposition (CVD). The conductive layer contains, for example, polysilicon. The opening OP1 is filled by the conductive layer. The upper surface of the conductive layer is etched by wet etching. As a result, the conductive layer is divided into multiple parts, as shown in Figure 3(b), and a gate electrode 10 is formed inside each opening OP1.

[0031] An insulating layer 12x is formed on the gate electrode 10. The opening OP1 is filled by the insulating layer 12x. - Chemical dry etching (CDE) is performed until the upper surface of the semiconductor layer 1x is exposed. As a result, as shown in Figure 4(a), a portion of the insulating layer 11x and a portion of the insulating layer 12x are removed, n - The upper surface of the shaped semiconductor layer 1x is exposed.

[0032] CDE allows n between the insulating layers 12x. - A portion of the semiconductor layer 1x is removed. In CDE, a gas is selected in which the etching rate for the semiconductor is higher than the etching rate for the insulating layer. For example, HBr (hydrogen bromide) is used as the gas. When CDE is performed, a difference in etching rate occurs between the part near the insulating layer 12x and the part away from the insulating layer 12x. Near the insulating layer 12x, n - The semiconductor layer 1x is difficult to remove. As a result, as shown in Figure 4(b), the upper surface of the portion near the insulating layer 12x is sloped. The upper surface of the portion near the insulating layer 12x is located above the upper surface of the portion further away from the insulating layer 12x.

[0033] n -p-type and n-type impurities are sequentially ion-implanted onto the upper surface of the p-type semiconductor layer 1x, forming a p-type semiconductor region 2x and n + A semiconductor region 3x is formed by CVD, as shown in Figure 5(a). + An insulating layer 13x is formed to cover the shaped semiconductor region 3x and the insulating layer 12x. For example, the insulating layer 13x contains an insulating material such as silicon oxide or silicon nitride. As will be described later, the material of the insulating layer 13x can be changed as appropriate, as long as it can be used as a mask when etching the semiconductor layer.

[0034] A portion of the insulating layer 13x is n + It is located above both ends of the shaped semiconductor region 3x in the X direction. Another part of the insulating layer 13x is n + It is located above the center of the semiconductor region 3x in the X direction. The thickness (dimension in the Z direction) of this portion of the insulating layer 13x is greater than the thickness of this other portion of the insulating layer 13x.

[0035] Anisotropic etching, n + A portion of the insulating layer 13x is removed until a part of the upper surface of the semiconductor region 3x is exposed. At this time, as shown in Figure 5(b), the thinner portion of the insulating layer 13x is removed, and the thicker portion remains. As a result, n + An insulating layer 13x remains on both ends of the shaped semiconductor region 3x, while the rest of the insulating layer 13x is removed. This forms a mask 13y consisting of the insulating layer 13x. The mask 13y is n + It covers the vicinity of the insulating layer 12x of the shaped semiconductor region 3x. + The central portion of the shaped semiconductor region 3x in the X direction is exposed.

[0036] RIE using mask 13y, n + A portion of the p-type semiconductor region 3x and a portion of the p-type semiconductor region 2x are removed. This forms an opening OP2. As shown in Figure 6(a), p-type impurities are ion-implanted into the bottom surface of the opening OP2 through the opening OP2, and p + A contact region 4 is formed.

[0037] Remove the mask 13y. By sputtering, a metal layer 22x and a metal layer 22y are formed along the surfaces of the p-type semiconductor region 2x and the n + -type semiconductor region 3x. The metal layer 22x contains titanium nitride. The metal layer 22y contains titanium. As shown in FIG. 6(b), a metal layer 22z is formed on the metal layer 22y by sputtering. The metal layer 22z contains aluminum. The opening OP2 is filled with the metal layer 22z.

[0038] n + -type semiconductor layer 5x until it reaches a predetermined thickness, grind the lower surface of the n + -type semiconductor layer 5x. As shown in FIG. 7, a metal layer 21x is formed on the lower surface of the ground n + -type semiconductor layer 5x by sputtering. The metal layer 21x contains titanium. A metal layer 21y is formed on the metal layer 21x by plating. The metal layer 21y contains silver. Alternatively, the metal layer 21y may contain a eutectic of gold and tin. Through the above steps, the semiconductor device 100 according to the embodiment is manufactured.

[0039] The n - -type semiconductor layer 1x shown in FIG. 7 corresponds to the n - -type drift region 1 shown in FIG. 1. The p-type semiconductor region 2x corresponds to the p-type base region 2. The n + -type semiconductor region 3x is the n + -type source region 3. The n + -type semiconductor layer 5x corresponds to the n + -type drain region 5. The insulating layer 11x corresponds to the first insulating layer 11. The insulating layer 12x corresponds to the second insulating layer 12. The metal layers 21x and 21y correspond to the drain electrode 21. The metal layers 22x to 22z correspond to the source electrode 22. A part of the metal layer 22x, a part of the metal layer 22y, and a part of the metal layer 22z are located in the opening OP2. The said part of the metal layer 22x, the said part of the metal layer 22y, and the said part of the metal layer 22z correspond to the contact portion 22a.

[0040] Explain the advantages of the embodiment. The pitch P of the semiconductor device 100 is preferably short. The shorter the pitch P, the greater the number of gate electrodes 10 that can be placed per unit area. As a result, the channel density increases. The greater the channel density, the greater the current path in the ON state. Therefore, the ON resistance of the semiconductor device 100 can be reduced.

[0041] When manufacturing a semiconductor device 100 with a short pitch P, it is preferable that the positional displacement of the contact portion 22a in the X direction is small. If the position of the contact portion 22a is misaligned, the distance between any of the insulating layers 11x and the contact portion 22a becomes shorter. As shown in Figure 6(a), p + When the p-type contact region 4 is formed, p-type impurities tend to diffuse into the vicinity of the insulating layer 11x. As a result, the threshold voltage of the gate electrode 10 increases. In particular, when the pitch P is short, the distance between the insulating layer 11x and the contact portion 22a is short. Therefore, the increase in threshold voltage due to the misalignment of the contact portion 22a is also large.

[0042] In the above manufacturing method, a mask 13y is used when forming the opening OP2, as shown in Figure 6(a). The position of the mask 13y is determined based on the difference in thickness of each part of the insulating layer 13x. Specifically, the mask 13y is formed only on the side of the insulating layer 12x and not at a position far from the insulating layer 12x. That is, the position of the mask 13y is determined self-aligningly with the position of the insulating layer 12x as the reference. Therefore, even when the spacing between insulating layers 12x is narrow, the misalignment of the mask 13y can be suppressed. As a result, the misalignment of the opening OP2 formed using the mask 13y is also suppressed. Fluctuations in the threshold voltage due to misalignment of the contact portion 22a can be suppressed.

[0043] On the other hand, when the above manufacturing method is used, n +The height of a part of the upper surface of the p-shaped semiconductor region 3x is reduced by etching. As a result, in FIG. 7, the distance between the gate electrode 10 shown by the arrow A and the metal layer 22x becomes shorter. When this distance becomes shorter, leakage current is likely to occur between the gate electrode 10 and the source electrode 22. In order to suppress the occurrence of leakage current, it is preferable to increase the distance between the gate electrode 10 and the source electrode 22. For example, by increasing the second distance D2 shown in FIG. 2, the occurrence of leakage current can be suppressed.

[0044] As a result of the study by the inventor of the present application, it was confirmed that by increasing the second distance D2, the occurrence of leakage current between the gate electrode 10 and the source electrode 22 can be suppressed. However, when the second distance D2 is increased, it was found that crystal defects are likely to occur in the vicinity of the bottom of the first insulating layer 11 in the n - -type drift region 1. Although the detailed reason for this is unknown, it is considered to be related to the stress applied to semiconductor regions such as the n - -type drift region 1, the p-type base region 2, and the n + -type source region 3.

[0045] For example, when the second insulating layer 12 is formed, volume expansion occurs. In particular, when the second insulating layer 12 contains an oxide, the volume expansion is large. Due to the volume expansion, a large tensile stress remains in the second insulating layer 12. As the second distance D2 increases, the volume of the second insulating layer 12 increases, and the compressive stress applied from the second insulating layer 12 to the semiconductor region increases. It is considered that crystal defects occur in the vicinity of the bottom of the first insulating layer 11 due to this stress. The occurrence of crystal defects leads to an increase in the leakage current between the drain electrode 21 and the source electrode 22 in the off state. Also, compressive stress is applied from the second insulating layer 12 to the gate electrode 10. At this time, tensile stress is generated in the gate electrode 10. The tensile stress generated in the gate electrode 10 relaxes the stress applied to the semiconductor region. Therefore, in order to suppress the occurrence of crystal defects while suppressing the leakage current between the gate electrode 10 and the source electrode 22, it is considered important to appropriately design the ratio D2 / D1.

[0046] Figures 8(a) and 8(b) show the results of observations of a portion of a semiconductor device, a reference example, using a transmission electron microscope. In the semiconductor device described in the reference example, the ratio of the second distance D2 to the first distance D1, D2 / D1, is 0.28. In this case, as shown in Figures 8(a) and 8(b), between the lower ends of the gate electrodes 10, n - A linear crystal defect d was confirmed to have occurred in the shape drift region 1.

[0047] Figure 9 shows experimental results illustrating the leakage current in a semiconductor device. In the experiment, three types of semiconductor devices with different ratios D2 / D1 were prepared. For each ratio D2 / D1, the leakage current I between the gate electrode 10 and the source electrode 22 in multiple semiconductor devices was measured. GS The leakage current I was measured. GS In the measurement, the voltage V between the gate electrode 10 and the source electrode 22 is GS The voltage was set to 5V. The result is shown in Figure 9. In Figure 9, the vertical axis is expressed in arbitrary units, and the leakage current I GS Only data where the detection limit was exceeded are plotted.

[0048] As shown in Figure 9, when the ratio D2 / D1 is 0.12 or 0.28, the measured leakage current I GS Most values ​​were below the detection limit, and the mean and median values ​​were nearly zero. Some semiconductor devices exhibited large leakage currents I GS While some leakage currents were measured, the number was very small. In contrast, when the ratio D2 / D1 is 0.03, the measured leakage current I GS Many of the values ​​were very large, and the mean and median exceeded the upper limit of the measurement.

[0049] Figure 10 is a table showing the experimental results. The presence or absence of crystal defects and the generation of leakage current were investigated by repeating similar experiments while varying the ratio D2 / D1. The third distance D3, pitch P, and the length of the gate electrode 10 in the Z direction were designed within the ranges described above. The results are shown in Figure 10. In the experiment, the voltage V GSWhen the voltage is 5V, the leakage current I GS The number of semiconductor devices with a leakage current of 10 μA or less was counted. The ratio of the counted semiconductor devices to the total number of semiconductor devices measured was calculated. In Figure 10, ratios D2 / D1 with a ratio of 80% or more are evaluated as good and are shown with a circle. Ratios D2 / D1 with a ratio of less than 80% are evaluated as poor and are shown with a cross. In addition, for each ratio D2 / D1, the leakage current I GS A selection of semiconductor devices was randomly chosen from those with good performance. The cross-sections of the selected semiconductor devices were observed using a transmission electron microscope (TEM). In the TEM images, observation areas were randomly determined, and the vicinity of the lower end of at least 20 gate electrodes 10 was observed. In Figure 10, a ratio D2 / D1 in which no crystal defects were found is evaluated as good and indicated by a circle. A ratio D2 / D1 in which crystal defects were found is evaluated as poor and indicated by a cross. From the results shown in Figure 10, if the ratio D2 / D1 is within the range of 0.05 to 0.22, the leakage current I in many semiconductor devices is low. GS It can be seen that the size is small and the occurrence of crystal defects is sufficiently suppressed.

[0050] In the semiconductor device according to the embodiment, the ratio D2 / D1 is in the range of 0.05 to 0.22. According to the embodiment, even when the pitch P is shortened, the generation of leakage current between the gate electrode 10 and the source electrode 22 can be suppressed, and the generation of leakage current between the drain electrode 21 and the source electrode 22 due to crystal defects can also be suppressed. In other words, according to the embodiment, the on-resistance of the semiconductor device can be reduced by shortening the pitch P while suppressing the generation of such leakage currents.

[0051] Embodiments of the present invention are suitable for semiconductor devices in which a conductor (so-called field plate electrode) is not provided below the gate electrode 10. Generally, the field plate electrode is n in the Z direction. - It is located between the drift region 1 and the gate electrode 10 and is electrically connected to the gate electrode 10 or the source electrode 22. When a field plate electrode is provided, n -A thick insulating layer is required between the drift region 1 and the field plate electrode. This makes it difficult to set the pitch of the gate electrode 10 to 450 nm to 650 nm. By applying the above configuration to a semiconductor device that does not have a field plate electrode, the on-resistance of the semiconductor device 100 can be effectively reduced while suppressing the rise in the threshold voltage of the gate electrode 10.

[0052] For example, according to one embodiment, the density of crystal defects is 0.06 / um 2 The following can be done. The density of crystal defects is measured by the following method. First, the semiconductor device is cut along the XZ plane so as to pass through the center of the source electrode 22 in the XY plane. The cut surface is processed into a flat surface using a focused ion beam (FIB) or the like, and observed with a TEM. The observation magnification is set to 5000 to 10000 times. The number of crystal defects in the observed area is counted. If the crystal defects are point-like, each point is counted as one crystal defect. As shown in Figures 8(a) and 8(b), if the crystal defects are linear, a line of continuous crystal defects is counted as one crystal defect. The density of crystal defects is calculated by dividing the counted number of crystal defects by the area of ​​the observed semiconductor region.

[0053] n + In the source region 3, the n-type impurity concentrations in the first part 3a and the second part 3b may be the same or different. For example, the n-type impurity concentration in the second part 3b is lower than that in the first part 3a. This is because the width W2 of the second part 3b is shorter than the width W1 of the first part 3a, making it easier for the n-type impurities in the second part 3b to diffuse into the surroundings. In this case, the electrical resistivity of the second part 3b is higher than that of the first part 3a.

[0054] From the viewpoint of reducing on-resistance, the second portion 3b is undesirable. On the other hand, the electrical resistivity of the second portion 3b is higher than that of the first portion 3a. Therefore, the voltage drop when current flows through the second portion 3b is greater than the voltage drop when current flows through the first portion 3a. For example, when the semiconductor device 100 is short-circuited, a large current flows through the semiconductor device 100. At this time, the voltage drop by the second portion 3b is large, which can suppress the current flowing through the semiconductor device 100. By providing the second portion 3b, which is narrower than the first portion 3a, it is possible to reduce the current density during a short circuit while suppressing the increase in the on-resistance of the semiconductor device 100.

[0055] Embodiments of the present invention include the following features. (Feature 1) First electrode and, A first semiconductor region of a first conductivity type provided on the first electrode, A gate electrode provided on the first semiconductor region via a first insulating layer, A second insulating layer provided on the gate electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region and faces the gate electrode via the first insulating layer in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, A third semiconductor region of a first conductivity type provided on the second semiconductor region, The first portion in contact with the second semiconductor region, and A second portion provided on the first portion, having a length shorter than the first portion in the second direction, and in contact with the second insulating layer, The third semiconductor region includes, wherein the ratio of the second distance from the upper surface of the first portion to the upper end of the gate electrode to the first distance in the first direction from the upper surface of the first portion to the lower end of the gate electrode is 0.05 or more and 0.22 or less, The second semiconductor region includes a contact portion that contacts a part of the second semiconductor region and the first portion in the second direction, and the second electrode is provided on the second semiconductor region, the third semiconductor region, and the second insulating layer, A semiconductor device equipped with the following features. (Feature 2) The semiconductor device according to Feature 1, wherein the length of the second portion in the second direction is 0.5 times or less the length of the first portion in the second direction, and decreases as it approaches the first direction. (Feature 3) The inclination of the upper surface of the first portion with respect to the second direction is 0 degrees or more and 15 degrees or less. The semiconductor device according to feature 1 or 2, wherein the second part has an inclined surface whose inclination with respect to the second direction is greater than 15 degrees and 85 degrees or less. (Feature 4) The first distance is between 600 nm and 1000 nm. The semiconductor device according to any one of features 1 to 3, wherein the second distance is 30 nm or more and 220 nm or less. (Feature 5) The semiconductor device according to any one of features 1 to 4, wherein the length in the first direction from the lower end of the gate electrode to the upper end of the gate electrode is 550 nm or more and 890 nm or less. (Feature 6) The semiconductor device according to any one of features 1 to 5, wherein the ratio of the third distance in the first direction from the upper surface of the first portion to the upper surface of the second insulating layer to the first distance is 0.05 or more and 0.25 or less. (Feature 7) The semiconductor device according to feature 6, wherein the third distance is 50 nm or more and 250 nm or less. (Feature 8) The gate electrode and the second semiconductor region are arranged alternately in the second direction. The plurality of gate electrodes include a first gate electrode and a second gate electrode that are adjacent to each other in the second direction. A semiconductor device according to any one of features 1 to 7, wherein the distance between the center of the first gate electrode in the second direction and the center of the second gate electrode in the second direction is 450 nm or more and 650 nm or less.

[0056] The relative levels of impurity concentrations between semiconductor regions in each embodiment described above can be confirmed, for example, using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered equal to the concentration of activated impurities in that region. Therefore, the relative levels of carrier concentrations between semiconductor regions can also be confirmed using SCM. Furthermore, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0057] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other. [Explanation of Symbols]

[0058] 1:n - Shape of drift region, 1x:n - 1:p-type semiconductor layer, 2:p-type base region, 2x:p-type semiconductor region, 3:n + shape source area, 3a: first part, 3b: second part, 3x:n + Semiconductor region, 4:p + Shape of contact area, 5:n + Shape of drain region, 5x:n +Semiconductor layer, 10: gate electrode, 10a: first gate electrode, 10b: second gate electrode, 11: first insulating layer, 12: second insulating layer, 11x~13x: insulating layer, 13y: mask, 21: drain electrode, 21x,21y: metal layer, 22: source electrode, 22a: contact area, 22x~22z: metal layer, 100: semiconductor device, D1: first distance, D2: second distance, D3: third distance, E1: bottom end, E2: top end, OP1,OP2: opening, P: pitch, S1: top surface, S2: inclined surface, S3: top surface, W1,W2: width

Claims

1. First electrode and A first semiconductor region of a first conductivity type provided on the first electrode, A gate electrode provided on the first semiconductor region via a first insulating layer, A second insulating layer provided on the gate electrode, A second semiconductor region of a second conductivity type is provided on the first semiconductor region and faces the gate electrode via the first insulating layer in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region, A third semiconductor region of a first conductivity type provided on the second semiconductor region, The first portion in contact with the second semiconductor region, and A second portion provided on the first portion, having a length shorter than the first portion in the second direction, and in contact with the second insulating layer, The third semiconductor region includes, wherein the ratio of the second distance from the upper surface of the first portion to the upper end of the gate electrode to the first distance in the first direction from the upper surface of the first portion to the lower end of the gate electrode is 0.05 or more and 0.22 or less, The second semiconductor region includes a contact portion that contacts a part of the second semiconductor region and the first portion in the second direction, and the second electrode is provided on the second semiconductor region, the third semiconductor region, and the second insulating layer, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the length of the second portion in the second direction is 0.5 times or less the length of the first portion in the second direction, and decreases as it approaches the first direction.

3. The inclination of the upper surface of the first portion with respect to the second direction is 0 degrees or more and 15 degrees or less. The semiconductor device according to claim 1, wherein the second portion has an inclined surface whose inclination with respect to the second direction is greater than 15 degrees and 85 degrees or less.

4. The first distance is 600 nm or more and 1000 nm or less. The semiconductor device according to claim 1, wherein the second distance is 30 nm or more and 220 nm or less.

5. The semiconductor device according to claim 1, wherein the length in the first direction from the lower end of the gate electrode to the upper end of the gate electrode is 550 nm or more and 890 nm or less.

6. The semiconductor device according to claim 1, wherein the ratio of the third distance in the first direction from the upper surface of the first portion to the upper surface of the second insulating layer to the first distance is 0.05 or more and 0.25 or less.

7. The semiconductor device according to claim 6, wherein the third distance is 50 nm or more and 250 nm or less.

8. The gate electrode and the second semiconductor region are arranged alternately in the second direction. The plurality of gate electrodes include a first gate electrode and a second gate electrode that are adjacent to each other in the second direction. The semiconductor device according to any one of claims 1 to 7, wherein the distance between the center of the first gate electrode in the second direction and the center of the second gate electrode in the second direction is 450 nm or more and 650 nm or less.

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