Semiconductor equipment

Abstract

The objective is to provide a semiconductor device that can suppress leakage current. [Solution] The semiconductor device of the embodiment comprises a semiconductor member, a gate electrode, and a source electrode. The semiconductor member has a plurality of grooves and recesses. At least a portion of the source electrode is located inside the recesses. The semiconductor member has a drift region and a mesa region. The drift region has a first conductivity type impurity. The drift region is located first to the bottom of the grooves. The mesa region has a first conductivity type impurity. The mesa region is located between a pair of grooves in a second direction. The mesa region has a Schottky junction that forms a Schottky junction with the source electrode. The Schottky junction is located second to the first end of the source electrode and second to the first end of the gate electrode.

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] Some semiconductor devices, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), form a Schottky barrier diode within the device. In such structures, a problem arises where leakage current increases when the electric field at the Schottky junction is high. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-182235 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a semiconductor device that can suppress leakage current. [Means for solving the problem]

[0005] In the semiconductor device of this embodiment, three intersecting directions are designated as the first, second, and third directions. One side of the third direction is designated as the first side, and the other side as the second side. The semiconductor device comprises a semiconductor member, a drain electrode, a gate electrode, a source electrode, a first insulating layer, and a second insulating layer. The semiconductor member has a plurality of grooves and recesses. The plurality of grooves extend in the first direction, are aligned in the second direction, and are recessed toward the first side. The recesses are located between a pair of grooves in the second direction and are recessed toward the first side. The drain electrode is located on the first side of the semiconductor member. The gate electrode is located inside the grooves. At least a portion of the source electrode is located inside the recesses. The first insulating layer is located inside the grooves. The first insulating layer is located between the inner surface of the grooves and the gate electrode. The second insulating layer is located inside the recesses. The second insulating layer is located between the inner surface of the recesses and the source electrode. The semiconductor member has a drift region and a mesa region. The drift region contains a first-type impurity. The drift region is located first to the bottom of the groove. The mesa region contains a first-type impurity. The mesa region is located between the pair of grooves in a second direction. The mesa region has a Schottky junction that forms a Schottky joint with the source electrode. The Schottky junction is located second to the first end of the source electrode and second to the first end of the gate electrode. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device of the third embodiment, viewed from the thickness direction. [Figure 4] Schematic cross-sectional view of a semiconductor device along the IV-IV line in Figure 3. [Figure 5] Schematic cross-sectional view of a semiconductor device along the VV line in Figure 3. [Figure 6] A schematic cross-sectional view of the semiconductor device according to the fourth embodiment. [Figure 7] A schematic cross-sectional view of the semiconductor device of the fifth embodiment, viewed from the thickness direction. [Figure 8]Schematic cross-sectional view of a semiconductor device along the IIX-IIX line in Figure 7. [Figure 9] Schematic cross-sectional view of a semiconductor device along the line IX-IX in Figure 7. [Figure 10] A schematic cross-sectional view showing the process of forming a gate electrode groove and the internal structure of the gate electrode groove in a semiconductor member in a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 11] A schematic cross-sectional view showing the step of protruding the first insulating layer from the upper surface of a semiconductor member in a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 12] A schematic cross-sectional view showing the step of forming a sidewall on the upper surface of a semiconductor member in the manufacturing method of a semiconductor device according to the fifth embodiment. [Figure 13] A schematic cross-sectional view showing the step of forming an insulating film on the second cross-section of a semiconductor member in the manufacturing method of a semiconductor device according to the fifth embodiment. [Figure 14] A schematic cross-sectional view showing the step of forming a preliminary recess on the upper surface of a semiconductor member in the manufacturing method of a semiconductor device according to the fifth embodiment. [Figure 15] A schematic cross-sectional view showing the step of ion implanting n-type impurities into a semiconductor material in a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 16] A schematic cross-sectional view showing the step of forming a recess for a source electrode in a semiconductor member in the manufacturing method of the fifth embodiment of a semiconductor device. [Figure 17] A schematic cross-sectional view showing the step of removing the wall and insulating film again in the manufacturing method of a semiconductor device according to the fifth embodiment. [Figure 18] A schematic cross-sectional view showing the step of forming a second insulating layer on the surface of a semiconductor member in the manufacturing method of a semiconductor device according to the fifth embodiment. [Figure 19] A schematic cross-sectional view showing the step of forming a contact portion inside a recess for a source electrode in a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 20] A schematic cross-sectional view showing a step of partially removing the second insulating layer in a semiconductor device manufacturing method according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, the semiconductor device of the embodiment will be described with reference to the drawings.

[0008] (First Embodiment) FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to the first embodiment. In the drawings, the X-axis, Y-axis, and Z-axis are shown as appropriate. The X-axis, Y-axis, and Z-axis are orthogonal to each other.

[0009] In this specification, "direction" is defined as a vector including positive and negative concepts parallel to a specific axis. Therefore, "direction" is a concept including two directions (one side and the other side) facing opposite sides. In the following embodiments, the direction parallel to the X-axis corresponds to the "first direction", the direction parallel to the Y-axis corresponds to the "second direction", and the direction parallel to the Z-axis corresponds to the "third direction". Therefore, the first direction X, the second direction Y, and the third direction Z are three directions intersecting each other. Further, in the following embodiments, the side opposite to the side to which the arrow of the Z-axis in the third direction Z points (-Z) is called the lower side or the first side, and the side to which the arrow of the Z-axis in the third direction Z points (+Z) is called the upper side or the second side. Also, the side to which the arrow of the Y-axis in the second direction Y points (+Y) is called the right side or the third side, and the side opposite to the side to which the arrow of the Y-axis in the second direction Y points (-Y) is called the left side or the fourth side. Note that in this specification, the concepts of "upper" and "lower" are not necessarily terms indicating the relationship with the direction of gravity.

[0010] In the following description, n, n + , n - notations represent the relative high and low levels of impurity concentrations in each conductivity type. That is, n + indicates that the impurity concentration of the n-type is relatively higher than that of n, and n - indicates that the impurity concentration of the n-type is relatively lower than that of n.

[0011] As shown in Figure 1, the semiconductor device 1 according to this embodiment comprises a semiconductor member 10, a drain electrode 51, a source electrode 52, a gate electrode 53, a field plate (conductive member) 61, a first insulating layer 42, and a second insulating layer 45. In this specification, the thickness direction of the semiconductor device 1 is the third direction Z.

[0012] The semiconductor device 1 in this embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET). Furthermore, the semiconductor device 1 in this embodiment is a Schottky contact type transistor. The semiconductor device 1 can control the channel layer 14 of the semiconductor material 10 by the potential of the gate electrode 53. That is, the semiconductor device 1 can control the current flowing between the drain electrode 51 and the source electrode 52 by the potential of the gate electrode 53.

[0013] The semiconductor component 10 includes, for example, at least one selected from the group consisting of silicon (Si), nitride semiconductors (e.g., GaN), silicon carbide (SiC), and oxide semiconductors (e.g., GaO).

[0014] The semiconductor member 10 is provided with a plurality of gate electrode grooves (grooves) 21 and a plurality of source electrode grooves (recesses) 22. The gate electrode grooves 21 and source electrode grooves 22 are recessed from the upper surface of the semiconductor member 10 downwards (to one side in the third direction Z). The gate electrode grooves 21 and source electrode grooves 22 extend in the first direction X and are arranged alternately in the second direction Y. Therefore, gate electrode grooves 21 are provided on both sides of the source electrode groove 22 in the second direction Y.

[0015] The inner surface of the gate electrode groove 21 is provided with an upward-facing bottom portion 21a and a pair of side wall portions 21b that face each other in the second direction Y. Similarly, the inner surface of the source electrode groove 22 is provided with an upward-facing bottom portion 22a and a pair of side wall portions 22b that face each other in the second direction Y. The gate electrode groove 21 is formed deeper than the source electrode groove 22.

[0016] The semiconductor component 10 is provided with a substrate portion 15, a drift region 11, and a mesa region 12. The substrate portion 15, the drift region 11, and the mesa region 12 are all n-type semiconductors. When the semiconductor component 10 contains silicon, examples of first conductivity type impurities include pentavalent elements such as phosphorus and arsenic. In other words, the first conductivity type impurities are n-type impurities. In this embodiment, no p-type semiconductor is formed in the semiconductor component 10. Therefore, the manufacturing process of the semiconductor device 1 can be simplified.

[0017] The substrate portion 15 is located at the lower end of the semiconductor member 10. The substrate portion 15 extends along the drain electrode 51 in a first direction X and a second direction Y. The substrate portion 15 is, for example, n + It is a layer.

[0018] The drift region 11 is located below the bottom 21a of the gate electrode groove 21. The drift region 11 extends along the substrate portion 15 in a first direction X and a second direction Y. The drift region 11 is, for example, n layers, or n - It is a layer.

[0019] The mesa region 12 is located in the second direction Y between the pair of gate electrode grooves 21. Except for the source layer 13 described later, n-type impurities diffuse into the mesa region 12 at a concentration similar to that of the drift region 11. That is, except for the source layer 13 described later, the mesa region 12 is, for example, an n-layer, or n - It is a layer.

[0020] The mesa region 12 has a first region 12a, a second region 12b, and a third region 12c. The first region 12a is located to the right (+Y) of the source electrode groove 22, between the gate electrode groove 21 and the source electrode groove 22. The second region 12b is located to the left (-Y) of the source electrode groove 22, between the gate electrode groove 21 and the source electrode groove 22. The third region 12c is located below the first region 12a and the second region 12b. The third region 12c is located below the source electrode groove 22. The third region 12c connects the drift region 11 and the first region 12a. Also, the third region 12c connects the drift region 11 and the second region 12b.

[0021] The second region 12b has a source layer 13 and a channel layer 14. The source layer 13 is located at the upper end of the second region 12b. That is, the source layer 13 is located at the upper end of the semiconductor member 10. The source layer 13 is formed to a certain depth from the upper surface of the semiconductor member 10. The channel layer 14 is located below the source layer 13. The channel layer 14 connects the source layer 13 and the third region 12c. In the source layer 13, n-type impurities are diffused at a higher concentration than in the drift region 11. On the other hand, the channel layer 14 has n-type impurities at a concentration similar to that of the drift region 11. The source layer 13 is, for example, n + It is a layer.

[0022] The drain electrode 51, source electrode 52, gate electrode 53, and field plate 61 each extend along a first direction X. The gate electrode 53 and source electrode 52 are aligned in a second direction Y. The gate electrode 53 and field plate 61 are aligned in a third direction Z.

[0023] The drain electrode 51 is provided on the lower surface of the semiconductor member 10. The drain electrode 51 includes, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0024] The source electrode 52 is positioned, at least in part, inside the source electrode groove 22. The source electrode 52 has an electrode portion 52a and a contact portion 52b. The electrode portion 52a is located on the upper side of the upper surface of the semiconductor member 10. The contact portion 52b is positioned inside the source electrode groove 22.

[0025] The metallic material constituting the source electrode 52 has a higher work function than the semiconductor constituting the drift region 11 and the mesa region 12. Therefore, the source electrode 52 can be Schottky bonded with the first region 12a. In this embodiment, the source electrode 52 is in contact with the first region 12a at the electrode portion 52a. Furthermore, the portion of the first region 12a that is in contact with the electrode portion 52a and forms a Schottky bond is called the Schottky junction portion 32. That is, the first region 12a has a Schottky junction portion 32.

[0026] In this specification, when comparing the work functions of multiple parts, the energy levels of each part shall be compared.

[0027] As described above, the source layer 13 contains a high concentration of n-type impurities. Therefore, the source electrode 52 can form an ohmic bond with the source layer 13. In this embodiment, the source electrode 52 contacts the source layer 13 at the electrode portion 52a. The portion of the source layer 13 that contacts the electrode portion 52a and forms an ohmic bond is called the ohmic junction portion 31. That is, the source layer 13 has an ohmic junction portion 31.

[0028] For example, if the semiconductor material 10 includes silicon, the source electrode 52 includes at least one selected from the group consisting of, for example, Ti, TiN, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf.

[0029] In this embodiment, the case where the electrode portion 52a and the contact portion 52b of the source electrode 52 are made of the same material has been described. However, the electrode portion 52a and the contact portion 52b may be made of different materials.

[0030] The gate electrode 53 is positioned inside the gate electrode groove 21. The gate electrode 53 includes, for example, polysilicon. The gate electrode 53 is insulated from the semiconductor member 10. The gate electrode 53 and the contact portion 52b overlap in the second direction Y. The upper end of the gate electrode 53 is located below the upper end of the contact portion 52b. The lower end of the gate electrode 53 is located below the lower end of the contact portion 52b.

[0031] The field plate 61 is positioned inside the gate electrode groove 21. The field plate 61 is located below the gate electrode 53. The field plate 61 is insulated from the gate electrode 53 and the semiconductor member 10. The field plate 61 is also electrically connected to the source electrode 52, for example, via wiring 52L. This ensures that the field plate 61 and the source electrode 52 are at the same potential.

[0032] By providing a field plate 61 in the gate electrode groove 21, the electric field strength in the drift region 11 can be mitigated. This improves the withstand voltage characteristics between the drain electrode 51 and source electrode 52 of the semiconductor component 10. Furthermore, as the withstand voltage improves, the impurity concentration in the drift region 11 can be set higher, thereby reducing the on-resistance of the semiconductor device 1.

[0033] The first insulating layer 42 is located inside the gate electrode groove 21. The first insulating layer 42 includes a gate insulating film 42a and a field plate insulating film 42b. The gate insulating film 42a is located between the gate electrode 53 and the mesa region 12 of the semiconductor member 10. On the other hand, the field plate insulating film 42b is located between the field plate 61 and the gate electrode 53, and between the field plate 61 and the mesa region 12 and drift region 11 of the semiconductor member 10.

[0034] The second insulating layer 45 is formed on the inner surface of the source electrode groove 22. In this embodiment, the second insulating layer 45 covers the entire inner surface of the source electrode groove 22 (i.e., the entire side wall portion 22b and the entire bottom portion 22a). The second insulating layer 45 is located between the contact portion 52b and the mesa region 12 of the semiconductor member 10, and insulates the contact portion 52b from the mesa region 12.

[0035] The second insulating layer 45 of this embodiment has a first layer 45a and a second layer 45b that are stacked on top of each other. The first layer 45a is located on the side of the mesa region 12 between the mesa region 12 and the contact portion 52b. On the other hand, the second layer 45b is located on the side of the contact portion 52b between the mesa region 12 and the contact portion 52b. In this embodiment, the first layer 45a is, for example, silicon oxide (SiO2), and the second layer 45b is, for example, aluminum oxide (Al2O3). Alternatively, the first layer 45a may be lanthanum(III) oxide (La2O3) and the second layer 45b may be silicon oxide (SiO2). Furthermore, the first layer 45a may be lanthanum(III) oxide (La2O3) and the second layer 45b may be aluminum oxide (Al2O3).

[0036] In this embodiment, a dipole effect can be expected in the second insulating layer 45. That is, polarization occurs in the first layer 45a and the second layer 45b in the second insulating layer 45. As a result, an electric field is generated inside the second insulating layer 45, and depletion is promoted in the portion of the mesa region 12 facing the first layer 45a (for example, the first region 12a).

[0037] Next, the operating principle of the semiconductor device 1 of this embodiment will be described. In this embodiment, the electrode portion 52a and the source layer 13 of the second region 12b are ohmic junctions. Therefore, the electrode portion 52a and the second region 12b are electrically connected. Furthermore, because the work function of the contact portion 52b is higher than the electron affinity of the channel layer 14, a depletion layer is formed in the channel layer 14 of the second region 12b. In addition, the first layer 45a and the second layer 45b of the second insulating layer 45 promote depletion of the channel layer 14 due to the dipole effect of polarization between them. Therefore, when no voltage is applied to the gate electrode 53, an off state is obtained in which no current flows in the channel layer 14 due to the depletion layer. By controlling the potential of the gate electrode 53, an electron storage layer is formed in the channel layer 14, and an on state is obtained in which a drain current flows in the channel layer 14. Therefore, in the semiconductor device 1, the current between the drain electrode 51 and the electrode portion 52a is controlled by the potential of the gate electrode 53. Here, the potential of the gate electrode 53 is a potential relative to the potential of the electrode portion 52a.

[0038] In this embodiment, the electrode portion 52a and the first region 12a are connected by a Schottky junction. Therefore, the electrode portion 52a and the first region 12a function as a Schottky barrier diode S, making it possible to pass current from the electrode portion 52a to the first region 12a.

[0039] If a strong electric field is formed in the first region 12a where the source electrode 52 and Schottky junction are connected, the leakage current of the Schottky barrier diode S will increase. In this embodiment, the Schottky junction 32 is provided at the upper end of the first region 12a. The upper end of the first region 12a is surrounded by the gate electrode 53 and the contact portion 52b and electrode portion 52a of the source electrode 52. Therefore, a strong electric field is less likely to be generated at the upper end of the first region 12a, and the leakage current of the Schottky barrier diode S can be suppressed.

[0040] In this embodiment, it is preferable that the Schottky junction 32 is located above the upper end of the gate electrode 53. If the Schottky junction 32 is positioned to overlap with the gate electrode 53 in the second direction Y, the gate electrode 53 and the contact portion 52b will be close together. In this case, it becomes difficult to ensure insulation between the gate electrode 53 and the contact portion 52b, and it becomes necessary to increase the thickness of the first insulating layer 42. By positioning the Schottky junction 32 above the upper end of the gate electrode 53, it becomes easier to ensure insulation between the contact portion 52b and the gate electrode 53. As a result, the first insulating layer 42 can be made thinner, reducing the channel resistance of the semiconductor device 1 and suppressing its size increase.

[0041] In this embodiment, the Schottky joint 32 is arranged on the same plane as the ohmic joint 31. However, the Schottky joint 32 may be located, for example, below the ohmic joint 31.

[0042] Next, the effects and advantages of this embodiment will be described. In the semiconductor device 1 of this embodiment, the three intersecting directions are defined as the first direction X, the second direction Y, and the third direction Z, with one side of the third direction Z being the lower side (-Z) and the other side being the upper side (+Z). The semiconductor device 1 includes a semiconductor member 10, a drain electrode 51, a gate electrode 53, a source electrode 52, a first insulating layer 42, and a second insulating layer 45. The semiconductor member 10 has a plurality of gate electrode grooves 21 and a source electrode groove 22. The plurality of gate electrode grooves 21 extend in the first direction X, are aligned in the second direction Y, and are recessed to the lower side (-Z). The source electrode groove 22 is located between a pair of gate electrode grooves 21 in the second direction Y and is recessed to the lower side (-Z). The drain electrode 51 is located on the lower side (-Z) of the semiconductor member 10. The gate electrode 53 is arranged inside the gate electrode groove 21. At least a portion of the source electrode 52 is arranged inside the source electrode groove 22. The first insulating layer 42 is located inside the gate electrode groove 21. The first insulating layer 42 is located between the inner surface of the gate electrode groove 21 and the gate electrode 53. The second insulating layer 45 is located inside the source electrode groove 22. The second insulating layer 45 is located between the inner surface of the source electrode groove 22 and the source electrode 52. The semiconductor member 10 has a drift region 11 and a mesa region 12. The drift region 11 has n-type impurities. The drift region 11 is located below the bottom (-Z) of the gate electrode groove 21. The mesa region 12 has n-type impurities. The mesa region 12 is located between a pair of gate electrode grooves 21 in the second direction Y. The mesa region 12 has a Schottky junction 32 that forms a Schottky junction with the source electrode 52. The Schottky junction 32 is located above (+Z) the lower (-Z) end of the source electrode 52 and above (+Z) the lower (-Z) end of the gate electrode 53.

[0043] In this configuration, the source electrode 52 can form a Schottky junction with the mesa region 12 to constitute a Schottky barrier diode S. A Schottky barrier diode S tends to have a large leakage current when the electric field strength of the Schottky junction 32 is high. In this configuration, the Schottky junction 32 is located above the lower ends of both the source electrode 52 and the gate electrode 53. Therefore, the Schottky junction 32 is provided in the region of the mesa region 12 sandwiched between the source electrode 52 and the gate electrode 53 (the first region 12a in this embodiment). As a result, the electric field strength of the first region 12a can be mitigated, and the leakage current of the Schottky barrier diode S can be suppressed.

[0044] In the semiconductor device 1 of this embodiment, the mesa region 12 has a source layer 13 at its upper (+Z) end where the concentration of n-type impurities is higher than that of the drift region 11. The source layer 13 has an ohmic junction 31 that forms an ohmic junction with the source electrode 52. With this configuration, current can be passed from the ON-state mesa region 12 to the source electrode 52 via the ohmic junction 31.

[0045] In the semiconductor device 1 of this embodiment, one side of the second direction Y is designated as the right side (+Y), and the other side as the left side (-Y). The mesa region 12 has a first region 12a and a second region 12b. The first region 12a is located to the right (+Y) of the source electrode groove 22. The second region 12b is located to the left (-Y) of the source electrode groove 22. The second region 12b has a source layer 13. The Schottky junction 32 is provided in the first region 12a.

[0046] This configuration allows for the separation of the first region 12a and the second region 12b with a source electrode groove 22 in a simple structure. This enables the construction of a semiconductor device 1 in which the channel layer 14 and the Schottky barrier diode S are densely arranged in a single mesa region 12.

[0047] In the semiconductor device 1 of this embodiment, the Schottky junction 32 is located above (+Z) the upper (+Z) end of the gate electrode 53. This configuration makes it easier to secure the distance between the gate electrode 53 and the contact portion 52b. As a result, it becomes easier to ensure insulation between the gate electrode 53 and the contact portion 52b, the first insulating layer 42 can be made thinner, the channel resistance of the semiconductor device 1 can be reduced and miniaturized.

[0048] The semiconductor device 1 of this embodiment has a field plate 61. The field plate 61 is located inside the gate electrode groove 21, between the gate electrode 53 and the drift region 11. The field plate 61 is insulated from the gate electrode 53. The field plate 61 is electrically connected to the source electrode 52. With this configuration, by providing the field plate 61, the electric field strength of the drift region 11 can be mitigated, and the dielectric strength of the semiconductor device 1 can be improved. In addition, by providing the field plate 61, the electric field strength of the first region 12a can also be mitigated, and the leakage current of the Schottky barrier diode S can be suppressed. In this embodiment, the case in which the semiconductor device 1 has a field plate 61 has been described, but the semiconductor device 1 does not have to have a field plate 61.

[0049] The second insulating layer 45 of this embodiment has a polarizing first layer 45a and a second layer 45b. As a result, the depletion of the channel layer 14 becomes significant due to the dipole effect, and it becomes impossible to pass current through the channel layer 14 (i.e., turn it on) without applying a large voltage to the gate electrode 53. In other words, according to this embodiment, the gate threshold voltage can be increased by having a polarizing first layer 45a and a second layer 45b in the second insulating layer 45.

[0050] In the semiconductor device 1 of this embodiment, the case where the concentrations of the n-type impurities in the first region 12a, the channel layer 14 of the second region 12b, the third region 12c, and the drift region 11 are equal has been described. However, the concentration of the n-type impurities in the first region 12a and the channel layer 14 may be adjusted. For example, in FIG. 1, the concentration of the n-type impurities in the region A surrounded by the virtual line (dashed double-dotted line) may be made lower than the concentration of the n-type impurities in the drift region 11. The region A is, for example, an n - layer. The region A includes the first region 12a and the channel layer 14 of the second region 12b.

[0051] In this embodiment, by making the concentration of the n-type impurities in the first region 12a lower than the concentration of the n-type impurities in the drift region 11, the electric field strength in the first region 12a can be further relaxed. Thereby, it becomes possible to further reduce the leakage current of the Schottky barrier diode S.

[0052] In this embodiment, by making the concentration of the n-type impurities in the channel layer 14 of the second region 12b lower than the concentration of the n-type impurities in the drift region 11, the channel layer 14 is more likely to be further depleted in the off state. Thereby, it becomes possible to increase the gate threshold voltage.

[0053] (Second Embodiment) FIG. 2 is a schematic cross-sectional view of the semiconductor device 101 of the second embodiment. Compared with the first embodiment, the semiconductor device 101 of the second embodiment mainly differs in the ranges where the Schottky junction 132 and the ohmic junction 131 are formed.

[0054] In each of the embodiments described below, for the components having the same aspects as those of the already described embodiments, the same reference numerals are given and the description thereof is omitted.

[0055] Similar to the embodiment described above, the semiconductor member 10 is provided with a gate electrode groove 21 and a source electrode groove 22. A second insulating layer 145 is formed on the inner surface of the source electrode groove 22. A contact portion 52b is also arranged inside the source electrode groove 22.

[0056] In this embodiment, the second insulating layer 145 is formed on the inner surface of the source electrode groove 22, excluding the upper end of the side wall portion 22b. That is, the second insulating layer 145 is not formed on the upper end of the side wall portion 22b. In other words, the upper end of the inner surface of the source electrode groove 22 is exposed from the second insulating layer 145. Therefore, the upper end of the contact portion 52b contacts the upper end of the first region 12a and the upper end of the second region 12b (source layer 13), respectively. Here, the portion of the upper end of the contact portion 52b that contacts the first region 12a is called the first portion 52c, and the portion that contacts the source layer 13 is called the second portion 52d. That is, the contact portion 52b has a first portion 52c and a second portion 52d. The first portion 52c is located at the upper end of the surface of the contact portion 52b facing to the right (+Y). The second portion 52d is located at the upper end of the left (-Y) facing surface of the contact portion 52b.

[0057] In this embodiment, the first portion 52c is Schottky bonded with the first region 12a at the upper end of the source electrode groove 22. Therefore, in this embodiment, the first region 12a is Schottky bonded not only with the lower surface of the electrode portion 52a, but also with the upper end of the right-facing (+Y) surface of the contact portion 52b.

[0058] According to this embodiment, the Schottky junction 132 has a first junction 132a that is joined to the electrode portion 52a, and a second junction 132b that is joined to the first portion 52c of the contact portion 52b. The first junction 132a extends along a plane (XY plane) perpendicular to the third direction Z. The second junction 132b extends along a plane (XZ plane) perpendicular to the second direction Y. According to this embodiment, the joining area of ​​the Schottky junction 132 can be made larger without increasing the size of the semiconductor device 101, and the electrical resistance of the Schottky junction 132 can be reduced.

[0059] In this embodiment, the Schottky junction 132 is located above the lower ends of both the source electrode 52 and the gate electrode 53, similar to the embodiment described above. Therefore, the electric field strength in the first region 12a can be reduced, and the leakage current of the Schottky barrier diode S can be suppressed.

[0060] In this embodiment, the second portion 52d is ohmic-bonded to the source layer 13 at the upper end of the source electrode groove 22. Therefore, the source layer 13 in this embodiment is Schottky-bonded not only to the lower surface of the electrode portion 52a but also to the upper end of the left side (-Y) of the contact portion 52b.

[0061] According to this embodiment, the ohmic junction 131 has a third junction 131a that is joined to the electrode portion 52a, and a fourth junction 131b that is joined to the second portion 52d of the contact portion 52b. The third junction 131a extends along a plane (XY plane) perpendicular to the third direction Z. The fourth junction 131b extends along a plane (XZ plane) perpendicular to the second direction Y. According to this embodiment, the joining area of ​​the ohmic junction 131 can be made larger without increasing the size of the semiconductor device 101, and the electrical resistance of the ohmic junction 131 can be reduced.

[0062] Furthermore, in this embodiment, it is preferable that the lower ends of the second junction 132b and the fourth junction 131b are located above (+Z) the upper end of the gate electrode 53. In this case, the alignment of the second junction 132b and the gate electrode 53 in the second direction Y can be suppressed. This makes it easier to ensure insulation between the gate electrode 53 and the first portion 52c. Also, the alignment of the fourth junction 131b and the gate electrode 53 in the second direction Y can be suppressed. This makes it easier to ensure insulation between the gate electrode 53 and the second portion 52d. According to this embodiment, the electrical resistance of the Schottky junction 132 and the ohmic junction 131 can be reduced while the first insulating layer 42 can be made thinner, thereby enabling miniaturization of the semiconductor device 101.

[0063] In addition, in the semiconductor device 101 of this embodiment, similar to the first embodiment, the concentration of n-type impurities in the channel layer 14 of the first region 12a and the second region 12b may be lower than the concentration of n-type impurities in the drift region 11.

[0064] (Third embodiment) Figure 3 is a schematic cross-sectional view of the semiconductor device 201 of the third embodiment, viewed from the thickness direction. Figure 4 is a schematic cross-sectional view of the semiconductor device 201 along the line IV-IV in Figure 3. Figure 5 is a schematic cross-sectional view of the semiconductor device 201 along the line VV in Figure 3. The semiconductor device 201 of the third embodiment differs from the first embodiment mainly in the arrangement of the Schottky junction 232 and the ohmic junction 231.

[0065] In this embodiment, the semiconductor device 201 has the cross-sections shown in Figure 4 and Figure 5 alternately formed along the first direction X. Hereinafter, the cross-section shown in Figure 4 will be referred to as the first cross-section, and the cross-section shown in Figure 5 will be referred to as the second cross-section.

[0066] As shown in Figures 4 and 5, in the semiconductor device 201 of this embodiment, the semiconductor member 210 is provided with a substrate portion 15, a drift region 11, and a mesa region 212. The mesa region 212 is located between a pair of gate electrode grooves 21. The mesa region 212 has a first region 212a provided in the first cross section (Figure 4), a second region 212b provided in the second cross section (Figure 5), and a third region 12c provided in both the first and second cross sections. The third region 12c is located below the source electrode groove 22. The third region 12c connects the drift region 11 and the first region 212a. The third region 12c also connects the drift region 11 and the second region 212b.

[0067] In the first cross-section shown in Figure 4, the first region 212a is located between the gate electrode groove 21 and the source electrode groove 22 on the right side (+Y) and left side (-Y) of the source electrode groove 22. The upper end of the first region 212a is in contact with the electrode portion 52a. A Schottky junction 232 is provided in the portion of the first region 212a that is in contact with the electrode portion 52a. In the first cross-section, the Schottky junction 232 is provided on the right side and left side of the source electrode groove 22, respectively.

[0068] In the second cross-section shown in Figure 5, the second region 212b is located between the gate electrode groove 21 and the source electrode groove 22 on the right side (+Y) and left side (-Y) of the source electrode groove 22. The second region 212b has a source layer 13 and a channel layer 14. The source layer 13 is located at the upper end of the second region 212b. The upper end of the source layer 13 is in contact with the electrode portion 52a. An ohmic junction 231 is provided in the portion of the source layer 13 that is in contact with the electrode portion 52a. In the second cross-section, the ohmic junction 231 is provided on the right side and left side of the source electrode groove 22, respectively.

[0069] According to the semiconductor device 201 of this embodiment, similar to the embodiment described above, the Schottky junction 232 is located above the lower ends of both the source electrode 52 and the gate electrode 53. Therefore, the electric field strength of the first region 212a can be reduced, and the leakage current of the Schottky barrier diode S can be suppressed.

[0070] In the semiconductor device 201 of this embodiment, the mesa region 212 has a first region 212a and a second region 212b. The first region 212a and the second region 212b are located between the gate electrode groove 21 and the source electrode groove 22 in the second direction Y. The first region 212a and the second region 212b are aligned in the first direction X. The second region 212b has a source layer 13. The Schottky junction 232 is provided in the first region 212a.

[0071] According to this embodiment, the Schottky junction 232 and the ohmic junction 231 can be arranged side by side in the first direction X. In this embodiment, the ratio of the Schottky junction 232 to the ohmic junction 231 in the first direction X may be changed. In this case, the ratio of the resistance values ​​of the Schottky junction 232 and the ohmic junction 231 can be easily adjusted. For example, by making the length dimension of the ohmic junction 231 in the first direction X larger than the length dimension of the Schottky junction 232 in the first direction X, the resistance value of the Schottky junction 232 can be reduced. In this case, the length dimension of the channel layer 14 in the first direction X is also increased, making it possible to configure a semiconductor device 201 with low on-resistance.

[0072] In this embodiment, the semiconductor device 201 has first regions 212a located to the right and left of the source electrode groove 22 in the first cross-section (see Figure 4). In the second cross-section (see Figure 5), second regions 212b are located to the right and left of the source electrode groove 22. That is, in this embodiment, the positions in the first direction X of the first region 212a located to the right of the source electrode groove 22 and the first region 212a located to the left of the source electrode groove 22 overlap. Also, in this embodiment, the positions in the first direction X of the second region 212b located to the right of the source electrode groove 22 and the second region 212b located to the left of the source electrode groove 22 overlap. However, the first regions 212a located to the right and left of the source electrode groove 22 may be offset from each other in the first direction X. Similarly, the second regions 212b located to the right and left of the source electrode groove 22 may be offset from each other in the first direction X. For example, in the first cross-section, the first region 212a may be located to the right of the source electrode groove 22 and the second region 212b to the left, and in the second cross-section, the second region 212b may be located to the right of the source electrode groove 22 and the first region 212a to the left. In this case, it becomes possible to pass current over a wider range in the first direction X, thereby further reducing the on-resistance.

[0073] In typical semiconductor devices, the current flowing through the channel layer in the ON state tends to concentrate near the corners of the source electrode grooves. According to this embodiment, since the first region 212a and the second region 212b are aligned in the first direction X, the current flowing through the channel layer 14 in the ON state can be spread out in the first direction X on the underside of the channel layer 14. As a result, the current flows not only in the third region 12c of the second cross-section (Figure 5) but also in the third region 12c of the first cross-section (Figure 4). According to this embodiment, current concentration in the mesa region 212 is mitigated, and the ON resistance of the semiconductor device 201 is suppressed.

[0074] In the semiconductor device 201 of this embodiment, the concentrations of n-type impurities in the first region 212a and the second region 212b may be adjusted. For example, the concentration of n-type impurities in region A, enclosed by dashed lines (dotted lines) shown in Figures 4 and 5, may be lower than the concentration of n-type impurities in the drift region 11. By lowering the concentration of n-type impurities in the first region 212a to that of the drift region 11, the electric field strength of the first region 212a can be further reduced. Also, by lowering the concentration of n-type impurities in the channel layer 14 of the second region 212b to that of the drift region 11, the channel layer 14 becomes more easily depleted when it is off.

[0075] (Fourth Embodiment) Figure 6 is a schematic cross-sectional view of the semiconductor device 301 according to the fourth embodiment. The semiconductor device 301 of the fourth embodiment differs from that of the first embodiment mainly in the number of source electrode grooves 322.

[0076] Similar to the embodiment described above, the semiconductor member 310 is provided with gate electrode grooves 21 and source electrode grooves (recesses) 322. In this embodiment, a pair of source electrode grooves 322 are arranged between a pair of gate electrode grooves 21 aligned in the second direction Y. A second insulating layer 45 is formed on the inner surface of each of the pair of source electrode grooves 322. Contact portions 352b are provided inside each of the pair of source electrode grooves 322. Therefore, a pair of contact portions 352b aligned in the second direction Y are arranged between a pair of gate electrode grooves 53 aligned in the second direction Y.

[0077] In the semiconductor device 301 of this embodiment, the semiconductor member 310 is provided with a substrate portion 15, a drift region 11, and a mesa region 312. The mesa region 312 is located between a pair of gate electrode grooves 21. The mesa region 312 has a first region 312a, a pair of second regions 312b, and a third region 12c. The third region 12c is located below the source electrode groove 322. The third region 12c connects the drift region 11 and the first region 312a. The third region 12c also connects the drift region 11 and the second region 312b.

[0078] The first region 312a is located between a pair of source electrode grooves 322. The upper end of the first region 312a is in contact with the electrode portion 52a. A Schottky junction 332 is provided in the portion of the first region 312a that is in contact with the electrode portion 52a. The Schottky junction 332 is provided between the pair of source electrode grooves 322.

[0079] The second region 312b is located on the right (+Y) and left (-Y) sides of the pair of source electrode grooves 322, respectively. One of the pair of second regions 312b located on the right (+Y) side is located between the one of the pair of source electrode grooves 322 located on the right (+Y) side and the gate electrode groove 21. The other of the pair of second regions 312b located on the left (-Y) side is located between the other of the pair of source electrode grooves 322 located on the left (-Y) side and the gate electrode groove 21. The second region 312b has a source layer 13 and a channel layer 14. The source layer 13 is located at the upper end of the second region 312b. The upper end of the source layer 13 is in contact with the electrode portion 52a. An ohmic junction 331 is provided in the portion of the source layer 13 that is in contact with the electrode portion 52a. The ohmic junction 331 is provided on the right and left sides of the pair of source electrode grooves 322, respectively.

[0080] In this embodiment, the Schottky junction 332 is located above the lower ends of both the source electrode 52 and the gate electrode 53, similar to the embodiment described above. This allows for a reduction in the electric field strength of the first region 312a, thereby suppressing the leakage current of the Schottky barrier diode S. In this embodiment, the Schottky junction 332 is arranged on the same plane as the ohmic junction 331. However, the Schottky junction 332 may also be located below, for example, the ohmic junction 331.

[0081] In the semiconductor device 301 of this embodiment, the semiconductor member 310 has a pair of source electrode grooves 322 located between a pair of gate electrode grooves 21 and aligned in the second direction Y. The mesa region 312 has a first region 312a and a pair of second regions 312b. The first region 312a is located between the pair of source electrode grooves 322. The second regions 312b are located to the right (+Y) and left (-Y) of the pair of source electrode grooves, respectively. The second regions 312b have a source layer 13. A Schottky junction 332 is provided in the first region 312a. According to the semiconductor device 301 of this embodiment, two channel layers 14 can be arranged in one mesa region 312. This reduces the resistance value of the channel layers 14, and provides a semiconductor device 301 with low on-resistance.

[0082] In the semiconductor device 301 of this embodiment, the concentrations of n-type impurities in the first region 312a and the second region 312b may be adjusted. For example, the concentration of n-type impurities in region A, enclosed by the dashed lines (two-dot lines) shown in Figure 6, may be lower than the concentration of n-type impurities in the drift region 11. By lowering the concentration of n-type impurities in the first region 312a to that of the drift region 11, the electric field strength of the first region 312a can be further reduced. Also, by lowering the concentration of n-type impurities in the channel layer 14 of the second region 312b to that of the drift region 11, the channel layer 14 becomes more easily depleted when it is off.

[0083] (Fifth embodiment) Figure 7 is a schematic cross-sectional view of the semiconductor device 401 of the fifth embodiment, viewed from the thickness direction. Figure 8 is a schematic cross-sectional view of the semiconductor device 401 along the line IIX-IIX in Figure 7. Figure 9 is a schematic cross-sectional view of the semiconductor device 401 along the line IX-IX in Figure 7. The semiconductor device 401 of the fifth embodiment differs from the first embodiment mainly in the arrangement of the Schottky junction 432 and the ohmic junction 431.

[0084] In this embodiment, the semiconductor device 401 has the cross-sections shown in Figure 8 and Figure 9 alternately formed along the first direction X. Hereinafter, the cross-section shown in Figure 8 will be referred to as the first cross-section, and the cross-section shown in Figure 9 will be referred to as the second cross-section.

[0085] As shown in Figure 7, the semiconductor member 410 is provided with a plurality of gate electrode grooves 21 and a plurality of source electrode recesses (recesses) 422. Similar to the embodiment described above, the plurality of gate electrode grooves 21 are aligned in the second direction. The plurality of source electrode recesses 422 are aligned along the first direction X between a pair of gate electrode grooves 21. A second insulating layer 445 is formed on the inner surface of each of the plurality of source electrode recesses 422. A contact portion 452b is provided inside each of the plurality of source electrode recesses 422. Therefore, the plurality of contact portions 452b aligned in the first direction X are arranged between a pair of gate electrodes 53 aligned in the second direction Y.

[0086] As shown in Figures 8 and 9, in the semiconductor device 401 of this embodiment, the semiconductor member 410 is provided with a substrate portion 15, a drift region 11, and a mesa region 412. The mesa region 412 is located between a pair of gate electrode grooves 21. The mesa region 412 has a first region 412a provided in the second cross section (Figure 9), a second region 412b provided in the first cross section (Figure 8), and a third region 12c provided in both the first and second cross sections. The third region 12c is located below the source electrode recess 422. The third region 12c connects the drift region 11 and the first region 412a. The third region 12c also connects the drift region 11 and the second region 412b.

[0087] As shown in Figure 7, the first region 412a is located between the source electrode recesses 422 aligned in the first direction X. As shown in Figure 9, the upper end of the first region 412a is in contact with the electrode portion 52a. A Schottky junction 432 is provided in the portion of the first region 412a that is in contact with the electrode portion 52a.

[0088] In the first cross-section shown in Figure 8, the second region 412b is located between the gate electrode groove 21 and the source electrode recess 422 on the right side (+Y) and left side (-Y) of the source electrode recess 422. The second region 412b has a source layer 13 and a channel layer 14. The source layer 13 is located at the upper end of the second region 412b. The upper end of the source layer 13 is in contact with the electrode portion 52a. An ohmic junction 431 is provided in the portion of the source layer 13 that is in contact with the electrode portion 52a. In the first cross-section, the ohmic junction 431 is provided on the right side and left side of the source electrode recess 422, respectively.

[0089] In the semiconductor device 401 of this embodiment, similar to the embodiment described above, the Schottky junction 432 is located above the lower ends of both the source electrode 52 and the gate electrode 53. Therefore, the electric field strength of the first region 412a can be reduced, and the leakage current of the Schottky barrier diode S can be suppressed. In this embodiment, the Schottky junction 432 is arranged on the same plane as the ohmic junction 431. However, the Schottky junction 432 may be located below, for example, the ohmic junction 431.

[0090] In the semiconductor device 401 of this embodiment, the semiconductor member 410 has a plurality of source electrode recesses 422. The plurality of source electrode recesses 422 are located between a pair of gate electrode grooves 21. The plurality of source electrode recesses 422 are aligned in a first direction X. The mesa region 412 has a first region 412a and a second region 412b. The first region 412a is located between the plurality of source electrode recesses 422 in the first direction X. The second region 412b is located between the gate electrode groove 21 and the source electrode recesses 422 in a second direction Y. The second region 412b has a source layer 13. A Schottky junction 432 is provided in the first region 412a.

[0091] According to this embodiment, the first region 412a and the second region 412b are aligned in the first direction X. Therefore, the current flowing through the channel layer 14 in the ON state can be spread out in the first direction X on the underside of the channel layer 14. As a result, the current flows not only in the third region 12c of the first cross-section (Figure 8) but also in the third region 12c of the second cross-section (Figure 9). According to this embodiment, current concentration in the mesa region 412 is mitigated, and the electrical resistance of the mesa region 412 is reduced. As a result, the ON resistance of the semiconductor device 401 is suppressed.

[0092] As shown in Figure 7, in the semiconductor device 401 of this embodiment, the dimension w1 of the first region 412a in the first direction X is smaller than the dimension w2 of the source electrode recess 422 in the first direction X. In this embodiment, if the dimension of the first region 412a in the first direction X is too large, the central part of the first region 412a in the first direction X may separate from the contact portion 452b, potentially increasing the electric field strength. According to this embodiment, the dimension w1 of the first region 412a in the first direction X can be made sufficiently small compared to the size of the contact portion 452b provided in the source electrode recess 422. This makes it possible to mitigate the electric field strength across the entire area of ​​the first region 412a in the first direction X, thereby suppressing the leakage current of the Schottky barrier diode S. The dimension w1 of the first region 412a in the first direction X is preferably 1 μm or less, and more preferably 500 nm or less. In addition, according to this embodiment, by ensuring a large dimension w2 in the first direction X of the source electrode recess 422, the channel layers 14 located on both sides of the source electrode recess 422 in the second direction Y can be made larger in the first direction X. This makes it possible to construct a semiconductor device 401 with low on-resistance.

[0093] In the semiconductor device 401 of this embodiment, the concentrations of n-type impurities in the first region 412a and the second region 412b may be adjusted. For example, by lowering the concentration of n-type impurities in the first region 412a to a lower level than the concentration of n-type impurities in the drift region 11, the electric field strength of the first region 412a can be further reduced. Also, by lowering the concentration of n-type impurities in the channel layer 14 of the second region 412b to a lower level than the concentration of n-type impurities in the drift region 11, the channel layer 14 becomes more easily depleted when it is off.

[0094] Next, the manufacturing method of the semiconductor device 401 of this embodiment will be described using Figures 10 to 20. In Figures 10 to 20, the first cross-section of each process is placed on the upper side of the paper and the second cross-section is placed on the lower side of the paper. That is, in each of Figures 10 to 20, the cross-section placed on the upper side of the paper corresponds to the IIX-IIX line in Figure 7, and the cross-section placed on the lower side of the paper corresponds to the IX-IX line in Figure 7.

[0095] In the manufacturing method of the semiconductor device 401 of this embodiment, first, a semiconductor member 410 containing n-type impurities throughout is prepared. Next, n-type impurities are diffused into the lower end of the semiconductor member 410 to form a substrate portion 15 with a high concentration of n-type impurities. Alternatively, the substrate portion 15 may be prepared and the semiconductor member 410 may be formed by epitaxial growth or the like. Next, as shown in Figure 10, a gate electrode groove 21 is formed in the semiconductor member 410, and a field plate 61 embedded in the first insulating layer 42 and a gate electrode 53 are formed inside the gate electrode groove 21.

[0096] Next, as shown in Figure 11, the upper surface of the semiconductor member 410 is etched. This causes the first insulating layer 42 to protrude from the upper surface of the semiconductor member 410.

[0097] Next, as shown in Figure 12, sidewalls 441 are formed on both the left and right sides of the upper end of the first insulating layer 42 that protrudes from the upper surface of the semiconductor member 410. The sidewalls 441 are formed, for example, by forming an insulating film on the surface of the first insulating layer 42 and the semiconductor member 410 using a film deposition method such as CVD, and then etching this insulating film by anisotropic etching. After etching, the insulating film remaining on both the left and right sides of the upper end of the first insulating layer 42 is the sidewall 441.

[0098] Next, as shown in Figure 13, an insulating film 471 or resist is selectively formed on the second cross-section. Furthermore, as shown in Figure 14, by etching the semiconductor member 410, a preliminary recess 410a is formed only on the first cross-section of the semiconductor member 410. At this time, the sidewall 441 functions as a mask, and the portion of the semiconductor member 410 directly beneath the sidewall 441 is not etched. Therefore, the preliminary recess 410a is formed in a region that is separated from the gate electrode groove 21 by the thickness of the sidewall 441 in the left-right direction.

[0099] Next, as shown in Figure 15, n-type impurities are ion-implanted into the upper surface of the semiconductor member 410. This forms a source layer 13 on the upper part of the semiconductor member 410 where n-type impurities diffuse at a high concentration. At this time, the insulating film 471 formed on the upper surface of the semiconductor member 410 in the second cross-section functions as a mask, and the source layer 13 is not formed on the semiconductor member 410 in the second cross-section.

[0100] Next, as shown in Figure 16, the semiconductor member 410 is etched only on the first cross-section to form a source electrode recess 422 in the semiconductor member 410. At this time, since the sidewall 441 functions as a mask, the source electrode recess 422 is formed in a region that is separated from the gate electrode groove 21 by the thickness of the sidewall 441 in the left-right direction. According to this embodiment, the distance between the source electrode recess 422 and the gate electrode groove 21 can be precisely adjusted by the dimensions of the sidewall 441. Therefore, it becomes possible to precisely control the dimensions of the channel layer 14 shown in Figure 8, and a semiconductor device 401 with suppressed variations in gate threshold voltage can be manufactured.

[0101] Next, as shown in Figure 17, the sidewall 441 is removed in the first cross-section, and the insulating film 471 is removed in the second cross-section. Then, as shown in Figure 18, a second insulating layer 445 is formed on the surface of the semiconductor member 410 and the first insulating layer 42. Next, as shown in Figure 19, a contact portion 452b is formed inside the source electrode recess 422. In the process of forming the contact portion 452b, for example, first, a film of the material constituting the contact portion 452b is formed so as to embed the source electrode recess 422 on the upper side of the semiconductor member 410. Next, the portion of this film located above the source electrode recess 422 is removed, for example, by CMP (Chemical Mechanical Polishing), leaving only the contact portion 452b.

[0102] Next, as shown in Figure 20, the second insulating layer 445 is etched until the source layer 13 is exposed. Furthermore, as shown in Figures 8 and 9, an electrode portion 52a is formed on the upper side of the semiconductor member 410, and a drain electrode 51 is formed on the lower side of the semiconductor member 410. In this way, the semiconductor device 401 is obtained.

[0103] The method for manufacturing the semiconductor device 401 in this embodiment is just one example, and the semiconductor device 401 may be manufactured by other procedures. In this specification, the method for manufacturing a semiconductor device has been described using the semiconductor device 401 of the fifth embodiment as an example. However, semiconductor devices 1, 101, 201, and 301 of other embodiments can also be manufactured by appropriately modifying each step of the manufacturing method of the fifth embodiment to suit the configuration of each embodiment.

[0104] According to at least one embodiment described above, the Schottky junctions 32, 132, 232, 332, and 432 located above the lower ends of both the source electrode 52 and the gate electrode 53 can suppress the leakage current of the Schottky barrier diode S.

[0105] The present invention includes the following appended embodiments. (Note 1) The three intersecting directions are designated as the first direction, the second direction, and the third direction, with one side of the third direction designated as the first side and the other side as the second side. A semiconductor member having a plurality of grooves extending in the first direction and aligned in the second direction and recessed toward the first side, and a recess located between a pair of the grooves in the second direction and recessed toward the first side, The drain electrode 51 located on the first side of the semiconductor member, A gate electrode disposed inside the groove, A source electrode, at least a portion of which is disposed inside the recess, A first insulating layer is disposed inside the groove and located between the inner surface of the groove and the gate electrode, The system comprises a second insulating layer disposed inside the recess and positioned between the inner surface of the recess and the source electrode, The aforementioned semiconductor member is A drift region having a first type of conductive impurity and located on the first side of the bottom of the groove, Having the first conductive impurity and a mesa region located between a pair of grooves in a second direction, The mesa region has a Schottky junction that forms a Schottky bond with the source electrode, The Schottky junction is located on the second side of the first end of the source electrode, and on the second side of the first end of the gate electrode. Semiconductor equipment. (Note 2) The mesa region has a source layer at the second end where the concentration of the first conductivity type impurity is higher than that of the drift region. The source layer has an ohmic junction that ohmic-bonds with the source electrode. The semiconductor device described in Appendix 1. (Note 3) Let one side of the second direction be the third side and the other side be the fourth side. The aforementioned mesa region is The first region located on the third side of the recess, The recess has a second region located on the fourth side and having the source layer, The Schottky junction is provided in the first region, Semiconductor device as described in Appendix 2. (Note 4) The mesa region has a first region and a second region located between the groove and the recess in the second direction and aligned in the first direction. The second region has the source layer, The Schottky junction is provided in the first region, Semiconductor device as described in Appendix 2. (Note 5) The Schottky junction is located on the second side of the second end of the gate electrode, The semiconductor device described in Appendix 3 or 4. (Note 6) Let one side of the second direction be the third side and the other side be the fourth side. The semiconductor member has a pair of recesses located between the pair of grooves and aligned in the second direction, The aforementioned mesa region is A first region located between the pair of recesses, It has a second region located on the third and fourth sides of the pair of recesses, respectively, The second region has the source layer, The Schottky junction is provided in the first region, Semiconductor device as described in Appendix 2. (Note 7) The semiconductor member has a plurality of recesses located between the pair of grooves and aligned in the first direction, The aforementioned mesa region is A first region located between the plurality of recesses in the first direction, A second region having the source layer is located between the groove and the recess in the second direction, The Schottky junction is provided in the first region, Semiconductor device as described in Appendix 2. (Note 8) The dimension of the first region in the first direction is smaller than the dimension of the recess in the first direction. Semiconductor device as described in Appendix 7. (Note 9) The concentration of the first conductivity type impurity in the first region is lower than the concentration of the first conductivity type impurity in the drift region. A semiconductor device as described in any one of the appendices 3 to 8. (Note 10) The second region has a channel layer located on the first side of the source layer, The concentration of the first conductivity type impurity in the channel layer is lower than the concentration of the first conductivity type impurity in the drift region. A semiconductor device as described in any one of the appendices 3 to 9. (Note 11) The source electrode has a contact portion disposed inside the recess, The second end of the inner surface of the recess is exposed from the second insulating layer. The aforementioned contact portion is The first portion of the recess has a Schottky bond with the mesa region at the second end of the recess, The recess has a second portion that is ohmic bonded with the source layer at the second end of the recess, A semiconductor device as described in any one of the appendices 2 to 10. (Note 12) The groove portion includes a conductive member located between the gate electrode and the drift region, The conductive member is insulated from the gate electrode and is electrically connected to the source electrode. A semiconductor device as described in any one of the appendices 1 to 11.

[0106] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0107] 1,101,201,301,401…Semiconductor equipment, 10,210,310,410…Semiconductor components, 11…Drift region, 12,212,312,412…Mesa region, 12a,212a,312a,412a…First region, 12b,212b,312b,412b…Second region, 13…Source layer, 14…Channel layer, 21…Gate electrode groove (groove portion), 22,322…Source electrode groove (recess), 31, 131,231,331,431…Ohmic junction, 32,132,232,332,432…Schottky junction, 42…First insulating layer, 45,145,445…Second insulating layer, 51…Drain electrode, 52…Source electrode, 53…Gate electrode, 61…Field plate (conductive member), 422…Recess for source electrode (recess), A…Region, w1,w2…Dimensions, X…First direction, Y…Second direction, Z…Third direction

Claims

1. The three intersecting directions are designated as the first direction, the second direction, and the third direction, with one side of the third direction designated as the first side and the other side as the second side. A semiconductor member having a plurality of grooves extending in the first direction and aligned in the second direction and recessed toward the first side, and a recess located between a pair of the grooves in the second direction and recessed toward the first side, The drain electrode 51 located on the first side of the semiconductor member, A gate electrode disposed inside the groove, A source electrode, at least a portion of which is disposed inside the recess, A first insulating layer is disposed inside the groove and located between the inner surface of the groove and the gate electrode, The facility comprises a second insulating layer disposed inside the recess and positioned between the inner surface of the recess and the source electrode, The aforementioned semiconductor member is A drift region having a first conductive impurity and located on the first side of the bottom of the groove, Having the first conductive impurity and a mesa region located between a pair of grooves in a second direction, The mesa region has a Schottky junction that forms a Schottky bond with the source electrode, The Schottky junction is located on the second side of the first end of the source electrode, and on the second side of the first end of the gate electrode. Semiconductor equipment.

2. The mesa region has a source layer at the second end where the concentration of the first conductivity type impurity is higher than that of the drift region. The source layer has an ohmic junction that ohmic-bonds with the source electrode. The semiconductor device according to claim 1.

3. Let one side of the second direction be the third side and the other side be the fourth side. The aforementioned mesa region is The first region located on the third side of the recess, The recess has a second region located on the fourth side and having the source layer, The Schottky junction is provided in the first region, The semiconductor device according to claim 2.

4. The mesa region has a first region and a second region located between the groove and the recess in the second direction and aligned in the first direction. The second region has the source layer, The Schottky junction is provided in the first region, The semiconductor device according to claim 2.

5. The Schottky junction is located on the second side of the second end of the gate electrode, The semiconductor device according to claim 3.

6. Let one side of the second direction be the third side and the other side be the fourth side. The semiconductor member has a pair of recesses located between the pair of grooves and aligned in the second direction, The aforementioned mesa region is A first region located between the pair of recesses, It has a second region located on the third and fourth sides of the pair of recesses, The second region has the source layer, The Schottky junction is provided in the first region, The semiconductor device according to claim 2.

7. The semiconductor member has a plurality of recesses located between the pair of grooves and aligned in the first direction, The aforementioned mesa region is A first region located between the plurality of recesses in the first direction, A second region having the source layer is located between the groove and the recess in the second direction, The Schottky junction is provided in the first region, The semiconductor device according to claim 2.

8. The dimension of the first region in the first direction is smaller than the dimension of the recess in the first direction. The semiconductor device according to claim 7.

9. The concentration of the first conductivity type impurity in the first region is lower than the concentration of the first conductivity type impurity in the drift region. A semiconductor device according to any one of claims 3 to 8.

10. The second region has a channel layer located on the first side of the source layer, The concentration of the first conductivity type impurity in the channel layer is lower than the concentration of the first conductivity type impurity in the drift region. A semiconductor device according to any one of claims 3 to 8.

11. The source electrode has a contact portion disposed inside the recess, The second end of the inner surface of the recess is exposed from the second insulating layer. The aforementioned contact portion is The first portion of the recess has a Schottky bond with the mesa region at the second end of the recess, The recess has a second portion that is ohmic bonded with the source layer at the second end of the recess, The semiconductor device according to claim 2.

12. The groove portion includes a conductive member located between the gate electrode and the drift region, The conductive member is insulated from the gate electrode and is electrically connected to the source electrode. The semiconductor device according to claim 1.

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