Electronic devices and methods for manufacturing the same

Abstract

This disclosure provides a method for manufacturing electronic devices. [Solution] The manufacturing method includes providing a target substrate and arranging a circuit structure on the target substrate. The step of providing the target substrate includes the following steps: (a) providing a base layer; (b) performing a planarization step on the base layer and then measuring a first thickness variation of the base layer; (c) forming a target substrate by arranging two planarization layers on each side of the base layer; and (d) measuring a second thickness variation of the target substrate, where the second thickness variation is smaller than the first thickness variation.

Description

Technical Field

[0001] This application claims the priority of U.S. Provisional Application No. 63 / 695,851, filed on September 18, 2024. The content of the said application is incorporated herein by reference.

[0002] 1. Disclosure Field

[0003] This disclosure relates to electronic devices and manufacturing methods thereof, and more specifically, to package elements and manufacturing methods thereof.

Background Art

[0004] 2. Description of the Prior Art

[0005] With the increasing area requirements in the packaging step, large substrates (such as glass substrates) are needed to solve the shortage of substrate size. However, the large substrates formed by the current manufacturing methods have the problem of excessive thickness variation (dispersion). Therefore, when arranging circuit structures on the substrate, the process yield of the circuit structures may decrease or it may be impossible to form high-fine-line circuit structures. Thus, solving the above problems remains an important issue in the art.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Problems to be Solved by the Invention

[0007] The present disclosure is designed to improve the flatness of a substrate used in a manufacturing process of an electronic device, thereby providing an electronic device and a manufacturing method thereof that aim to improve the process yield of elements or layers on the substrate (or carrier).

Means for Solving the Problems

[0008] The present disclosure provides a method for manufacturing an electronic device. The manufacturing method includes providing a target substrate and disposing a circuit structure on the target substrate. The step of providing the target substrate includes the following steps: (a) providing a base layer; (b) performing a planarization step on the base layer and then measuring the first thickness variation (variation) of the base layer; (c) disposing two planarization layers on both sides of the base layer respectively to form a target substrate; and (d) measuring the second thickness variation of the target substrate, where the second thickness variation is smaller than the first thickness variation.

[0009] The present disclosure provides an electronic device. The electronic device includes a target substrate and a circuit structure disposed on the target substrate. The target substrate includes a base layer and two planarization layers disposed on both sides of the base layer respectively. The base layer has a first thickness variation, and the target substrate has a second thickness variation, where the second thickness variation is smaller than the first thickness variation.

Brief Description of the Drawings

[0010] These objects and other objects of the present specification will become apparent to those skilled in the art after reading the detailed description of the embodiments shown in various drawings and illustrations.

[0011] FIG. 1 shows a flowchart of a method for manufacturing an electronic device according to a first embodiment of the present disclosure.

[0012] Figures 2 to 5 schematically illustrate the manufacturing process of an electronic device according to the first embodiment of this disclosure.

[0013] Figures 6 to 8 schematically illustrate the manufacturing process of an electronic device according to a second embodiment of the present disclosure.

[0014] Figure 9 schematically shows a cross-sectional view of an electronic device according to a third embodiment of the present disclosure.

[0015] Figure 10 schematically shows a cross-sectional view of an electronic device according to a fourth embodiment of the present disclosure. [Modes for carrying out the invention]

[0016] This disclosure can be understood by the following detailed description, which is referenced in conjunction with the drawings described below. Note that, for clarity and to facilitate the reader's understanding, the various drawings in this disclosure show only parts of the apparatus, and certain elements in the drawings may not be depicted to actual size. Furthermore, the number and dimensions of each element shown in the drawings are illustrative only and are not intended to limit the scope of this disclosure.

[0017] Certain terms are used to refer to specific elements throughout this description and in the following claims. As those skilled in the art will understand, electronic equipment manufacturers may refer to elements by different names. This specification is not intended to distinguish between elements that have different names but the same function.

[0018] In the following description and claims, the terms “includes,” “constitutes,” and “have” are used in an open sense and should therefore be interpreted as “includes, but is not limited to….”

[0019] In this disclosure, when an element is described as being “placed” on another element, it will be understood that the order of process steps between that element and the other element is not limited. Alternatively, when an element is described as being “placed” on another element, this includes cases where the element is formed on the sidewall of the other element. When an element or layer is described as being “placed on” or “connected to” another element or layer, it may be directly placed on or directly connected to the other element or layer, or an intervening element or layer may be presented (indirectly). In this disclosure, when an element is described as being “placed” on another element, the order of process steps between that element and the other element is not limited. In contrast, when an element is described as being “directly on” or “directly connected” to another element or layer, there is no intervening element or layer. When an element or layer is described as being “electrically connected” to another element or layer, it may be either a direct or indirect electrical connection. Electrical connections or couplings described herein may refer to direct or indirect connections. In a direct connection, the ends of two elements on the circuit are directly connected via a conductor segment. In an indirect connection, a switch, diode, capacitor, inductor, resistor, or other suitable element or combination thereof may be included between the ends of two elements on the circuit, but is not limited to these.

[0020] Terms such as "first," "second," and "third" may be used to describe various components, but such components are not limited by these terms. These terms are used in the specification solely to distinguish components from other components. The same terms may not be used in the claims; instead, terms such as "first," "second," and "third" may be used depending on the order in which the elements are claimed in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0021] Furthermore, any two values ​​or directions used in a comparison may have some degree of error. Also, terms such as “equal to,” “same,” “identical,” “approximately,” or “substantially” are generally interpreted as being within a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a given value.

[0022] Furthermore, the phrases "the specified range is from the first value to the second value" or "the specified range lies between the first value and the second value" indicate that the specified range includes the first value, the second value, and other values ​​in between.

[0023] If the first direction is perpendicular to the second direction, the angle of inclusion between the first and second directions may range from 80 to 100 degrees. If the first direction is parallel to the second direction, the angle of inclusion between the first and second directions may range from 0 to 10 degrees.

[0024] According to this disclosure, depth, thickness, length, width, and pore size can be measured by optical microscope (OM), electron microscope (such as scanning electron microscope (SEM)), or other suitable methods, but are not limited thereto.

[0025] In this disclosure, roughness can be determined by observation using a scanning electron microscope (SEM). On uneven surfaces, the distance between the peaks and valleys of the surface can be confirmed to be between 0.15 micrometers (μm) and 1 μm. Roughness can be measured by observing the surface relief at the same appropriate magnification using an SEM, transmission electron microscope (TEM), etc., and taking a sample of a unit length (e.g., 10 μm) and comparing its relief state as a roughness range. Here, "appropriate magnification" means that at least 10 peaks of roughness (Rz) or average roughness (Ra) can be observed on at least one surface at this magnification.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those ordinarily understood by those skilled in the art. Where defined in a general dictionary, these terms should be interpreted in a way consistent with the relevant art and the context and content of this specification; idealized or overly formal interpretations should be avoided unless specifically defined in the embodiments herein.

[0027] It should be noted that the technical features of the different embodiments described below may be substituted, combined, or mixed with each other to constitute other embodiments without departing from the spirit of this disclosure.

[0028] The electronic devices of this disclosure are applicable to, but not limited to, power modules, semiconductor packaging devices, display devices, light-emitting devices, backlight devices, antenna devices, sensing devices, or tiled devices. Electronic devices may be foldable, flexible, or stretchable. Display devices may be applicable to, but not limited to, notebook computers, general displays, tiled displays, automotive displays, touch displays, televisions, monitors, smartphones, tablets, light source modules, lighting devices, or electronic devices applied to such products. Display devices may be non-self-illuminating or self-illuminating. Sensing devices may include biosensors, touch sensors, fingerprint sensors, other suitable sensors, or combinations of such sensors. Antenna devices may include, for example, liquid crystal antenna devices or non-liquid crystal antenna devices. Tiled devices may include, for example, tiled display devices or tiled antenna devices. The contours of electronic devices may be rectangular, circular, polygonal, curved-edge shapes, or other suitable shapes. Electronic devices may include electronic elements. Electronic elements may include semiconductor elements. Semiconductor elements may be, but are not limited to, electronic elements including a semiconductor layer or electronic elements formed by a semiconductor process. Electronic elements include, for example, passive or active elements such as capacitors, resistors, inductors, diodes, transistors, and integrated circuits. Diodes may include light-emitting diodes, photodiodes, or varactor diodes. Light-emitting diodes include, for example, organic light-emitting diodes (OLEDs), mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), and quantum dot light-emitting diodes (QLEDs). It should be noted that electronic devices include, but are not limited to, combinations of the above devices.Electronic devices may include peripheral systems such as drive systems, control systems, light source systems supporting display devices, antenna devices, wearable devices (such as augmented reality and virtual reality devices), vehicle devices (such as car windshields), and tile-like devices. The manufacturing methods for electronic devices of this disclosure may be applied to, for example, wafer-level packaging (WLP) processes or panel-level packaging (PLP) processes. The manufacturing methods for electronic devices of this disclosure may include, but are not limited to, chip-first processes or chip-last processes. Electronic devices may include, but are not limited to, high-bandwidth memory (HBM) packages, system-on-chip (SoC), system-in-package (SiP), antenna-in-package (AiP), co-packaged optical (CPO) packages, or combinations of the above devices.

[0029] Referring to Figures 1 to 5, Figure 1 shows a flowchart of a method for manufacturing an electronic device according to a first embodiment of the present disclosure, and Figures 2 to 5 schematically show the manufacturing process of an electronic device according to a first embodiment of the present disclosure. As shown in Figure 1, the manufacturing method M100 of the electronic device of this embodiment (hereinafter referred to as electronic device E0) may include the following steps:

[0030] S100: Provide a target substrate; and

[0031] S102: Place the circuit structure on the target substrate. Here, the step of providing the target substrate (step S100) includes the following steps:

[0032] S1001: Provides a base layer;

[0033] S1002: Perform a planarization step on the base layer, and then measure the first thickness variation (variation) of the base layer;

[0034] S1003: A target substrate is formed by arranging two planarization layers on each side of the base layer; and

[0035] S1004: Measure the second thickness variation of the target substrate.

[0036] Details of each step in manufacturing method M100 are described below.

[0037] According to this embodiment, the method for manufacturing an electronic device M100 may include step S100: first providing a target substrate TS. Specifically, the manufacturing process for the target substrate TS may include step S1001: first providing a base layer BS, as shown in structure (I) of Figure 2. The base layer BS may include any suitable material that can provide a support or carrying function. For example, the base layer BS may include, but is not limited to, a transparent material or glass in this embodiment. The transmittance of the base layer BS to white light is preferably, for example, 80% or more. The base layer BS may function as a large carrier to facilitate the step of arranging elements (such as the circuit structure CS described later) over a large area on it. For example, the base layer BS can be a large glass carrier. In some embodiments, the shape of the base layer BS in the upper direction (i.e., parallel to the Z direction) may be rectangular (e.g., square, but not limited thereto), and the length or width of this rectangle may be at least 300 millimeters (mm), but is not limited thereto. In such cases, the size of the base layer BS in the upward direction (i.e., the direction parallel to the Z direction) may be 300 mm × 300 mm. In some embodiments, the size of the base layer BS in the upward direction may be 500 mm × 500 mm. In some embodiments, the size of the base layer BS in the upward direction may be 600 mm × 600 mm. In some embodiments, the size of the base layer BS in the upward direction may be 700 mm × 700 mm or larger. In some embodiments, the shape of the base layer BS in the upward direction may be circular or nearly circular, with a diameter of at least 500 mm. In some embodiments, the base layer BS may have other suitable shapes in the upward direction and is not limited to the above shapes. Because the size of the base layer BS is relatively large, the surface of the base layer BS (including surfaces S1 and S2) may be uneven, i.e., the base layer BS may have a non-uniform surface. Specifically, the base layer BS may have a first thickness variation TV1. The first thickness variation TV1 may be 20 micrometers (μm) or more, but is not limited to this.The "first thickness variation TV1" is the variation in the thickness TH0 of the base layer BS, and can be defined, for example, by the thickness measured at at least five locations on the base layer BS. The thickness TH0 of the base layer BS is, for example, the thickness of the base layer BS viewed from the top. It should be noted that the thickness TH0 measured at different locations may be different because the thickness of the base layer BS may be non-uniform. Specifically, first, select at least five locations on the base layer BS and measure the thickness TH0 of the base layer BS at those five locations. Then, the variation in the measured thickness TH0 becomes the first thickness variation TV1 of the base layer BS. Specifically, after measuring N values ​​of thickness TH0 (these values ​​are represented by THi in equation (1), where i ranges from 1 to N), first calculate the average value M of the N values ​​of thickness TH0, and then calculate the first thickness variation TV1 (but not limited to) using the following equation (1).

number

[0038] After the base layer BS is provided, the manufacturing process of the target substrate TS may further include step S1002: a planarization step performed on the base layer BS, followed by a step of measuring the first thickness variation TV1 of the base layer BS. Specifically, as shown in structure (II) of Figure 2, a planarization treatment can be performed on the surface S1 and / or surface S2 of the base layer BS to improve the flatness of the surfaces S1 and S2 or to reduce the waviness of the surfaces S1 and S2. The planarization step of the base layer BS may include, for example, chemical mechanical polishing (CMP), grinding, sandblasting, or other appropriate steps. After the planarization step of the base layer BS, the first thickness variation TV1 of the base layer BS may be reduced to less than a certain value. Under such conditions, "first thickness variation TV1" refers to the variation in the thickness TH1 of the base layer BS, and the method of calculating it can be found in the above description. For example, in this embodiment, it is desirable, but not limited to, that the first thickness variation TV1 of the base layer BS measured after the planarization step is 20 μm or less (i.e., TV1 ≤ 20 μm). Under these conditions, if the first thickness variation TV1 of the base layer BS measured after the planarization step exceeds 20 μm, step S1002 can be performed again, that is, the planarization treatment described above can be performed again on the surface S1 and / or surface S2 of the base layer BS, and then the first thickness variation TV1 can be measured again. In other words, the planarization step of the base layer BS (step S1002) can be performed repeatedly until the measured first thickness variation TV1 is 20 μm or less, but is not limited thereto. In some embodiments, step S1002 may be performed repeatedly until the measured first thickness variation TV1 is 18 μm or less. In some embodiments, step S1002 may be performed repeatedly until the measured first thickness variation TV1 is 16 μm or less. Note that the first thickness variation TV1 of the base layer BS can be measured before the planarization step of the base layer BS, and if the measured first thickness variation TV1 is 20 μm or less, the planarization step of the base layer BS can be omitted, but is not limited thereto.

[0039] After performing a planarization step on the base layer BS and the first thickness variation TV1 of the base layer BS satisfies the above conditions, the manufacturing process of the target substrate TS further includes step S1003: placing two planarization layers on each side of the base layer BS. Specifically, as shown in structure (III) of Figure 2, after the planarization step of the base layer BS is completed, planarization layer PL2 can be placed on the surface S1 side of the base layer BS and planarization layer PL1 can be placed on the surface S2 side of the base layer BS. Planarization layer PL2 can be placed entirely on one side of the base layer BS and cover surface S1, and planarization layer PL1 can be placed entirely on the other side of the base layer BS and cover surface S2. That is, the base layer BS can be sandwiched between planarization layers PL1 and PL2. After planarization layers PL1 and PL2 are placed, the target substrate TS may be formed. Planarization layers PL1 and PL2 may include any material that can provide a flat surface. Furthermore, the transmittance of planarization layers PL1 and PL2 to light having wavelengths from 300 nanometers (nm) to 700 nm may be greater than or equal to 70%, but is not limited thereto. According to some embodiments, the transmittance of planarization layer PL1 may be greater than that of planarization layer PL2 in order to improve peel quality, but is not limited thereto. That is, any material that satisfies the above characteristics can be used as the material for planarization layers PL1 and PL2. Note that planarization layers PL1 and PL2 may contain the same material or different materials, and are not limited thereto in this disclosure. In some embodiments, the planarization layers may be located on only one side of the base layer BS. Planarization layers PL1 and PL2 may contain organic or inorganic materials, or the materials of planarization layers PL1 and PL2 may contain silicon-containing compounds, but are not limited thereto. Planarization layers PL1 and PL2 may contain materials that have affinity with the base layer BS. Specifically, van der Waals forces may be present between the planarization layer PL1 (or planarization layer PL2) and the base layer BS. Planarization layers PL1 and PL2 may have good leveling characteristics.As a result, after forming planarization layers PL1 and PL2 on the base layer BS, planarization layers PL1 and PL2 fill the recesses in the base layer BS, reducing thickness variations in the target substrate TS and reducing surface roughness on both sides of the target substrate TS.

[0040] After the target substrate TS is formed, step S1004 can be performed to measure the second thickness variation TV2 of the target substrate TS. The definition of the second thickness variation TV2 can refer to the definition of the first thickness variation TV1 described above. Specifically, first, at least five locations on the target substrate TS are selected, and the thickness TH2 of the target substrate TS is measured at the five locations. The measured variation in thickness TH2 is then the second thickness variation TV2 of the target substrate TS. Thickness TH2 may be the thickness of the target substrate TS in the upper direction. After the planarization layers PL1 and PL2 are formed, the surface S3 of the planarization layer PL2 away from the base layer BS and the surface S4 of the planarization layer PL1 away from the base layer BS may be more flat than the surfaces S1 and S2 of the base layer BS. The above surfaces S3 and S4 can also be considered as the surface of the target substrate TS. That is, the surface of the target substrate TS may be flatter than the surface of the base layer BS. Therefore, the second thickness variation TV2 of the target substrate TS may be smaller than the first thickness variation TV1 of the base layer BS. According to this embodiment, after forming a target substrate TS by placing planarization layers on both sides of the base layer BS, the second thickness variation TV2 of the target substrate TS may be smaller than a certain value. For example, in this embodiment, the second thickness variation TV2 of the target substrate TS formed by placing the planarization layers may be 3 μm or less (i.e., TV2 ≤ 3 μm), but is not limited thereto. In some embodiments, if, after the target substrate TS is formed, the measured second thickness variation TV2 of the target substrate TS exceeds 3 μm (for example, excessive surface waviness of the planarization layer due to dust or other factors), the planarization layers PL1 and PL2 may be removed first, and then the steps of placing the planarization layers (i.e., step S1003) and measuring the second thickness variation TV2 (i.e., step S1004) may be repeated. Note that the above process (i.e., steps S1003 and S1004) may be repeated until the measured second thickness variation TV2 is 3 μm or less.In some embodiments, if the measured second thickness variation TV2 of the target substrate TS exceeds 3 μm after the target substrate TS is formed, a further planarization step can be performed on the planarization layer PL1 and planarization layer PL2 to improve the flatness of the planarization layer PL1 and planarization layer PL2, thereby reducing the measured second thickness variation TV2. The planarization step referred to here may refer to the same steps as those described above for the base layer BS, and will not be described redundantly. Note that the planarization step of the planarization layer PL1 and planarization layer PL2 can be repeated until the measured second thickness variation TV2 is 3 μm or less.

[0041] Through the above procedure, a target substrate TS may be formed. Here, the target substrate TS may be a composite layer including a base layer BS and two planarization layers (i.e., planarization layer PL1 and planarization layer PL2) positioned on either side of the base layer BS. Planarization layers PL1 and PL2 may, but are not limited to, be in contact with the base layer BS. Due to the arrangement of planarization layers PL1 and PL2, the second thickness variation TV2 in the target substrate TS is smaller than the first thickness variation TV1 of the base layer BS positioned within the target substrate TS. As described above, in this embodiment, it is desirable, but not limited to, that the first thickness variation TV1 of the base layer BS in the target substrate TS is 20 μm or less and the second thickness variation TV2 of the target substrate TS is 3 μm or less. The target substrate TS can function as a carrier for positioning other elements or layers.

[0042] After the target substrate TS is formed, the electronic device manufacturing method M100 may further include step S102: placing the circuit structure CS on the target substrate TS. Specifically, as shown in Figure 3, after the target substrate TS is formed, a release layer RL is placed on the target substrate TS, and then the circuit structure CS is placed on the release layer RL. Here, "the circuit structure CS is placed on the target substrate TS" includes embodiments in which the circuit structure CS is formed on the target substrate TS, and embodiments in which the circuit structure CS is formed first and then transferred to the target substrate TS. The circuit structure CS can be placed on any side of the target substrate TS on which the planarization layer is placed. For example, as shown in Figure 3, the circuit structure CS can be placed on the side of the target substrate TS on which the planarization layer PL2 is placed, i.e., the planarization layer PL2 can be placed between the circuit structure CS and the base layer BS, but is not limited to this. In some embodiments, the circuit structure CS can be placed on the side of the target substrate TS on which the planarization layer PL1 is placed, i.e., the planarization layer PL1 can be placed between the circuit structure CS and the base layer BS.

[0043] The circuit structure CS can include various types of wiring, circuits, or electronic units. The electronic units can include any suitable active and / or passive elements. The circuit structure CS can include any suitable structure formed by laminating conductive and insulating layers, where the conductive layers may, but are not limited to, being used to form the wiring, circuits, or electronic units mentioned above. According to some embodiments, after the release layer RL is placed, the circuit structure CS can be formed by alternately forming conductive and insulating layers on the release layer RL. For example, as shown in Figure 3, the circuit structure CS may, but are not limited to, a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, an insulating layer I1, and an insulating layer I2. The insulating layer I1 is located between the first conductive layer M1 and the second conductive layer M2, and the insulating layer I2 is located between the second conductive layer M2 and the third conductive layer M3. The first conductive layer M1 may, but are not limited to, being placed directly on the release layer RL. In some embodiments, a buffer layer (not shown) or other suitable layer may be provided between the first conductive layer M1 and the release layer RL. The second conductive layer M2 may be located on the first conductive layer M1 and electrically connected to the first conductive layer M1 via vias (e.g., via V1) penetrating the insulating layer I1. The third conductive layer M3 may be located on the second conductive layer M2 and electrically connected to the second conductive layer M2 via vias (e.g., via V2) penetrating the insulating layer I2. As shown in Figure 3, the uppermost conductive layer in the circuit structure CS (or the conductive layer furthest from the target substrate TS) (e.g., the third conductive layer M3) is an underbump metallization (UBM) layer located on the surface of the insulating layer I2, and the surface S5 of the third conductive layer M3 may be aligned with the surface S6 of the insulating layer I2. In some embodiments, a portion of the surface S5 of the third conductive layer M3 may be concave (not shown). In some embodiments, the third conductive layer M3 may be located on the insulating layer I2, i.e., the third conductive layer M3 protrudes from the surface of the insulating layer I2. The first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may, but are not limited to, any suitable conductive material such as a metallic material. The insulating layers I1 and I2 may include any suitable organic or inorganic insulating material.For example, insulating layers I1 and I2 are made of polyimide (PI), photosensitive polyimide (PSPI), epoxy resin, polymer, ABF material, silicon dioxide (SiO). x ), silicon nitride (SiN x ), other suitable materials, or combinations of the above materials may be included. Note that the circuit structure CS shown in Figure 3 is an example, and the configuration of the circuit structure CS in this embodiment (e.g., the number of conductive and insulating layers, or the arrangement of conductive layers) is not limited to that shown in Figure 3. In some embodiments, the circuit structure CS may include a rewiring structure. The rewiring structure is a structure that allows the positions of signal input terminals and signal output terminals to be adjusted, or a structure that allows the layout of wiring to be adjusted. That is, it is possible to extend the circuit to widen the spacing, or to rewire the circuit to another circuit with different spacing via the rewiring structure. Thus, it is possible to rewire the circuit and / or expand the fan-out area of ​​the circuit.

[0044] According to this embodiment, when forming the circuit structure CS on the target substrate TS, wiring with a smaller size may be formed first, or a conductive layer used for forming wiring with a smaller size may be formed first. In this case, the size of the wiring formed by the conductive layer at a position closer to the target substrate TS may be smaller than the size of the wiring formed by the conductive layer at a position farther from the target substrate TS. Specifically, in this embodiment, the size of the wire formed by the conductive layer of the circuit structure CS may be configured to gradually increase as it moves away from the target substrate TS, but is not limited thereto. For example, as shown in FIG. 3, the conductive layer of the circuit structure CS includes a conductive layer closest to the target substrate TS (i.e., the first conductive layer M1) and another conductive layer farthest from the target substrate TS (i.e., the third conductive layer M3). The first conductive layer M1 is patterned to include a plurality of separated conductive parts P1, and the third conductive layer M3 may be patterned to include a plurality of separated conductive parts P2. Each conductive part P1 can function as a wiring or wiring pattern formed by the first conductive layer M1, and each conductive part P2 can function as a wiring or wiring pattern formed by the third conductive layer M3, but is not limited thereto. According to this embodiment, the size of one of the conductive parts P1 may be smaller than the size of one of the conductive parts P2. The "size of the conductive part" referred to here refers to, for example, the width or thickness of the conductive part in the cross-sectional view of the circuit structure CS, the area of the conductive part in the plan view of the circuit structure CS, or the pitch between two adjacent conductive parts, but is not limited thereto. Specifically, one width of the conductive part P1 can be set as W1, and one width of the conductive part P2 can be set as W2. In this case, the width W1 may be smaller than the width W2. Further, the conductive layer (for example, the second conductive layer M2) located between the first conductive layer M1 and the third conductive layer M3 may be patterned to include a plurality of separated conductive parts P3. One of the conductive parts P3 may have a width W3. Here, the width W3 may be between the width W1 and the width W2, that is, the width W3 may be larger than the width W1 and smaller than the width W2 (i.e., W1 < W3 < W2). In some embodiments, one of the conductive parts P1 has a thickness T1, and one of the conductive parts P2 has a thickness T2, and the thickness T1 may be smaller than the thickness T2.Furthermore, one of the conductive portions P3 has a thickness T3, and the thickness T3 may be greater than the thickness T1 and less than the thickness T2 (i.e., T1 < T3 < T2). The width W1 and the thickness T1 can each be regarded as the width and the thickness of the wire formed by the first conductive layer M1. Also, the width W2 and the thickness T2 can each be regarded as the width and the thickness of the wire formed by the third conductive layer M3. In other words, the width and / or thickness of the wire closer to the target substrate TS may be smaller than the width and / or thickness of the wire farther from the target substrate TS, respectively. In some embodiments, in the plan view of the circuit structure CS, the area of one of the conductive portions P1 may be smaller than the area of one of the conductive portions P2. Furthermore, in the present embodiment, the circuit structure CS includes the insulating layer closest to the target substrate TS (i.e., the insulating layer I1) and the insulating layer farthest from the target substrate TS (i.e., the insulating layer I2), the insulating layer I1 has a thickness TK1, the insulating layer I2 has a thickness TK2, and the thickness TK1 may be smaller than the thickness TK2.

[0045] Furthermore, in this embodiment, the number of wires formed by the first conductive layer M1 closest to the target substrate TS may be greater than the number of wires formed by the third conductive layer M3 furthest from the target substrate TS. That is, the number of conductive parts P1 may be greater than the number of conductive parts P2. Also, the number of multiple conductive parts P3 included in the second conductive layer M2 may be less than the number of conductive parts P1 and greater than the number of conductive parts P2. Specifically, in the circuit structure CS, the number of conductive parts included in the conductive layer may gradually decrease as the distance between the conductive layer and the target substrate TS increases, but is not limited to this. In some embodiments, each of the conductive parts P1 and conductive parts P2 located on both sides of the circuit structure CS may function as input / output points (I / O points) connected to other electronic elements. That is, the number of I / O points located on the side of the circuit structure CS closer to the target substrate TS may exceed the number of I / O points located on the side of the circuit structure CS farther from the target substrate TS. In other words, when forming the circuit structure CS on the target substrate TS, it is possible to initially form a conductive layer having more I / O points (or conductive parts). Under these conditions, in a cross-sectional view of the circuit structure CS, a distance D1 is included between two adjacent conductive portions P1 (or two adjacent I / O points) in the first conductive layer M1, and a distance D2 is included between two adjacent conductive portions P2 (or two adjacent I / O points) in the third conductive layer M3, where distance D1 may be smaller than distance D2. In some embodiments, the conductive portions P1 and P2 (or I / O points) may be arranged at a specific pitch. In this case, the distance D1 may be considered as the pitch of the I / O points in the first conductive layer M1, and the distance D2 may be considered as the pitch of the I / O points in the third conductive layer M3. After arranging the circuit structure CS by the above method, an electronic device E0 shown in Figure 3 can be formed, and the electronic device E0 may include a target substrate TS and the circuit structure CS arranged on the target substrate TS.

[0046] According to this embodiment, after providing the target substrate TS as a carrier by the method described above, when forming a circuit structure CS on the carrier, it becomes possible to increase the process area while reducing the possibility of excessive fluctuations in the wiring size of the circuit structure CS due to an excessive carrier area, thereby improving the process of the circuit structure CS. Alternatively, by using the target substrate TS as a carrier, it becomes possible to form a circuit structure CS with finer wiring. Furthermore, by forming a conductive layer containing more conductive parts (or I / O points) or finer wiring, it is possible to reduce the possibility that the manufacturing process of high-density I / O points or wiring (for example, formed by the first conductive layer M1) within the circuit structure CS is affected by surface irregularities of the carrier. Therefore, the flatness of high-density I / O points or wiring in the circuit structure CS can be improved. Specifically, by using the target substrate TS as a carrier, the formed circuit structure CS may have the following characteristics. As shown in Figure 3, the circuit structure CS (or the insulating layer I1 of the circuit structure CS) may include a plurality of vias corresponding to (or in contact with) the first conductive layer M1 closest to the target substrate TS, with via width variations between 0.1 μm and 2 μm (i.e., 0.1 μm < variation < 2 μm). That is, by forming the circuit structure CS with the target substrate TS as a carrier, the width difference between vias in the insulating layer (e.g., the insulating layer I1 closest to the target substrate TS) can be reduced. The definition of via width variation can refer to the definition of the first thickness variation described above. For example, at least five vias in the insulating layer I1, e.g., vias V11, V12, V13, V14 and V15, can be identified first, having widths W41, W42, W43, W44 and W45, respectively. Here, the variation of widths W41, W42, W43, W44 and W45 is in the range of 0.1 μm to 2 μm, but is not limited to this range. The "via width" mentioned above may refer, for example, to the maximum via width in a cross-sectional view of the circuit structure CS.Furthermore, there may be multiple distances between the multiple conductive parts P1 of the first conductive layer M1 closest to the target substrate TS and the conductive parts P3 of the second conductive layer M2 to which the conductive parts P1 are electrically connected, and the variation in these distances is within the range of less than 0.01 μm to 1 μm (i.e., 0.01 μm < variation < 1 μm). In other words, by forming a circuit structure CS with the target substrate TS as a carrier, the difference in these distances can be reduced. For example, by first identifying at least five conductive parts P1 and then identifying conductive parts P3 electrically connected to these conductive parts P1, the distances between these conductive parts P1 and conductive parts P3, for example, distances D31, D32, D33, D34, and D35, can be defined, and the variation in distances D31, D32, D33, D34, and D35 is between 0.01 μm and 1 μm. The distance D31 to D35 described above can be defined, for example, as the distance between the bottom surface of the first conductive layer M1 and the bottom surface of the second conductive layer M2 in the upper direction (i.e., the Z direction). In other words, the distance D31 to D35 can also be considered as the thickness of the insulating layer closest to the target substrate TS (i.e., insulating layer I1), meaning that the variation in the thickness TK1 of insulating layer I1 is between 0.01 μm and 1 μm.

[0047] According to this embodiment, after the electronic device E0 shown in Figure 3 is formed, other electronic devices, such as the electronic device E1 shown in Figure 5, can be further formed via the electronic device E0. Specifically, as shown in Figure 4, after the electronic device E0 is formed, the method for manufacturing the electronic device E1 further includes placing at least one connecting element CE1 on the side of a circuit structure CS adjacent to the third conductive layer M3. The connecting element CE1 is positioned corresponding to the third conductive layer M3 (or the conductive portion P2 of the third conductive layer M3) and is in contact with the third conductive layer M3 (or the conductive portion P2 of the third conductive layer M3), thereby electrically connecting the connecting element CE1 to the circuit structure CS. Although not shown in the figure, after the connecting element CE1 is placed, the circuit structure CS may be positioned between the target substrate TS and the connecting element CE1. The connecting element CE1 includes, but is not limited to, solder, for example. The target substrate TS may be used to provide a support function when the connecting element CE1 is placed. After the connecting element CE1 is positioned, an adhesive layer AD may be placed on the connecting element CE1, and a support layer SUP may be placed on the adhesive layer AD. Specifically, after the adhesive layer AD is placed on the connecting element CE1, the support layer SUP may be attached to the circuit structure CS via the adhesive layer AD. In some embodiments, as shown in Figure 4, the adhesive layer AD may cover the connecting element CE1 and be in contact with the circuit structure CS (e.g., in contact with the insulating layer I2), but is not limited to this. In such a configuration, the adhesive layer AD may be used to reduce the possibility of the connecting element CE1 being affected by the external environment (e.g., moisture and oxygen). In some embodiments, the adhesive layer AD may be placed on the connecting element CE1 but not in contact with the circuit structure CS.

[0048] After the connecting element CE1 is positioned, the method for manufacturing the electronic device E1 may further include removing the target substrate TS and positioning at least one electronic element on the side of the circuit structure CS adjacent to the first conductive layer M1. Specifically, after the connecting element CE1 is formed, the target substrate TS can be separated from the circuit structure CS by removing the release layer RL. The structure can then be inverted so that the support layer SUP is positioned below the circuit structure CS, and the conductive element C1 can be positioned on the first conductive layer M1 (or the conductive portion P1 of the first conductive layer M1). The conductive element C1 can be electrically connected to the circuit structure CS so as to correspond to the first conductive layer M1 (or the conductive portion P1 of the first conductive layer M1) and to be in contact with the first conductive layer M1 (or the conductive portion P1 of the first conductive layer M1). Subsequently, electronic elements EU1 and EU2 are positioned on the side of the circuit structure CS adjacent to the first conductive layer M1. Specifically, the conductive pad CP1 of electronic element EU1 and the conductive pad CP2 of electronic element EU2 contact the conductive element C1 and are bonded to the circuit structure CS via the conductive element C1. The support layer SUP may provide support when electronic elements EU1 and EU2 are positioned. In some embodiments, the conductive pad CP1 of electronic element EU1 and the conductive pad CP2 of electronic element EU2 may directly contact the conductive layer of the circuit structure CS (i.e., the first conductive layer M1). For example, electronic elements EU1 and EU2 are electrically connected to the circuit structure CS via hybrid bonding, but are not limited to this. In such a configuration, the aforementioned conductive element C1 is unnecessary. Electronic elements EU1 and EU2 may each include a semiconductor unit, a memory unit, an antenna unit, a sensing unit, a capacitor, or other suitable active / passive electronic elements. In some embodiments, electronic elements EU1 and EU2 positioned on the side of the circuit structure CS adjacent to the first conductive layer M1 may each include electronic elements with a large number of I / O points or a high density of I / O points. For example, although not shown in the diagram, the circuit structure CS can be further electrically connected to another electronic element via the connecting element CE1.In this case, the number and / or density of I / O points in another electronic element electrically connected to the circuit structure CS may be less than, but not limited to, the number and / or density of I / O points in electronic elements EU1 and EU2 electrically connected to the circuit structure CS.

[0049] After arranging electronic elements EU1 and EU2, the method for manufacturing the electronic device E1 further includes the step of arranging an underfill layer UF and a mold layer MD. Specifically, after joining electronic elements EU1 and EU2 to the circuit structure CS, the underfill layer UF can be arranged on the side of the circuit structure CS adjacent to the first conductive layer M1. The underfill layer UF is arranged between the circuit structure CS and electronic components EU1 (and electronic components EU2) and can surround conductive element C1, conductive pad CP1 and / or conductive pad CP2. In some embodiments, the underfill layer UF can further surround electronic components EU1 and EU2. In this specification, "one element surrounds another element" may mean that the element can contact at least a portion of the side surface of the other element. That is, as shown in Figure 4, the underfill layer UF can further contact at least a portion of the side surfaces of electronic elements EU1 and EU2, but is not limited thereto. The underfill layer UF may include, but is not limited to, any suitable insulating material such as epoxy resin or acrylic resin. The underfill layer UF may provide moisture and oxygen barriers to the conductive element C1, conductive pad CP1, and / or conductive pad CP2. After the underfill layer UF is in place, the molded layer MD may be placed on the side of the circuit structure CS adjacent to the first conductive layer M1. Here, the molded layer MD may surround the electronic components EU1, EU2, and the underfill layer UF. This encapsulates the electronic components EU1 and EU2. The molded layer MD may, but is not limited to, any suitable organic or inorganic material, such as epoxy molding compound (EMC), epoxy resin, oxide, or nitride. In some embodiments, the surface S7 of the molded layer MD facing the circuit structure CS is substantially aligned with the surface S8 of electronic component EU1 and / or the surface S9 of electronic component EU2 facing the circuit structure CS. That is, as shown in Figure 4, the surface S8 of electronic component EU1 and / or the surface S9 of electronic component EU2 are exposed. In some embodiments, the molded layer MD can cover the surface S8 of electronic component EU1 and the surface S9 of electronic component EU2. After the above steps are completed, the structure shown in Figure 4 is formed.

[0050] Subsequently, as shown in Figure 5, after arranging the underfill layer UF and the molded layer MD, the adhesive layer AD and the support layer SUP can be removed to form the electronic device E1. That is, the electronic device E1 can be formed from the electronic device E0 shown in Figure 3 through the above manufacturing process. The types of electronic elements included in electronic elements EU1 and EU2 can be determined according to the type or purpose of the electronic device E1. According to this embodiment, in the manufacturing process of the electronic device E1, the target substrate TS is used as the carrier for forming the circuit structure CS, so the flatness of the elements or layers (including the first conductive layer M1, conductive element C1, conductive pad CP1 and / or conductive pad CP2) in the circuit structure CS that are electrically connected to the electronic elements (including electronic elements EU1 and EU2) can be improved, and the reliability of the electronic device E1 can be improved. As mentioned above, although not shown in the figures, the electronic device E1 may further be electrically connected to another electronic element via a connecting element CE1, thereby the electronic elements EU1 and EU2 may be electrically connected to another electronic element via the circuit structure CS and the connecting element CE1. Note that the structure of electronic device E1 is not limited to that shown in Figure 5, and may include other appropriate elements or layers.

[0051] Next, embodiments for forming other electronic devices via the target substrate TS will be described. To simplify the explanation, the same symbols will be used for the same elements or layers in the following embodiments, and their characteristics will not be described redundantly. Differences between embodiments will be described in detail below.

[0052] Referring to Figures 6 to 8, Figures 6 to 8 schematically illustrate the manufacturing process of an electronic device according to a second embodiment of the present disclosure. The manufacturing method of the electronic device E2 in this embodiment can refer to the manufacturing method M100 described above. Specifically, as shown in Figure 6, a target substrate TS can be provided first, and then a circuit structure CS can be placed on the target substrate TS. The method of forming the target substrate TS and its detailed structure can be found in the above description and will not be explained again. Subsequently, a release layer RL can be placed on the target substrate TS, and then the circuit structure CS can be placed on the release layer RL. In some embodiments, as shown in Figure 6, a warp prevention layer AW1 can be optionally placed on the target substrate TS first, and then the release layer RL can be placed, i.e., the warp prevention layer AW1 can be placed between the target substrate TS and the release layer RL. By placing the warp prevention layer AW1, the influence of stress in the subsequent manufacturing process of the electronic device can be reduced. The warp prevention layer AW1 may contain any suitable organic or inorganic material. In this embodiment, when forming the circuit structure CS on the target substrate TS, it is possible to form larger wires first, or to form a conductive layer used for forming larger wires first. Specifically, the size of the wiring formed by the conductive layers of the circuit structure CS gradually decreases as it moves away from the target substrate TS, but is not limited to this. For example, the layer formation order of the circuit structure CS in this embodiment may be the reverse of the layer formation order of the circuit structure CS shown in Figure 3, that is, the circuit structure CS may be formed in the order of third conductive layer M3, insulating layer I2, second conductive layer M2, insulating layer I1, and first conductive layer M1. Under such conditions, the size of the wires formed by the conductive layers closer to the target substrate TS may be larger than the size of the wires formed by the conductive layers further away from the target substrate TS. For example, as shown in Figure 6, the multiple conductive layers of the circuit structure CS include the third conductive layer M3 closest to the target substrate TS and the first conductive layer M1 furthest from the target substrate TS, and the size of one conductive portion P1 of the first conductive layer M1 may be smaller than the size of one conductive portion P2 of the third conductive layer M3. The "size of the conductive portion" here may refer to the above.For example, the width W1 of conductive part P1 may be smaller than the width W2 of conductive part P2, or the thickness T1 of conductive part P1 may be smaller than the thickness T2 of conductive part P2.

[0053] Furthermore, as shown in Figure 6, the circuit structure CS of this embodiment may further include a planarization layer PLN adjacent to a conductive layer used to form smaller-sized wiring, or adjacent to a conductive layer containing more conductive portions (or I / O points). For example, the planarization layer PLN may be adjacent to, but is not limited to, a first conductive layer M1 having the smallest conductive portion (i.e., conductive portion P1). That is, the planarization layer PLN may be adjacent to the uppermost conductive layer in the circuit structure CS. Specifically, the first conductive layer M1 may be placed on the planarization layer PLN. In some embodiments, as shown in Figure 6, the first conductive layer M1 may be placed directly on the planarization layer PLN. Under such conditions, in the manufacturing process of the circuit structure CS, the planarization layer PLN is placed first, and then the first conductive layer M1 is placed directly on the planarization layer PLN. Although not shown in the figure, in some embodiments, other layers may be included between the planarization layer PLN and the first conductive layer M1. In some embodiments, as shown in Figure 6, the planarization layer PLN may be placed between the first conductive layer M1 and an insulating layer I1. That is, after the second conductive layer M2 is formed, an insulating layer I1 may be formed first, then a planarization layer PLN may be formed, and then the first conductive layer M1 may be formed on the planarization layer PLN. Under these conditions, two insulating layers, namely the insulating layer I1 and the planarization layer PLN, are included between the first conductive layer M1 and another conductive layer adjacent to the first conductive layer M1 (i.e., the second conductive layer M2). A via V1 used to electrically connect the first conductive layer M1 and the second conductive layer M2 may be formed by removing a portion of the insulating layer I1 and a portion of the planarization layer PLN. In some embodiments, only the planarization layer PLN may be included between the first conductive layer M1 and the second conductive layer M2, i.e., the planarization layer PLN may replace the insulating layer I1. Under these conditions, after the second conductive layer M2 is formed, the planarization layer PLN may be formed on the second conductive layer M2, and then the first conductive layer M1 may be formed on the planarization layer PLN. The planarization layer PLN may include any material that can provide a flat surface for facilitating the formation of the first conductive layer M1 thereon. The material of the planarization layer PLN may be the same as or different from the material of the planarization layers PL1 and PL2, and is not limited in this embodiment.The material of the planarization layer PLN may differ from the material of other insulating layers (e.g., insulating layers I1 and I2) within the circuit structure CS. That is, in the circuit structure CS, the material of at least one insulating layer (i.e., the planarization layer PLN) between the first conductive layer M1 and the second conductive layer M2 may differ from the material of other insulating layers (e.g., insulating layers I1 and I2). The planarization layer PLN may have good affinity with insulating layer I1, or van der Waals forces may be present between the planarization layer PLN and insulating layer I1. Therefore, a material satisfying the above conditions can be selected as the material for the planarization layer PLN. By placing the planarization layer PLN in the circuit structure CS, the possibility of the manufacturing process of high-density I / O points or wiring (e.g., formed by the first conductive layer M1) within the circuit structure CS being affected by surface irregularities can be reduced. After placing the circuit structure CS on the target substrate TS, the electronic device E0' shown in Figure 6 can be formed.

[0054] According to this embodiment, after the electronic device E0' shown in Figure 6 is formed, other electronic devices (for example, electronic device E2 described later) can be formed via electronic device E0'. Specifically, as shown in Figure 7, after electronic device E0' is formed, the method for manufacturing electronic device E2 may further include the step of placing at least one electronic element on the side surface of the circuit structure CS adjacent to the first conductive layer M1. Specifically, after the circuit structure CS is formed, the conductive element C1 can be placed on the first conductive layer M1 (or the conductive portion P1 of the first conductive layer M1), and electronic elements EU1 and EU2 can be joined to the circuit structure CS via the conductive element C1. In detail, the conductive pad CP1 of electronic element EU1 and the conductive pad CP2 of electronic element EU2 contact the conductive element C1, thereby joining them to the circuit structure CS via the conductive element C1. In this state, the circuit structure CS is placed between the target substrate TS and the electronic elements EU1 (and EU2). The target substrate TS provides support when placing electronic elements EU1 and EU2. The features of electronic elements EU1 and EU2 will not be described again, as they are covered in the above description. It should be noted that, although not shown in the figures, in some embodiments, electronic elements EU1 and EU2 may be electrically connected to each other via a circuit structure CS (for example, a first conductive layer M1 within the circuit structure CS). After arranging electronic elements EU1 and EU2, the method for manufacturing the electronic device E2 may further include the step of arranging an underfill layer UF and a molded layer MD. Details of this can be found in the above description and will not be described again.

[0055] After electronic elements EU1 and EU2 are placed, the method for manufacturing the electronic device E2 may further include removing the target substrate TS and placing at least one connecting element CE1 on the side of the circuit structure CS adjacent to the third conductive layer M3. Specifically, as shown in Figure 8, after placing electronic elements EU1 and EU2, the target substrate TS can be separated from the circuit structure CS by removing the release layer RL. After removing the release layer RL, the warp prevention layer AW1 may also be separated from the circuit structure CS. Thus, the third conductive layer M3 of the circuit structure CS is exposed. Subsequently, the connecting element CE1 can be placed corresponding to the third conductive layer M3 (or the conductive portion P2 of the third conductive layer M3) and brought into contact with the third conductive layer M3 (or the conductive portion P2 of the third conductive layer M3). This electrically connects the connecting element CE1 to the circuit structure CS. In some embodiments, as shown in Figure 8, a solder mask MK can be placed on the side of the circuit structure CS adjacent to the third conductive layer M3 before placing the connecting element CE1, thereby defining the placement position of the connecting element CE1 within the solder mask MK. Specifically, the portion of the solder mask MK corresponding to the conductive portion P2 of the third conductive layer M3 can be removed to expose at least a part of the conductive portion P2, and then the connecting element CE1 can be placed corresponding to the exposed portion of the conductive portion P2. After completing the above steps, the electronic device E2 shown in Figure 8 can be formed. Note that the structure of the electronic device E2 is not limited to that shown in Figure 8 and may further include other appropriate elements and layers.

[0056] Referring to Figure 9, Figure 9 schematically shows a cross-sectional view of an electronic device according to a third embodiment of the present disclosure. The manufacturing method of the electronic device E3 of this embodiment can be described by referring to the manufacturing method M100 described above. Specifically, a target substrate TS can be provided first, and then the circuit structure CS' can be placed on the target substrate TS. According to this embodiment, in the manufacturing process of the target substrate TS, before placing the planarization layers PL1 and PL2 on both sides of the base layer BS, respectively, the warp prevention layer AW2 can be placed on at least one side of the base layer BS. Specifically, as shown in Figure 9, after the planarization step of the base layer BS, the warp prevention layer AW2 can be placed first on and / or below the surface S1 and / or surface S2 of the base layer BS, and then the planarization layers can be placed. In some embodiments, as shown in Figure 9, the warp prevention layer AW2 can be placed on both sides of the substrate layer BS, that is, the warp prevention layer AW2 can be placed on surface S1 and below surface S2, respectively. In this state, the substrate layer BS can be placed between the two warp prevention layers AW2. In some embodiments, the anti-warping layer AW2 may be located on only one side of the base layer BS. For example, the anti-warping layer AW2 may be located on surface S1 or below surface S2. After the anti-warping layer AW2 is located, planarization layers PL1 and PL2 are located, thereby forming the target substrate TS. That is, the target substrate TS of this embodiment may further include at least one anti-warping layer AW2 located between the base layer BS and at least one of the planarization layers PL1 and PL2. In embodiments in which the target substrate TS includes two anti-warping layers AW2 on each side of the base layer BS, the thicknesses of the two anti-warping layers AW2 may be the same or different. Furthermore, the thermal expansion coefficients of the two anti-warping layers AW2 may be the same or different. The anti-warping layer AW2 may include any suitable organic or inorganic material. By including the anti-warping layer AW2 in the target substrate TS, the possibility that the manufacturing process of the elements on the target substrate TS may be affected by warping of the target substrate TS can be reduced. The above-described feature, in which the target substrate TS includes a warp prevention layer AW2, can be applied to embodiments of this disclosure.

[0057] After the target substrate TS is formed, the circuit structure CS' can be placed on the target substrate TS. The circuit structure CS' may include at least one conductive layer and at least one insulating layer. For example, as shown in Figure 9, the circuit structure CS' may include, but is not limited to, a conductive layer M4, a conductive element CN', an insulating layer I3, an insulating layer I4, and an insulating layer I5. The conductive layer M4 is placed within the insulating layer I3, and the conductive element CN' is placed within the insulating layers I4 and I5 and electrically connected to the conductive layer M4. Note that the circuit structure CS' shown in Figure 9 is an example, and the actual structure of the circuit structure CS' is not limited to that shown in Figure 9. In some embodiments, the circuit structure CS' may include a structure formed by laminating a conductive layer and an insulating layer. In some embodiments, the circuit structure CS' may be the circuit structure CS in any of the above embodiments.

[0058] In this embodiment, after the circuit structure CS' is placed, at least one electronic element is placed on the circuit structure CS' to form the electronic device E3. For example, as shown in Figure 9, after the circuit structure CS' is placed on the target substrate TS, electronic elements EU3 and EU4 are placed on the circuit structure CS' (or on the side of the circuit structure CS' opposite to the target substrate TS), but are not limited to this. That is, the electronic device E3 may include at least one electronic element placed on the circuit structure CS' opposite to the target substrate TS. Furthermore, in this embodiment, the target substrate TS may function as the substrate for the electronic device E3, i.e., the target substrate TS may not be removed during the manufacturing process of the electronic device E3. Electronic elements EU3 and EU4 may be electrically connected to the circuit structure CS' (or the conductive element CN' and / or conductive layer M4 within the circuit structure CS'). For example, the conductive layer within the circuit structure CS' (including the conductive layer M4 and the conductive element CN') may form wiring or other suitable elements electrically connected to electronic elements EU3 and / or electronic elements EU4. Furthermore, electronic element EU3 may be electrically connected to electronic element EU4 via a circuit structure CS' (e.g., a conductive layer M4 and a conductive element CN'). In one embodiment, electronic element EU3 may include an application-specific integrated circuit (ASIC) chip, and electronic element EU4 may include an optical engine and be connected to an optical fiber FB, but is not limited to these. In other embodiments, electronic elements EU3 and EU4 may include other suitable electronic elements depending on the type or purpose of the electronic device E3. By using a target substrate TS as the substrate for the electronic device E3, the stability of the electronic elements (e.g., electronic elements EU3 and EU4) placed on the target substrate TS is improved, and situations that cause coupling failures between electronic elements (e.g., between electronic element EU4 and the optical fiber FB, but not limited to these) can be reduced. Thus, the reliability of the electronic device E3 is improved.

[0059] Referring to Figure 10, Figure 10 schematically shows a cross-sectional view of an electronic device 14 according to a fourth embodiment of the present disclosure. One of the main differences between the electronic device E4 of this embodiment and the electronic device E3 shown in Figure 9 is the structural design of the target substrate TS. According to this embodiment, after the target substrate TS is formed, the method for manufacturing the electronic device E4 may further include forming at least one via VH within the target substrate TS. For example, Figure 10 shows, but is not limited to, a structure in which the target substrate TS includes two vias VH. The vias VH may penetrate the target substrate TS. In this state, the vias VH can connect the upper surface (i.e., surface S3) and the lower surface (i.e., surface S4) of the target substrate TS, i.e., the sidewalls of the vias VH are connected between surfaces S3 and S4. In this embodiment, the vias VH can be formed by performing modification and etching treatments on the target substrate TS, but is not limited to this. Specifically, a modification treatment can be performed on a portion of the target substrate TS corresponding to a predetermined position of the vias VH, thereby weakening the structure of that portion of the target substrate TS. The modification process may include, but is not limited to, laser modification. Subsequently, an etching step is performed on the target substrate TS to remove the modified portion of the target substrate TS, thereby forming vias VH that penetrate the target substrate TS. The "portion of the target substrate TS" includes the base layer BS, the planarization layer PL1, and the planarization layer PL2. That is, vias VH can be formed by removing a portion of the base layer BS, a portion of the planarization layer PL1, and a portion of the planarization layer PL2, but is not limited to this. In some embodiments, if the target substrate TS further includes the aforementioned warp prevention layer AW2, vias VH can be formed by further removing a portion of the warp prevention layer AW2. According to some embodiments, the target substrate TS may include a plurality of base layers BS and a plurality of planarization layers (planarization layer PL1 and planarization layer PL2) stacked alternately along the direction Z. Specifically, another base layer BS is placed on planarization layer PL2, and another planarization layer is provided on another base layer BS, thereby reducing the thickness variation of the target substrate TS to 3 μm or less.Here, the materials of these base layers BS may be the same or different, the thicknesses of these base layers BS may be the same or different, and the thermal expansion coefficients of these base layers BS may be the same or different. For example, in the Z direction, the thickness of the base layer BS away from the electronic element EU3 may be greater than the thickness of the base layer BS adjacent to the electronic element EU3, and the thermal expansion coefficient of the base layer BS away from the electronic element EU3 may be smaller than the thermal expansion coefficient of the base layer BS adjacent to the electronic element EU3.

[0060] According to this embodiment, the method for manufacturing the electronic device E4 may further include the step of forming a conductive element CN within a via VH. Specifically, after forming the via VH, the conductive element CN is formed by filling the via VH with the material for the conductive element CN. The conductive element CN may, but is not limited to, completely fill the via VH. The conductive element CN may include copper (Cu), aluminum (Al), other suitable metals, or a combination of the above materials. In some embodiments, as shown in Figure 10, after the via VH is formed, a buffer layer BF may be placed within the via VH first, and then the conductive element CN may be placed. The buffer layer BF may, but is not limited to, be placed along the sidewall of the via VH, or the buffer layer BF may cover the sidewall of the via VH. In some embodiments, the buffer layer BF may further extend onto the surface of the target substrate TS (i.e., surfaces S3 and S4). The buffer layer BF may include any suitable organic or inorganic insulating material. Note that the buffer layer BF shown in Figure 10 is a single-layer structure, but is not limited to this embodiment. In some embodiments, the buffer layer BF may include a multilayer structure.

[0061] The method for manufacturing the electronic device E4 of this embodiment may further include arranging a circuit structure CS' on a target substrate and arranging at least one electronic element (e.g., electronic element EU3 and electronic element EU4) on the circuit structure CS'. Details can be found in the above description and will not be repeated. Compared to the embodiment shown in Figure 9, in this embodiment, electronic elements EU3 and / or electronic element EU4 may be electrically connected to the circuit structure CS' via a conductive element C2, but this is not limited. For the structure of the circuit structure CS', please refer to Figure 9 and the above related content. The circuit structure CS' may be electrically connected to a conductive element CN arranged in a via VH. For example, the conductive element CN' in the circuit structure CS' may be electrically connected to a conductive layer M4, and the conductive layer M4 may be in contact with the conductive element CN, but this is not limited. Therefore, electronic elements EU3 and / or electronic element EU4 may be electrically connected to the conductive element CN via the conductive element CN' and the conductive layer M4. Furthermore, the manufacturing method of the electronic device E4 in this embodiment may further include the step of arranging the connecting element CE1 on the side of the target substrate TS opposite to the circuit structure CS' (see Figure 8). Specifically, the conductive element CN'', insulating layer IL, insulating layer I1, conductive layer M2, insulating layer I2, conductive layer M3, connecting element CE1, and solder mask MK may, but are not limited to, be formed below the surface S4 of the target substrate TS. The conductive element CN'' is located within the insulating layer IL and may be in contact with the conductive element CN. The layers or elements below the insulating layer IL will not be described again, as they are shown in Figure 8 and described above. The conductive layer M2 may be electrically connected to the conductive element CN'', and the conductive layer M3 may be electrically connected to the conductive layer M2. Thus, the conductive element CN may be electrically connected to the connecting element CE1 via the conductive element CN'', conductive layer M2, and conductive layer M3. In this configuration, electronic elements (e.g., electronic elements EU3 and EU4) placed on the circuit structure CS' can be electrically connected to the connecting element CE1 via the circuit structure CS', conductive elements CN and CN'', conductive layers M2 and M3, which are placed within the via VH. In some embodiments, although not shown in the figure, the connecting element CE1 can be electrically connected to another electronic element.In this case, electronic elements EU3 and / or EU4 may be electrically connected to another electronic element via the circuit structure CS', conductive element CN, conductive element CN'', conductive layer M2, conductive layer M3, and connecting element CE1.

[0062] In summary, this disclosure provides an electronic device and a method for manufacturing the same. The electronic device may include a target substrate, or the target substrate may be used in a manufacturing process for the electronic device. The target substrate may include a base layer treated by a planarization process and planarization layers positioned on both sides of the base layer to reduce variations in the thickness of the target substrate. Thus, the flatness or stability of elements or layers placed on the target substrate is improved, thereby improving the reliability of the electronic device.

[0063] Those skilled in the art will readily understand that numerous changes and modifications are possible to the apparatus and methods while retaining the teachings of this disclosure. Therefore, the above disclosure should be construed as being limited only to the scope of the appended claims.

Claims

1. A method for manufacturing electronic devices, The steps include (a) through (d) below, and providing a target substrate: (a) Provide a base layer; (b) Perform a planarization step on the base layer, and then measure the first thickness variation of the base layer; (c) Forming the target substrate by arranging two planarization layers on each side of the base layer; and (d) Measure the second thickness variation of the target substrate, wherein the second thickness variation is smaller than the first thickness variation; A manufacturing method comprising the step of arranging a circuit structure on the target substrate.

2. In the manufacturing method according to claim 1, if the measured first thickness variation exceeds 20 micrometers, the manufacturing method further includes the following step (e) before step (c): (e) Repeat step (b) until the measured first thickness variation is 20 micrometers or less.

3. In the manufacturing method according to claim 1, if the measured second thickness variation exceeds 3 micrometers, the manufacturing method further comprises the following steps (f) and (g): (f) Remove the planarization layer; and (g) Repeat steps (c) and (d). Here, steps (f) and (g) are repeated until the measured second thickness variation is 3 micrometers or less.

4. A manufacturing method according to claim 1, wherein if the measured second thickness variation exceeds 3 micrometers, the manufacturing method further includes repeatedly performing the planarization step on the planarized layer until the measured second thickness variation becomes 3 micrometers or less.

5. A manufacturing method according to claim 1, wherein the circuit structure includes a plurality of conductive layers, the plurality of conductive layers include a first conductive layer closest to the target substrate and a second conductive layer furthest from the target substrate, the first conductive layer includes a plurality of first conductive parts, the second conductive layer includes a plurality of second conductive parts, and the size of one of the plurality of first conductive parts is smaller than the size of one of the plurality of second conductive parts.

6. A manufacturing method according to claim 5, further comprising the following steps: The step of removing the target substrate; and The step of placing at least one electronic element on the side surface of the circuit structure adjacent to the first conductive layer.

7. A manufacturing method according to claim 6, further comprising arranging at least one connecting element on a side surface of the circuit structure adjacent to the second conductive layer.

8. A manufacturing method according to claim 1, wherein the circuit structure includes a plurality of conductive layers, the plurality of conductive layers include a first conductive layer located furthest from the target substrate and a second conductive layer located closest to the target substrate, the first conductive layer includes a plurality of first conductive parts, the second conductive layer includes a plurality of second conductive parts, and the size of one of the plurality of first conductive parts is smaller than the size of one of the plurality of second conductive parts.

9. A manufacturing method according to claim 8, further comprising arranging at least one electronic element on a side surface of the circuit structure adjacent to the first conductive layer, wherein the circuit structure is arranged between the target substrate and the at least one electronic element.

10. A manufacturing method according to claim 9, further comprising the following steps: The step of removing the target substrate; and The step of placing at least one connecting element on the side of the circuit structure adjacent to the second conductive layer.

11. A manufacturing method according to claim 1, further comprising the following steps: A step of forming vias in the target substrate; The step of forming a conductive element in the via; and A step of arranging a connecting element on the target substrate side opposite to the circuit structure, Here, the circuit structure is electrically connected to the connecting element via the conductive element.

12. A manufacturing method according to claim 1, further comprising placing a warp-preventing layer on at least one side of the base layer before placing the two planarizing layers on both sides of the base layer.

13. It is an electronic device, Base layer; and Two planarization layers, each positioned on either side of the aforementioned base layer; A target substrate comprising: The circuit structure is arranged on the target substrate, Herein, the base layer has a first thickness variation, and the target substrate has a second thickness variation, the second thickness variation being smaller than the first thickness variation, in this electronic device.

14. An electronic device according to claim 13, wherein the first thickness variation is 20 micrometers or less.

15. An electronic device according to claim 13, wherein the second thickness variation is 3 micrometers or less.

16. An electronic device according to claim 13, further comprising at least one electronic element disposed on the side of the circuit structure opposite to the target substrate.

17. An electronic device according to claim 13, further comprising the following: A connecting element located on the target substrate side opposite to the circuit structure, Here, the target substrate has vias, conductive elements are arranged within the vias, and the circuit structure is electrically connected to the connecting elements via the conductive elements.

18. An electronic device according to claim 13, further comprising at least one anti-warping layer disposed between the base layer and at least one of the planarizing layers.

19. An electronic device according to claim 13, wherein the base layer includes glass.

20. An electronic device according to claim 13, wherein the transmittance of the two planarization layers exceeds 70%.

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