Semiconductor memory device, memory system, control method for semiconductor memory device

Abstract

A semiconductor memory device capable of improving block efficiency is provided. [Solution] The semiconductor memory device comprises a first plane and a second plane, signal lines, a determination circuit, and a control unit. The signal lines apply voltage to a first word line connected to a first memory cell transistor in a first block of the first plane, and to a second word line connected to a second memory cell transistor in a second block of the second plane. The determination circuit determines whether leakage has occurred in the first word line and the second word line based on the voltage of the signal lines. Based on the determination result of the determination circuit, the control unit registers the first block as a bad block and registers the second block as a damaged block that can be used as a good block.

Description

Technical Field

[0001] Embodiments relate to a semiconductor memory device, a memory system, and a method for controlling a semiconductor memory device.

Background Art

[0002] A semiconductor memory device has a multi-plane configuration including a plurality of planes and has a multi-plane mode in which data is written to the plurality of planes simultaneously.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to an embodiment, a semiconductor memory device capable of improving block efficiency is provided.

Means for Solving the Problems

[0005] The semiconductor memory device of this embodiment comprises a first plane and a second plane, signal lines, a determination circuit, and a control unit. The first plane and the second plane each have a plurality of blocks, which are collections of a plurality of memory cell transistors. The signal lines apply voltage to a first word line connected to the gate of a first memory cell transistor included in the first block of the first plane, and to a second word line connected to the gate of a second memory cell transistor included in the second block of the second plane. The determination circuit determines whether leakage occurs in the first word line and the second word line based on the voltage of the signal lines. The control unit controls the first plane and the second plane. When the determination result of the determination circuit indicates that leakage has occurred in the first word line and that there is no leakage in the second word line, the control unit registers the first block as a bad block and registers the second block as a damaged block that can be used as a good block. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing the schematic configuration of the memory system of the embodiment. [Figure 2] A block diagram showing the schematic configuration of the semiconductor memory device according to the embodiment. [Figure 3] A block diagram showing the schematic configuration of the register in the embodiment. [Figure 4] A circuit diagram showing the configuration of a semiconductor memory device according to an embodiment. [Figure 5] A cross-sectional view showing the cross-sectional structure of the semiconductor memory device according to the embodiment. [Figure 6] A figure showing an example of the threshold voltage distribution of a memory cell transistor in an embodiment. [Figure 7] A diagram showing the potential change of each wire during programmed operation of the memory cell transistor in the embodiment. [Figure 8] A diagram showing the potential change of each wire during the read operation of the memory cell transistor in the embodiment. [Figure 9] A diagram showing the potential change of the word line during the writing operation of the embodiment. [Figure 10] This figure shows the relationship between the number of loops and the verification operation during the write operation of the embodiment. [Figure 11] A diagram showing the relationship between the number of loops and program operation during the writing operation of the embodiment. [Figure 12] A block diagram showing the schematic configuration of the plane control circuit of the embodiment. [Figure 13] A block diagram showing the schematic configuration of the raw decoder of the embodiment. [Figure 14] A schematic diagram illustrating an example of the operation of a semiconductor memory device in a comparative example. [Figure 15] A block diagram showing the schematic configuration of the voltage supply circuit of the embodiment. [Figure 16] A flowchart illustrating an example of the operation of the semiconductor memory device according to the embodiment. [Figure 17] A schematic diagram illustrating an example of the operation of a semiconductor memory device according to the embodiment. [Figure 18] A schematic diagram illustrating an example of the operation of a semiconductor memory device according to the embodiment. [Figure 19] (A) to (C) are timing charts showing the changes in the voltage of the selection word line, the voltage of the first global signal line, and the output signal of the determination circuit of the semiconductor memory device of the embodiment. [Figure 20] A schematic diagram illustrating an example of the operation of a semiconductor memory device according to the embodiment. [Figure 21] A schematic diagram illustrating an example of the operation of a semiconductor memory device according to the embodiment. [Figure 22] (A) to (C) are timing charts showing the changes in the voltage of the selection word line, the voltage of the first global signal line, and the output signal of the determination circuit of the semiconductor memory device of the embodiment. [Figure 23] A flowchart illustrating an example of the operation of the memory controller in the embodiment. [Figure 24] A cross-sectional view showing the cross-sectional structure of a semiconductor memory device of another embodiment. [Modes for carrying out the invention]

[0007] Hereinafter, embodiments will be described with reference to the drawings. For ease of understanding of the description, the same components in each drawing are given the same reference numerals as much as possible, and redundant descriptions are omitted.

[0008] 1 Embodiment The semiconductor memory device of the embodiment will be described. The semiconductor memory device according to the present embodiment is a non-volatile memory device configured as a NAND type flash memory.

[0009] 1.1 Configuration of Memory System First, the configuration of the memory system of the present embodiment will be described.

[0010] As shown in FIG. 1, the memory system 3 of the present embodiment includes a memory controller 1 and a semiconductor memory device 2. The memory system 3 can be connected to a host. The host is an electronic device such as a personal computer or a mobile terminal.

[0011] The memory controller 1 controls the writing of data to the semiconductor memory device 2 according to a write request from the host. Also, the memory controller 1 controls the reading of data from the semiconductor memory device 2 according to a read request from the host.

[0012] Between the memory controller 1 and the semiconductor memory device 2, signals such as chip enable signal / CE, ready busy signal R / B, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal / RE, RE, write protect signal / WP, signal DQ<7:0>, and data strobe signal DQS, / DQS are transmitted and received.

[0013] The chip enable signal / CE is transmitted from the memory controller 1 to the semiconductor memory device 2. The chip enable signal / CE is a signal to enable the semiconductor memory device 2. The ready / busy signal R / B is transmitted from the semiconductor memory device 2 to the memory controller 1. The ready / busy signal R / B is a signal to indicate whether the semiconductor memory device 2 is in a ready state or a busy state. "Ready state" is, for example, a state in which it is ready to accept commands from the outside. "Busy state" is a state in which it is not ready to accept commands from the outside.

[0014] The command latch enable signal CLE is transmitted from memory controller 1 to semiconductor storage device 2. The command latch enable signal CLE indicates that signal DQ<7:0> is a command. The address latch enable signal ALE is transmitted from memory controller 1 to semiconductor storage device 2. The address latch enable signal ALE indicates that signal DQ<7:0> is an address. The write enable signal / WE is transmitted from memory controller 1 to semiconductor storage device 2. The write enable signal / WE is a signal for capturing the received signal in semiconductor storage device 2, and is asserted by memory controller 1 each time a command, address, or data is received. Memory controller 1 instructs semiconductor storage device 2 to capture signal DQ<7:0> while signal / WE is at the "L (Low)" level.

[0015] The read enable signal / RE is transmitted from the memory controller 1 to the semiconductor memory device 2. Signal RE is the complementary signal to signal / RE. The read enable signals / RE and RE are signals for the memory controller 1 to read data from the semiconductor memory device 2. The read enable signals / RE and RE are used to control the operating timing of the semiconductor memory device 2 when, for example, outputting signal DQ<7:0>. Signal DQ<7:0> is the data entity transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes commands, addresses, and data. The data strobe signal DQS is a timing control signal transmitted and received between the semiconductor memory device 2 and the memory controller 1 in conjunction with signal DQ<7:0>. Signal / DQS is the complementary signal to signal DQS. The data strobe signals DQS and / DQS are signals for controlling the input and output timing of signal DQ<7:0>.

[0016] The memory controller 1 comprises RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. These are connected to each other by an internal bus 16.

[0017] The host interface 13 outputs requests and user data (write data), etc., received from the host to the internal bus 16. The host interface 13 also sends user data read from the semiconductor memory device 2 and responses from the processor 12, etc., to the host.

[0018] The memory interface 15 controls the process of writing user data, etc., to the semiconductor storage device 2 and the process of reading data from the semiconductor storage device 2, based on instructions from the processor 12.

[0019] The processor 12 comprehensively controls the memory controller 1. The processor 12 is a CPU, MPU, etc. When the processor 12 receives a request from the host via the host interface 13, it performs control according to that request. For example, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor storage device 2 according to a request from the host. The processor 12 also instructs the memory interface 15 to read user data and parity from the semiconductor storage device 2 according to a request from the host.

[0020] The processor 12 determines the storage area (memory area) on the semiconductor memory device 2 for the user data stored in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data in page units (page data), which are the writing units. User data stored in one page of the semiconductor memory device 2 will also be referred to as "unit data" below. Unit data is generally encoded and stored in the semiconductor memory device 2 as a codeword. In this embodiment, encoding is not mandatory. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding, but Figure 1 shows a configuration in which encoding is performed as an example.

[0021] The processor 12 determines the memory area of ​​the semiconductor storage device 2 to which each unit data should be written. A physical address is assigned to the memory area of ​​the semiconductor storage device 2. The processor 12 manages the memory area to which the unit data should be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor storage device 2 by specifying the determined memory area (physical address). The processor 12 manages the correspondence between the logical address (logical address managed by the host) and the physical address of the user data. When the processor 12 receives a read request from the host that includes a logical address, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0022] The ECC circuit 14 encodes user data stored in the RAM 11 to generate a codeword. The ECC circuit 14 also decodes the codeword read from the semiconductor memory device 2.

[0023] RAM11 temporarily stores user data received from the host before storing it in the semiconductor memory device 2, and also temporarily stores data read from the semiconductor memory device 2 before sending it to the host. RAM11 is a general-purpose memory such as SRAM or DRAM.

[0024] Figure 1 shows an example configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be integrated into the memory interface 15. Alternatively, the ECC circuit 14 may be integrated into the semiconductor memory device 2. The specific configuration and arrangement of each element shown in Figure 1 are not particularly limited.

[0025] When a write request is received from the host, the memory system 3 in Figure 1 operates as follows: The processor 12 temporarily stores the data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory device 2.

[0026] When a read request is received from the host, the memory system 3 in Figure 1 operates as follows: The memory interface 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0027] 1.2 Schematic Configuration of Semiconductor Memory Devices Next, we will describe the general configuration of the semiconductor memory device 2.

[0028] Figure 2 is a block diagram showing the configuration of the semiconductor memory device 2. As shown in Figure 2, the semiconductor memory device 2 comprises two planes PL0 and PL1, an input / output circuit 21, a logic control circuit 22, a sequencer 41, a register 42, a voltage supply circuit 43, a plane control circuit 44, an input / output pad group 31, a logic control pad group 32, and a power input terminal group 33.

[0029] Plane PL0 comprises a memory cell array 110, a sense amplifier 120, and a row decoder 130. Similarly, the other plane PL1 comprises a memory cell array 210, a sense amplifier 220, and a row decoder 230. Each plane PL0 and PL1 has the same configuration as the others.

[0030] The memory cell arrays 110 and 210 are the data storage parts. Each of the memory cell arrays 110 and 210 contains multiple memory cell transistors associated with word lines and bit lines. Each plane PL0 and PL1 has multiple blocks BLK (BLK(0), BLK(1), ..., BLK(n-1)), where n is an integer representing the number of blocks contained in each plane PL0 and PL1. Each block BLK functions as a unit of erase operation. The semiconductor memory device 2 has a multiplane configuration in which write operations to multiple planes PL0 and PL1 are performed simultaneously.

[0031] The input / output circuit 21 transmits and receives signals DQ<7:0> and data strobe signals DQS, / DQS to and from the memory controller 1. The input / output circuit 21 transfers the command and address within signal DQ<7:0> to register 42. The input / output circuit 21 also transmits and receives write data and read data to and from sense amplifiers 120,220.

[0032] The logic control circuit 22 receives the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE,RE, and write protect signal / WP from the memory controller 1. The logic control circuit 22 also forwards the ready busy signal R / B to the memory controller 1 to notify the external system of the state of the semiconductor memory device 2.

[0033] The sequencer 41 controls the operation of various parts such as planes PL0 and PL1 and voltage supply circuit 43 based on control signals input from the memory controller 1 to the input / output circuit 21 and logic control circuit 22. In this embodiment, the sequencer 41 is an example of a control unit.

[0034] Register 42 is a part that temporarily holds commands, addresses, etc. As shown in Figure 3, register 42 has a command register 42a, an address register 42b, and a status register 42c.

[0035] Command register 42a is where commands instructing write, read, and erase operations on planes PL0 and PL1 are stored. These commands are input from the memory controller 1 to the input / output circuit 21, and then transferred from the input / output circuit 21 to command register 42a for storage. Command register 42a then transfers the stored commands to the sequencer 41.

[0036] The address register 42b is the part that holds the addresses of planes PL0 and PL1, respectively, corresponding to commands to planes PL0 and PL1. For example, when the addresses of planes PL0 and PL1 are input from the memory controller 1 to the input / output circuit 21, those addresses are transferred from the input / output circuit 21 to the address register 42b. The address register 42b then transfers the block address and row address included in the address corresponding to plane PL0 to the row decoder 130 of plane PL0. The address register 42b also transfers the block address and row address included in the address corresponding to plane PL1 to the row decoder 230 of plane PL1.

[0037] The status register 42c is where status information indicating the state of planes PL0 and PL1 is stored. The status information is updated each time by the sequencer 41 according to the operating state of planes PL0 and PL1. The status information stored in the status register 42c is transmitted to the memory controller 1 as a status signal from the input / output circuit 21 in response to a request from the memory controller 1.

[0038] The voltage supply circuit 43 shown in Figure 2 generates the voltages necessary for writing, reading, and erasing operations based on instructions from the sequencer 41, and supplies these generated voltages to the row decoders 130 and 230 and the sense amplifiers 120 and 220.

[0039] The plane control circuit 44 consists of a group of switch circuits for controlling the voltage supplied from the voltage supply circuit 43 to the row decoders 130 and 230. The plane control circuit 44 can switch between, for example, a state in which voltage is supplied from the voltage supply circuit 43 to the row decoders 130 and 230 and a state in which the voltage supply from the voltage supply circuit 43 to the row decoders 130 and 230 is cut off by switching the open / closed state of the group of switch circuits. The plane control circuit 44 is controlled by the sequencer 41.

[0040] The sense amplifier 120 in plane PL0 is a circuit for adjusting the voltage applied to the bit line of the memory cell array 110 and for reading the voltage on the bit line of the memory cell array 110 and converting it into data. When reading data, the sense amplifier 120 acquires the data read from the memory cell transistors of the memory cell array 110 onto the bit line and transfers the acquired read data to the input / output circuit 21. When writing data, the sense amplifier 120 transfers the data to be written via the bit line to the memory cell transistors of the memory cell array 110.

[0041] The row decoder 130 of plane PL0 is a circuit for applying voltage to multiple word lines and multiple select gate lines in any block BLK included in the memory cell array 110. The row decoder 130 receives the block address and row address corresponding to plane PL0 from the address register 42b of register 42, selects a block in the memory cell array 110 based on the block address, and selects a word line in the memory cell array 110 based on the row address. The row decoder 130 switches the open / closed state of the switch group so that voltage from the voltage supply circuit 43 is applied to the selected word line.

[0042] The sense amplifier 220 of plane PL1 operates on the memory cell array 210 of plane PL1 in the same way as the sense amplifier 120 of plane PL0. Similarly, the row decoder 230 of plane PL1 operates on the memory cell array 210 of plane PL1 in the same way as the row decoder 130 of plane PL0. The operation of the sense amplifiers 120 and 220 and the row decoders 130 and 230 are controlled by the sequencer 41.

[0043] The input / output pad group 31 is a section where multiple terminals (pads) are provided for sending and receiving signals between the memory controller 1 and the input / output circuit 21. Each terminal is individually provided to correspond to the signal DQ<7:0> and the data strobe signals DQS, / DQS, respectively.

[0044] The logic control pad group 32 is a section provided with multiple terminals (pads) for sending and receiving various signals between the memory controller 1 and the logic control circuit 22. Each terminal is individually provided to correspond to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE,RE, write protect signal / WP, and ready busy signal R / B.

[0045] The power input terminal group 33 is a section provided with multiple terminals for receiving the voltages necessary for the operation of the semiconductor memory device 2. The voltages applied to each terminal include the power supply voltage Vcc, VccQ, Vpp, and the ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage supplied externally as the operating power supply, and is, for example, a voltage of about 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is the voltage used when sending and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage Vpp is a power supply voltage that is higher than the power supply voltage Vcc, and is, for example, a voltage of 12V.

[0046] Furthermore, at least one of the multiple blocks BLK contained in each of the memory cell arrays 110 and 210 functions as a ROM block. The ROM block stores data necessary for the operation of the semiconductor memory device 2, such as various operating parameters, rather than user data. The ROM block also contains status information (good block / bad block information) indicating whether the multiple blocks BLK provided in each of the memory cell arrays 110 and 210 are in a normal or faulty state. Users are prohibited from instructing the writing of user data to the ROM block or from instructing the erasure of data stored in the ROM block. In other words, the ROM block is a block specially provided in each of the memory cell arrays 110 and 210 as a storage area that cannot be written to or erased from the outside, separate from the storage area that can be written to or erased from the outside.

[0047] In the memory system 3 of this embodiment, the semiconductor memory device 2 performs a power-on read operation when power is supplied to the memory system 3. Specifically, when power is supplied to the memory system 3, the processor 12 of the memory controller 1 shown in Figure 1 instructs the semiconductor memory device 2 to perform a power-on read operation via the memory interface 15. As a result, the semiconductor memory device 2 reads data from ROM blocks provided in, for example, the memory cell arrays 110 and 210, and stores this data in the registers of the sequencer 41. This puts the semiconductor memory device 2 into a state where it can operate properly, in other words, the semiconductor memory device 2 is started up. The good block / bad block information read from the ROM blocks is transmitted to the memory controller 1 via the input / output circuit 21 and stored in the RAM 11 shown in Figure 1. Based on the good block / bad block information stored in this RAM, the memory controller 1 instructs the semiconductor memory device 2 to operate in a way that avoids bad blocks.

[0048] 1.3 Circuit configuration of memory cell array Next, the circuit configurations of memory cell arrays 110 and 210 will be described. Since the configurations of each memory cell array 110 and 210 are identical, only the configuration of memory cell array 110 will be described below, and the description of memory cell array 210 will be omitted.

[0049] As shown in Figure 4, the memory cell array 110 is composed of multiple block blocks (BLKs). In Figure 4, only one of the block blocks is shown. The configuration of the other block blocks in the memory cell array 110 is the same as that shown in Figure 4.

[0050] As shown in Figure 4, block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU also includes multiple NAND strings NS. Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and selection transistors ST1 and ST2.

[0051] The memory cell transistor MT is arranged to be connected in series between the selection transistor ST1 and the selection transistor ST2. One end of the memory cell transistor MT7 is connected to the source of the selection transistor ST1, and the other end of the memory cell transistor MT0 is connected to the drain of the selection transistor ST2.

[0052] The gates of the selection transistors ST1 in each of the string units SU0 to SU3 are commonly connected to the select gate lines SGD0 to SGD3, respectively. The gate of the selection transistor ST2 is commonly connected to the same select gate line SGS among multiple string units SU within the same block BLK. The gates of the memory cell transistors MT0 to MT7 within the same block BLK are commonly connected to the word lines WL0 to WL7, respectively. In other words, the word lines WL0 to WL7 and the select gate line SGS are common among multiple string units SU0 to SU3 within the same block BLK, whereas the select gate line SGD is provided individually for each string unit SU0 to SU3, even within the same block BLK.

[0053] The memory cell array 110 is provided with m bit lines BL(BL0, BL1, ..., BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS contained in one string unit SU. The drain of each selection transistor ST1 of the NAND string NS is connected to the corresponding bit line BL. The source of each selection transistor ST2 of the NAND string NS is connected to the source line SL. The source line SL is common to the sources of multiple selection transistors ST2 in block BLK.

[0054] Data stored in multiple memory cell transistors MT within the same block BLK is erased collectively. On the other hand, data reading and writing are performed collectively on multiple memory cell transistors MT connected to a single word line WL and belonging to a single string unit SU.

[0055] Each memory cell transistor MT can hold 3 bits of data consisting of a high-order bit, a middle-order bit, and a low-order bit. In other words, the semiconductor memory device 2 according to this embodiment employs a TLC method, in which 3 bits of data are stored in one memory cell transistor MT, as the method for writing data to the memory cell transistor MT. Alternatively, the method for writing data to the memory cell transistor MT may be an MLC method, in which 2 bits of data are stored in one memory cell transistor MT, or an SLC method, in which 1 bit of data is stored in one memory cell transistor MT, etc.

[0056] In the following explanation, a "page" refers to a set of 1-bit data stored by multiple memory cell transistors MT connected to a single word line WL and belonging to a single string unit SU. In Figure 4, one of the sets of multiple memory cell transistors MT described above is denoted with the code "MG".

[0057] As in this embodiment, when 3 bits of data are stored in one memory cell transistor MT, a set of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU can store 3 pages of data.

[0058] 1.4 Cross-sectional structure of semiconductor memory devices Next, the structure of the memory cell arrays 110 and 210 and their surrounding areas will be described. Since the configurations of each memory cell array 110 and 210 are identical, only the configuration of memory cell array 110 will be described below, and the description of memory cell array 210 will be omitted.

[0059] As shown in Figure 5, in the memory cell array 110, multiple NAND strings NS are formed on the conductive layer 320. The conductive layer 320 is also called the embedded source line (BSL) and corresponds to the source line SL shown in Figure 4.

[0060] Above the conductive layer 320, multiple wiring layers 333 functioning as select gate lines (SGS), multiple wiring layers 332 functioning as word lines (WL), and multiple wiring layers 331 functioning as select gate lines (SGD) are stacked. An insulating layer (not shown) is placed between each of the stacked wiring layers 333, 332, and 331.

[0061] Multiple memory holes 334 are formed in the memory cell array 110. The memory holes 334 penetrate vertically through the wiring layers 333, 332, 331 and the insulating layer (not shown) between them, and reach the conductive layer 320. Block insulating film 335, charge storage layer 336, and gate insulating film 337 are sequentially formed on the side surface of the memory hole 334, and a conductive column 338 is embedded further inside. The conductive column 338 is made of polysilicon, for example, and functions as a region where a channel is formed when the memory cell transistor MT and selection transistors ST1, ST2 included in the NAND string NS are in operation. Hereinafter, the columnar body formed by the block insulating film 335, charge storage layer 336, gate insulating film 337, and conductive column 338 inside the memory hole 334 will also be referred to as a memory pillar MP.

[0062] Within the memory pillar MP, each portion that intersects with the stacked wiring layers 333, 332, and 331 functions as a transistor. Of these transistors, the portion that intersects with wiring layer 331 functions as a selection transistor ST1. Of these transistors, the portions that intersect with wiring layer 332 function as memory cell transistors MT (MT0 to MT7). Of these transistors, the portion that intersects with wiring layer 333 functions as a selection transistor ST2. With this configuration, the memory pillar MP functions as a NAND string NS as shown in Figure 4. The conductive pillar 338 inside the memory pillar MP is the portion that functions as the channel for the memory cell transistors MT and selection transistors ST1 and ST2.

[0063] Above the conductive column 338, a wiring layer that functions as a bit line BL is formed. At the upper end of the conductive column 338, a contact plug 339 is formed to connect the conductive column 338 and the bit line BL.

[0064] Multiple configurations similar to the one shown in Figure 5 are arranged along the depth direction of the page in Figure 5. A single string unit SU is formed by a collection of multiple NAND strings NS arranged in a line along the depth direction of the page in Figure 5.

[0065] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided below the memory cell array 110, that is, at a position between the memory cell array 110 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to realize data writing, reading, and erasing operations in the memory cell array 110. The sense amplifier 120, row decoder 130, voltage supply circuit 43, and plane control circuit 44 shown in Figure 2 are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors and RC circuits. In the example shown in Figure 5, a transistor TR formed on the semiconductor substrate 300 and a bit line BL located above the memory cell array 110 are electrically connected via a contact 924.

[0066] 1.5 Threshold voltage distribution of memory cell transistors Next, we will explain the threshold voltage distribution of memory cell transistors (MTs). Figure 6 is a schematic diagram showing the threshold voltage distribution of memory cell transistors (MTs). The diagram in the middle of Figure 6 shows the correspondence between the threshold voltage of a memory cell transistor (horizontal axis) and the number of memory cell transistors (vertical axis).

[0067] In the case where the TLC method is adopted as in this embodiment, the multiple memory cell transistors MT form eight threshold voltage distributions, as shown in the middle section of Figure 6. These eight threshold voltage distributions (write levels) are referred to as "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from the lowest threshold voltage.

[0068] The table in the upper part of Figure 6 shows examples of data assigned to each of the threshold voltage levels mentioned above. As shown in the table, different 3-bit data are assigned to the "ER", "A", "B", "C", "D", "E", "F", and "G" levels, for example, as shown below.

[0069] "ER" level: "111" ("Lower bit / Middle bit / Upper bit") "A" Level: "011" "B" Level: "001" "C" level: "000" "D" Level: "010" "E" level: "110" "F" level: "100" "G" level: "101" Thus, the threshold voltage of the memory cell transistor MT in this embodiment can take one of eight preset candidate levels, and data is assigned to each candidate level as described above.

[0070] Between pairs of adjacent threshold voltage distributions, a verify voltage used for the write operation is set. Specifically, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0071] The verify voltage VfyA is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. When the verify voltage VfyA is applied to the word line WL, memory cell transistors MT connected to the word line WL whose threshold voltage is included in the "ER" level turn ON, and memory cell transistors MT whose threshold voltage is included in the threshold voltage distribution of "A" level or higher turn OFF.

[0072] Other verify voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same way as the verify voltage VfyA described above. The verify voltage VfyB is set between the "A" level and the "B" level, the verify voltage VfyC is set between the "B" level and the "C" level, the verify voltage VfyD is set between the "C" level and the "D" level, the verify voltage VfyE is set between the "D" level and the "E" level, the verify voltage VfyF is set between the "E" level and the "F" level, and the verify voltage VfyG is set between the "F" level and the "G" level.

[0073] For example, the verify voltages VfyA, VfyB, VfyC, VfyC, VfyD, VfyE, VfyF, and VfyG may be set to 0.8V, 1.6V, 2.4V, 3.1V, 3.8V, 4.6V, and 5.6V, respectively. However, the system is not limited to these values, and the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG may be set in steps as appropriate, for example, within the range of 0V to 7.0V.

[0074] Furthermore, a read voltage used in the read operation is set between adjacent threshold voltage distributions. The "read voltage" is the voltage applied to the word line WL connected to the memory cell transistor MT to be read, i.e., the selected word line, during the read operation. In the read operation, the data is determined based on whether or not the threshold voltage of the memory cell transistor MT to be read is higher than the applied read voltage.

[0075] As schematically shown in the lower part of Figure 6, specifically, the read voltage VrA, which determines whether the threshold voltage of the memory cell transistor MT falls within the "ER" level or above the "A" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level.

[0076] Other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same way as read voltage VrA above. Read voltage VrB is set between level "A" and level "B", read voltage VrC is set between level "B" and level "C", read voltage VrD is set between level "C" and level "D", read voltage VrE is set between level "D" and level "E", read voltage VrF is set between level "E" and level "F", and read voltage VrG is set between level "F" and level "G".

[0077] Then, the read path voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold voltage distribution (for example, the "G" level). When the read path voltage VPASS_READ is applied to the gate of a memory cell transistor MT, it turns ON regardless of the data to be stored.

[0078] Furthermore, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set to higher voltages than, for example, the read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG. In other words, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set near the lower tail of the threshold voltage distributions for the "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, respectively.

[0079] When the data allocation described above is applied, the lower-order bit page data (lower page data) can be determined in the read operation by the read results using read voltages VrA and VrE. The middle-order bit page data (middle page data) can be determined by the read results using read voltages VrB, VrD, and VrF. The upper-order bit page data (upper page data) can be determined by the read results using read voltages VrC and VrG. Thus, since the lower-order, middle-order, and upper-order page data are determined by 2, 3, and 2 read operations, respectively, this type of data allocation is called a "2-3-2 code".

[0080] 1.6 Potential changes in each wiring during the writing operation of semiconductor memory devices Next, the writing operation of the semiconductor memory device 2 will be explained. The writing operation involves a program operation and a verify operation. The "program operation" is an operation that changes the threshold voltage of some memory cell transistors MT by injecting electrons into the charge storage layer 336 of those memory cell transistors MT. The "verification operation" is an operation that, after the above program operation, reads the data to determine and verify whether the threshold voltage of the memory cell transistors MT has reached the target level. Memory cell transistors MT whose threshold voltage has reached the target level are then disabled for writing. The "target level" here refers to a specific candidate level set as the target level from among the eight candidate levels mentioned earlier.

[0081] During the write operation, the above program and verification operations are repeatedly performed. This causes the threshold voltage of the memory cell transistor MT to rise to the target level.

[0082] Among the multiple word lines WL, the word line WL connected to the memory cell transistor MT that is the target of the write operation (i.e., the target whose threshold voltage is changed) will be referred to as the "selected word line" below. Similarly, the word line WL connected to the memory cell transistor MT that is not the target of the write operation will be referred to as the "unselected word line" below. The memory cell transistor MT that is the target of the write operation will also be referred to as the "selected memory transistor" below.

[0083] Among multiple string units SU, the string unit SU that is the target of the write operation will be referred to as the "selected string unit" below. Conversely, the string unit SU that is not the target of the write operation will be referred to as the "unselected string unit" below.

[0084] In the following, the conductive column 338 of each NAND string NS included in the selection string unit, that is, each channel in the selection string unit, will also be referred to as the "selection channel." Similarly, the conductive column 338 of each NAND string NS included in the non-selection string unit, that is, each channel in the non-selection string unit, will also be referred to as the "non-selection channel."

[0085] Among the multiple bit lines BL, the bit line BL connected to the selection memory transistor will be referred to as the "selection bit line" below. Conversely, the bit line BL not connected to the selection memory transistor will be referred to as the "non-selection bit line" below.

[0086] Figure 7 shows the potential changes of each wire during program operation. During program operation, sense amplifiers 120 and 220 change the potential of each bit line BL in accordance with the program data. For bit lines BL connected to memory cell transistors MT that are the target of the program (where the threshold voltage should be increased), an "L" level voltage, such as the ground voltage Vss (0V), is applied. For bit lines BL connected to memory cell transistors MT that are not the target of the program (where the threshold voltage should be maintained), an "H" level voltage, such as 2.5V, is applied. The former bit line BL is labeled "BL(0)" in Figure 7. The latter bit line BL is labeled "BL(1)" in Figure 7.

[0087] The row decoders 130 and 230 select one of the blocks BLK as the target for the write operation, and then select one of the string units SU. More specifically, a voltage of, for example, 5V is applied from the voltage supply circuit 43 to the select gate line SGD (selection select gate line SGDsel) of the selected string unit SU via the row decoders 130 and 230. This turns on the selection transistor ST1. On the other hand, a voltage of, for example, Vss is applied to the select gate line SGS from the voltage supply circuit 43 to the row decoders 130 and 230. This turns off the selection transistor ST2.

[0088] Furthermore, a voltage of, for example, 5V is applied from the voltage supply circuit 43 to the select gate line SGD (non-select select gate line SGDusel) of the non-select string unit SU in the selection block BLK via the row decoders 130 and 230. This turns on the selection transistor ST1. Note that the select gate line SGS is commonly connected in the string unit SU included in each block BLK. Therefore, the selection transistor ST2 is also in the off state in the non-select string unit SU.

[0089] Furthermore, a voltage Vss is applied to the select gate lines SGD and SGS in the non-selected block BLK from the voltage supply circuit 43 via the low decoders 130 and 230. This turns off the select transistors ST1 and ST2.

[0090] The source line SL is set to a higher potential than the select gate line SGS. This potential is, for example, 1V.

[0091] Next, the potential of the selection gate line SGDsel in the selection block BLK is set to, for example, 2.5V. This potential turns on the selection transistor ST1 corresponding to bit line BL(0) which is given 0V in the above example, but cuts off the selection transistor ST1 corresponding to bit line BL(1) which is given 2.5V. As a result, in the selection string unit SU, the selection transistor ST1 corresponding to bit line BL(0) is turned on, and the selection transistor ST1 corresponding to bit line BL(1) which is given 2.5V is cut off. On the other hand, the potential of the non-selection gate line SGDusel is set to, for example, voltage Vss. As a result, in the non-selection string unit SU, the selection transistor ST1 is cut off regardless of the potentials of bit line BL(0) and bit line BL(1).

[0092] The row decoders 130 and 230 then select one of the word lines WL as the target for the write operation in the selection block BLK. The program voltage VPGM is applied to the word line WL that is the target of the write operation (selected word line WLsel) from the voltage supply circuit 43 via the row decoders 130 and 230. On the other hand, the program path voltage VPASS_PGM is applied to the other word line WL (unselected word line WLusel) from the voltage supply circuit 43 via the row decoders 130 and 230. The program voltage VPGM is a high voltage for injecting electrons into the charge storage layer 336 by tunneling. The program path voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL, but does not change the threshold voltage. VPGM is a higher voltage than VPASS_PGM.

[0093] In the NAND string NS corresponding to the programmable bit line BL(0), the selection transistor ST1 is turned ON. As a result, the channel potential of the memory cell transistor MT connected to the selection word line WLsel becomes 0V. The potential difference between the control gate and the channel increases, and as a result, electrons are injected into the charge storage layer 336, causing the threshold voltage of the memory cell transistor MT to rise.

[0094] In the NAND string NS corresponding to the bit line BL(1), which is not programmed, the selection transistor ST1 is cut off. As a result, the channel of the memory cell transistor MT connected to the selection word line WLsel becomes electrically floating, and the channel potential is raised to near the program voltage VPGM due to capacitive coupling with the word line WL, etc. The potential difference between the control gate and the channel becomes small, and as a result, electrons are not injected into the charge storage layer 336, so the threshold voltage of the memory cell transistor MT is maintained. More precisely, the threshold voltage does not fluctuate to the extent that the threshold voltage distribution level transitions to a higher distribution.

[0095] Note that the operation of applying a 5V voltage to the selected gate line SGDsel and the unselected gate line SGDusel during the initial stages of program operation may be omitted.

[0096] The verification operation that follows the program operation is identical to the read operation described below, so its explanation will be omitted.

[0097] 1.7 Potential changes in each wiring during read operation of semiconductor memory device Next, the read operation of the semiconductor memory device 2 will be described. Figure 8 shows the potential change of each wiring during the read operation. In the read operation, the NAND string NS containing the memory cell transistor MT to be read is selected. Alternatively, the string unit SU containing the page to be read is selected.

[0098] First, a voltage of, for example, 5V is applied to the select gate line SGDsel, the non-select select gate line SGDusel, and the select gate line SGS from the voltage supply circuit 43 via the row decoders 130 and 230. This turns on the select transistors ST1 and ST2 included in the select block BLK. In addition, a read path voltage, for example, VPASS_READ, is applied to the select word line WLsel and the non-select word line WLusel from the voltage supply circuit 43 via the row decoders 130 and 230. The read path voltage VPASS_READ is a voltage that can turn on the memory cell transistor MT regardless of the threshold voltage of the memory cell transistor MT, and does not change the threshold voltage. As a result, current conducts in all NAND strings NS included in the select block BLK, regardless of whether they are select string units SU or non-select string units SU.

[0099] Next, a read voltage VCGRV, such as VrA, is applied from the voltage supply circuit 43 to the word line WL (selected word line WLsel) connected to the memory cell transistor MT that is the target of the read operation, via the row decoders 130 and 230. For the other word lines (non-selected word lines WLusel), the read path voltage VPASS_READ is applied.

[0100] Furthermore, while maintaining the voltages applied to the select gate line SGDsel and the select gate line SGS, a voltage Vss is applied to the non-select select gate line SGDusel from the voltage supply circuit 43 via the row decoders 130 and 230. As a result, the select transistor ST1 included in the select string unit SU remains ON, while the select transistor ST1 included in the non-select string unit SU is OFF. Regardless of whether it is a select string unit SU or a non-select string unit SU, the select transistor ST2 included in the select block BLK remains ON.

[0101] As a result, the NAND string NS included in the non-selected string unit SU does not form a current path because at least the selection transistor ST1 is in the off state. On the other hand, the NAND string NS included in the selected string unit SU forms or does not form a current path depending on the relationship between the read voltage VCGRV applied to the selected word line WLsel and the threshold voltage of the memory cell transistor MT.

[0102] The sense amplifiers 120 and 220 apply a voltage to the bit line BL connected to the selected NAND string NS. In this state, the sense amplifiers 120 and 220 read data based on the value of the current flowing through the bit line BL. Specifically, they determine whether the threshold voltage of the memory cell transistor MT that is the target of the read operation is higher than the read voltage applied to the memory cell transistor MT. Alternatively, data reading may be performed based on the time change of the potential in the bit line BL, rather than based on the value of the current flowing through the bit line BL. In the latter case, the bit line BL is pre-charged to a predetermined potential.

[0103] The verification operation described above is performed in the same way as the read operation described above. In the verification operation, a verification voltage such as VfyA is applied from the voltage supply circuit 43 to the word line WL connected to the memory cell transistor MT to be verified, via the row decoders 130 and 230.

[0104] Note that the operation of applying a 5V voltage to the non-selected select gate line SGDusel and applying the read path voltage VPASS_READ to the selected word line WLsel during the initial stage of the read operation (verification operation) may be omitted.

[0105] 1.8 Flow of writing operations for semiconductor memory devices Next, we will explain the specific flow of the entire write operation. In the write operation, the program operation and verification operation described above are repeated until it is confirmed that the data has been written correctly. Figure 9 shows an example where the combination of program operation and verification operation is repeated 19 times to write the data. Each of these repeated operations will be referred to as a "loop" below.

[0106] Figure 9 shows an example of the potential change of the selected word line WLsel during a write operation. As shown in the figure, the above loop is executed up to 19 times. In Figure 9, "VPGM1" refers to the VPGM applied to the selected word line WLsel in the first loop. "VPGM2" refers to the VPGM applied to the selected word line WLsel in the second loop. Similarly, in Figure 9, the VPGM applied to the selected word line WLsel in each loop is labeled "VPGM3", "VPGM4", ..., "VPGM19". As shown in the figure, with each repetition of the loop, the value of the VPGM is gradually increased in steps.

[0107] Figure 10 shows the target level of the verification operation performed in each loop. Figure 11 shows the target level of the program operation performed in each loop. In Figure 11, "1" means that no write operation is performed at that level, and "0" means that a write operation is performed at that level. "0 / 1" means that a write operation is basically performed at that level, but if verification was passed during the previous write operation, the write operation will not be performed.

[0108] As shown in Figures 9, 10, and 11, in the first loop in these examples, after VPGM1 is applied to the selected word line WLsel during program operation, the verification operation is performed only on the "A" level. That is, during the verification operation, the verification voltage VfyA is applied to the selected word line WLsel, and the verification voltages VfyB to VfyG are not applied.

[0109] In the first loop, the memory cell transistors (MTs) that are programmed are all memory cell transistors (MTs) whose threshold voltage should ultimately be at or above level "A". On the other hand, in the first loop, the memory cell transistors (MTs) that are verified at level "A" are those whose threshold voltage ultimately becomes at level "A". Memory cell transistors (MTs) whose threshold voltage ultimately becomes at or above level "B" are excluded from verification at level "A".

[0110] In the second loop, after VPGM2 is applied to the selected word line WLsel, the same programming and verification operations as in the first loop are performed. However, memory cell transistors MT whose threshold voltage ultimately reaches level "A" that passed verification at level "A" in the first loop are excluded from the programming and verification operations in the second loop. In other words, in the second loop, memory cell transistors MT whose threshold voltage ultimately reaches level "B" or higher, and memory cell transistors MT that failed verification in the previous loop, are the targets of the programming operation.

[0111] In the third loop, VPGM3 is applied to the selected word line WLsel and the program operation is performed, after which the verification operation is performed on the "A" level and the "B" level. In other words, during the verification operation, the verification voltages VfyA and VfyB are sequentially applied to the selected word line WLsel, while the verification voltages VfyC to VfyG are not applied.

[0112] In the third loop, the memory cell transistors (MTs) that are programmed are all memory cell transistors (MTs) whose threshold voltage should ultimately be at or above level "B", and memory cell transistors (MTs) that failed to verify in the previous loops. In the third loop, the memory cell transistors (MTs) that are verified at level "A" are those memory cell transistors (MTs) whose threshold voltage ultimately reaches level "A", and which failed to verify in the previous loops. In the third loop, the memory cell transistors (MTs) that are verified at level "B" are those memory cell transistors (MTs) whose threshold voltage ultimately reaches level "B".

[0113] In the fourth loop, after VPGM4 is applied to the selected word line WLsel, the same programming and verification operations as in the third loop are performed. However, among the memory cell transistors MT whose threshold voltage ultimately reaches level "A", those that passed the "A" level verification in the third loop are excluded from the programming and verification operations in the second loop. Similarly, those that passed the "B" level verification in the third loop are excluded from the programming and verification operations in the fourth loop. In other words, in the fourth loop, memory cell transistors MT whose threshold voltage ultimately reaches level "C" or higher, and memory cell transistors MT that failed verification in the previous loop, are the targets of the programming operation.

[0114] Similarly, in subsequent loops, after the program operation, verification operations at each predetermined level, as shown in Figure 7, are performed. Memory cell transistors MT whose threshold voltage has reached the final target level are excluded from the program operation and verification operation in subsequent loops.

[0115] As the loop repeats, the number of memory cell transistors MT whose threshold voltage reaches the final target level increases, and consequently, the number of memory cell transistors MT excluded from program operation and verification operation gradually increases. This is also reflected in Figure 11, where the number of levels labeled "1" increases and the number of levels labeled "0" decreases as the number of loop iterations increases.

[0116] In the example shown in Figure 10, the verification operation targeting level "A" is completed in the 6th loop. This is because, for example, from the previously obtained characteristics of the memory cell array 110, it is known that the writing of data to level "A" is almost completed after a total of 6 loops. Similarly, in the example shown in Figure 10, the verification operation targeting level "B" is completed in the 8th loop. This is because it is known that the writing of data to level "B" is almost completed after a total of 6 loops, from the 3rd to the 8th.

[0117] 1.9 Schematic Configuration of Plane Control Circuit and Row Decoder Next, we will describe the general configurations of the plane control circuit 44 and the row decoders 130 and 230. Since the configurations of the row decoders 130 and 230 are identical, we will only describe the configuration of row decoder 130 below, and omit the description of row decoder 230.

[0118] Figure 12 is a block diagram showing the schematic configuration of the plane control circuit 44. Figure 13 is a block diagram showing the schematic configuration of the low decoder 130.

[0119] The voltage supply circuit 43 shown in Figure 12 is controlled by the sequencer 41 and generates various voltages, including those necessary for writing, reading, and erasing operations on the memory cell transistor MT. The voltage supply circuit 43 selects an appropriate voltage from the generated voltages and supplies it to the signal lines GSG0-GSG4 and GCG0-GCG7, respectively.

[0120] The signal lines GSG0~GSG4 and GCG0~GCG7 branch into two at a point between the voltage supply circuit 43 and the plane control circuit 44. One branch of the signal lines GSG0~GSG4 and GCG0~GCG7 is connected to the signal lines SG0~SG4 and CG0~CG7, which correspond to plane PL0, via the plane control circuit 44. The other branch of the signal lines GSG0~GSG4 and GCG0~GCG7 is connected to the signal lines SG0~SG4 and CG0~CG7, which correspond to plane PL1, via the plane control circuit 44.

[0121] As shown in Figure 13, the signal lines SG0~SG4 and CG0~CG7 extending from the plane control circuit 44 to plane PL0 branch into multiple lines midway between the plane control circuit 44 and the row decoder 130. The branched signal lines SG0~SG4 and CG0~CG7 are connected via the row decoder 130 to the select gate lines SGD0~SGD3, select gate line SGS, and word lines WL0~WL7 of each block BLK of plane PL0. The same applies to plane PL1.

[0122] Thus, the signal lines GSG0~GSG4 and GCG0~GCG7 function as global signal lines for planes PL0 and PL1, and are connected to each plane PL0 and PL1 via the plane control circuit 44. Hereafter, the signal lines GSG0~GSG4 and GCG0~GCG7 will also be referred to as the "first global signal lines GSG0~GSG4 and GCG0~GCG7".

[0123] Furthermore, signal lines SG0~SG3 function as global drain-side select gate lines and are connected to select gate lines SGD0~SGD3 of each block BLK in planes PL0 and PL1 via row decoders 130 and 230. Signal lines CG0~CG7 function as global word lines and are connected to word lines WL0~WL7 of each block BLK in planes PL0 and PL1 via row decoders 130 and 230. Signal line SG4 functions as a global source-side select gate line and is connected to select gate line SGS of each block BLK in planes PL0 and PL1 via row decoders 130 and 230. Hereafter, signal lines SG0~SG4 and CG0~CG7 will also be referred to as "second global signal lines SG0~SG4 and CG0~CG7".

[0124] As shown in Figure 12, the plane control circuit 44 has a plurality of switch circuit groups 44a corresponding to each plane PL0, PL1, and a plurality of plane decoders 44b provided corresponding to each of the plurality of switch circuit groups 44a.

[0125] Each switch circuit group 44a includes multiple transistors TR_GSG0 to TR_GSG4 connected between the first global signal lines GSG0 to GSG4 and the second global signal lines SG0 to SG4. Furthermore, each switch circuit group 44a includes multiple transistors TR_GCG0 to TR_GCG7 connected between the first global signal lines GCG0 to GCG7 and the second global signal lines CG0 to CG7. Each of the transistors TR_GSG0 to TR_GSG4 and TR_GCG0 to TR_GCG7 is a high-voltage transistor.

[0126] Each plane decoder 44b supplies a "H (High)" level plane selection signal PLNSEL to the gates of transistors TR_GSG0~TR_GSG4 and TR_GCG0~TR_GCG7 based on instructions from the sequencer 41. In the switch circuit group 44a to which the "H" level plane selection signal PLNSEL is supplied from the plane decoder 44b, each of the transistors TR_GSG0~TR_GSG4 and TR_GCG0~TR_GCG7 turns on and conducts. As a result, the voltage generated by the voltage supply circuit 43 is supplied to the second global signal lines SG0~SG4 and CG0~CG7 via the first global signal lines GSG0~GSG4 and GCG0~GCG7. Consequently, the plane corresponding to the plane decoder 44b to which the "H" level plane selection signal PLNSEL is supplied becomes operational.

[0127] Meanwhile, each plane decoder 44b supplies an "L" level plane selection signal PLNSEL to the gates of transistors TR_GSG0~TR_GSG4 and TR_GCG0~TR_GCG7 based on instructions from the sequencer 41. In the switch circuit group 44a, to which the "L" level plane selection signal PLNSEL is supplied from the plane decoder 44b, each of the transistors TR_GSG0~TR_GSG4 and TR_GCG0~TR_GCG7 is turned off and becomes non-conductive. Therefore, the voltage generated by the voltage supply circuit 43 is not supplied to the second global signal lines SG0~SG4 and CG0~CG7 via the first global signal lines GSG0~GSG4 and GCG0~GCG7. Consequently, the plane corresponding to the plane decoder 44b to which the "L" level plane selection signal PLNSEL is supplied becomes inoperable.

[0128] In this way, the operating state of each plane PL0 and PL1 can be switched by the plane selection signal PLNSEL output from each plane decoder 44b. For example, if both plane decoders 44b corresponding to each plane PL0 and PL1 output a plane selection signal PLNSEL at the "H" level, both planes PL0 and PL1 will be operational. On the other hand, if, for example, the plane decoder 44b corresponding to plane PL0 outputs a plane selection signal PLNSEL at the "H" level, while the plane decoder 44b corresponding to plane PL1 outputs a plane selection signal PLNSEL at the "L" level, then plane PL0 will be operational, but plane PL1 will be inoperable.

[0129] As shown in Figure 13, the row decoder 130 has a plurality of switch circuit groups 130a corresponding to each block BLK of the plane PL0, and a plurality of block decoders 130b provided corresponding to each of the plurality of switch circuit groups 130a.

[0130] Each switch circuit group 130a includes multiple transistors TR_SG0 to TR_SG4 connected between the second global signal lines SG0 to SG4 and the select gate lines SGD0 to SGD4. Furthermore, each switch circuit group 130a includes multiple transistors TR_CG0 to TR_CG7 connected between the second global signal lines CG0 to CG7 and the word lines WL0 to WL7. Each of the transistors TR_SG0 to TR_SG4 and TR_CG0 to TR_CG7 is a high-voltage transistor.

[0131] Each block decoder 130b, when it is designated by a row address, supplies a "H" level block selection signal BLKSEL to the switch circuit group 130a. As a result, the "H" level block selection signal BLKSEL is supplied to the gates of the transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 included in the switch circuit group 130a, causing those transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 to turn on and conduct. Therefore, the voltage supplied from the first global signal lines GSG0~GSG4 and GCG0~GCG7 to the second global signal lines SG0~SG4 and CG0~CG7, in other words, the voltage generated by the voltage supply circuit 43, is supplied to the select gate lines SGD0~SGD3 and SGS and word lines WL0~WL7 included in the block BLK to be operated.

[0132] On the other hand, each block decoder 130b, if it is not designated by a low address, supplies an "L" level block selection signal BLKSEL to the switch circuit group 130a. As a result, the "L" level block selection signal BLKSEL is supplied to the gates of transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 included in the switch circuit group 130a, causing these transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 to turn off and become non-conductive. Therefore, the voltage supplied from the first global signal lines GSG0~GSG4 and GCG0~GCG7 to the second global signal lines SG0~SG4 and CG0~CG7, in other words, the voltage generated by the voltage supply circuit 43, is not supplied to the select gate lines SGD0~SGD3 and SGS and word lines WL0~WL7 included in the non-operating block BLK.

[0133] As a result, when performing a write operation on planes PL0 and PL1, for example, the plane control circuit 44 outputs a plane selection signal PLNSEL at the "H" level from the plane decoder 44b corresponding to plane PL0 and the plane decoder 44b corresponding to plane PL1. This causes the transistors TR_GSG0~TR_GSG4 and TR_GCG0~TR_GCG7 corresponding to each plane PL0 and PL1 in the plane control circuit 44 to turn on. Therefore, the voltage generated by the voltage supply circuit 43 is supplied to the second global signal lines SG0~SG4 and CG0~CG7 via the first global signal lines GSG0~GSG4 and GCG0~GCG7.

[0134] Furthermore, if, for example, a write operation is performed simultaneously on a predetermined page of block BLK(0) of plane PL0 and a predetermined page of block BLK(2) of plane PL1, the row decoders 130 and 230 corresponding to planes PL0 and PL1, respectively, will operate.

[0135] Specifically, in the row decoder 130 corresponding to plane PL0, the block decoder 130b corresponding to the selected block BLK(0) outputs a block selection signal BLKSEL at the "H" level. As a result, the transistors TR_SG0~TR_SG4 and TR_CG0~TR_CG7 corresponding to the selected block BLK(0) are turned on, and the voltage generated by the voltage supply circuit 43 is supplied to the select gate lines SGD0~SGD3, word lines WL0~WL7, and select gate line SGS of the selected block BLK(0) of plane PL0 via the first global signal lines GSG0~GSG4, GCG0~GCG7 and the second global signal lines SG0~SG4, CG0~CG7. This enables program operation and verification operation for a predetermined page in the selected block BLK(0) of plane PL0.

[0136] Furthermore, in the row decoder 130 corresponding to plane PL0, the block decoder 130b corresponding to the unselected blocks BLK(2) to BLK(n-1) outputs a "L" level block selection signal BLKSEL. As a result, the transistors TR_SG0 to TR_SG4 and TR_CG0 to TR_CG7 corresponding to the unselected blocks BLK(2) to BLK(n-1) are turned off, and the voltage generated by the voltage supply circuit 43 is not supplied to the select gate lines SGD0 to SGD3, word lines WL0 to WL7, and select gate line SGS of the unselected blocks BLK(2) to BLK(n-1) of plane PL0. Therefore, program operation and verification operation are not performed in the unselected blocks BLK(2) to BLK(n-1) of plane PL0.

[0137] On the other hand, in the row decoder 130 corresponding to plane PL1, the block decoder 130b for the selected block BLK(2) outputs a block selection signal BLKSEL at the "H" level. Also, in the row decoder 130 corresponding to plane PL1, the block decoders 130b corresponding to the unselected blocks BLK(0), BLK(1), BLK(3) to BLK(n-1), respectively, output a block selection signal BLKSEL at the "L" level. As a result, program and verification operations are performed for a predetermined page in the selected block BLK(2) of plane PL1, while program and verification operations are not performed for the unselected blocks BLK(0), BLK(1), BLK(3) to BLK(n-1) of plane PL1.

[0138] Incidentally, in such a semiconductor memory device 2, electrical leakage may occur in the word lines WL of the memory cell arrays 110 and 210 due to stress cycles associated with its use. For example, if word line WL4 included in block BLK(0) of plane PL0 is electrically short-circuited with word line WL3, electrical leakage will occur in word line WL4. In such a case, the voltage of word line WL4 will be affected by the voltage of word line WL3, which may lead to the detection of an abnormality in block BLK(0).

[0139] For example, when programming the memory cell transistor MT4 in block BLK(0), word line WL4 becomes the selected word line WLsel, and word line WL3 becomes the unselected word line WLusel. At this time, as shown in Figure 7, the program voltage VPGM is applied to the selected word line WL4, and the program path voltage VPASS_PGM is applied to the unselected word line WL3. In such a case, if the selected word line WL4 and the unselected word line WL3 are electrically short-circuited, the voltage of the selected word line WL4 will be pulled down by the voltage of the unselected word line WL3, causing the voltage of the unselected word line WL3 to become lower than the program voltage VPGM. Therefore, the program operation may not be performed properly. Similarly, during the verify operation, the voltage of the selected word line WL4 may be pulled down by the voltage of the unselected word line WL3, which may cause the verify operation to not be performed properly. If the program operation or verification operation is not performed properly in this manner, the number of times the verification operation fails will increase, causing the sequencer 41 to determine that the write operation to block BLK(0) of plane PL0 has failed. At this time, the sequencer 41 writes information that the write operation to block BLK(0) of plane PL0 has failed to the status register 42c. Based on the information written to this status register 42c, information that block BLK(0) of plane PL0 is a bad block is written to the ROM block of the memory cell array 210, and block BLK(0) of plane PL0 is excluded from subsequent operations.

[0140] On the other hand, in semiconductor memory device 2, there is a possibility that write operations may occur simultaneously on block BLK(0) of plane PL0 and block BLK(2) of plane PL1. In such a case, an electrical leak in the word line WL4 of block BLK(0) of plane PL0 may cause block BLK(2) of plane PL1 to be registered as a bad block, even though it is otherwise normal. Specifically, this is as follows:

[0141] Figure 14 schematically shows the circuit configuration of the semiconductor memory device 2. As shown in Figure 14, in the semiconductor memory device 2, when a write operation is performed simultaneously on block BLK(0) of plane PL0 and block BLK(2) of plane PL1, the word line WL4 of block BLK(0) of plane PL0 may be electrically connected to the word line WL4 of block BLK(2) of plane PL1 via the second global signal line CG4 corresponding to plane PL0, the first global signal line GCG4, and the second global signal line CG4 corresponding to plane PL1. Therefore, the voltage of the word line WL4 of block BLK(2) of plane PL1 is also affected by the electrical leakage in the word line WL4 of block BLK(0) of plane PL0 via the path indicated by the arrow in Figure 14. As a result, the program operation or verify operation of the memory cell transistor MT4 of block BLK(2) of plane PL1 may not be performed properly, and a fail judgment may be made during the verify operation. Furthermore, even if a fail determination is not made during the verification operation of the memory cell transistor MT4 in block BLK(2) of plane PL1, a fail determination may be made during the subsequent read operation of the same memory cell transistor MT4. In such a case, block BLK(2) of plane PL1 may be registered as a bad block in the ROM block of the memory cell array 210, even though it is a normal block.

[0142] As described above, in the semiconductor memory device 2, if an electrical leak occurs in the word line WL of either plane PL0 or PL1, it may cause not only one block BLK of either plane PL0 or PL1 to be determined as a bad block, but also cause the other block BLK of either plane PL0 or PL1, which was being written to at the same time, to be determined as a bad block due to tailgating. Since the block BLK that is determined as a bad block due to tailgating is actually a normal block, if that block can be used as a good block, it is possible to improve the block utilization efficiency of the semiconductor memory device 2.

[0143] Therefore, in the semiconductor memory device 2 of this embodiment, killer blocks, which are blocks where electrical leakage is occurring, and damaged blocks, which may be judged as bad blocks due to tailgating, are detected, and the detected blocks are re-registered as good blocks, thereby enabling the reuse of blocks that may be judged as bad blocks due to tailgating.

[0144] 1.10 Configuration of the Judgment Circuit Next, we will describe the configuration of a detection circuit capable of determining killer blocks and damaged blocks.

[0145] Figure 15 is a block diagram showing the internal configuration of the voltage supply circuit 43. As shown in Figure 15, the voltage supply circuit 43 comprises a voltage generation circuit 430, a multiplexer 431, and a determination circuit 432. Note that Figure 15 only shows the configuration in which the voltage supply circuit 43 applies voltage to the first global signal lines GCG0 to GCG7, and the configuration for applying voltage to the other first global signal lines GSG0 to GSG4 is omitted.

[0146] The voltage generation circuit 430 includes a first voltage generation unit 430a, a second voltage generation unit 430b, and a third voltage generation unit 430c. The first voltage generation unit 430a generates the program voltage VPGM, which is applied to the selected word line WLsel during a write operation. The second voltage generation unit 430b generates the program path voltage VPASS_PGM, which is applied to the unselected word line WLusel during a write operation, and the voltage VPASS_READ, which is applied to the unselected word line WLusel during a read operation. The third voltage generation unit 430c generates the read voltage VCGRV, which is applied to the selected word line WLsel during a read operation.

[0147] Within the multiplexer 431, a first voltage generation unit 430a is connected to the first global signal lines GCG0 to GCG7 via multiple signal lines SVA0 to SVA7. A second voltage generation unit 430b is connected to the first global signal lines GCG0 to GCG7 via multiple signal lines SVB0 to SVB7. Furthermore, a third voltage generation unit 430c is connected to the first global signal lines GCG0 to GCG7 via multiple signal lines SVC0 to SVC7. The multiplexer 431 includes transistors TR_SVA0 to TR_SVA7, TR_SVB0 to TR_SVB7, and TR_SVC0 to TR_SVC7. Transistors TR_SVA0 to TR_SVA7 are located along the SVA0 to SVA7 signal lines, respectively. Transistors TR_SVB0 to TR_SVB7 are located along the SVB0 to SVB7 signal lines, respectively. Transistors TR_SVC0 to TR_SVC7 are each located in the middle of multiple signal lines SVC0 to SVC7. The operation of transistors TR_SVA0 to TR_SVA7, TR_SVB0 to TR_SVB7, and TR_SVC0 to TR_SVC7 is controlled by sequencer 41.

[0148] The multiplexer 431 selectively applies the voltages generated by the voltage generation units 430a, 430b, and 430c to the first global signal lines GCG0 to GCG7 by switching the on / off states of the transistors TR_SVA0 to TR_SVA7, TR_SVB0 to TR_SVB7, and TR_SVC0 to TR_SVC7, respectively.

[0149] For example, during a write operation, if word line WL4 is the selected word line WLsel, the multiplexer 431 applies the program voltage VPGM to the first global signal line GCG4 connected to the selected word line WL4 by turning on transistor TR_SVA4 and turning off transistors TR_SVB4 and TR_SVC4. The multiplexer 431 also applies the program path voltage VPASS_PGM to the other first global signal lines GCG0 to GCG3 and GCG5 to GCG7 connected to the unselected word lines WL0 to WL3 and WL5 to WL7 by turning on transistors TR_SVB0 to TR_SVB3 and TR_SVB5 to TR_SVB7 and turning off transistors TR_SVA1 to TR_SVA3, TR_SVA5 to TR_SVA7, TR_SVC1 to TR_SVC3, and TR_SVC5 to TR_SVC7.

[0150] Furthermore, in the read operation, if word line WL4 is the selected word line WLsel, the multiplexer 431 applies the read voltage VCGRV to the first global signal line GCG4 connected to the selected word line WL4 by turning on transistor TR_SVC4 and turning off transistors TR_SVA4 and TR_SVB4. Also, the multiplexer 431 applies the read path voltage VPASS_READ to the other first global signal lines GCG0~GCG3 and GCG5~GCG7 connected to the unselected word lines WL0~WL3 and WL5~WL7 by turning on transistors TR_SVB0~TR_SVB3 and TR_SVB5~TR_SVB7 and turning off transistors TR_SVA0~TR_SVA3, TR_SVA5~TR_SVA7, TR_SVC0~TR_SVC3, and TR_SVC5~TR_SVC7.

[0151] The determination circuit 432 includes a comparison circuit 432a and transistors TR_SVD0 to TR_SVD7.

[0152] The non-inverting input terminal of the comparator circuit 432a is connected to the first global signal lines GCG0 to GCG7 via signal lines SVD0 to SVD7. Transistors TR_SVD0 to TR_SVD7 are located in the middle of each of the signal lines SVD0 to SVD7. The operation of each of the transistors TR_SVD0 to TR_SVD7 is controlled by the sequencer 41. When write, read, or erase operations are being performed, transistors TR_SVD0 to TR_SVD7 are turned off. A determination voltage VCGRV2 is applied to the inverting input terminal of the comparator circuit 432a. The determination voltage VCGRV2 is a voltage generated by the voltage generation circuit 430, and is a voltage generated by stepping down the read voltage VCGRV, i.e., a voltage less than or equal to the read voltage VCGRV. The operation of each of the transistors TR_SVD0 to TR_SVD7 is controlled by the sequencer 41.

[0153] The comparison circuit 432a outputs an output signal FLAG according to the comparison result by comparing the voltage applied to any of the first global signal lines GCG0 to GCG7 with the determination voltage VCGRV2. For example, if the voltage applied to the first global signal line GCG0 is to be determined, the sequencer 41 turns on transistor TR_SVD0 and turns off the other transistors TR_SVD1 to TR_SVD7. As a result, the voltage of the first global signal line GCG0 is applied to the non-inverting input terminal of the comparison circuit 432a. In this case, if the voltage of the first global signal line GCG0 is higher than the determination voltage VCGRV2, the comparison circuit 432a outputs a "L" level signal. Also, if the voltage of the first global signal line GCG0 is less than or equal to the determination voltage VCGRV2, the comparison circuit 432a outputs a "H" level signal.

[0154] 1.11 Example of Memory System Operation Next, an example of the operation of the memory system 3 of this embodiment will be described. First, a method for detecting killer blocks and damaged blocks using the determination circuit 432 shown in Figure 15 will be described.

[0155] Figure 16 shows an example of the procedure for detecting killer blocks and damaged blocks performed by the sequencer 41. The following explanation will use the case where a write operation is performed simultaneously on block BLK(0) of plane PL0 and block BLK(2) of plane PL1 as an example.

[0156] As shown in Figure 16, the sequencer 41 first determines whether or not it is time to perform a leak check (step S10). The timing for performing the leak check is, for example, the time when data writing to a predetermined memory cell transistor is completed in block BLK(0) of plane PL0 and block BLK(2) of plane PL1. Specifically, for example, if data writing to a predetermined memory cell transistor starts at time t10 as shown in Figure 9, and the verification operation using the verify voltage VfyG is completed at time t11, the sequencer 41 determines that it is time to perform a leak check at time t11. In the following explanation, the case where the predetermined memory cell transistor is MT4, that is, where the word line WL4 is the selected word line WLsel, will be used as an example.

[0157] If the sequencer 41 determines that it is time to perform a leak detection (step S10: YES), it connects one of the planes PL0 or PL1 to the first global signal line CGC4 (step S11). First, the sequencer 41 connects, for example, plane PL0 to the first global signal line CGC4 and disconnects the connection between plane PL1 and the first global signal line CGC4. Specifically, in the plane control circuit 44 shown in Figure 12, the sequencer 41 outputs a plane selection signal PLNSEL at the "H" level from the plane decoder 44b corresponding to plane PL0, and also outputs a plane selection signal PLNSEL at the "L" level from the plane decoder 44b corresponding to plane PL1. As a result, the transistors TR_GCG0 to TR_GCG7 corresponding to plane PL0 are turned on, and plane PL0 is connected to the first global signal line GCG4. Furthermore, because transistors TR_GCG0 to TR_GCG7 corresponding to plane PL1 are turned off, the connection between plane PL1 and the first global signal line GCG4 is broken. As a result, as shown in Figure 17, the selection word line WL4 of plane PL0 is connected to the first global signal line GCG4, while the selection word line WL4 of plane PL1 is not connected to the first global signal line GCG4.

[0158] Next, the sequencer 41 applies the voltage VCGRV generated by the third voltage generation unit 430c to the first global signal line GCG4 corresponding to the selection word line WL4 of plane PL0 (step S12). Specifically, in the voltage supply circuit 43 shown in Figure 15, the sequencer 41 turns on transistor TR_SVC4 and turns off transistors TR_SVA4 and TR_SVB4 in order to apply the voltage VCGRV to the first global signal line GCG4 corresponding to the selection word line WL4. As a result, as shown in Figure 17, the voltage VCGRV generated by the third voltage generation unit 430c is applied to the selection word line WL4 of block BLK(0) of plane PL0 via the first global signal line GCG4 and the second global signal line CG4 corresponding to plane PL0. In Figure 9, the time t12 is shown when the voltage VCGRV is applied to the selection word line WL4 of block BLK(0) of plane PL0.

[0159] Furthermore, the voltage Vss is applied to the other first global signal lines GCG0~GCG3 and GCG5~GCG7 by the voltage supply circuit 43. Therefore, the voltage Vss is applied to the unselected word lines WL0~WL3 and WL5~WL7 of block BLK(0) of plane PL0.

[0160] Next, as shown in Figure 16, the sequencer 41 puts the first global signal line GCG4, which corresponds to the selection word line WL4 of plane PL0, into a floating state (step S13). Specifically, in the plane control circuit 44 shown in Figure 12, the sequencer 41 causes the plane decoder 44b corresponding to plane PL0 to output a plane selection signal PLNSEL at the "L" level. As a result, the transistors TR_GCG0~TR_GCG7 corresponding to plane PL0 switch from the on state to the off state, and the first global signal line GCG4 becomes floating, as shown in Figure 18.

[0161] Next, as shown in Figure 16, the sequencer 41 determines whether a predetermined time Ta has elapsed since the first global signal line GCG4 was put into a floating state (step S14). If the predetermined time Ta has elapsed (step S14: YES), the sequencer 41 inputs the voltage of the first global signal line GCG4 to the determination circuit 432 shown in Figure 15 (step S15). Specifically, the sequencer 41 turns on transistor TR_SVD4 while keeping transistors TR_SVD0~TR_SVD3, TR_SVD5~TR_SVD7 shown in Figure 15 in the off state. As a result, the voltage of the first global signal line GCG4 is input to the non-inverting input terminal of the comparison circuit 432a of the determination circuit 432.

[0162] Next, as shown in Figure 16, the sequencer 41 acquires the output signal FLAG of the determination circuit 432 shown in Figure 15 (step S16). At this time, as shown in Figure 18, if a leak occurs in the selected word line WL4 of block BLK(0) of plane PL0, for example, if a leak occurs between the selected word line WL4 and the unselected word line WL3, the voltage of the selected word line WL4 discharges toward the unselected word line WL3 to which the voltage Vss is applied. Therefore, as shown in Figure 19(A), after the first global signal line GCG4 becomes floating at time t20, the voltage of the selected word line WL4 gradually decreases from VCGRV. At this time, the voltage of the first global signal line GCG4 also decreases, pulled down by the voltage of the selected word line WL4, based on the path shown by the arrow in Figure 18. Therefore, as shown in Figure 19(B), the voltage of the first global signal line GCG4 also gradually decreases from VCGRV after time t20. As a result, at time t21, the voltage of the first global signal line GCG4 becomes smaller than the determination voltage VCGRV2, so the output signal FLAG of the comparison circuit 432a changes from "L" level to "H" level, as shown in Figure 19(C). Therefore, when the sequencer 41 acquires the output signal FLAG of the determination circuit 432 at time t22, after a predetermined time Ta has elapsed from time t20, the output signal FLAG shows an "H" level. The sequencer 41 stores the correspondence between the acquired output signal FLAG and block BLK(0) of plane PL0 in an internal register (not shown) within the sequencer 41.

[0163] Next, as shown in Figure 16, the sequencer 41 determines whether or not the leak detection for all planes PL0 and PL1 has been completed (step S17). If the leak detection for plane PL1 has not been performed (step S17: NO), the sequencer 41 returns to step S11 and performs the same processing as in steps S11 to S16 for plane PL1. At this time, as a result of the processing in steps S11 and S12, as shown in Figure 20, the voltage VCGRV generated by the third voltage generation unit 430c is applied to the selection word line WL4 of block BLK(2) of plane PL1 via the first global signal line GCG4 and the second global signal line CG4 corresponding to plane PL1. In Figure 9, the time at t13 is shown when the voltage VCGRV is applied to the selection word line WL4 of block BLK(2) of plane PL1. Also, as a result of the processing in step S13 shown in Figure 16, as shown in Figure 21, the first global signal line GCG4 becomes floating. At this time, for example, if no leakage occurs in the word line WL4 of block BLK(2) of plane PL1, the processes S14 to S16 shown in Figure 16 are executed, and the voltage of the selected word line WL4 of block BLK(2) of plane PL1, the voltage of the first global signal line GCG4, and the output signal FLAG of the determination circuit 432 change as shown in Figures 22(A) to (C). In Figures 22(A) to (C), the transition after the first global signal line GCG4 becomes floating at time t20 is shown by the dashed line.

[0164] As shown in Figures 22(A) to (C), even after the first global signal line GCG4 enters a floating state at time t20, the voltage of the first global signal line GCG4 is maintained at VCGRV. Therefore, since the voltage of the first global signal line GCG4 remains greater than the determination voltage VCGRV2, the output signal FLAG of the comparator circuit 432a remains at the "L" level. Consequently, when the sequencer 41 acquires the output signal FLAG of the determination circuit 432 at time t22, after a predetermined time Ta has elapsed from time t20, the output signal FLAG shows the "L" level. The sequencer 41 stores the correspondence between the acquired output signal FLAG and block BLK(2) of plane PL1 in an internal register (not shown) within the sequencer 41.

[0165] Once leak detection is performed for each of the planes PL0 and PL1 in this manner, the sequencer 41 determines in step S17 shown in Figure 16 that leak detection has been performed for all of the planes PL0 and PL1 (step S17: YES). Based on this, the sequencer 41 determines whether or not a leak has been detected in one or more blocks based on the correspondence between the respective blocks BLK(0) and BLK(2) of planes PL0 and PL1 and the output signal FLAG of the detection circuit 432 (step S18).

[0166] As described above, if the output signal FLAG corresponding to block BLK(2) of plane PL1 is at the "L" level, the PLC 41 determines that there is no leak in block BLK(2) of plane PL1. On the other hand, if the output signal FLAG corresponding to block BLK(0) of plane PL0 is at the "H" level, the PLC 41 determines that there is a leak in block BLK(0) of plane PL0. Therefore, the PLC 41 determines that a leak has been detected in one or more blocks (step S18: YES). In this case, the PLC 41 performs a bad block process for block BLK(0) of plane PL0, which was determined to have a leak (step S19), and performs a status fail process for block BLK(2) of plane PL1, which was determined not to have a leak (step S20).

[0167] Specifically, as part of the bad block processing in step S19, the sequencer 41 stores in the status register 42c information that block BLK(0) of plane PL0, which has been determined to have a leak, is a bad block. Also, as part of the status fail processing in step S20, the sequencer 41 stores in the status register 42c information that block BLK(2) of plane PL1, which has been determined not to have a leak, is a damaged block.

[0168] When this information is stored in the status register 42c, it is stored in the ROM blocks of the memory cell arrays 110 and 210 of planes PL0 and PL1, respectively. As a result, the memory controller 1 obtains information that block BLK(0) of plane PL0 is a bad block by reading data from the ROM block of memory cell array 110, for example, when performing a power-on read operation. As a result, the memory controller 1 excludes block BLK(0) of plane PL0 from subsequent operations.

[0169] On the other hand, the memory controller 1 obtains information that block BLK(2) of plane PL1 is a damaged block by reading data from the ROM block of the memory cell array 210, for example, when performing a power-on read operation. In this case, the memory controller 1 performs a process as shown in Figure 23, for example.

[0170] As shown in Figure 23, the memory controller 1 determines whether or not there is a block registered as a damaged block (step S30), and if there is a block registered as a damaged block (step S30: YES), it performs an erase operation on the block registered as a damaged block (step S31). Therefore, if block BLK(2) of plane PL1 is a damaged block as described above, an erase operation is performed on block BLK(2) of plane PL1.

[0171] Next, the memory controller 1 registers block BLK(2) of plane PL1, which has been erased, as a good block (step S32). Specifically, the memory controller 1 registers information that block BLK(2) is a good block in the ROM block of the memory cell array 210 of plane PL1.

[0172] In the explanation of the process shown in Figure 16 above, the example given is when a write operation is performed simultaneously on the memory cell transistor MT4 of block BLK(0) of plane PL0 and the memory cell transistor MT4 of block BLK(2) of plane PL1. However, the process shown in Figure 16 is also executed similarly when a write operation is performed simultaneously on the other memory cell transistor MT of block BLK(0) of plane PL0 and the other memory cell transistor MT of block BLK(2) of plane PL1. Furthermore, the process shown in Figure 16 is also executed similarly when a write operation is performed simultaneously on the other block BLK of plane PL0 and the other block BLK of plane PL1.

[0173] 1.12 Function and Effects of Semiconductor Memory Devices As described above, the semiconductor memory device 2 of this embodiment comprises a plane PL0 (first plane), a plane PL1 (second plane), first global signal lines GCG0 to GCG7, a determination circuit 432, and a sequencer 41 (control unit). Planes PL0 and PL1 comprise a plurality of blocks BLK, which are collections of a plurality of memory cell transistors MT. The first global signal lines GCG0 to GCG7 apply voltage to word lines WL0 to WL7 (first word lines) connected to the gates of the memory cell transistors MT (first memory cell transistors) included in the block BLK (first block) of plane PL0, and to word lines WL0 to WL7 (second word lines) connected to the gates of the memory cell transistors MT (second memory cell transistors) included in the block BLK (second block) of plane PL1. The determination circuit 432 determines whether or not leakage occurs in the word lines WL0 to WL7 of the block BLK of plane PL0 and the word lines WL0 to WL7 of the block BLK of plane PL1, based on the voltages of the first global signal lines GCG0 to GCG7. The sequencer 41 controls planes PL0 and PL1. When the determination result of the determination circuit 432 indicates, for example, that leakage has occurred in the word line WL4 of block BLK(0) of plane PL0, and that there is no leakage in the word line WL4 of block BLK(2) of plane PL1, the sequencer 41 registers block BLK(0) of plane PL0 as a bad block and registers block BLK(2) of plane PL1 as a damaged block that can be used as a good block.

[0174] With this configuration, block BLK(2) of plane PL1, which may be determined to be a bad block due to tailgating with block BLK(0) of plane PL0, can be used as a good block. Therefore, the block efficiency of the semiconductor memory device 2 can be improved.

[0175] The semiconductor memory device 2 further comprises transistors TR_GCG0~TR_GCG7 (first switching elements) corresponding to plane PL0, transistors TR_GCG0~TR_GCG7 (second switching elements) corresponding to plane PL1, a voltage generation unit 430c (voltage generation circuit), and transistors TR_SVC0~TR_SVC7 (third switching elements). Transistors TR_GCG0~TR_GCG7 corresponding to plane PL0 are provided between the first global signal lines GCG0~GCG7 and plane PL0. Transistors TR_GCG0~TR_GCG7 corresponding to plane PL1 are provided between the first global signal lines GCG0~GCG7 and plane PL1. The voltage generation unit 430c applies a voltage to the first global signal lines GCG0~GCG7. Transistors TR_SVC0~TR_SVC7 are provided between the first global signal lines GCG0~GCG7 and the voltage generation unit 430c. The determination circuit 432, for example, applies a predetermined voltage VCGRV from the voltage generation unit 430c to the first global signal line GCG4, then turns on the transistor TR_GCG4 corresponding to plane PL0 to connect the first global signal line GCG4 to the word line WL4 of block BLK(0) of plane PL0, and then turns off the transistors TR_GCG4 and TR_SVC4 corresponding to plane PL1 to electrically float the first global signal line GCG4, and then determines whether or not a leak has occurred in the word line WL4 of block BLK(0) of plane PL0 based on the voltage (first voltage) that the first global signal line GCG4 has.The determination circuit 432, for example, applies a predetermined voltage VCGRV to the first global signal line GCG4 from the voltage generation unit 430c, then turns on the transistor TR_GCG4 corresponding to plane PL1 to connect the first global signal line GCG4 to the word line WL4 of block BLK(2) of plane PL1, and then turns off the transistors TR_GCG4 and TR_SVC4 corresponding to plane PL1 to electrically float the first global signal line GCG4, and then determines whether or not a leak has occurred in the word line WL4 of block BLK(2) of plane PL1 based on the voltage (second voltage) that the first global signal line GCG4 has.

[0176] This configuration makes it easy to determine whether or not a leak is occurring in the word line WL4 of block BLK(0) of plane PL0 and in the word line WL4 of block BLK(2) of plane PL1.

[0177] The determination circuit 432 has a comparison circuit 432a. The comparison circuit 432a compares the voltages of the first global signal lines GCG0 to GCG7 with a predetermined determination voltage VCGRV2 and outputs a signal FLAG indicating the comparison result. For example, when the first global signal line GCG4 is connected to the word line WL4 of block BLK(0) of plane PL0 and the first global signal line GCG4 is electrically floating, the comparison circuit 432a compares the voltage of the first global signal line GCG4 (first voltage) with the determination voltage VCGRV2 and outputs a signal FLAG indicating whether or not leakage is occurring in the word line WL4 (first word line) of block BLK(0) of plane PL0. The comparison circuit 432a outputs a signal FLAG indicating whether or not leakage is occurring in the word line WL4 (second word line) of block BLK(2) of plane PL1 by, for example, connecting the first global signal line GCG4 to the word line WL4 of block BLK(2) of plane PL1 and making the first global signal line GCG4 electrically floating, and comparing the voltage of the first global signal line GCG4 (second voltage) with the determination voltage VCGRV2.

[0178] With this configuration, the determination circuit 432 will appropriately output a signal FLAG indicating whether or not leakage is occurring in the word lines WL0 to WL7 of the block BLK of each plane PL0 and PL1.

[0179] The semiconductor memory device 2 further includes transistors TR_SVD0~TR_SVD7 (fourth switching elements) provided between the comparison circuit 432a and the first global signal lines GCG0~GCG7. The sequencer 41 turns off transistors TR_SVD0~TR_SVD7 when the determination circuit 432 has not determined whether or not leakage is occurring in the word lines WL0~WL7 of each block BLK of plane PL0 and the word lines WL0~WL7 of each block BLK of plane PL1. The sequencer 41 turns on transistors TR_SVD0~TR_SVD7 when the determination circuit 432 has determined whether or not leakage is occurring in the word lines WL0~WL7 of each block BLK of plane PL0 or the word lines WL0~WL7 of each block BLK of plane PL1.

[0180] This configuration makes it possible to suppress current leakage from the first global signal lines GCG0 to GCG7 to the comparator circuit 432a when it is not being determined whether or not a leak is occurring.

[0181] After the sequencer 41 performs a write operation on, for example, the memory cell transistor MT4 (first memory cell transistor) of block BLK(0) of plane PL0 and the memory cell transistor MT4 (second memory cell transistor) of block BLK(1) of plane PL1, the determination circuit 432 performs a leakage detection process.

[0182] This configuration allows for more accurate leak detection.

[0183] When, for example, block BLK(2) of plane PL1 is registered as a damaged block, the memory controller 1 performs an erase operation on block BLK(2) of plane PL1 and then registers block BLK(2) as a good block.

[0184] With this configuration, even if the status of block BLK(2) of plane PL1, which is a good block, temporarily goes into a fail state, it becomes possible to use that block BLK(2) again.

[0185] 2 Other Embodiments This disclosure is not limited to the specific examples given above.

[0186] For example, the timing of the leak detection used in the process of step S10 shown in Figure 16 can be changed as appropriate. The timing of the leak detection may be, for example, a time when the semiconductor memory device 2 is idle, or a time when the semiconductor memory device 2 is not performing any write, read, or erase operations.

[0187] The number of planes in the semiconductor memory device 2 is not limited to two, but can be arbitrarily changed.

[0188] The structure of the semiconductor memory device 2 is not limited to the structure shown in Figure 5 and can be modified as appropriate. For example, the semiconductor memory device 2 may have a CBA (CMOS Bonding Array) structure as shown in Figure 24. In the semiconductor memory device 2 shown in Figure 24, the memory section 80, which is provided with the memory cell array 110, and the control circuit section 90, which is provided with the peripheral circuit PER, are manufactured separately. This semiconductor memory device 2 is constructed by bonding the separately manufactured memory section 80 and control circuit section 90 together on a bonding surface B1. The memory cell array 110 and the peripheral circuit PER are electrically connected to each other via wiring layers 800, 801 and vias 810, 811 provided on the bonding surface B1.

[0189] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the claims of the invention and its equivalents. [Explanation of Symbols]

[0190] GCG0~GCG7: First global signal lines, MT: Memory cell transistor, PL0: Plane (first plane), PL1: Plane (second plane), TR_SVC0~TR_SVC7: Transistor (third switching element), TR_SVD0~TR_SVD7: Transistor (fourth switching element), 2: Semiconductor memory device, 41: Sequencer (control unit), 430c: Voltage generation unit (voltage generation circuit), 432: Decision circuit, 432a: Comparison circuit, TR_GCG0~TR_GCG7 corresponding to plane PL0: Transistor (first switching element), BLK of plane PL0: Block (first block), WL0~WL7 of plane PL0: Word lines (first word lines), TR_GCG0~TR_GCG7 corresponding to plane PL1: Transistor (second switching element), BLK of plane PL1: Block (second block), WL0~WL7 of plane PL1: Word lines (second word lines).

Claims

1. A first plane and a second plane each have multiple blocks, which are collections of multiple memory cell transistors, A signal line that applies voltage to a first word line connected to the gate of a first memory cell transistor included in the first block of the first plane, and to a second word line connected to the gate of a second memory cell transistor included in the second block of the second plane, A determination circuit that determines whether or not leakage is occurring in the first word line and the second word line based on the voltage of the signal line, The system comprises a control unit that controls the first plane and the second plane, When the determination result of the determination circuit indicates that a leak has occurred in the first word line and that no leak has occurred in the second word line, the control unit registers the first block as a bad block and registers the second block as a damaged block that can be used as a good block. Semiconductor memory device.

2. A first switching element is provided between the signal line and the first plane, A second switching element is provided between the signal line and the second plane, A voltage generation circuit that applies voltage to the signal line, The system further comprises a third switching element provided between the signal line and the voltage generation circuit, The aforementioned determination circuit is After applying a predetermined voltage to the signal line from the voltage generation circuit, the signal line is connected to the first word line by turning on the first switching element, and the signal line is electrically floated by turning off the second and third switching elements. Based on the first voltage present in the signal line, it is determined whether or not leakage occurs in the first word line. After applying the predetermined voltage to the signal line from the voltage generation circuit, the signal line is connected to the gate of the second memory cell transistor by turning on the second switching element, and the signal line is electrically floated by turning off the first and third switching elements. Based on the second voltage present in the signal line, it is determined whether or not leakage is occurring in the second word line. The semiconductor memory device according to claim 1.

3. The determination circuit includes a comparison circuit that compares the voltage of the signal line with a predetermined determination voltage and outputs a signal indicating the comparison result. The aforementioned comparison circuit is By comparing the first voltage of the signal line with the determination voltage, a signal is output indicating whether or not leakage is occurring in the first word line. By comparing the second voltage of the signal line with the determination voltage, a signal is output indicating whether or not leakage is occurring in the second word line. The semiconductor memory device according to claim 2.

4. The determination voltage is a voltage less than or equal to the predetermined voltage. The semiconductor memory device according to claim 3.

5. The circuit further comprises a fourth switching element provided between the comparison circuit and the signal line. The semiconductor memory device according to claim 3.

6. The control unit, If the determination circuit has not determined whether or not leakage is occurring in the first word line and the second word line, the fourth switching element is turned off. When the determination circuit determines whether or not a leak has occurred in the first word line or the second word line, the fourth switching element is turned on. The semiconductor memory device according to claim 5.

7. After the control unit has performed a write operation on the first memory cell transistor and the second memory cell transistor, the determination circuit performs a determination process to determine whether or not leakage has occurred in the first word line and the second word line. The semiconductor memory device according to claim 1.

8. A semiconductor memory device including a first plane and a second plane, each having multiple blocks which are collections of multiple memory cell transistors, The system includes a memory controller for controlling the aforementioned semiconductor storage device, The aforementioned semiconductor memory device is A signal line that applies voltage to a first word line connected to the gate of a first memory cell transistor included in the first block of the first plane, and to a second word line connected to the gate of a second memory cell transistor included in the second block of the second plane, A determination circuit that determines whether or not leakage is occurring in the first word line and the second word line based on the voltage of the signal line, The control unit, when the determination result of the determination circuit indicates that a leak has occurred in the first word line and that no leak has occurred in the second word line, registers the first block as a bad block and registers the second block as a damaged block that can be used as a good block, When the second block is registered as the damaged block, the memory controller performs an erase operation on the second block and then registers the second block as a good block. Memory system.

9. A first plane and a second plane each have multiple blocks, which are collections of multiple memory cell transistors, A signal line that applies voltage to a first word line connected to the gate of a first memory cell transistor included in the first block of the first plane, and to a second word line connected to the gate of a second memory cell transistor included in the second block of the second plane, A determination circuit that determines whether or not leakage is occurring in the first word line and the second word line based on the voltage of the signal line, A control method for a semiconductor memory device comprising a control unit for controlling the first plane and the second plane, When the determination result of the determination circuit indicates that a leak has occurred in the first word line and that no leak has occurred in the second word line, the control unit registers the first block as a bad block and the second block as a damaged block. A method for controlling semiconductor memory devices.

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