memory devices

Abstract

To reduce the manufacturing cost of memory devices. [Solution] The memory device 1 includes a substrate W1, a first circuit layer 100, and a second circuit layer 200. The substrate has a first region AA and a second region PR. The second circuit layer includes a laminate containing a first insulator layer 26 and a first conductor layer 31 alternately stacked in a second direction within the first region, a plurality of first pillars MP penetrating the laminate in a second direction within the first region and electrically connected to a source line SL above the laminate, and at least one first contact C3 having a portion provided at the same height as the laminate within the second region. The source line includes a second conductor layer 51 having a portion provided covering the upper part of each of the plurality of first pillars within the first region and a portion provided covering the upper part of at least one first contact within the second region. The surface of the second conductor layer is provided in a non-planar manner above at least one of the plurality of first pillars and at least one first contact.

Description

Technical Field

[0001] The embodiments relate to a memory device.

Background Art

[0002] A NAND type flash memory capable of storing data non-volatilely is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress the manufacturing cost of the memory device.

Means for Solving the Problems

[0005] The memory device of the embodiment has a bonding surface. The memory device includes a substrate, a first circuit layer, and a second circuit layer. The substrate has a first region and a second region aligned in a first direction. The first circuit layer is provided between the substrate and the bonding surface and includes a CMOS circuit. The second circuit layer is provided above the bonding surface. The second circuit layer has a memory cell array that includes a laminate containing first insulating layers and first conductive layers alternately stacked in a second direction intersecting the first direction within the first region, and a plurality of first pillars that penetrate the laminate in a second direction and are electrically connected to a source line above the laminate. Within the second region, it includes at least one first contact that has a portion provided at the same height as the laminate and is electrically connected to the CMOS circuit. The source line includes a second conductive layer that has a portion provided in the first region covering the upper part of each of the plurality of first pillars included in the memory cell array, and a portion provided in the second region covering the upper part of the at least one first contact. The second conductive layer electrically connects the plurality of first pillars to at least one first contact. The surface of the second conductive layer is non-planar above at least one of the plurality of first pillars and at least one first contact. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example of the overall configuration of a memory system equipped with a memory device according to the first embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the first embodiment. [Figure 3] A perspective view showing an example of the appearance of a memory device according to the first embodiment. [Figure 4] A plan view showing an example of a planar layout of a memory device according to the first embodiment. [Figure 5] A plan view showing an example of a planar layout in the core region of a memory cell array in a memory device according to the first embodiment. [Figure 6]A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure in the storage area of ​​a memory cell array in a memory device according to the first embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar in a memory device according to the first embodiment. [Figure 8] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the first embodiment. [Figure 9] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the first embodiment. [Figure 10] A plan view showing an example of the arrangement of bonding pads in a memory device according to the first embodiment. [Figure 11] A cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bonding pads in a memory device according to the first embodiment. [Figure 12] A plan view showing an example of a planar layout of semiconductor layers in a memory device according to the first embodiment. [Figure 13] A plan view showing an example of a planar layout of the conductive layer in a memory device according to the first embodiment. [Figure 14] A plan view showing an example of a planar layout near the pad portion in a memory device according to the first embodiment. [Figure 15] A cross-sectional view along the line XV-XV in Figure 14, showing an example of the cross-sectional structure near the pad portion in the memory device according to the first embodiment. [Figure 16] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory cell array provided in a memory device according to the first embodiment. [Figure 17] A flowchart showing an example of a method for manufacturing a memory device according to the first embodiment. [Figure 18] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the first embodiment. [Figure 19] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the first embodiment. [Figure 20]Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 21] Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 22] Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 23] Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 24] Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 25] Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 26] Cross-sectional view showing an example of the cross-sectional structure in the manufacturing process of the memory device according to the first embodiment. [Figure 27] Planar view showing an example of the planar layout of the memory device according to the comparative example of the first embodiment. [Figure 28] Cross-sectional view showing an example of the cross-sectional structure of the memory device according to the comparative example of the first embodiment. [Figure 29] Planar view showing an example of the planar layout of the memory device according to the first embodiment. [Figure 30] Planar view showing an example of the planar layout of the conductor layer in the memory device according to the second embodiment. [Figure 31] Cross-sectional view showing an example of the cross-sectional structure of the memory device according to the second embodiment. [Figure 32] Planar view showing an example of the planar layout in the vicinity of the pad portion in the memory device according to the third embodiment. [Figure 33] Cross-sectional view taken along line XXXIII-XXXIII of FIG. 32, showing an example of the cross-sectional structure in the vicinity of the pad portion in the memory device according to the third embodiment. [Figure 34] Cross-sectional view showing an example of the cross-sectional structure of the memory device according to the fourth embodiment. [Figure 35]A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the fourth embodiment. [Figure 36] A flowchart showing an example of a method for manufacturing a memory device according to the fourth embodiment. [Figure 37] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 38] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 39] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 40] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 41] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 42] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 43] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fourth embodiment. [Figure 44] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the fifth embodiment. [Figure 45] A plan view showing an example of a planar layout of the conductive layer in a memory device according to the fifth embodiment. [Figure 46] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fifth embodiment. [Figure 47] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fifth embodiment. [Figure 48] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fifth embodiment. [Figure 49] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fifth embodiment. [Figure 50] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fifth embodiment. [Figure 51] A cross-sectional view showing an example of a cross-sectional structure in the manufacturing process of a memory device according to the fifth embodiment. [Figure 52] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to a comparative example of the fifth embodiment. [Modes for carrying out the invention]

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and proportions in each drawing are not necessarily the same as those in reality. The illustration of the components is omitted where appropriate. Hatching added to the plan views is not necessarily related to the material or properties of the components. In this specification, components having substantially the same function and configuration are assigned the same reference numeral. Numbers and letters added to reference numerals are used to distinguish between elements that are referred to by the same reference numeral and are similar to each other.

[0008] <1> First Embodiment The memory device according to the first embodiment has a junction structure in which a metal material used as part of the source wire and a contact used to connect the source wire to a CMOS circuit are directly connected. The memory device 1 according to the first embodiment will be described below.

[0009] <1-1> Composition First, the configuration of the memory device 1 according to the first embodiment will be described.

[0010] <1-1-1> Overall configuration of memory device 1 Figure 1 is a block diagram showing an example of the overall configuration of a memory system comprising a memory device 1 according to the first embodiment. As shown in Figure 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 is, for example, a NAND flash memory capable of storing data non-volatilely. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where "n" is an integer of 1 or more). A block BLK is a collection of multiple memory cells. A block BLK corresponds, for example, to a unit of data erasure. A block BLK includes multiple pages. A page corresponds to a unit in which data reading and writing are performed. Although not shown in the diagram, the memory cell array 10 is provided with multiple bit lines BL0 to BLm (where "m" is an integer of 1 or more) and multiple word lines WL. Each memory cell is associated, for example, with one bit line BL and one word line WL.

[0012] The input / output circuit 11 is an interface circuit that controls the transmission and reception of input / output signals to and from the memory controller 2. These input / output signals include, for example, data DAT, status information, address information, and commands. The input / output circuit 11 can input and output data DAT to and from the sense amplifier module 17 and the memory controller 2, respectively. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output address information and commands transferred from the memory controller 2 to the register circuit 13.

[0013] The logic controller 12 controls the input / output circuit 11 and the sequencer 14 based on the control signals input from the memory controller 2. For example, the logic controller 12 controls the sequencer 14 to enable the memory device 1. The logic controller 12 notifies the input / output circuit 11 that the input / output signal it has received is a command or address information. The logic controller 12 commands the input / output circuit 11 to input or output the input / output signal.

[0014] The register circuit 13 temporarily stores status information, address information, and commands. The status information is updated based on the control of the sequencer 14 and transferred to the input / output circuit 11. The address information includes block addresses, page addresses, column addresses, etc. The commands include instructions for various operations of the memory device 1.

[0015] The sequencer 14 controls the overall operation of the memory device 1. Based on the commands and address information stored in the register circuit 13, the sequencer 14 performs read operations, write operations, erase operations, etc.

[0016] The driver circuit 15 generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 then supplies the generated voltages to the raw decoder module 16, sense amplifier module 17, and other components.

[0017] The row decoder module 16 is a circuit used for selecting the block BLK to be operated on and for transferring voltage to wiring such as word lines WL. The row decoder module 16 includes multiple row decoders RD0 to RDn. Row decoders RD0 to RDn are each associated with blocks BLK0 to BLKn and are used for selecting blocks BLK. Each row decoder RD transfers the voltage generated by the driver circuit 15 to various wirings provided in the memory cell array 10.

[0018] The sense amplifier module 17 is a circuit used for transferring voltage to each bit line BL and reading data. The sense amplifier module 17 includes multiple sense amplifier units SAU0 to SAUm. Each sense amplifier unit SAU0 to SAUm is associated with multiple bit lines BL0 to BLm. Each sense amplifier unit SAU includes a sense amplifier capable of determining data based on the voltage of the associated bit line BL, as well as a latch circuit for temporarily holding the data.

[0019] The combination of memory device 1 and memory controller 2 may constitute a single semiconductor device. For example, an SD card is one such semiconductor device. TM Examples include memory cards and SSDs (solid state drives). Furthermore, the memory device 1 may comprise multiple memory cell arrays 10. Each memory cell array 10 may also comprise a row decoder module 16 and a sense amplifier module 17. A set of memory cell arrays 10, row decoder module 16, and sense amplifier module 17 is referred to, for example, as a "plane." That is, the memory device 1 may comprise multiple planes.

[0020] <1-1-2> Circuit configuration of the memory cell array 10 Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array 10 provided in a memory device 1 according to the first embodiment. Figure 2 shows two blocks BLK0 and BLK1 among a plurality of block BLKs included in the memory cell array 10. As shown in Figure 2, in the memory cell array 10, selection gate lines SGD and SGS and word lines WL0 to WL(N-1) (where N is an integer of 2 or more) are provided for each block BLK. Bit lines BL0 to BLm and source line SL are shared, for example, by multiple block BLKs.

[0021] Each block BLK contains multiple NAND strings NS. Each of the multiple NAND strings NS is associated with a bit line BL0 to BLm. In other words, each bit line BL is shared by NAND strings NS that are assigned the same column address across multiple block BLKs. Each NAND string NS is connected between the associated bit line BL and the source line SL. Each NAND string NS contains, for example, N memory cell transistors MT0 to MT(N-1) and selection transistors ST1 and ST2. Each memory cell transistor MT is a memory cell having a control gate and a charge storage layer, which holds (stores) data non-volatilely. Selection transistors ST1 and ST2 are used for selecting block BLKs, respectively.

[0022] In each NAND string NS, the selection transistor ST1, memory cell transistors MT(N-1) to MT0, and selection transistor ST2 are connected in series in this order. Specifically, the drain and source terminals of selection transistor ST1 are connected to the associated bit line BL and the drain terminal of memory cell transistor MT(N-1), respectively. The drain and source terminals of selection transistor ST2 are connected to the source terminal of memory cell transistor MT0 and the source line SL, respectively. The memory cell transistors MT0 to MT(N-1) are connected in series between selection transistors ST1 and ST2.

[0023] Each selection gate line SGD is connected to the gate terminal of each of the multiple selection transistors ST1 contained in the associated block BLK. The selection gate line SGS is connected to the gate terminal of each of the multiple selection transistors ST2 contained in the associated block BLK. Word lines WL0 to WL(N-1) are connected to the control gate terminals of each of the multiple memory cell transistors MT0 to MT(N-1) contained in the associated block BLK. A “page” corresponds to a set of multiple memory cell transistors MT connected to a common word line WL within the same block BLK. A set of multiple memory cell transistors MT connected to a common word line WL within the same block BLK may have a storage capacity of two pages or more, depending on the number of bits stored by the memory cell transistors MT.

[0024] The circuit configuration of the memory cell array 10 may be other configurations. For example, each block BLK may be provided with a plurality of independently controllable selection gate line SGDs. In this case, each block BLK is configured to be selectable in units of multiple units, each associated with a plurality of selection gate line SGDs.

[0025] In the following, the memory device 1 according to the first embodiment will be described using the case where each NAND string NS has eight memory cell transistors MT0 to MT7 connected to word lines WL0 to WL7 (i.e., when N=8) as an example.

[0026] <1-1-3> Structure of memory device 1 The structure of the memory device 1 according to the first embodiment will be described below.

[0027] Note that the drawings referenced below use a three-dimensional Cartesian coordinate system. The X direction corresponds to the extension direction of the word line WL. The X direction may also be referred to as the word line (WL) direction. The Y direction corresponds to the extension direction of the bit line BL. The Y direction may also be referred to as the bit line (BL) direction. The Z direction corresponds to the direction perpendicular to the surface of the reference semiconductor substrate. "Up and down" is defined based on the direction along the Z direction. The positive direction (up) corresponds to the direction away from the reference semiconductor substrate. The XY plane (cross section) corresponds to the plane (cross section) parallel to the X and Y directions, respectively. The YZ cross section corresponds to the cross section parallel to the Y and Z directions, respectively. The XZ cross section corresponds to the cross section parallel to the X and Z directions, respectively.

[0028] (1: Appearance of memory device 1) First, the appearance of the memory device 1 according to the first embodiment will be described. The memory device 1 according to the first embodiment is formed by joining two semiconductor circuit boards, each having a semiconductor circuit formed on it, and then separating the joined semiconductor circuit boards chip by chip. In other words, the memory device 1 according to the first embodiment has a joint surface formed by joining semiconductor substrates W1 and W2. Each of the semiconductor substrates W1 and W2 is a silicon substrate. The following describes the case in which the semiconductor substrate W2 is removed during the manufacturing process of the memory device 1. Depending on the structure of the memory cell array 10, a part of the semiconductor substrate W2 may remain after the semiconductor substrates W1 and W2 are bonded together.

[0029] Figure 3 is a perspective view showing an example of the appearance of a memory device 1 according to the first embodiment. As shown in Figure 3, the memory device 1 includes, for example, a semiconductor substrate W1, a CMOS layer 100, a junction layer B1, a junction layer B2, a memory layer 200, and a wiring layer 300.

[0030] The CMOS layer 100 is arranged on a semiconductor substrate W1. The CMOS layer 100 includes a CMOS circuit (control circuit) formed using the semiconductor substrate W1. The semiconductor substrate W1 has impurity diffusion regions, etc., according to the design of the CMOS circuit. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a low decoder module 16, and a sense amplifier module 17. The CMOS layer 100 may also be called a circuit layer.

[0031] The junction layer B1 is placed on the CMOS layer 100. The junction layer B1 is formed using the semiconductor substrate W1. The junction layer B1 includes a plurality of junction pads that are electrically connected to the CMOS circuit provided on the CMOS layer 100 and form a part of the semiconductor circuit.

[0032] The junction layer B2 is placed on the junction layer B1. The junction layer B2 is formed using a semiconductor substrate W2 (not shown). The junction layer B2 includes a plurality of junction pads that are electrically connected to the memory cell array 10 provided on the memory layer 200 and form a part of the semiconductor circuit. The plurality of junction pads included in the junction layer B2 are each connected to the plurality of junction pads included in the junction layer B1. The space between the junction layers B1 and B2 corresponds to the boundary portion, i.e., the junction surface, between the layer formed using the semiconductor substrate W1 and the layer formed using the semiconductor substrate W2.

[0033] The memory layer 200 is placed on the junction layer B2. The memory layer 200 includes a memory cell array 10 formed using the semiconductor substrate W2. The memory layer 200 may also be called a circuit layer.

[0034] The wiring layer 300 is placed on the memory layer 200. The wiring layer 300 is formed after the semiconductor substrates W1 and W2 are bonded together. The wiring layer 300 includes wiring connected to semiconductor circuits provided on the memory layer 200, and a plurality of pad portions PD. The plurality of pad portions PD include conductive portions (pads) exposed on the surface of the memory device 1. The plurality of pad portions PD are used for connecting the memory device 1 to the memory controller 2, etc., and for supplying power.

[0035] (2: Planar layout of memory device 1) Figure 4 is a plan view showing an example of a planar layout of the memory device 1 according to the first embodiment. As shown in Figure 4, the memory device 1 includes, for example, at least one core region CR, a peripheral region PR, a wall region WR, and a kerf region KR.

[0036] The core region CR is, for example, a rectangular region located near the center of the semiconductor substrate W1. The core region CR contains, for example, a memory cell array 10, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, and a sense amplifier module 17. In this example, the memory device 1 includes four core regions CR1 to CR4 arranged in a grid. The memory device 1 includes, for example, four memory cell arrays 10, each corresponding to one of the four core regions CR1 to CR4.

[0037] The wall region WR is, for example, a rectangular ring-shaped region provided to surround the outer periphery of four core regions CR. At least one sealing portion (not shown) is provided to surround the outer periphery of the peripheral region PR within the wall region WR. The sealing portion is a structure capable of releasing positive and negative charges generated inside and outside the wall region WR to the semiconductor substrate W1. The sealing portion can suppress the penetration of moisture and the like into the core regions CR from the outside of the wall region WR. The sealing portion can suppress stress generated in the interlayer insulating film (e.g., tetraethoxysilane (TEOS)) of the memory device 1. The sealing portion can also be used as a crack stopper.

[0038] The peripheral region PR is the area inside the wall region WR and does not overlap with each core region CR. The peripheral region PR has a rectangular ring-shaped portion that surrounds the outer periphery of core regions CR1 to CR4, and a portion sandwiched between two adjacent core regions CR. For example, input / output circuits 11 and logic controllers 12 are arranged in the peripheral region PR. In addition, for example, contacts for connecting wiring provided in the wiring layer 300 to circuits provided in the CMOS layer 100 and memory layer 200 are arranged in the peripheral region PR.

[0039] The kerf region KR is a rectangular ring-shaped region that surrounds the outer periphery of the wall region WR. The kerf region KR is in contact with the outermost periphery of the memory device 1. Alignment marks used during the manufacturing of the memory device 1 are placed in the kerf region KR, for example. The structure of the kerf region KR may be removed during the dicing process, which separates the semiconductor circuit board into individual chips (memory devices 1).

[0040] (3: Planar layout of memory cell array 10) Figure 5 is a plan view showing an example of a planar layout in the core region CR of the memory cell array 10 of the memory device 1 according to the first embodiment. As shown in Figure 5, the memory cell array 10 includes a plurality of slits SLT, a plurality of memory pillars MP, and a plurality of contacts CV and CC. The memory cell array 10 also includes, for example, a storage region SA, a dummy region DAc, and a contact region CA arranged in the X direction.

[0041] Each slit SLT is a plate-shaped member that extends along the X direction. Each slit SLT has a portion that extends along the X direction and crosses the storage area SA, dummy area DAc, and contact area CA along the X direction. Multiple slit SLTs are arranged in the Y direction. Each slit SLT separates adjacent wiring (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. Each slit SLT may have a conductor with insulating spacers on its side wall that is insulated from these wirings, or the insulator may be embedded in it. In the memory cell array 10, each region separated along the Y direction by the slit SLT corresponds to one block BLK.

[0042] The storage area SA includes multiple memory pillars MP. Each memory pillar MP is a pillar-shaped member that functions, for example, as a single NAND string NS. The multiple memory pillars MP are arranged in a grid pattern for each block BLK. At least one bit line BL is arranged overlapping each memory pillar MP. Each of the multiple bit lines BL has a portion extending in the Y direction and is aligned in the X direction. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The associated memory pillar MP and bit line BL are electrically connected via contacts CV.

[0043] The dummy area DAc is located at the X-edge of the storage area SA. Two dummy areas DAc may be located in the core area CR so as to sandwich the storage area SA in the X-direction. The dummy area DAc contains multiple dummy pillar DMPs. The dummy pillar DMPs are patterns to compensate for the shape of the memory pillar MPs and have a similar structure to the memory pillar MPs. Bit lines BL may be arranged on top of each dummy pillar DMP. The bit lines BL located in the dummy area DAc are patterns to compensate for the shape of the bit lines BL located in the storage area SA and are not used for data storage. Therefore, the dummy pillar DMPs are not connected to contact CVs and are not connected to bit lines BLs.

[0044] The contact area CA is used to connect the stacked wiring (e.g., word lines WL, selection gate lines SGD and SGS) of the memory cell array 10 to the row decoder module 16. Multiple contacts CC are arranged in the contact area CA for each block BLK. Each of the multiple contacts CC in each block BLK is electrically connected to one corresponding wiring in the stacked wiring. In each block BLK, at least one contact CC is electrically connected to each of the selection gate line SGS, word lines WL0 to WL7, and selection gate line SGD.

[0045] Furthermore, within the contact area CA, the multiple contacts CC in each block BLK are not limited to being arranged in a single line in the X direction as shown in Figure 5, but may be arranged in a grid pattern for each block BLK. In the core area CR, two contact areas CA may be arranged so as to sandwich the storage area SA in the X direction. Alternatively, the contact areas CA may be arranged so as to divide the storage area SA in the X direction. In this specification, we will describe the case in the core area CR where two contact areas CA are arranged so as to sandwich the storage area SA in the X direction.

[0046] Furthermore, the core region CR includes the active region AA and the dummy region DAr, which are aligned in the Y direction. Each of the active region AA and the dummy region DAr overlaps with the storage region SA, the dummy region DAc, and the contact region CA, respectively. Multiple memory pillars MP, used for data storage, are located in the area where the storage region SA and the active region AA overlap. Multiple contacts CC, used for controlling the active block BLK, are located in the area where the contact region CA and the active region AA overlap.

[0047] The dummy region DAr is located at the Y-direction end of the core region CR. Two dummy regions DAr may be arranged in the core region CR so as to sandwich the active region AA in the Y-direction. A dummy block DBLK corresponds to a region within the dummy region DAr that is partitioned in the Y-direction by a slit SLT. The dummy region DAr contains at least one dummy block DBLK. Figure 5 shows two dummy blocks DBLK0 and DBLK1 aligned in the Y-direction. Multiple dummy pillars DMP may be arranged in the region of the dummy block DBLK that overlaps with the storage region SA.

[0048] The dummy region DAar further includes a dummy stepped section DS in the portion corresponding to the outer edge of the core region CR. The dummy stepped section DS includes the stepped ends of the laminated wiring. In the dummy stepped section DS, sacrificial members SM remain in the portion corresponding to the laminated wiring. Sacrificial members SM are members used in the replacement process that forms the laminated wiring. In the replacement process, the laminated wiring is formed by replacing the sacrificial members SM with conductors among the alternately stacked sacrificial members SM and insulating layers. More specifically, in the replacement process, the sacrificial members SM are removed through the slit SLT, and conductors are embedded in the space where the sacrificial members SM were removed. Therefore, sacrificial members SM located away from the slit SLT may remain without being replaced with conductors in the replacement process. As a result, the ends of the stacked sacrificial members SM are arranged in a stepped shape. An example of the structure of the dummy stepped section DS is shown in Figure 8, which will be described later.

[0049] (4: Cross-sectional structure of the storage area SA of the memory cell array 10) Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure in the storage area SA of the memory cell array 10 provided in the memory device 1 according to the first embodiment. Figure 6 shows an example of the structure of the circuit layer including the memory cell array 10 and the junction layer B2 below it, and displays coordinate axes with respect to a semiconductor substrate W1 (not shown). As shown in Figure 6, the circuit layer including the memory cell array 10 and the junction layer B2 include, for example, an insulating member 301, a conductive layer 51, a semiconductor layer 50, a semiconductor layer 24, insulating layers 25-29, an insulating member 30, conductive layers 31-34, and contacts CV, V1 and V2 within the storage area SA.

[0050] Below the insulating member 301, a conductive layer 51, a semiconductor layer 50, and a semiconductor layer 24 are provided in this order. The combination of conductive layer 51, semiconductor layer 50, and semiconductor layer 24 is used as a source wire SL. The conductive layer 51 is made of a metallic material, for example, tungsten (W) or aluminum (Al). The conductive layer 51 may also contain a barrier metal. Each of the semiconductor layers 50 and 24 is, for example, polysilicon. Each of the semiconductor layers 50 and 24 is doped with impurities. Therefore, each of the semiconductor layers 50 and 24 can function as a conductor.

[0051] An insulating layer 25 is provided beneath the semiconductor layer 24. Conductive layers 31 and insulating layers 26 are provided alternately in the Z direction beneath the insulating layer 25. That is, multiple conductive layers 31 are arranged in the Z direction. Thus, the laminate corresponding to the memory cell array 10 includes conductive layers 31 and insulating layers 26 arranged alternately in the Z direction. The number of conductive layers 31 corresponds, for example, to the number of layers of the laminated wiring (selective gate line SGS, word line WL, and selective gate line SGD). In this example, the 10 conductive layers 31 arranged in the Z direction are used, in order from the source line SL side, as selective gate line SGS, word lines WL0 to WL7, and selective gate line SGD. The conductive layers 31 are formed, for example, in a plate shape extending along the XY plane. The conductive layers 31 contain, for example, tungsten (W).

[0052] Below the bottom conductive layer 31, an insulating layer 27, a conductive layer 32, and an insulating layer 28 are provided in this order. The conductive layer 32 has, for example, a portion formed in the shape of a line extending in the Y direction. In this example, the conductive layer 32 is used as a bit line BL. The conductive layer 32 contains, for example, copper (Cu).

[0053] A conductive layer 33 is provided below the conductive layer 32. The conductive layer 33 is wiring that relays the connection between the bit line BL and the sense amplifier module 17. The conductive layer 32 and the conductive layer 33 are connected via contact V1. A conductive layer 34 is provided below the conductive layer 33. The conductive layer 34 corresponds to a bonding pad. The conductive layer 33 and the conductive layer 34 are connected via contact V2. The sides of the conductive layer 33 and contacts V1 and V2 are covered by an insulating layer 28. The insulating layer 28 may be composed of multiple insulating films. The sides of the conductive layer 34 are covered by an insulating layer 29. The insulating layer 29 and the conductive layer 34 are included in the bonding layer B2. The memory cell array 10 may include multiple conductive layers 34. The bonding layer B2 may include multiple conductive layers 34. The conductive layer 34 contains, for example, copper (Cu).

[0054] The insulating member 30 has a plate-shaped portion that extends along the XZ plane. The insulating member 30 separates the semiconductor layer 24, the insulating layer 25, and the alternately arranged conductive layers 31 and insulating layers 26. The upper part of the insulating member 30 is covered by the semiconductor layer 50. In this example, the insulating member 30 is embedded in the slit SLT. In the slit SLT, a conductor with insulating spacers on its sidewall may be arranged in isolation from each of the multiple conductive layers 31.

[0055] Each memory pillar MP is provided extending along the Z direction and penetrates a semiconductor layer 24, an insulating layer 25, and alternately arranged conductive layers 31 and insulating layers 26. The upper part of each memory pillar MP is covered by a semiconductor layer 50. The surface of the semiconductor layer 50 is provided in a non-planar manner above the multiple memory pillar MPs. Similarly, the surface of the conductive layer 51 is provided in a non-planar manner above the multiple memory pillar MPs.

[0056] Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, a multilayer film 42, and a semiconductor layer 46. The core member 40 is an insulator provided stretched along the Z direction. The pair of semiconductor layers 41 and 46 covers the core member 40. The semiconductor layer 41 faces each of the multiple conductive layers 31 aligned in the Z direction in the planar direction (e.g., the Y direction). The semiconductor layer 46 is provided on the top of the memory pillar MP. The semiconductor layer 46 corresponds to an impurity-doped semiconductor layer 41. The impurity concentration of the semiconductor layer 46 is higher than the impurity concentration of the portion of the semiconductor layer 41 facing the conductive layer 31 in the Y direction. The top of the semiconductor layer 46 is in contact with the semiconductor layer 50. The multilayer film 42 covers the sides of the semiconductor layer 41 and a portion of the sides of the semiconductor layer 46. The upper end of the multilayer film 42 faces the semiconductor layer 50 in the Z direction. The associated semiconductor layer 41 (memory pillar MP) and the conductive layer 32 (bit line BL) are connected via contact CV.

[0057] The portion where the conductive layer 31, used as the selection gate line SGS, intersects with the memory pillar MP functions as a selection transistor ST2. The portion where the conductive layer 31, used as the word line WL, intersects with the memory pillar MP functions as a memory cell transistor MT. The portion where the conductive layer 31, used as the selection gate line SGD, intersects with the memory pillar MP functions as a selection transistor ST1. In each memory pillar MP, the semiconductor layer 41 is used as a channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2 included in the NAND string NS.

[0058] (5: Cross-sectional structure of memory pillar MP) Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure of a memory pillar MP provided in a memory device 1 according to the first embodiment. Figure 7 shows a cross-section including the memory pillar MP and the conductive layer 31, and parallel to the surface of the semiconductor substrate W1. As shown in Figure 7, the laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 31 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 includes, for example, silicon oxide (SiO2). The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The insulating film 44 includes, for example, silicon nitride (SiN).

[0059] (6: Cross-sectional structure of memory device 1 in the BL direction) Figure 8 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment, and shows a cross-section along the BL direction (Y direction). Figure 8 shows the active region AA, the dummy region DAr, and a part of the peripheral region PR, and displays coordinate axes with respect to the semiconductor substrate W1. As shown in Figure 8, the CMOS layer 100 includes an insulating layer 110. The junction layer B1 includes an insulating layer 111. The memory layer 200 includes an insulating layer 210. The wiring layer 300 includes an insulating member 301, a conductive layer 302, and insulating layers 303, 304, and 305.

[0060] The insulating layer 110 is provided on the semiconductor substrate W1. The insulating layer 110 covers at least a portion of the wiring, contacts, elements, etc. provided on the CMOS layer 100. The insulating layer 110 may be composed of multiple types of insulating films. The insulating layer 111 is provided on the insulating layer 110. The insulating layer 111 covers the side surface of the bonding pad provided on the bonding layer B1. The insulating layer 29 of the bonding layer B2 is provided on the insulating layer 111.

[0061] The insulating layer 210 is provided on the insulating layer 29. The insulating layer 210 covers at least a portion of the wiring, contacts, elements, etc., provided on the memory layer 200. The insulating layer 210 may be composed of multiple types of insulating films and may include insulating layers 27 and 28. A semiconductor layer 24 is provided on the insulating layer 210. In a part of the peripheral region PR, the component 23, semiconductor layer 22, and insulating layer 21 are stacked on the semiconductor layer 24 in this order. Details of the component 23, semiconductor layer 22, and insulating layer 21 will be described later.

[0062] Within the active region AA, the dummy region DAr, and the peripheral region PR, a semiconductor layer 50 is provided on the stack corresponding to the memory cell array 10. The semiconductor layer 50 covers the semiconductor layer 46 on top of each memory pillar MP, the semiconductor layer 46 on top of each dummy pillar DMP, and the upper part of the insulating member 30 (slit SLT). The semiconductor layer 50 is electrically connected to the semiconductor layers 41 and 46 of each memory pillar MP. Hereinafter, in a plan view, the region where the semiconductor layer 50 is provided on the semiconductor layer 24 will be referred to as the "source line region SLA". In a plan view, the region within the peripheral region PR that does not include the insulating layer 21, semiconductor layer 22, member 23, and semiconductor layer 24 will be referred to as the "insulating region BA".

[0063] Within the active region AA, the dummy region DAr, and the peripheral region PR, a conductive layer 51 is provided on the semiconductor layer 50 or the insulating layer 210. The conductive layer 51 covers the semiconductor layer 46 on top of each memory pillar MP, the semiconductor layer 46 on top of each dummy pillar DMP, and the upper part of the insulating member 30 (slit SLT) via the semiconductor layer 50. In other words, each of the semiconductor layer 50 and the conductive layer 51 has a portion that covers the upper part of the memory pillar MP, the dummy pillar DMP, and the slit SLT, respectively. Furthermore, the conductive layer 51 has a portion that is provided along the sides of the semiconductor layers 24 and 50 at the boundary between the source line region SLA and the insulating region BA. In addition, the conductive layer 51 has a portion that covers the upper part of at least one contact C3 in the insulating region BA. The conductive layer 51 is in contact with the upper part of at least one contact C3 in the insulating region BA. As a result, the conductive layer 51 electrically connects the multiple memory pillars MP and at least one contact C3. The surface of the conductive layer 51 is provided in a non-planar manner above at least one of the multiple memory pillars MP and at least one contact C3.

[0064] The insulating member 301 is provided, for example, on the conductive layer 51, the insulating layer 210, or the insulating layer 21. The insulating member 301 is provided so as to be embedded in the step formed between the source line region SLA and the insulating region BA. The upper surface of the insulating member 301 is flattened. The insulating member 301 includes at least one via VA within the active region AA. The via VA penetrates the insulating member 301. The bottom of the via VA reaches the conductive layer 51.

[0065] The conductive layer 302 is provided on the insulating member 301. The conductive layer 302 in the active region AA may have a portion that is provided along via VA and connected to the conductive layer 51 via via VA. The conductive layer 302 may also have a portion that is provided on the insulating member 301 in the peripheral region PR and the wall region WR. The conductive layer 302 is separated (insulated) at least between the peripheral region PR and the wall region WR. The conductive layer 302 may have a portion that is continuously provided between the active region AA and the peripheral region PR.

[0066] The insulating layer 303, insulating layer 304, and insulating layer 305 are provided on the insulating member 301 or the conductive layer 302 in this order. Each of the insulating member 301 and insulating layer 303 contains, for example, silicon oxide (SiO2). Insulating layer 304 contains, for example, silicon nitride (SiN). Insulating layer 305 contains, for example, polyimide.

[0067] Within the active region AA, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, while the junction layer B1 includes a conductive layer 105. The gate insulating film 101 is provided on the semiconductor substrate W1. The gate electrode 102 of the active region AA is provided on the gate insulating film 101 and is used as the gate electrode of transistor TR1. Transistor TR1 is included, for example, in a sense amplifier module 17. Conductive layer 103 is wiring above the gate electrode 102. Contact C0 connects the gate electrode 102 and the conductive layer 103. Contact C1 connects the impurity diffusion region of transistor TR1 provided on the semiconductor substrate W1 to the conductive layer 103. Conductive layer 104 is wiring provided at the height between conductive layer 103 and junction layer B1. Contact C2 is provided at the height between conductive layer 103 and junction layer B1. At least one conductive layer 103 is connected to conductive layer 105 via at least one contact C2 and at least one conductive layer 104. Conductive layer 105 corresponds to a junction pad located in junction layer B1. Conductive layer 105 is in contact with conductive layer 34 located opposite conductive layer 105 within junction layer B2. As a result, semiconductor layer 41 in active region AA is electrically connected to transistor TR1 via contact CV, conductive layers 32-34 and 103-105, and contacts CV, V1, V2, C1 and C2.

[0068] Within the peripheral region PR, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, similar to the active region AA, while the junction layer B1 includes a conductive layer 105. The gate electrode 102 of the peripheral region PR is used as the gate electrode of transistor TR2. Transistor TR2 is included, for example, in the driver circuit 15. Within the peripheral region PR, the junction layer B2 includes a conductive layer 34, and the memory layer 200 includes conductive layers 33 and 35, and contacts V1, V2, and C3. Conductive layer 35 is wiring provided in the same layer as conductive layer 32. At least one contact C3 is provided on conductive layer 35. The top of each contact C3 reaches at least the height of semiconductor layer 22. The top of each contact C3 is covered by conductive layer 51 and electrically connected to conductive layer 51.

[0069] As a result, the conductive layer 51 in the peripheral region PR is electrically connected to the transistor TR2 via at least one contact C3, conductive layers 33-35 and 103-105, and contacts V1, V2, C1, and C2. Therefore, the semiconductor layer 46 of each memory pillar MP is electrically connected to the transistor TR2 via the semiconductor layer 50, the conductive layer 51, at least one contact C3, conductive layers 33-35 and 103-105, and contacts V1, V2, C1, and C2.

[0070] In memory device 1, the stack corresponding to the memory cell array 10 includes an insulating layer 26 and a conductive layer 31 alternately stacked in the Z direction within a dummy region DAr, or an insulating layer 26 and a sacrificial member SM alternately stacked in the Z direction. The sacrificial member SM is made of a different material from the insulating layer 26 and the conductive layer 31, respectively. The dummy staircase portion DS is composed, for example, of an insulating layer 26 and a sacrificial member SM alternately stacked in the Z direction. In other words, the stack corresponding to the memory cell array 10 has a stack portion within the dummy region DAr in which the insulating layer 26 and the sacrificial member SM are alternately stacked in the Z direction. In this stack portion, the ends of the stacked sacrificial member SM are provided in a staircase shape. Multiple dummy pillars DMP penetrate the stack corresponding to the memory cell array 10 in the Z direction within the dummy region DAr.

[0071] (7: Cross-sectional structure of memory device 1 in the WL direction) Figure 9 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment, and shows a cross-section along the WL direction (X direction). Figure 9 shows the contact region CA, the dummy region DAc, and a part of the storage region SA, and displays coordinate axes with respect to the semiconductor substrate W1. As shown in Figure 9, a part of the source line region SLA overlaps with the dummy region DAc. The dummy region DAc includes the edge of the conductive layer 51. In the contact region CA and a part of the dummy region DAc, the member 23, semiconductor layer 22, and insulating layer 21 are stacked on the semiconductor layer 24 in this order. In the dummy region DAc, the edge of the conductive layer 51 has a portion that covers a part of the insulating layer 21. In the portion of the conductive layer 51 that covers a part of the insulating layer 21, it is separated from the dummy pillar DMP.

[0072] The contact region CA includes a plurality of columnar members HR. The columnar members HR are configured to maintain the laminated structure within the contact region CA during replacement processing. Specifically, each columnar member HR is provided extending along the Z direction and penetrates, for example, member 23, semiconductor layer 24, insulating layer 25, and alternately provided conductive layers 31 and insulating layers 26. The upper part of each columnar member HR reaches the semiconductor layer 22. Note that, if the conductive layers 31 are provided in a stepped manner within the contact region CA, the number of conductive layers 31 that each columnar member HR penetrates may differ depending on its position. The columnar members HR include, for example, silicon oxide (SiO2).

[0073] Within the contact region CA, the CMOS layer 100 includes a gate insulating film 101, a gate electrode 102, conductive layers 103 and 104, and contacts C0 to C2, similar to the active region AA, while the junction layer B1 includes a conductive layer 105. The gate electrode 102 of the contact region CA is used as the gate electrode of transistor TR3. Transistor TR3 is included, for example, in a low decoder module 16. Within the contact region CA, the junction layer B2 includes a conductive layer 34, and the memory layer 200 includes conductive layers 32 and 33, contacts V1, V2, and CC. Each conductive layer 31 is electrically connected to transistor TR3 via contact CC, conductive layers 32 to 34 and 103 to 105, and contacts V1, V2, C1, and C2.

[0074] In this example, the wiring layer 300 has a conductive layer 302 extending in the Y direction. Multiple conductive layers 302 are arranged in the X direction. The spaces between adjacent conductive layers 302 are filled with an insulating layer 303. In a cross-section along the WL direction, the semiconductor layer 50 only needs to be provided so as to cover at least the source line region SLA. However, it is not limited to this, and in the memory device 1 according to the first embodiment, the semiconductor layer 50 may be provided between the insulating layer 21 and the conductive layer 51 in the dummy region DAc.

[0075] (8: Planar layout of bonding pads) Figure 10 is a plan view showing an example of the arrangement of bonding pads in a memory device 1 according to the first embodiment. Figure 10 illustrates the arrangement of conductive layers 34 provided corresponding to the semiconductor substrate W2 as an example of bonding pad arrangement. As shown in Figure 10, the multiple conductive layers 34 are arranged, for example, in a staggered pattern inside the wall region WR. The multiple conductive layers 34 may also be arranged in a grid pattern. A portion of the multiple conductive layers 34 corresponds to a dummy pattern not used in the operation of the memory device 1. Each conductive layer 105 provided corresponding to the semiconductor substrate W1 is arranged to face the corresponding conductive layer 34. The wall region WR may include conductive layers 34 and 105 provided in an annular shape corresponding to the sealing portion. In addition, multiple conductive layers 34 may be arranged in the kerf region KR.

[0076] (9: Detailed cross-sectional structure of the bonding pad) Figure 11 is a cross-sectional view showing an example of a detailed cross-sectional structure near two opposing bonding pads in a memory device 1 according to the first embodiment. Figure 11 shows a conductive layer 105 (bonding pad) formed using a semiconductor substrate W1 (not shown), a conductive layer 34 (bonding pad) formed using a semiconductor substrate W2 (not shown), and some contacts C2 and V2 and conductive layers 104 and 33 connected thereto.

[0077] As shown in Figure 11, the two opposing bonding pads may have different taper shapes depending on the etching direction during formation. Specifically, the conductive layer 105 formed using the semiconductor substrate W1 has, for example, an inverse taper shape. The conductive layer 34 formed using the semiconductor substrate W2 has, for example, a forward taper shape. Therefore, the cross-sectional shape along the Z direction at the point where the conductive layer 105 and the conductive layer 34 are joined may not have straight sidewalls, but rather be non-rectangular. Furthermore, the pair of opposing bonding pads may be joined with a misalignment depending on the alignment during the bonding process. Therefore, a step may be formed between the side surface of the conductive layer 105 and the side surface of the conductive layer 34.

[0078] The pair of opposing bonding pads may have a boundary or be integrated. The bonding pad and the contacts C2 and V2 connected to it may be formed as a single unit. Multiple corresponding contacts C2 and V2 may be connected to the bonding pad. For example, the conductive layer 105 may be connected to the conductive layer 104 via multiple contacts C2. Similarly, the conductive layer 34 may be connected to the conductive layer 33 via multiple contacts V2. Furthermore, if the pair of opposing bonding pads is a dummy pattern, the connection of contact C2 to the conductive layer 105 and the connection of contact V2 to the conductive layer 34 may be omitted.

[0079] (10: Planar layout of semiconductor layer 22) Figure 12 is a plan view showing an example of a planar layout of the semiconductor layer 22 in the memory device 1 according to the first embodiment. As shown in Figure 12, the semiconductor layer 22 is located, for example, in the contact area CA of each core area CR and is not included in the storage area SA and peripheral area PR. Of two adjacent core areas CR, the semiconductor layer 22 provided in one core area CR is separated from the semiconductor layer 22 provided in the other core area CR. Note that the wall area WR may include a semiconductor layer 22 provided in an annular shape corresponding to the sealing portion.

[0080] (11: Planar layout of conductive layer 302) Figure 13 is a plan view showing an example of a planar layout of the conductive layer 302 in the memory device 1 according to the first embodiment. As shown in Figure 13, a plurality of conductive layers 302 are arranged inside the wall region WR. Each of the plurality of conductive layers 302 has, for example, a portion that extends in the Y direction. The plurality of conductive layers 302 include, for example, a conductive layer 302A used as shunt wiring for the source line SL and a conductive layer 302B used as part of the power line PL.

[0081] The conductive layer 302A corresponds to the conductive layer 302 having a portion connected to the conductive layer 51 via via VA in the core region CR shown in Figure 8, for example. In this example, each conductive layer 302A is provided for each core region CR. In this example, each conductive layer 302B extends from the outer peripheral end of the memory device 1 in core regions CR1 and CR3 to the outer peripheral end of the memory device 1 in core regions CR2 and CR4. In each core region CR, the conductive layers 302A and 302B are arranged alternately, for example, in the X direction. The conductive layer 302A is not included in the peripheral region PR, for example. The arrangement of the conductive layers 302A and 302B can be appropriately changed depending on the layout of the pad portion PD (not shown) and the CMOS circuit.

[0082] (12: Detailed planar layout near the pad area PD) Figure 14 is a plan view showing an example of a planar layout near the pad portion PD in the memory device 1 according to the first embodiment. Figure 14 shows the pad portion PD used for connection with input / output circuits 11 and logic controllers 12 in the memory device 1, and parts of the core region CR2 and peripheral region PR near it. As shown in Figure 14, the peripheral region PR includes via TV and via VB used as the pad portion PD.

[0083] The via TV is positioned so as not to overlap in the Z direction with the area where the conductive layer 51, used as the source line SL, is provided. At the bottom of the via TV, for example, the conductive layer 302B, used as the power line PL, is exposed. The portion of the conductive layer 302B exposed at the bottom of the via TV is used as the pad portion PD. The conductive layer 302B is provided in a rectangular shape in a plan view, for example. The conductive layer 302B has a portion that overlaps with via VB. Via VB overlaps in the Z direction with conductive layer 51A, which is used as wiring to relay the connection between conductive layer 302B and at least one contact C3. Conductive layer 51A is separate from conductive layer 51, which is used as the source line SL. Conductive layer 302B is electrically connected to at least one contact C3 via the portion along via VB and via conductive layer 51A.

[0084] The conductive layer 302A, used as a shunt wiring for the source wire SL, is provided in a rectangular shape in a plan view, for example. The conductive layer 302A is included in the active region AA and the dummy region DAr, and is separate from the conductive layer 302B. The source wire SL to which the conductive layer 302A is connected is electrically connected to at least one contact C3 in the region where the conductive layer 51 used as the source wire SL extends into the peripheral region PR.

[0085] (13: Cross-sectional structure near the pad portion PD) Figure 15 is a cross-sectional view along the line XV-XV in Figure 14, showing an example of the cross-sectional structure near the pad portion PD in the memory device 1 according to the first embodiment. As shown in Figure 15, the via TV penetrates the insulating layers 303, 304, and 305. At the bottom of the via TV, a portion of the conductive layer 302B, which is used as the power line PL, is exposed. In the first embodiment, the portion of the conductive layer 302B whose surface is exposed through the via TV does not overlap with the conductive layer 51, which is used as the source line SL, in the Z direction.

[0086] The conductive layer 302B has a portion provided along via VB and is connected to a plurality of contacts C3 via via VB and conductive layer 51A. The conductive layer 302B is then electrically connected to a transistor TR4 on the semiconductor substrate W1 via the plurality of contacts C3. The transistor TR4 is included in the power supply circuit of memory device 1, for example. In other words, the conductive layer 302B corresponding to the pad portion PD is electrically connected to a power supply circuit included in the CMOS circuit provided on the CMOS layer 100 via the memory layer 200. The conductive layer 302B has a portion facing the plurality of contacts C3 connected to the conductive layer 51 (source line SL) in the Z direction.

[0087] <1-2> Manufacturing method Next, a method for manufacturing the memory device 1 according to the first embodiment will be described.

[0088] <1-2-1> Structure of the memory cell array 10 before junction Figure 16 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 10 in the manufacturing process of a memory device 1 according to the first embodiment. Figure 16 shows an example of the structure of a circuit layer including the memory cell array 10 before bonding of semiconductor substrate W1 and semiconductor substrate W2, and a bonding layer B2 above it, and displays coordinate axes with respect to semiconductor substrate W2. As shown in Figure 16, the circuit layer including the memory cell array 10 before bonding and the bonding layer B2 include, for example, an insulating layer 21, a semiconductor layer 22, a member 23, a semiconductor layer 24, insulating layers 25-29, an insulating member 30, conductive layers 31-34, and contacts CV, V1 and V2 within the storage area SA.

[0089] An insulating layer 21 is provided on the semiconductor substrate W2. A semiconductor layer 22, a component 23, and a semiconductor layer 24 are provided on the insulating layer 21 in this order. A source line SL is formed after the semiconductor substrates W1 and W2 are joined using the portion where the semiconductor layers 22, component 23, and semiconductor layer 24 are provided. Each of the semiconductor layers 22 and component 23 is used, for example, as a memory pillar MP or an etching stopper layer when forming a slit SLT. Each of the semiconductor layers 22 and 24 is, for example, polysilicon. Component 23 contains, for example, silicon oxide (SiO2).

[0090] An insulating layer 25 is provided on the semiconductor layer 24. Conductive layers 31 and insulating layers 26 are alternately provided on the insulating layer 25 in the Z direction. The insulating member 30 separates member 23, semiconductor layer 24, insulating layer 25, and the alternately provided conductive layers 31 and insulating layers 26. The bottom of the insulating member 30 reaches the semiconductor layer 22. Each memory pillar MP is provided extending along the Z direction and penetrates member 23, semiconductor layer 24, insulating layer 25, and the alternately provided conductive layers 31 and insulating layers 26. The bottom of each memory pillar MP reaches the semiconductor layer 22. The other structures of the memory cell array 10 before bonding are the same as the structure of the memory cell array 10 described with reference to Figure 6.

[0091] <1-2-2> Method for forming source wire SL and wiring layer 300 after joining The following describes a method for manufacturing the memory device 1 according to the first embodiment, specifically a method for forming the source line SL and wiring layer 300 after joining the semiconductor substrate W1 and semiconductor substrate W2, with appropriate reference to Figure 17. Figure 17 is a flowchart showing an example of a method for manufacturing the memory device 1 according to the first embodiment. Figures 18 to 26 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing process of the memory device 1 according to the first embodiment. Figures 18, 19, 21, 22, 23, 25, and 26 correspond to cross-sections along the BL direction and display regions similar to those in Figure 8. Figures 20 and 24 correspond to cross-sections along the WL direction and display regions similar to those in Figure 9.

[0092] First, as shown in Figure 18, semiconductor substrate W2 is removed from semiconductor substrates W1 and W2 after bonding (step ST101). For example, CMP (Chemical Mechanical Polishing) is used to remove semiconductor substrate W2. The surface of the insulating layer 21 is exposed by the process in step ST101. Part of the insulating layer 21 may be removed by this process. Note that the insulating layer 21 may be formed after semiconductor substrates W1 and W2 are bonded together. In this case, in the process in step ST101, for example, the insulating layer 21 is formed after semiconductor substrate W2 is removed.

[0093] Next, as shown in Figures 19 and 20, an opening SLA+BA is formed (step ST102). Specifically, first, a mask is formed with openings in the source line region SLA and the insulating region BA in a plan view. Then, by anisotropic etching, the insulating layer 21, semiconductor layer 22, and member 23 are removed at the openings in the mask, forming the opening SLA+BA. That is, the opening SLA+BA corresponds to a region where the source line region SLA and the insulating region BA are combined. In the process of step ST102, the semiconductor layer 24 can be used as an etching stopper layer. As shown in Figure 19, the end of the opening SLA+BA in the BL direction is included in the peripheral region PR. As shown in Figure 20, the end of the opening SLA+BA in the WL direction is included in the dummy region DAc. In the opening SLA+BA, the upper parts of multiple memory pillars MP, the upper parts of insulating member 30, the upper parts of multiple dummy pillars DMP, and the upper parts of multiple contacts C3 are exposed. The upper parts of each of the multiple memory pillars MP, insulating member 30, dummy pillar DMP, and contact C3 protrude above the semiconductor layer 24 within the opening SLA+BA.

[0094] Next, the laminated film 42 on the upper part of the memory pillar MP is removed (step ST103). Specifically, for example, the laminated film 42 located above the semiconductor layer 24 within the opening SLA+BA is selectively removed by wet etching. As a result, the semiconductor layer 41 on the upper part of each memory pillar MP and the semiconductor layer 41 on the upper part of each dummy pillar DMP are exposed within the opening SLA+BA. In this process, the upper part of the columnar member HR within the contact region CA is protected by the semiconductor layer 22.

[0095] Next, a semiconductor layer 50 is formed (step ST104). In the process of step ST104, for example, CVD (Chemical Vapor Deposition) is used to form the semiconductor layer 50. At this point, the semiconductor layer 50 is, for example, amorphous silicon.

[0096] Next, ion implantation and annealing are performed (step ST105). This process is performed on the opening SLA+BA. Specifically, first, impurities are implanted into the upper part of each memory pillar MP by ion implantation. Then, the implanted impurities diffuse into the upper part of the semiconductor layer 41 by the annealing process. Crystallization also occurs in the semiconductor layer 50, and the semiconductor layer 50 is modified from amorphous silicon to polysilicon. In Figure 21, the semiconductor layer 41 doped with impurities in this way is shown as semiconductor layer 46. In this process, impurities can also be doped into the semiconductor layer 24 that was exposed in the opening SLA+BA. The impurities doped into the semiconductor layer 41 by this process are, for example, at least one of phosphorus (P) and arsenic (As). Therefore, the semiconductor layer 24 in the active region AA contains impurities and can function as a conductor. On the other hand, in the region where the semiconductor layer 22 remains in the peripheral region PR, the semiconductor layer 24 does not contain such impurities and is not used as a conductor.

[0097] Next, as shown in Figure 22, the semiconductor layers 24 and 50 of the insulating region BA are removed (step ST106). This exposes the surface of the insulating layer 210 and the upper part of at least one contact C3 provided in the insulating region BA. In step ST106, the semiconductor layer 50 provided on the insulating layer 21, as well as the semiconductor layers 50 provided on the insulating layer 21, the semiconductor layer 22, and the side surfaces of the member 23, may also be removed. The portion of the opening SLA+BA that does not overlap with the insulating region BA corresponds to the source line region SLA.

[0098] Next, as shown in Figures 23 and 24, a conductive layer 51 is formed (step ST107). Specifically, first, the conductive layer 51 is formed on the surface of the semiconductor layer 50, the insulating layer 210, and the insulating layer 21 by CVD or the like. The conductive layer 51 has a portion that covers the upper part of the semiconductor layer 46 of each memory pillar MP, a portion that covers the upper part of the semiconductor layer 46 of each dummy pillar DMP, and a portion that covers the upper part of each contact C3. After that, a mask is formed, and the conductive layer 51 is processed by an anisotropic etching process. The conductive layer 51 processed in this step is provided, for example, to electrically connect the semiconductor layer 41 of each memory pillar MP and each contact C3. This forms a structure similar to the conductive layer 51 shown in Figures 8 and 9. As shown in Figure 23, the end of the conductive layer 51 in the BL direction is included in the insulating region BA. As shown in Figure 24, the edges of the conductive layer 51 in the WL direction are included in the dummy region DAc.

[0099] Next, as shown in Figure 25, the insulating member 301 is formed (step ST108). Specifically, the insulating member 301 is embedded in the opening SLA+BA (source line region SLA and insulating region BA) by the process in step ST108. Subsequently, the surface of the insulating member 301 is flattened by CMP or the like.

[0100] Next, vias VA and VB are formed (step ST109). Specifically, first, a mask is formed with openings for vias VA and VB in a plan view. Then, the insulating member 301 is removed from the openings in the mask by anisotropic etching, and vias VA and VB are formed. At the bottom of each of vias VA and VB, the surface of the conductive layer 51 is exposed.

[0101] Next, as shown in Figure 26, a conductive layer 302 is formed (step ST110). The conductive layer 302 is formed, and vias VA and VB (not shown) are embedded. Subsequently, the conductive layer 302 is processed into the desired shape by photolithography and etching. The conductive layer 302 may also be formed using the damascene method.

[0102] Subsequently, insulating layers 303, 304, and 305 are formed (step ST111), and via TVs are formed (step ST112). This completes the structure of the memory device 1 shown in Figures 8 and 9.

[0103] <1-3> Effects of the First Embodiment According to the memory device 1 of the first embodiment described above, the chip size can be reduced, and the manufacturing cost of the memory device 1 can be suppressed. The effects of the memory device 1 of the first embodiment will be explained below using comparative examples.

[0104] Figure 27 is a plan view showing an example of a planar layout of a memory device 1X according to a comparative example of the first embodiment. Figure 27 shows an example of the arrangement of conductive layers 51, 302A, and 302B in two adjacent core regions CR1 and CR2 in the Y direction and the peripheral region PR between them. As shown in Figure 27, a conductive layer 51 corresponding to the source line SL is arranged in each core region CR. In the peripheral region PR, multiple conductive layers 51 are arranged separately from the conductive layers 51 of each core region CR. The conductive layer 51 of each core region CR is connected to the conductive layer 302A via via VA. The conductive layer 302A is connected to the conductive layer 51 arranged in the peripheral region PR via via VB in the peripheral region PR. Multiple conductive layers 302B used as power lines PL may be connected to the conductive layer 51 in the peripheral region PR via via VB, similar to the conductive layer 302A. The conductive layer 302B may be positioned overlapping with one of the core regions CR1 and CR2, or it may be positioned overlapping with both the core regions CR1 and CR2.

[0105] Figure 28 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1X according to a comparative example of the first embodiment. As shown in Figure 28, the source line SL in the comparative example of the first embodiment is connected to contact C3 located in the peripheral region PR via the conductive layer 51 in the active region AA, the conductive layer 302A, vias VA and VB, and the conductive layer 51 in the peripheral region PR. That is, the connection path between the source line SL and transistor TR2 goes through the conductive layer 302A. In the comparative example of the first embodiment, the source line region SLA and the insulating region BA are opened separately. Although not shown, the insulating region BA in the comparative example of the first embodiment is provided in the portion that divides the semiconductor layer 22, member 23 and semiconductor layer 24 plane by plane, the portion where contact C3 is located and the portion where via TV is located. For this reason, in the comparative example of the first embodiment, the semiconductor layer 22 remains in most of the peripheral region PR.

[0106] In contrast, the memory device 1 according to the first embodiment has a configuration in which the conductive layer 51 used as the source line SL is directly connected to the contact C3 without going through the conductive layer 302A. Figure 29 is a plan view showing an example of the planar layout of the memory device according to the first embodiment, and shows the same area as in Figure 27. As shown in Figure 29, in the first embodiment, the conductive layer 51 of each core region CR is connected to the contact C3 in the peripheral region PR without going through the conductive layer 302A. As a result, in the memory device 1 according to the first embodiment, the portion of the conductive layer 302A used to connect the conductive layer 302A to the contact C3 in the peripheral region PR in the comparative example of the first embodiment is omitted, and becomes an empty region. As a result, in the memory device 1 according to the first embodiment, the free area created by omitting a portion of the conductive layer 302A can be used for other purposes. In other words, the memory device 1 according to the first embodiment can have improved design flexibility. Therefore, the memory device 1 according to the first embodiment can reduce the chip size as the design efficiency increases, and the manufacturing cost of the memory device 1 can be suppressed.

[0107] In the memory device 1 according to the first embodiment, the semiconductor layer 22 within the contact region CA remains. This prevents the oxide film within the columnar member HR from being etched during the process of removing the laminated film 42. As a result, the memory device 1 according to the first embodiment has a shorter distance between the source line SL and the selected gate line SGS, which reduces the risk of breakdown failure.

[0108] <2> Second Embodiment The memory device 1A according to the second embodiment has a configuration in which the shunt wiring of the source line SL is omitted compared to the memory device 1 according to the first embodiment. The details of the memory device 1A according to the second embodiment will be described below, mainly focusing on the differences from the first embodiment.

[0109] <2-1> Composition The configuration of the memory device 1A according to the second embodiment will be described below.

[0110] (1: Planar layout of conductive layer 302) Figure 30 is a plan view showing an example of the planar layout of the conductive layer 302 in the memory device 1A according to the second embodiment. As shown in Figure 30, the memory device 1A according to the second embodiment has a configuration in which the conductive layer 302A used as shunt wiring for the source line SL is omitted compared to the memory device 1 according to the first embodiment. In this example, each conductive layer 302B is provided extending from the outer peripheral end of the memory device 1A in the core regions CR1 and CR3 to the outer peripheral end of the memory device 1A in the core regions CR2 and CR4. The arrangement of the conductive layer 302B in the memory device 1A can be appropriately changed according to the layout of the pad portion PD (not shown) and the CMOS circuit.

[0111] (2: Cross-sectional structure of memory device 1A) Figure 31 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1A according to the second embodiment. As shown in Figure 31, the memory device 1A according to the second embodiment omits the conductive layer 302A and the via VA set compared to the memory device 1 according to the first embodiment described with reference to Figure 8. The conductive layer 302B, which is used as a power line PL, is arranged above the stack corresponding to the memory cell array 10. In the memory device 1A, it is preferable that the conductive layer 51 is provided with lower resistance than in the first embodiment. For example, if the conductive layer 51 of the second embodiment and the conductive layer 51 of the first embodiment have the same material composition, the conductive layer 51 of the second embodiment is provided thicker than the conductive layer 51 of the first embodiment. As the conductive layer 51 of the second embodiment, for example, a metal material mainly composed of aluminum (Al) is used. The other configurations of the memory device 1A according to the second embodiment are the same as those of the memory device 1 according to the first embodiment.

[0112] <2-2> Effects of the second embodiment The memory device 1A according to the second embodiment can increase the free space due to the omission of the conductive layer 302A compared to the first embodiment. As a result, the memory device 1A according to the second embodiment can improve design flexibility and reduce chip size. Therefore, the memory device 1A according to the second embodiment can reduce manufacturing costs compared to the first embodiment.

[0113] <3> Third Embodiment The memory device 1B according to the third embodiment has a configuration in which a part of the conductive layer 51 and via TV are arranged to overlap in the Z direction, compared to the memory device 1 according to the first embodiment. The details of the memory device 1B according to the third embodiment will be described below, mainly focusing on the differences from the first and second embodiments.

[0114] <3-1> Composition The configuration of the memory device 1B according to the third embodiment will be described below.

[0115] (1: Planar layout near the pad PD) Figure 32 is a plan view showing an example of a planar layout near the pad portion PD in the memory device 1B according to the third embodiment. Figure 32 shows the pad portion PD used for connecting to input / output circuits 11 and logic controllers 12 in the memory device 1B, and parts of the core region CR2 and peripheral region PR in its vicinity. As shown in Figure 32, the memory device 1B according to the third embodiment differs from the memory device 1 according to the first embodiment in that the via TV overlaps in the Z direction with the conductive layer 51 used as part of the source line SL. In addition, the via TV in the third embodiment overlaps in the Z direction with at least one contact C3 connected to the source line SL. Furthermore, in this example, as in the second embodiment, the conductive layer 302A and via VA used as shunt wiring for the source line SL may be omitted.

[0116] (2: Cross-sectional structure near the pad portion PD) Figure 33 is a cross-sectional view along the line XXXIII-XXXIII in Figure 32, showing an example of the cross-sectional structure near the pad portion PD in the memory device according to the third embodiment. As shown in Figure 33, in the memory device 1B according to the third embodiment, the portion of the conductive layer 302B whose surface is exposed through via TV has a portion that overlaps in the Z direction with the conductive layer 51 used as the source line SL and the contact C3, respectively. In this example, the case in which the conductive layer 302B has a portion that extends into the active region AA is illustrated, but the device is not limited to this. In the memory device 1B, at least a portion of the conductive layer 51 used as the source line SL has a portion that overlaps with via TV in the Z direction. The other configurations of the memory device 1B according to the third embodiment are the same as those of the memory device 1 according to the first embodiment.

[0117] <3-2> Effects of the Third Embodiment The memory device 1B according to the third embodiment can improve the design flexibility of the via TV compared to the first embodiment. As a result, the memory device 1B according to the third embodiment can reduce the chip size and lower the manufacturing cost of the memory device 1B compared to the first embodiment.

[0118] <4> Fourth Embodiment The memory device 1C according to the fourth embodiment has a configuration in which the semiconductor layer 46 of the memory pillar MP and the metal material used as part of the source line SL are directly connected, as in the memory device 1A according to the second embodiment. The details of the memory device 1B according to the fourth embodiment will be described below, mainly focusing on the differences from the first to third embodiments.

[0119] <4-1> Composition The configuration of the memory device 1C according to the fourth embodiment will be described below.

[0120] (1: Cross-sectional structure of memory device 1C in the BL direction) Figure 34 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1C according to the fourth embodiment. As shown in Figure 34, the memory device 1C has a configuration in which the semiconductor layer 24 of the source line region SLA is replaced with a semiconductor layer 60, and the semiconductor layer 50 and the conductive layer 51 are replaced with a conductive layer 61, compared to the memory device 1 according to the first embodiment.

[0121] The semiconductor layer 60 corresponds to the impurity-doped semiconductor layer 24. The conductive layer 61 is made of a metallic material. The conductive layer 61 includes, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), and aluminum (Al). Similar to the conductive layer 51 of the first embodiment, the conductive layer 61 has a portion that covers the upper part of the semiconductor layer 46 of each memory pillar MP and a portion that covers the upper part of the insulating member 30. The conductive layer 61 is in contact with the semiconductor layer 46 of each memory pillar MP and is electrically connected to the semiconductor layer 46 of each memory pillar MP. In other words, the semiconductor layer 46 of each memory pillar MP is electrically connected to the transistor TR2 via the conductive layer 61, at least one contact C3, conductive layers 33-35 and 103-105, and contacts V1, V2, C1 and C2.

[0122] (2: Cross-sectional structure of memory device 1C in the WL direction) Figure 35 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1C according to the fourth embodiment. Figure 35 shows a part of the contact area CA, the dummy area DAc, and the storage area SA, and displays coordinate axes with respect to the semiconductor substrate W1. As shown in Figure 35, the dummy area DAc of the fourth embodiment includes the edge of the conductive layer 61. In the dummy area DAc, the edge of the conductive layer 61 has a portion provided along the insulating layer 21. The conductive layer 61 has a portion that covers a part of the insulating layer 21. In the portion of the conductive layer 61 that covers a part of the insulating layer 21, it is separated from the dummy pillar DMP. The other configurations of the memory device 1C according to the fourth embodiment are the same as those of the memory device 1 according to the first embodiment.

[0123] <4-2> Manufacturing method Next, as a method for manufacturing the memory device 1C according to the fourth embodiment, the method for forming the source line SL and wiring layer 300 after joining the semiconductor substrate W1 and semiconductor substrate W2 will be described with reference to Figure 36 as appropriate. Figure 36 is a flowchart showing an example of a method for manufacturing the memory device 1C according to the fourth embodiment. Figures 37 to 43 are cross-sectional views showing an example of a cross-sectional structure in the manufacturing process of the memory device 1C according to the fourth embodiment. Figures 37, 39, 40, 42, and 43 correspond to a cross-section along the BL direction and show the same region as in Figure 34. Figures 38 and 41 correspond to a cross-section along the WL direction and show the same region as in Figure 35.

[0124] First, similar to the first embodiment, semiconductor substrate W2 is removed from semiconductor substrates W1 and W2 after bonding (step ST101), and the opening SLA+BA is formed (step ST102). At this point, the structure described with reference to Figures 19 and 20 in the first embodiment is formed.

[0125] Next, ion implantation and annealing are performed (step ST201). This process is performed on the opening SLA+BA. Specifically, first, impurities are implanted into the upper part of each memory pillar MP by ion implantation. Then, the implanted impurities diffuse into the upper part of the semiconductor layer 41 by annealing. In Figures 37 and 38, the semiconductor layer 41 doped with impurities in this way is shown as semiconductor layer 46. In this process, the semiconductor layer 24 that was exposed at the opening SLA+BA may also be doped with impurities. In Figures 37 and 38, the semiconductor layer 24 doped with impurities in this way is shown as semiconductor layer 60. The impurities doped into the semiconductor layer 41 by this process are, for example, at least one of phosphorus (P) and arsenic (As).

[0126] Next, the semiconductor layer 60 of the insulating region BA is removed (step ST202). This exposes the surface of the insulating layer 210 and the upper part of at least one contact C3 provided in the insulating region BA. The portion of the opening SLA+BA that does not overlap with the insulating region BA corresponds to the source line region SLA.

[0127] Next, as shown in Figure 39, the laminated film 42 on the upper part of the memory pillar MP is removed (step ST203). Specifically, for example, the laminated film 42 located above the semiconductor layer 60 in the source line region SLA is selectively removed by wet etching. As a result, the semiconductor layer 46 on the upper part of each memory pillar MP and the semiconductor layer 46 on the upper part of each dummy pillar DMP are exposed in the source line region SLA.

[0128] Next, as shown in Figures 40 and 41, a conductive layer 61 is formed (step ST204). Specifically, first, the conductive layer 61 is formed on the surface of the semiconductor layer 60, the insulating layer 210, and the insulating layer 21 by CVD or the like. The conductive layer 61 has a portion that covers the upper part of the semiconductor layer 46 of each memory pillar MP, a portion that covers the upper part of the semiconductor layer 46 of each dummy pillar DMP, and a portion that covers the upper part of each contact C3. After that, a mask is formed, and the conductive layer 61 is processed by an anisotropic etching process. The conductive layer 61 processed in this step is provided to electrically connect, for example, the semiconductor layer 46 of each memory pillar MP and each contact C3. This forms a structure similar to the conductive layer 61 shown in Figures 34 and 35. As shown in Figure 40, the end of the conductive layer 61 in the BL direction is included in the insulating region BA. As shown in Figure 41, the edges of the conductive layer 61 in the WL direction are included in the dummy region DAc.

[0129] Next, as shown in Figure 42, an insulating member 301 is formed in the insulating region BA (step ST108). Through the process in step ST108, the insulating member 301 is embedded in the opening SLA+BA (source line region SLA and insulating region BA). Subsequently, the surface of the insulating member 301 is flattened by CMP or the like.

[0130] Next, vias VB are formed (step ST205). Note that in the fourth embodiment, vias VB are provided, for example, near the pad portion PD, and are therefore not shown in Figures 34 and 43. Then, as shown in Figure 43, a conductive layer 302 is formed, similar to the first embodiment (step ST110). The vias VB are embedded by the formation of the conductive layer 302. After that, insulating layers 303, 304 and 305 are formed (step ST111), and vias TV are formed (step ST112). This completes the structure of the memory device 1C shown in Figures 34 and 35.

[0131] <4-3> Effects of the fourth embodiment The memory device 1C according to the fourth embodiment has a configuration in which a semiconductor layer 46 doped with impurities and a conductive layer 61 used as a source line SL are directly connected on the upper part of each memory pillar MP. As a result, the memory device 1C according to the fourth embodiment can reduce the manufacturing cost of the memory device 1C. Furthermore, similar to the second embodiment, the memory device 1C according to the fourth embodiment can omit the shunt wiring (conductive layer 302A) of the source line SL, thereby improving design flexibility. Consequently, the memory device 1C according to the fourth embodiment can have a smaller chip size than the first embodiment.

[0132] <5> Fifth Embodiment The memory device 1D according to the fifth embodiment relates to another method of using the conductive layer 51 described in the memory device 1 according to the first embodiment. The details of the memory device 1D according to the fifth embodiment will be described below, mainly focusing on the differences from the first to fourth embodiments.

[0133] <5-1> Composition The configuration of the memory device 1D according to the fifth embodiment is described below.

[0134] (1: Cross-sectional structure of memory device 1D) Figure 44 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1D according to the fifth embodiment. Figure 44 shows an extracted portion of the peripheral region PR of the memory device 1D according to the fifth embodiment, and displays coordinate axes with respect to a semiconductor substrate W1 (not shown). As shown in Figure 44, two conductive layers 302B1 and 302B2 are aligned in the X direction. Each of the conductive layers 302B1 and 302B2 is used as a power line PL with a different potential from each other. For example, a ground voltage VSS is applied to the conductive layer 302B1. The conductive layer 302B1 has a portion along via VB and is electrically connected to the conductive layer 51 below. Conductive layer 302B2 and conductive layer 51 are separated by an insulating member 301. The illustrated conductive layer 51 has a portion that extends in the X direction and overlaps with conductive layers 302B1 and 302B2 in the Z direction.

[0135] In this example, the memory layer 200 includes a conductive layer 33SH. The conductive layer 33SH is a wiring provided on the same layer as the conductive layer 33. The conductive layer 33SH is used as shielding wiring. The conductive layer 33SH can, for example, suppress the propagation of noise generated in the CMOS circuit on the semiconductor substrate W1 to the bit line BL.

[0136] The illustrated conductive layer 51 is electrically connected to the circuit in the CMOS layer 100 via at least one contact C3 that overlaps with conductive layer 302B1 in the Z direction, conductive layers 33-35 and 105, and contacts V1 and V2. The illustrated conductive layer 51 is also electrically connected to conductive layer 33SH via at least one contact C3 that overlaps with conductive layer 302B2 in the Z direction, conductive layer 35, and contact V1.

[0137] Furthermore, Figure 44 illustrates a plurality of bonding pads BP and DBP arranged in the Y direction. The plurality of bonding pads BP and DBP include bonding pad BP used for connecting circuits between the memory layer 200 and the CMOS layer 100, and bonding pad DBP corresponding to dummy patterns. In the memory device 1D according to the fifth embodiment, the bonding pad DBP and the conductive layer 33SH are separated by an insulating layer 28.

[0138] (2: Planar layout of conductive layers 33 and 33SH) Figure 45 is a plan view showing an example of a planar layout of a conductive layer in a memory device 1D according to the fifth embodiment. As shown in Figure 45, the conductive layer 33SH has a mesh-like portion. The conductive layer 33 is surrounded by the conductive layer 33SH. The conductive layer 33SH and the conductive layer 33 are separated in a plan view. The conductive layer 33SH may surround multiple conductive layers 33. The conductive layer 33SH is mainly arranged in the peripheral region PR. The conductive layer 33SH may have other shapes as long as it functions as shield wiring. For example, the conductive layer 33SH may be formed in a plate shape.

[0139] <5-2> Manufacturing method Next, the manufacturing method of the memory device 1D according to the fifth embodiment will be described, from the formation of the conductive layers 33 and 33SH to the formation of the conductive layer 302, with appropriate reference to Figure 17. Some steps of the memory device 1D according to the fifth embodiment can be manufactured by a flow similar to the flowchart described using Figure 17 in the first embodiment. Figures 46 to 51 are cross-sectional views showing an example of the cross-sectional structure in the manufacturing process of the memory device 1D according to the fifth embodiment. Figures 46 to 51 show the same region as in Figure 44, but unlike Figure 44, Figures 46 and 47 show coordinate axes based on the semiconductor substrate W2 before bonding.

[0140] First, as shown in Figure 46, an insulating layer 281 is formed on the insulating layer 27, and conductive layers 33 and 33SH are formed on the insulating layer 281 so as to be connected to the conductive layer 35 via contact V1 within the insulating layer 28. Then, an insulating layer 282 is provided so as to cover the conductive layers 33 and 33SH and the contact V2 formed on the conductive layer 33. The set of insulating layers 281 and 282 corresponds to the insulating layer 28 shown in Figure 44. The conductive layers 33 and 33SH and contacts V1 and V2 are formed above the semiconductor substrate W2 before bonding, simultaneously with the structure within the insulating layer 28 on the bit line BL, which is not shown. Then, an insulating layer 29 is formed on the insulating layer 282, and a conductive layer 34 is formed, for example, by the damascene method. As a result, the structure shown in Figure 47 is formed on the semiconductor substrate W2.

[0141] Next, as shown in Figure 48, semiconductor substrates W1 and W2 are joined together. Specifically, a bonding layer B1 formed using semiconductor substrate W1 and a bonding layer B2 formed using semiconductor substrate W2 are bonded together. This joins the opposing conductive layers 34 and 105. During the bonding process, the conductive layer 33SH and the bonding pad DBP corresponding to the dummy pattern are electrically insulated. Subsequently, for example, steps ST101 to ST106 described in the first embodiment are performed. As a result, as shown in Figure 49, the upper part of each contact C3 is exposed. The upper part of each contact C3 protrudes above the insulating layer 27.

[0142] Next, the conductive layer 51 is formed as shown in Figure 50 by performing the process of step ST107 as described in the first embodiment. The shown conductive layer 51 connects the contact C3 provided above the conductive layer 33SH and the contact C3 provided above the conductive layer 33. Subsequently, for example, the insulating member 301 and the conductive layers 302B1 and 302B2 are formed as shown in Figure 51 by performing the processes of steps ST108 to ST110 as described in the first embodiment. Other manufacturing methods of the memory device 1D according to the fifth embodiment are, for example, the same as in the first embodiment.

[0143] <5-3> Effects of the Fifth Embodiment The memory device 1D according to the fifth embodiment described above can improve yield and reduce the manufacturing cost of the memory device 1D. The effects of the memory device 1D according to the fifth embodiment will be explained below using comparative examples.

[0144] Figure 52 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 1Y according to a comparative example of the fifth embodiment. As shown in Figure 52, in the comparative example of the fifth embodiment, the conductive layer 33SHa used as shield wiring is electrically connected to contact C3 directly below via VB. In the comparative example of the fifth embodiment, in order to use the conductive layer 33SHa as shield wiring, the conductive layer 33SHa is connected to conductive layer 302, which is used as a power line PL to which the ground voltage VSS is applied. In addition, the conductive layer 33SHa is connected to bonding pad BP via contact V2.

[0145] During the manufacturing process of the memory device 1Y, the bonding pad BP is connected to the floating conductive layer 33SHa. When the bonding pad BP is connected to a long-distance wiring in a floating state in this way, Cu corrosion may occur during CMP and pre-bonding processing, potentially leading to open-circuit failures. Therefore, there are certain constraints on the wiring length of the conductive layer 33SHa. In addition, contact C3 is located directly beneath the conductive layer 302 at the same node. Therefore, there are certain constraints on the placement of contact C3.

[0146] In contrast, in the memory device 1D according to the fifth embodiment, the conductive layer 33SH, which is a long-distance wiring, and the conductive layer 302B1 are connected by utilizing the conductive layer 51 described in the first embodiment. In the memory device 1D according to the fifth embodiment, since the conductive layer 33SH is connected to the conductive layer 302B1 in the back wiring process after the bonding process, even if the conductive layer 33SH is a long-distance wiring, the occurrence of corrosion when connected to the bonding pad BP can be suppressed. Therefore, the memory device 1D according to the fifth embodiment can suppress the occurrence of defects in the bonding pad BP and improve yield.

[0147] Furthermore, the contact C3 connected to the conductive layer 302B1 may be positioned directly beneath the conductive layer 302B2 at a different potential. As a result, the memory device 1D according to the fifth embodiment can improve design flexibility and reduce chip size. Therefore, the memory device 1D according to the fifth embodiment can reduce manufacturing costs.

[0148] <6> Variations, etc. The memory device 1 described above can be modified in various ways.

[0149] The concepts described in the above embodiments can be combined as appropriate. For example, the second embodiment may be combined with the third embodiment. The fourth embodiment may be combined with the second and third embodiments. The fifth embodiment may be combined with the second to fourth embodiments.

[0150] In the above embodiment, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 can be modified as appropriate. Other contacts may be inserted between the memory pillar MP and the conductive layer 32. Other contacts may be inserted between contact C3 and the conductive layer 35. Conductive layers may be inserted at the connection points of multiple contacts. The number of wiring layers and contacts provided by the memory device 1 can be modified as appropriate depending on the circuit design. The memory pillar MP and each contact may have a tapered shape, an inverse tapered shape, or a bowed shape. The XY cross-sectional structure of the memory pillar MP may be circular or elliptical. Each wiring in the multilayer wiring may include a metal oxide film around a conductor such as tungsten. Conductive layers that are alternately stacked with insulating layers in the multilayer wiring may be considered to include such a metal oxide film.

[0151] In this specification, “connection” means that an electrical connection is made, and does not exclude, for example, the interposition of another element. “Electrically connected” may be via an insulator, as long as it is possible to operate in the same manner as an electrically connected connection. “Semiconductor substrate” may simply be called “substrate.” “Semiconductor layer” may be called “conductor layer.” “Region” may be considered as a configuration included by the substrate. For example, if semiconductor substrate W1 is defined to include a storage region SA and a contact region CA, then the storage region SA and the contact region CA are associated with different regions above the semiconductor substrate W1, respectively. “Height” corresponds to, for example, the distance in the Z direction between the configuration under measurement and the semiconductor substrate W1. A configuration other than the semiconductor substrate W1 may be used as the reference for “height.” “Top view” corresponds to, for example, viewing the surface of the semiconductor substrate W1 from the vertical direction of the semiconductor substrate W1. “Via” may be called an opening.

[0152] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0153] 1, 1A, 1B, 1C, 1D, 1X, 1Y…Memory device, 2…Memory controller, 10…Memory cell array, 11…Input / output circuit, 12…Logic controller, 13…Register circuit, 14…Programmable Logic Controller, 15…Driver circuit, 16…Raw decoder module, 17…Sense amplifier module, 21, 25~29, 110, 111, 210, 281, 282, 303, 304, 305…insulating layer, 22, 24, 41, 46, 50, 60…semiconductor layer, 23…component, 30, 301…insulating component, 31~35, 33SH, 51, 51A, 61, 103~105, 302, 302A, 302B, 302B1, 302B2…conductive layer, 40…core component, 42…laminated film, 43…tunnel insulating film, 44…insulating film, 45…block Block insulating film, 100...CMOS layer, 101...Gate insulating film, 102...Gate electrode, 200...Memory layer, 300...Wiring layer, B1, B2...Junction layer, C0~C3, V1, V2...Contact, CR...Core area, PR...Peripheral area, WR...Wall area, KR...Calf area, SA...Storage area, CA...Contact area, AA...Active area, DAr, DAc...Dummy area, DS...Dummy stair section, VA, VB, TV...Via, BA...Insulating area, W1, W2...Semiconductor substrate, BLK...Block, DBLK...Dummy block, SL...Source line, BL...Bit line, WL...Word line, MT...Memory cell transistor, ST1, ST2...Selection transistor, RD...Row decoder, SAU...Sense amplifier unit, TR1~TR4...Transistor

Claims

1. A memory device having a bonding surface, A substrate having a first region and a second region aligned in a first direction, A first circuit layer including a CMOS circuit is provided between the substrate and the bonding surface, A second circuit layer is provided above the aforementioned bonding surface, The second circuit layer has a memory cell array including a laminate containing first insulating layers and first conductive layers alternately stacked in a second direction intersecting the first direction within the first region, and a plurality of first pillars penetrating the laminate in the second direction and electrically connected to source lines above the laminate, and includes at least one first contact having a portion provided at the same height as the laminate within the second region and electrically connected to the CMOS circuit, The source line includes a second conductive layer having a portion in the first region that covers the upper part of each of the plurality of first pillars included in the memory cell array, and a portion in the second region that covers the upper part of the at least one first contact, wherein the second conductive layer electrically connects the plurality of first pillars and the at least one first contact, and the surface of the second conductive layer is provided in a non-planar manner above at least one of the plurality of first pillars and the at least one first contact. Memory device.

2. The laminate further includes a first semiconductor layer provided between the uppermost first conductive layer and the second conductive layer, which functions as part of the source line, and the second conductive layer has a portion provided along the side surface of the first semiconductor layer within the second region. The memory device according to claim 1.

3. Each of the plurality of first pillars includes a second semiconductor layer extending in the second direction, and the source line further includes a third semiconductor layer provided between the laminate and the second conductive layer and having a portion along the upper part of each of the plurality of first pillars, the third semiconductor layer being in contact with the second semiconductor layer of each of the plurality of first pillars. The memory device according to claim 1.

4. Each of the plurality of first pillars includes a second semiconductor layer extended in the second direction, and the second conductive layer is in contact with the second semiconductor layer of each of the plurality of first pillars. The memory device according to claim 1.

5. A memory device having a bonding surface, A substrate having a first region and a second region aligned in a first direction, A first circuit layer including a CMOS circuit is provided between the substrate and the bonding surface, A second circuit layer is provided above the aforementioned bonding surface, The second circuit layer includes a laminate containing first insulating layers and first conductive layers alternately stacked in a second direction intersecting the first direction within the first region; a plurality of first pillars penetrating the laminate in the second direction within the first region and electrically connected to a source line above the laminate; a bit line provided below the laminate within the first region and electrically connected to one of the plurality of first pillars; a second conductive layer provided between the bit line and the joint surface within the first region; third and fourth conductive layers provided at the same height as the second conductive layer within the second region and spaced apart from each other; a fifth conductive layer provided at the same height as the source line within the second region; and first and second contacts having portions provided at the same height as the laminate within the second region. The third conductive layer is electrically connected to the fifth conductive layer via the first contact. The fourth conductive layer is electrically connected to the fifth conductive layer via the second contact. The fifth conductive layer is electrically connected to the CMOS circuit via the second contact and the fourth conductive layer, but is not electrically connected to the CMOS circuit via the first contact and the third conductive layer. Memory device.

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