Information processing systems and memory systems

Abstract

Provided are an information processing system and a memory system with improved writing performance. 【Solution means】 The memory system includes a non-volatile memory having a plurality of memory cells, a host device that manages the size of write data to be written to the non-volatile memory, and a memory controller that manages the free capacity writable in SLC of the non-volatile memory. When the size of the write data exceeds the free capacity writable in SLC, the non-volatile memory stores the data by writing data in XLC (XLC is a write mode with a larger number of bits than SLC) per memory cell.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an information processing system and a memory system.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memory have become widespread. In a memory system, for example, NAND-type flash memory is used as the non-volatile memory. In such a memory system, a multi-valued technology for realizing a large capacity of the non-volatile memory has been introduced.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide an information processing system and a memory system with improved write performance.

Means for Solving the Problems

[0005] The memory system according to this embodiment includes a non-volatile memory having a plurality of memory cells, a host device that manages the size of the data to be written to the non-volatile memory, and a memory controller that manages the free space of the non-volatile memory that can be written using SLC. The non-volatile memory stores data by writing XLC (XLC is a write mode with a larger number of bits than SLC) per memory cell when the size of the data to be written exceeds the free space that can be written using SLC. [Brief explanation of the drawing]

[0006] [Figure 1] This block diagram shows the configuration of an information processing system according to one embodiment. [Figure 2] This is a block diagram showing the memory configuration of an information processing system according to one embodiment. [Figure 3] This is a perspective view showing the configuration of a memory cell array according to one embodiment. [Figure 4] This is a cross-sectional view showing the configuration of a memory cell according to one embodiment. [Figure 5] This is a circuit diagram showing the configuration of a memory cell array according to one embodiment. [Figure 6] This flowchart shows a method for optimizing the write performance of an information processing system according to one embodiment. [Figure 7] This figure shows an example of the operation sequence of an information processing system according to one embodiment. [Figure 8] This figure shows an example of the operation sequence of an information processing system related to one modification. [Figure 9] This figure shows an example of the operation sequence of an information processing system according to one embodiment. [Modes for carrying out the invention]

[0007] The information processing systems and memory systems of each embodiment will be described below with reference to the drawings. In the following description, components having the same or similar functions and configurations will be given common reference numerals. When distinguishing between multiple components having common reference numerals, subscripts (for example, uppercase letters, numbers, hyphens and uppercase letters and numbers, etc.) will be added to the common reference numerals, and redundant descriptions may be omitted.

[0008] <First Embodiment> <1-1. Overall Configuration of the Information Processing System> Referring to Figure 1, the overall configuration of the information processing system 1, including the memory system according to this embodiment, will be described. Figure 1 is a block diagram illustrating the configuration of the information processing system 1. The information processing system 1 includes a memory system 2 and a host device 3. The memory system is also referred to as a memory device or a memory card.

[0009] Memory system 2 is configured to communicate with host device 3 based on a client-server model. Memory system 2 acts as the target, and host device 3 acts as the initiator. More specifically, memory system 2 is a UFS memory device, and host device 3 is a host device that supports UFS memory devices. Host device 3 may be, for example, a system-on-chip (SoC) device, and may be a device installed in a smartphone or digital camera, etc.

[0010] The memory system 2 includes a plurality of non-volatile semiconductor memories 11 (hereinafter referred to as "memories") and a controller 12 for controlling the memories 11. The controller 12 controls each of the plurality of memories 11.

[0011] Memory 11 performs data writing and reading operations in specific write units consisting of multiple bits. Furthermore, memory 11 erases data in erase units consisting of multiple write units. For example, memory 11 consists of one or more NAND flash memories. Each NAND flash memory contains multiple blocks, and each block contains multiple pages. If memory 11 is a NAND flash memory, memory 11 performs write and read operations in page units and erases in block units.

[0012] When the memory cell's write mode is SLC (Single Level Cell), one page is composed of multiple memory cells connected to one word line. When the memory cell's write mode is MLC (Multi Level Cell), two pages (2 bits (2) are composed of multiple memory cells connected to one word line. 2 If it is a TLC (Triple Level Cell), then 3 pages (3 bits (2) are made up of multiple memory cells connected to one word line. 3 If it is a QLC (Quad Level Cell), then four pages (4 bits (2) are made up of multiple memory cells connected to one word line. 4 A configuration of 16 values ​​is formed. If the memory cell is a multi-bit cell, multiple pages can be supported by setting a single memory cell to a multi-bit threshold voltage.

[0013] The capacity of a memory cell depends on its write mode (number of bits). The capacity of a memory cell increases with the number of bits. The capacity of memory cells is greater for MLC than for SLC, greater for TLC than for MLC, and greater for QLC than for TLC. The write mode of a memory cell is set on a block-by-block basis. Each block is set to one of the following write modes: SLC, MLC, TLC, or QLC.

[0014] The write speed of a memory cell depends on the write mode (number of bits) of the memory cell. The write speed of a memory cell decreases as the number of bits increases. The write speed of a memory cell is lower for MLC than for SLC, lower for TLC than for MLC, and lower for QLC than for TLC.

[0015] Generally, as data writing to the memory 11, when the memory 11 includes QLC (4 bits / cell) memory cells, it may be written in QLC from the beginning. In order to improve the response performance to the host device 3, since the write speed is slow in QLC, the write data transferred from the host device 3 is once written in SLC, and then the data written in SLC is written to another block in QLC. Also, depending on the size of the write data and the free block availability described later, there may be a case where there are not enough free blocks and it is necessary to secure free blocks by the garbage collection (GC) process described later, resulting in a time-consuming write. Such a general method of writing data to the memory 11 is also referred to as writing in the normal write mode. In this embodiment, in addition to writing in the normal write mode, in order to be able to execute data writing by a more optimal writing method according to the size of the write data, it is possible to select writing in the write optimization mode.

[0016] Hereinafter, the case where the memory 11 is a three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked above a semiconductor substrate will be described. Note that the memory is not limited to a three-dimensional stacked NAND flash memory, and may be a planar NAND flash memory in which memory cell transistors are two-dimensionally arranged on a semiconductor substrate, or another non-volatile memory. Details of the memory 11 will be described later.

[0017] Memory system 2 includes I / O 21, core logic unit 22, and I / O 23. I / O 21 includes hardware configuration for memory system 2 to connect to host device 3. Memory system 2 is connected to host device 3 via a host bus. If information processing system 1 conforms to the UFS standard, the host bus corresponds to a serial interface. Signals transmitted and received between memory system 2 and host device 3 include RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c. RESET, REF_CLK, DOUT, DOUT_c, DIN, and DIN_c are communicated between host device 3 and I / O 21 via the host bus. RESET is a hardware reset signal. REF_CLK is a reference clock signal. DOUT and DOUT_c are signals that form a differential signal pair and are transmitted from host device 3 to memory system 2. DIN and DIN_c are signals that form a differential signal pair and are transmitted from memory system 2 to host device 3.

[0018] The core logic unit 22 is the main part of the controller 12, excluding I / O 21 and I / O 23. I / O 23 includes the hardware configuration for the controller 12 to connect to the memory 11.

[0019] The core logic unit 22 includes a host interface 31, a buffer 32, a data bus 33, a memory interface 34, a buffer 35, an ECC circuit (error correcting code) 36, a control bus 41, a CPU (central processing unit) 42, a ROM (read-only memory) 43, a RAM (random access memory) 44, and registers 45.

[0020] I / O21 is connected to the host interface 31. The host interface 31 performs the necessary processing for communication between the memory system 2 and the host device 3. More specifically, the host interface 31 handles communication between the memory system 2 and the host device 3 in accordance with the communication protocol to which both the memory system 2 and the host device 3 comply. If the memory system 2 is a UFS memory device, for example, the host interface 31 is a UFS interface. The UFS interface conforms to the M-PHY standard for the physical layer and the UniPro standard for the link layer.

[0021] The host interface 31 is connected to the buffer 32. The buffer 32 receives data sent from the host device 3 to the memory system 2 via the host interface 31 and temporarily holds it. The buffer 32 also temporarily holds data sent from the memory system 2 to the host device 3 via the host interface 31. The buffer 32 is connected to the data bus 33.

[0022] I / O 23 is connected to the memory interface 34. The memory interface 34 performs the processing necessary for the controller 12 to communicate with the memory 11. More specifically, the memory interface 34 transmits instructions (control signals) from the core logic unit 22 in a form that the memory 11 can recognize. Furthermore, the memory interface 34 sends and receives signals DQ with the memory 11 and receives ready / busy signals R / Bn from the memory 11. Signal DQ includes, for example, data, address, and command. Signal R / Bn is a signal that indicates the memory 11 is busy. If the memory 11 is a NAND flash memory, the memory interface 34 is a NAND flash interface.

[0023] The memory interface 34 is connected to the buffer 35. The buffer 35 receives data transmitted from the memory 11 to the controller 12 via the memory interface 34 and temporarily holds it. The buffer 35 also temporarily holds data that is scheduled to be transmitted from the controller 12 to the memory 11 via the memory interface 34. The buffer 35 is connected to the data bus 33. Note that buffers 32 and 35 may be a single buffer. The memory interface 34 and buffer 35 are connected to the ECC circuit 36. The ECC circuit 36 ​​receives write data from the host device 3 via the data bus 33, adds an error correction code (hereinafter referred to as "parity") to the write data, and supplies the parity-corrected write data to the buffer 35. The ECC circuit 36 ​​also receives data supplied from the memory 11 via the buffer 35, performs error correction using the parity added to this data, and supplies the error-corrected data to the data bus 33.

[0024] The control bus 41 is connected to the CPU 42, ROM 43, RAM 44, and registers 45. The CPU 42, ROM 43, RAM 44, and registers 45 communicate with each other via the control bus 41.

[0025] The CPU 42 controls the overall operation of the memory system 2. The CPU 42 executes predetermined processes (such as write operations, read operations, or erase operations) according to the control programs (instructions) stored in the ROM 43. For example, the CPU 42 may execute predetermined processes on the memory 11 according to commands received from the host device 3.

[0026] When CPU42 receives a read request (instruction) from host device 3 that includes a command and a logical address, it reads the logical address translation data corresponding to the logical address to be read from the address translation table (lookup table LUT) stored in memory 11, which associates logical addresses with physical addresses, and translates the logical address to a physical address. The physical address identifies a part of the memory space in memory 11. It then instructs memory I / F34 to perform a read operation to read the data from that physical address. When CPU42 receives a write request from host device 3 that includes a command, write data, and a logical address, it assigns a new physical address corresponding to the logical address and manages the lookup table LUT. It then instructs memory I / F34 to perform a write operation to write the data to that physical address.

[0027] CPU42 also performs garbage collection (GC) processing. Garbage collection (GC) is a process to increase the number of usable blocks among the physical blocks. For example, it means collecting valid data from multiple active blocks that contain both valid and invalid data, rewriting it into another block, and securing free blocks. Here, an active block is a physical block in which valid data is recorded. A free block is a physical block in which no valid data is recorded. After erasure, a free block can be reused as an erased block. A free block includes both blocks before erasure (in which no valid data is recorded) and erased blocks. Valid data is data associated with a logical address (described later), while invalid data is data not associated with a logical address. An erased block becomes an active block when data is written to it. For example, CPU42 counts the number of free blocks, and if the number of free blocks is below a predetermined threshold, it performs GC. If the number of free blocks is greater than the predetermined threshold, CPU42 does not need to perform GC processing.

[0028] Furthermore, the CPU 42 manages the capacity of the free space in the memory cell array 108. For example, it obtains and manages the free capacity of each write mode in the active block and the capacity of the free block from the memory 11. The CPU 42 stores the write mode, free capacity, and free block capacity for a specific block, along with the physical address of each block, in the RAM 44. In other words, the RAM 44 functions as a capacity counter where capacity information is stored. The CPU 42 manages the capacity information by updating the capacity counter in accordance with the execution of write and erase operations. In other words, the CPU 42 updates the capacity counter based on the capacity information. The capacity counter manages the physical address of a block in association with the free capacity of each write mode in that block.

[0029] ROM43 stores control programs and other data that are executed by the CPU42. The programs stored in ROM43 are read by the CPU42 and executed as needed.

[0030] RAM44 is used as a work area for CPU42 and temporarily stores variables necessary for CPU42 operations (such as write data and read data). Furthermore, RAM44 may be provided with storage areas for various values ​​used during processing (for example, the physical address of a block and the free space for each write mode in that block) and various tables (for example, lookup tables LUTs). RAM44 may be located outside of controller12.

[0031] Register 45 holds various values ​​necessary for the operation of memory system 2. Register 45 also holds various values ​​necessary for host device 3 to control memory system 2. For example, register 45 holds the amount of data (dWriteDataSize) that host device 3 writes.

[0032] The control bus 41 is further connected to a host interface 31, a buffer 32, a memory interface 34, and a buffer 35. The CPU 42 controls the host interface 31, buffer 32, memory interface 34, and buffer 35 based on the control program and instructions from the host device 3. Furthermore, the controller 12 may be provided with an analog circuit 51 that functions as a voltage regulator to supply a stabilized voltage, for example.

[0033] <1-2. Memory Configuration> The configuration of the memory 11 will be explained using Figure 2. Figure 2 is a block diagram showing the configuration of the memory 11 in the information processing system according to this embodiment. In Figure 2, some of the connections between blocks are shown by arrow lines, but the connections between blocks are not limited to the arrow lines shown in Figure 2.

[0034] As shown in Figure 2, the memory 11 includes an input / output circuit 100, a logic control circuit 101, a status register 102, an address register 103, a command register 104, a sequencer 105, a ready / busy circuit 106, a voltage generation circuit 107, a memory cell array 108, a row decoder 109, a sense amplifier 110, a data register 111, and a column decoder 112.

[0035] The input / output circuit 100 controls the input and output of the signal DQ to the controller 12. More specifically, the input / output circuit 100 sends the data DAT (write data) received from the controller 12 to the data register 111, the address ADD to the address register 103, and the command CMD to the command register 104. The input / output circuit 100 also sends the status information STS received from the status register 102, the data DAT (read data) received from the data register 111, and the address ADD received from the address register 103 to the controller 12.

[0036] The logic control circuit 101 receives various control signals from the controller 12. The logic control circuit 101 then controls the input / output circuit 100 and the sequencer 105 according to the received control signals.

[0037] The status register 102 temporarily holds status information STS for write, read, and erase operations, and notifies the controller 12 whether the operation was completed successfully.

[0038] The address register 103 temporarily holds the address ADD received from the controller 12 via the input / output circuit 100. The address register 103 then transfers the row address RA to the row decoder 109 and the column address CA to the column decoder 112.

[0039] The command register 104 temporarily stores the command CMD received from the controller 12 via the input / output circuit 100 and transfers it to the sequencer 105.

[0040] The sequencer 105 controls the operation of the entire memory 11. More specifically, the sequencer 105 controls, for example, the status register 102, the ready / busy circuit 106, the voltage generation circuit 107, the row decoder 109, the sense amplifier 110, the data register 111, and the column decoder 112, etc., in response to the command CMD held in the command register 104, and performs write operations, read operations, erase operations, etc.

[0041] The ready / busy circuit 106 sends a ready / busy signal R / Bn to the controller 12 according to the operating status of the sequencer 105.

[0042] The voltage generation circuit 107 generates the voltages necessary for writing, reading, and erasing operations in response to the control of the sequencer 105, and supplies these generated voltages to, for example, the memory cell array 108, the row decoder 109, and the sense amplifier 110. The row decoder 109 and the sense amplifier 110 apply the voltage supplied by the voltage generation circuit 107 to the memory cell transistors in the memory cell array 108.

[0043] The memory cell array 108 includes a plurality of non-volatile memory cell transistors (hereinafter also referred to as "memory cells") associated with rows and columns. The memory cell array 108 includes a user area 130 and a system area 131 as memory spatial regions.

[0044] The user area 130 is an area where data written to and read from the host device 3 (hereinafter referred to as "user data") is stored. It is preferable to allocate the user area 130 to a range other than the first quarter of the logical address range.

[0045] The system area 131 is an area where information for managing the memory system 2 (hereinafter referred to as "system data") is stored, such as control programs in memory 11, logical conversion data, or various setting parameters such as applied voltage during write operations. The system area 131 is an area that the host device 3 cannot access during write and read operations of data received from the host device 3. It is preferable to allocate the system area 131 within the first quarter of the logical address range.

[0046] The row decoder 109 decodes the row address RA. Based on the decoding result, the row decoder 109 applies a predetermined voltage to the memory cell array 108.

[0047] During a read operation, the sense amplifier 110 senses the data read from the memory cell array 108. The sense amplifier 110 then outputs the read data to the data register 111. During a write operation, the sense amplifier 110 writes the write data to the memory cell array 108.

[0048] The data register 111 includes multiple latch circuits. The latch circuits temporarily hold write data or read data. For example, during a write operation, the data register 111 temporarily holds the write data received from the input / output circuit 100 and transmits it to the sense amplifier 110. Similarly, during a read operation, the data register 111 temporarily holds the read data received from the sense amplifier 110 and transmits it to the input / output circuit 100.

[0049] The column decoder 112 decodes the column address CA during operations such as write, read, and erase, and selects a latch circuit in the data register 111 according to the decoding result.

[0050] <1-3. Configuration of Memory Cell Array> The configuration of the memory cell array 108 will be explained using Figure 3. Figure 3 is a schematic perspective view showing the arrangement of each element of the memory cell array 108 according to this embodiment.

[0051] In Figure 3, the two directions parallel to the main surface of the substrate S and mutually orthogonal are called the X direction and the Y direction, and the plane parallel to the main surface of the substrate S is called the XY plane. The direction perpendicular to both the X direction and the Y direction is called the Z direction (lamination direction).

[0052] As shown in Figure 3, the memory cell array 108 includes a substrate S, a stacked body 10 provided on the substrate S, a plurality of columnar body portions CL, and a plurality of bit lines BL provided on the stacked body 10.

[0053] The laminate 10 has multiple conductive layers that are insulated from each other and periodically stacked in a direction perpendicular to the main surface of the substrate S (the stacking direction), corresponding to a selection gate line SGS, multiple word lines WL, and a selection gate line SGD from the substrate side. The laminate 10 has openings ST and MH. The openings ST and MH extend in the stacking direction (Z direction) and penetrate the laminate 10 to reach the substrate S. The opening ST extends in the X direction, separating the laminate 10 into multiple blocks in the Y direction. A columnar portion CL is formed in the opening MH (see Figure 4).

[0054] The columnar sections CL are formed as cylinders that extend in the stacking direction within the laminate 10. Multiple columnar sections CL may be arranged, for example, in a staggered pattern. Alternatively, multiple columnar sections CL may be arranged in a square grid along the X and Y directions.

[0055] Multiple bit lines BL are separated from each other in the X direction, and each bit line BL extends in the Y direction.

[0056] The upper end of the semiconductor layer 20 (see Figure 4), described later, of the columnar portion CL is connected to the bit line BL via the contact portion Cb. Multiple columnar portions CL, one selected from each block separated in the Y direction by the aperture ST, are connected to a common bit line BL.

[0057] Furthermore, an insulating layer is formed between adjacent word lines WL in the stacking direction. An insulating layer is formed in the slit ST, and an insulating layer is formed on top of the laminate 10. However, for the sake of explanation, these insulating layers are omitted in Figure 3.

[0058] Figure 4 is a cross-sectional view showing the configuration of the memory cell according to this embodiment. Figure 4 is an enlarged cross-sectional view of the columnar portion CL in Figure 3.

[0059] As shown in Figure 4, the columnar portion CL is a structure having a memory layer M, a semiconductor layer 20, and an insulating core layer 50. The semiconductor layer 20 is continuously stretched in the stacking direction (Z direction) within the laminate 10. The material of the semiconductor layer 20 includes, for example, amorphous or polycrystalline silicon. The core layer 50 is provided inside the cylindrical semiconductor layer 20. The material of the core layer 50 includes, for example, silicon oxide. The memory layer M is provided between the word line WL and the semiconductor layer 20. The memory layer M surrounds the semiconductor layer 20 from the outer periphery.

[0060] The memory layer M has a tunnel insulating layer M1, a charge storage layer M2, and a block insulating layer M3 (here, when the tunnel insulating layer M1, charge storage layer M2, and block insulating layer M3 are not distinguished, they are referred to as the memory layer M). The block insulating layer M3, charge storage layer M2, and tunnel insulating layer M1 are extended continuously in the stacking direction of the laminate 10 together with the semiconductor layer 20. Between the word line WL and the semiconductor layer 20, the block insulating layer M3, charge storage layer M2, and tunnel insulating layer M1 are provided in order from the word line WL side. The tunnel insulating layer M1 is in contact with the semiconductor layer 20. The block insulating layer M3 is in contact with the word line WL. The charge storage layer M2 is provided between the block insulating layer M3 and the tunnel insulating layer M1.

[0061] The semiconductor layer 20, the memory layer M, and the word line WL constitute a memory cell MC. In Figure 5, one memory cell MC is schematically represented by a dashed line. The memory cell MC has a vertical transistor structure in which the semiconductor layer 20 is surrounded by the word line WL via the memory layer M.

[0062] In this vertical transistor memory cell MC, the semiconductor layer 20 functions as a channel, and the word line WL functions as the control gate of the memory cell. The charge storage layer M2 functions as a data layer that stores the charge injected from the semiconductor layer 20.

[0063] As described above, multiple memory cells (MCs) are arranged in the stacking direction of multiple word lines (WLs), and each of the multiple word lines (WLs) is connected to multiple memory cells (MCs). A word line (WL) near the block insulating layer (M3) functions as a control gate. By controlling the voltage to the word line (WL) connected to the memory cell (MC), writing to or erasing from the memory cell (MC) can be controlled.

[0064] A memory cell MC is, for example, a charge-trap type memory cell. The charge storage layer M2 has numerous trap sites for capturing charge within the insulating layer. The material of the charge storage layer M2 includes, for example, silicon nitride.

[0065] The tunnel insulating layer M1 acts as a potential barrier when charge is injected from the semiconductor layer 20 to the charge storage layer M2, or when charge stored in the charge storage layer M2 diffuses towards the semiconductor layer 20. The material of the tunnel insulating layer M1 includes, for example, silicon oxide.

[0066] The block insulating layer M3 prevents the charge accumulated in the charge storage layer M2 from diffusing to the word line WL. The material of the block insulating layer M3 includes, for example, silicon oxide.

[0067] Figure 5 is a circuit diagram of a block BLK included in the memory cell array 108 of memory 11. While block BLK0 is used as an example, the other blocks BLK1, 2, ... have similar circuits. Note that the circuit diagram shown in Figure 5 is an example and does not limit the circuit diagram of the memory cell array 108 of the first embodiment. In the description of the memory cell array 108, descriptions of configurations identical or similar to those in Figures 1 to 4 may be omitted.

[0068] Block BLK0 includes N bit lines BL (BL0, BL1, ..., BL(N-1) (where N is an integer greater than or equal to 2)) arranged in a column, and a plurality of NAND strings 116 and source lines SL arranged in a matrix. The NAND strings 116 are connected between the N bit lines BL and the source lines SL. The NAND strings 116 include, for example, eight memory cell transistors MT (MT0 to MT7), as well as selection transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer and hold data non-volatilely. The memory cell transistors MT are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The NAND strings 116 are provided on the N bit lines BL to form a string unit SU (SU0, SU1). In Figure 5, the NAND string 116 includes, for example, eight memory cell transistors MT, but the number of memory cell transistors MT included in the NAND string 116 is not limited to eight. For example, the number of memory cell transistors MT may be i, and the integer i may be greater than or less than 8.

[0069] The selection transistor ST1 is connected to the selection gate line SGD0. The gates of the selection transistor ST1 in each string unit SU are connected to the selection gate lines SGD (SGD0, SGD1, ...; when multiple SGD0, SGD1, ... are not distinguished, they are referred to as the selection gate line SGD). The gates of the eight memory cell transistors MT (MT0~MT7) are each connected to their corresponding word lines WL (WL7~WL0). In addition, the gates of the selection transistor ST2 in each string unit SU are connected to the selection gate line SGS. The gates of the selection transistor ST1 connected to each of the multiple bit lines BL within the same string unit SU are connected to the common selection gate line SGD. The gates of the memory cell transistors MT (MT0~MT7) within the same string unit SU are each connected to the common word lines WL (WL0~WL7). The gates of multiple selection transistors ST2 within the same block BLK are connected to the common selection gate line SGS. The source line SL is shared, for example, between multiple block BLKs.

[0070] Within the same string unit SU, memory cell transistors MT connected to the same word line WL (WL0 to WL7) constitute a unit for read and write operations. For example, the memory cell transistors MT7 in each NAND string 116 included in the string unit SU corresponding to the selected gate line SGD0 constitute a memory cell group MG as a unit for read and write operations, and read and write operations are performed collectively for the memory cell group MG.

[0071] <1-4. About the write performance optimization process> The write performance optimization process will be explained using Figure 6. Figure 6 is a flowchart showing a write performance optimization method for an information processing system 1 according to one embodiment. In write performance optimization, the amount of data to be written (s [MB]) is compared with the free capacity of the memory cell array 108 to determine the optimal write mode. The free capacity of the memory cell array 108 includes, for example, the free capacity that can be written with SLC (x [MB]), the free capacity that can be written with TLC (y [MB]), and the free capacity that can be written with QLC (x [MB]). The free capacity that can be written with each write mode indicates the capacity that can be written when a certain write mode is fixed. For example, the free capacity that can be written with each write mode indicates the sum of the capacity of pages in each active block that do not have valid data recorded on them and the capacity of the free block in each write mode. However, it is not limited to this, and the free capacity of the active block with a fixed write mode may be used when it is greater than or equal to a predetermined value, the free capacity of the active block may not be used, and the free capacity of the free block may be used when the write is greater than or equal to a predetermined value.

[0072] First, it is determined whether the amount of data to be written (s [MB]) can be written using SLC (Step S1). If the amount of data to be written (s [MB]) is less than or equal to the available free space (x [MB]) that can be written using SLC (x ≥ s) (YES in Step S1), the writing mode is determined to be SLC. On the other hand, if the amount of data to be written (s [MB]) is greater than the available free space (x [MB]) that can be written using SLC (NO in Step S1), the process proceeds to the next step.

[0073] Next, it is determined whether the amount of data to be written (s [MB]) can be written using SLC and TLC (step S2). If the amount of data to be written (s [MB]) is less than or equal to the sum of the free space that can be written using SLC (x [MB]) and the free space that can be written using TLC (y [MB]) (x + y ≥ s) (YES in step S2), the writing mode is determined to be SLC and TLC. On the other hand, if the amount of data to be written (s [MB]) is greater than the sum of the free space that can be written using SLC (x [MB]) and the free space that can be written using TLC (y [MB]) (NO in step S2), the process proceeds to the next step.

[0074] Next, it is determined whether the amount of data to be written (s [MB]) can be written using TLC (step S3). If the amount of data to be written (s [MB]) is less than or equal to the available free space that can be written using TLC (y [MB]) (y ≥ s) (YES in step S3), the write mode is determined to be TLC. On the other hand, if the amount of data to be written (s [MB]) is greater than the available free space that can be written using TLC (y [MB]) (NO in step S3), the process proceeds to the next step.

[0075] Next, it is determined whether the amount of data to be written (s [MB]) can be written using TLC and QLC (step S4). If the amount of data to be written (s [MB]) is less than or equal to the sum of the free space that can be written using TLC (y [MB]) and the free space that can be written using QLC (z [MB]) (y + z ≥ s) (YES in step S4), the writing mode is determined to be TLC and QLC. On the other hand, if the amount of data to be written (s [MB]) is greater than the sum of the free space that can be written using TLC (y [MB]) and the free space that can be written using QLC (z [MB]) (NO in step S4), the process proceeds to the next step.

[0076] Next, it is determined whether the amount of data to be written (s [MB]) can be written using QLC (step S5). If the amount of data to be written (s [MB]) is less than or equal to the available free space that can be written using QLC (z [MB]) (z ≥ s) (YES in step S5), the write mode is determined to be QLC. On the other hand, if the amount of data to be written (s [MB]) is greater than the available free space that can be written using QLC (z [MB]) (NO in step S4), the write mode is determined to be QLC and garbage collection (GC) processing is performed.

[0077] Figure 6 shows an example where the write mode is selected from SLC, TLC, QLC, SLC and TLC, TLC and QLC, or QLC and GC by the write performance optimization process. However, it is not limited to these, and the write mode may be SLC and QLC, or SLC, TLC and QLC, or a combination including MLC. In this case, it is preferable for the information processing system 1 to determine the write mode in order to perform the fastest write operation.

[0078] Next, the operation of the write performance optimization process will be explained using Figure 7. Figure 7 is a diagram showing an example of the operation sequence of the information processing system 1 according to this embodiment.

[0079] First, the host device 3 issues a command to the memory system 2 to enter write-optimized mode (a1). At this time, the host device 3 notifies the memory system 2 of the amount of data to be written (s [MB]) by writing it, for example, to the dWriteDataSize in register 45 (a2).

[0080] Upon receiving a command from the host device 3, the memory system 2 reads the amount of data written (s [MB]) in register 45's dWriteDataSize and the capacity of the free space in the memory cell array 108 to determine the optimal write mode. The memory system 2 selects the optimal write mode in the order of S1 to S5 in Figure 6 so that the writing of data to the memory cell array 108 is performed in the fastest possible write mode.

[0081] The host device 3 begins issuing write commands to instruct the writing of data (a3). In this case, the host device 3 continues issuing write commands until all the data has been sent, without knowing what write mode the memory system 2 will use to write the data to the memory cell array 108.

[0082] Meanwhile, the memory system 2 performs the write operation in the optimal write mode determined in response to the write command from the host device 3. Once the write operation is complete, the memory system 2 sends a response message to exit the write optimization mode (a4).

[0083] In this embodiment, the host device 3 sends a command to the memory system 2 to enter write optimization mode, causing the memory system 2 to begin write performance optimization processing. However, the embodiment is not limited to this, and the host device 3 may notify the memory system 2 to process the write command in write optimization mode, or it may notify the memory system 2 to process in write optimization mode by a method other than sending a command to enter write optimization mode to the memory system 2. In this case, it may be possible to control between write optimization mode and normal write mode for each write command.

[0084] Furthermore, internal background processes such as garbage collection (GC) may be disabled during optimization mode. This configuration can further improve write performance.

[0085] Furthermore, the host device 3 may have a configuration that allows it to set a flag to cancel or stop the optimization mode in the memory system 2. With this configuration, the write performance optimization process can be avoided depending on the available capacity and the amount of data written in the memory cell array 108 for each write mode.

[0086] In this embodiment, by performing write performance optimization processing, the amount of data to be written (s [MB]) can be compared with the free capacity of the memory cell array 108 to determine the optimal write mode. Therefore, an information processing system with improved write performance can be provided.

[0087] <Variation> In this modified example, if an additional write command arrives during the operation of the write performance optimization process according to the first embodiment, the memory system 2 sums the amounts of the two write data before performing the write performance optimization process.

[0088] Figure 8 shows an example of the operation sequence of the information processing system 1 according to this modified example. The operation of the write performance optimization process according to this modified example is the same as the operation of the write performance optimization process according to the first embodiment, except that the host device 3 writes two write data amounts (s [MB]) to dWriteDataSize (a21, 22), so its explanation is omitted.

[0089] Upon receiving two commands from the host device 3, the memory system 2 reads the sum of the two write data amounts written to register 45's dWriteDataSize and the capacity of the free space in the memory cell array 108 to determine the optimal write mode. The memory system 2 selects the optimal write mode in the order of S1 to S5 in Figure 6 so that the writing of data to the memory cell array 108 is performed in the fastest possible write mode.

[0090] In this modified example, when the memory system 2 receives a command from the host device 3 to enter write-optimized mode (a1), it waits for a predetermined amount of data to be written (s [MB]). Therefore, the amount of data to be written to dWriteDataSize is written before the first write command is issued (a3) ​​(a22). However, it is not limited to this; for example, the amount of data to be written to dWriteDataSize may be written after the first write command has been issued (a3) ​​(a22). In this case, the memory system 2 may read the sum of the two amounts of data to be written at that time and the capacity of the free space in the memory cell array 108 to determine the optimal write mode. The memory system 2 selects the optimal write mode in the order of S1 to S5 in Figure 6 so that the writing of data to the memory cell array 108 is performed in the fastest possible write mode.

[0091] <Second Embodiment> The configuration of the information processing system according to the second embodiment is the same as that of the information processing system according to the first embodiment, so its description will be omitted. In the first embodiment, the host device 3 notifies the memory system 2 of the amount of data to be written (s [MB]), and the memory system 2 performs write performance optimization processing. In the second embodiment, the memory system 2 notifies the host device 3 of the capacity of the free area of ​​the memory cell array 108, and the host device 3 performs write performance optimization processing. The write performance optimization processing method according to the second embodiment is the same as that according to the first embodiment, so its description will be omitted, and the operation of the write performance optimization processing will be described.

[0092] The operation of the write performance optimization process will be explained using Figure 9. Figure 9 is a diagram showing an example of the operation sequence of the information processing system 1 according to this embodiment.

[0093] First, host device 3 issues a command to memory system 2 to enter write-optimized mode (b1).

[0094] Upon receiving a command from the host device 3, the memory system 2 reads the capacity of the free space in the memory cell array 108 stored in the RAM 44 and notifies the host device 3 (b2). The capacity of the free space in the memory cell array 108 includes the physical address of the block and the free space for each write mode in that block. In addition to the free space for each write mode, the write speed under certain conditions may also be notified. The write speed for each write mode is a fixed value, but for example, if the capacity of the free space in the memory cell array 108 becomes insufficient and garbage collection (GC) processing becomes necessary, the write speed will vary depending on the situation. For this reason, the memory system 2 may calculate the write speed when garbage collection (GC) processing occurs from the write mode at that time and notify the host device 3.

[0095] Furthermore, the memory system 2, upon receiving a command from the host device 3, may read the capacity of the free space in the memory cell array 108 stored in RAM 44 and save the read capacity of the free space in the memory cell array 108 to register 45. In addition to the free space for each write mode, the write speed for each write mode may also be saved to register 45. In this case, the host device 3 will read the capacity of the free space in the memory cell array 108 and the write speed saved in register 45 to determine the capacity of the free space in the memory cell array 108 and the write speed.

[0096] The host device 3 determines the optimal write mode based on the amount of data to be written (s [MB]) and the capacity of the free space in the memory cell array 108 received from the memory system 2. The host device 3 may also determine the optimal write mode based on the amount of data to be written (s [MB]), the capacity of the free space in the memory cell array 108 received from the memory system 2, and the write speed under predetermined conditions. The host device 3 selects the optimal write mode in the order of S1 to S5 in Figure 6 so that the writing of data to the memory cell array 108 is performed in the fastest possible write mode. The host device 3 may also determine the optimal write mode based on the amount of data to be written (s [MB]), the capacity of the free space in the memory cell array 108 received from the memory system 2, and the write speed for each write mode. The host device 3 notifies the memory system 2 of the amount of data to be written (s [MB]) and the determined optimal write mode (b3).

[0097] Host device 3 begins issuing write commands to instruct the writing of data (b4).

[0098] Meanwhile, memory system 2 performs the write operation according to the optimal write mode and write command from host device 3. Once the write operation is complete, memory system 2 sends a response message to exit write-optimized mode (b5).

[0099] In this embodiment, the memory system 2 receives a command from the host device 3 to enter write-optimized mode, and the memory system 2 reads the capacity of the free space in the memory cell array 108 stored in the RAM 44. However, the system is not limited to this configuration, and the memory system 2 may periodically read the capacity of the free space in the memory cell array 108 stored in the RAM 44 and save (update) the read capacity of the free space in the memory cell array 108 in the register 45. In this case, there is no command to enter write-optimized mode, the memory system 2 may read the capacity of the free space in the memory cell array 108 stored in the register 45, or the host device 3 may read the capacity of the free space in the memory cell array 108 stored in the register 45.

[0100] In this embodiment, the host device 3 is shown to notify the memory system 2 of the amount of data to be written (s [MB]) and the determined optimal writing mode. However, the host device 3 is not limited to this, and may also notify the memory system 2 of the determined optimal writing mode by specifying it in a write command, or it may notify the memory system 2 of the optimal writing mode determined by other methods. In this case, it may be possible to control the write optimization mode and the normal write mode for each write command.

[0101] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0102] 1 Information processing system, 2 Memory system, 3 Host device, 10 Stacked structure, 11 Semiconductor memory, 12 Controller, 22 Core logic section, 31 Host interface, 32 Buffer, 33 Data bus, 34 Memory interface, 35 Buffer, 36 ECC circuit (error correcting code), 41 Control bus, 42 CPU (central processing unit), 43 ROM (read-only memory), 44 RAM (random access memory), 45 Register, 51 Analog circuit, 100 Input / output circuit, 101 Logic control circuit, 102 Status register, 103 Address register, 104 Command register, 105 Sequencer, 106 Busy circuit, 107 Voltage generation circuit, 108 Memory cell array, 130 User area, 131 System area

Claims

1. A non-volatile memory having multiple memory cells, A host device that manages the size of the data to be written to the non-volatile memory, The system includes a memory controller that manages the free space of the non-volatile memory that can be written to by the SLC, The non-volatile memory is a memory system that stores data by writing XLC (XLC is a writing mode with a larger number of bits than SLC) per memory cell when the size of the data to be written exceeds the available capacity that can be written by the SLC.

2. The memory system according to claim 1, wherein the non-volatile memory writes data to the SLC when the size of the data to be written is less than or equal to the free space that can be written to the SLC.

3. The memory controller further manages the TLC-writable free capacity of the non-volatile memory, The memory system according to claim 1, wherein the non-volatile memory writes YLC (YLC is a write mode with a larger number of bits than TLC) data per memory cell when the size of the data to be written exceeds the available capacity that can be written by TLC.

4. The memory controller further manages the free space of the non-volatile memory that can be written to by QLC, The memory system according to claim 1, wherein the non-volatile memory writes ZLC (ZLC is a write mode with a larger number of bits than TLC) data per memory cell when the size of the data to be written exceeds the free capacity that can be written by QLC.

5. The host device notifies the memory controller of the size of the data to be written. The memory system according to claim 1, wherein the memory controller decides to write XLC (XLC is a write mode with a larger number of bits than SLC) data per memory cell to the non-volatile memory.

6. The host device and A memory system comprising a host device connected in accordance with the UFS standard, and including non-volatile memory and a memory controller for controlling the non-volatile memory, Equipped with, The aforementioned non-volatile memory has a plurality of blocks, The memory controller is capable of writing data to the block in a first mode in which one bit of data is written per memory cell, or in a second mode in which data of more than one bit is written per memory cell. The memory controller writes to the register the amount of the free space in the non-volatile memory that can be written in the first mode, and the amount of the free space in the non-volatile memory that can be written in the second mode. When the host device writes first data to the memory system, it reads from the memory system the writable capacity in the first mode and the writable capacity in the second mode. Based on the writable capacity in the first mode and the writable capacity in the second mode that have been read, a second data set, which is the data to be written in the first mode from the first data set, and a third data set, which is the data to be written in the second mode from the first data set, are identified. A first write command specifying the second data and a second write command specifying the third data are sent to the memory system. Information processing system.

7. The memory controller writes the second data to the non-volatile memory in the first mode in response to the first write command, and writes the third data to the non-volatile memory in the second mode in response to the second write command. The information processing system according to claim 6.

8. The first write command specifies that the data should be written in the first mode, and the second write command specifies that the data should be written in the second mode. The information processing system according to claim 6.

9. The host device notifies the memory system to write in the first mode before sending the first write command, and notifies the memory system to write in the second mode before sending the second write command. The information processing system according to claim 6.

10. The host device sends a first command to the memory system. The memory controller writes the writable capacity in the first mode and the writable capacity in the second mode to the register in response to the first command. The information processing system according to claim 6.

11. The host device reads the capacity writable in the first mode and the capacity writable in the second mode from the register, thereby reading the capacity writable in the first mode and the capacity writable in the second mode from the memory system. The information processing system according to claim 6.

12. The host device sends a second command to the memory system to read the capacity writable in the first mode and the capacity writable in the second mode, and the memory controller sends the capacity writable in the first mode and the capacity writable in the second mode in response to the second command, thereby allowing the host device to read the capacity writable in the first mode and the capacity writable in the second mode from the memory system. The information processing system according to claim 6.

13. The memory controller further writes to the register the write speed of the first mode and the write speed of the second mode with respect to the free space of the non-volatile memory. When the host device writes first data to the memory system, it further reads from the memory system the write speed in the first mode and the write speed in the second mode. Based on the writable capacity in the first mode read out, the writable capacity in the second mode read out, the write speed in the first mode read out, and the write speed in the second mode read out, a second data set which is data from the first data set to be written in the first mode, and a third data set which is data from the first data set to be written in the second mode, are identified. The information processing system according to claim 6.

14. The memory system notifies the host device of the write speed under predetermined conditions, Based on the writable capacity in the first mode that has been read, the writable capacity in the second mode that has been read, and the writing speed under the predetermined conditions, a second data set which is the data from the first data that is written in the first mode, and a third data set which is the data from the first data that is written in the second mode are identified. The information processing system according to claim 6.

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