memory devices

Abstract

The parasitic capacity of memory devices is normalized. [Solution] The memory device comprises a plurality of first conductive layers spaced apart from each other in a first direction; a first member extending in a second direction intersecting the first direction and dividing the plurality of first conductive layers into first and second parts aligned in a third direction intersecting the first and second directions; a plurality of first memory pillars, each extending in the first direction and intersecting each of the first parts of the plurality of first conductive layers; and a plurality of second memory pillars, each extending in the first direction and intersecting each of the second parts of the plurality of first conductive layers. Viewed in the first direction, the plurality of second memory pillars are arranged offset in the second direction from the plurality of first memory pillars.

Description

Technical Field

[0001] The embodiment relates to a memory device.

Background Art

[0002] As a memory device capable of storing data non-volatiley, a NAND flash memory is known. In a memory device such as a NAND flash memory, a three-dimensional memory structure is adopted for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Equalize parasitic capacitance.

Means for Solving the Problems

[0005] The memory device of the embodiment includes a plurality of first conductor layers arranged apart from each other in a first direction, a first member extending in a second direction intersecting the first direction and dividing the plurality of first conductor layers into a first portion and a second portion arranged in a third direction intersecting the first direction and the second direction, a plurality of first memory pillars each extending in the first direction and intersecting each of the first portions of the plurality of first conductor layers, and a plurality of second memory pillars each extending in the first direction and intersecting each of the second portions of the plurality of first conductor layers. When viewed in the first direction, the plurality of second memory pillars are arranged shifted in the second direction with respect to the plurality of first memory pillars.

Brief Description of the Drawings

[0006] [Figure 1]A block diagram showing an example of the configuration of a memory system including a memory device according to the embodiment. [Figure 2] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the embodiment. [Figure 3] A plan view showing an example of a planar layout of a memory cell array in a memory device according to the embodiment. [Figure 4] A plan view showing an example of a planar layout in the memory area of ​​a memory cell array according to an embodiment. [Figure 5] A cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region of the memory cell array according to the embodiment. [Figure 6] A cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a memory cell array according to the embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 7, showing an example of the cross-sectional structure of a memory pillar in a memory cell array according to the embodiment. [Figure 8] A plan view showing an example of a planar layout in the adjustment region of a memory cell array according to an embodiment. [Figure 9] A schematic diagram showing an example of the connection relationship between the bit lines and memory pillars of a memory device in a comparative example. [Figure 10] A schematic diagram showing an example of the connection relationship between the bit lines and memory pillars of a memory device according to the embodiment. [Figure 11] A schematic diagram showing an example of the connection relationship between the bit lines and memory pillars of a memory device according to the first modified example. [Figure 12] A plan view showing an example of the planar layout of a memory cell array in a memory device according to the second modified example. [Figure 13] A plan view showing an example of a planar layout of a memory cell array in a memory device according to the third modified example. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. The dimensions and proportions in the drawings are not necessarily the same as those in reality.

[0008] In the following explanation, components having substantially the same function and structure will be assigned the same reference numeral. When elements with similar structures need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0009] 1. Embodiments 1.1 Configuration 1.1.1 Memory System Configuration Figure 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to an embodiment. Memory system 1 is a storage device configured to be connected to an external host (not shown). Memory system 1 is, for example, an SD TM These include memory cards, UFS (universal flash storage), and SSDs (solid state drives). Memory system 1 includes a memory controller 2 and a memory device 3.

[0010] The memory controller 2 is composed of an integrated circuit, such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on requests from the host. Specifically, for example, the memory controller 2 writes data to the memory device 3 when requested to write by the host. The memory controller 2 also reads data from the memory device 3 when requested to read by the host and sends it to the host.

[0011] Memory device 3 is a non-volatile memory. Memory device 3 is, for example, a NAND flash memory. Memory device 3 stores data in a non-volatile manner.

[0012] The communication between the memory controller 2 and the memory device 3 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Device Configuration Continuing, referring to the block diagram shown in FIG. 1, the internal configuration of the memory device according to the embodiment will be described. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). The number of blocks BLK included in the memory cell array 10 may be one. A block BLK is a set of a plurality of memory cells. A block BLK is used, for example, as an erasure unit of data. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD received by the memory device 3 from the memory controller 2. The command CMD includes, for example, an instruction to cause the sequencer 13 to execute a read operation, a write operation, an erase operation, etc.

[0016] The address register 12 stores the address information ADD received by the memory device 3 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used for the selection of the block BLK, the word line, and the bit line, respectively.

[0017] The sequencer 13 controls the operation of the entire memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD stored in the command register 11, to perform read operations, write operations, erase operations, etc.

[0018] The driver module 14 generates voltages used in read, write, and erase operations. Then, based on the page address PAd stored in the address register 12, for example, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address Bad stored in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a memory device according to the embodiment. In Figure 2, one of several block BLKs included in the memory cell array 10 is shown. As shown in Figure 2, the block BLK includes, for example, four string units SU0 to SU3.

[0022] Each string unit SU includes multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL may be one or less. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage unit, and stores data nonvolatilically. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0023] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0024] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 in string units SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gates of multiple selection transistors ST2 are connected to the selection gate line SGS.

[0025] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared among multiple block BLKs by a NAND string NS that is assigned the same column address. Word lines WL0 to WL7 are provided for each block BLK. Source lines SL are shared, for example, among multiple block BLKs.

[0026] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0027] The circuit configuration of the memory cell array 10 included in the memory device 3 according to this embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0028] 1.1.4 Structure of a memory cell array Next, an example of the structure of a memory cell array provided in the memory device according to the embodiment will be described. In the drawings referenced below, the X-rays correspond to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the stacking direction of the word line WL and the bit line BL. In the plan view, hatching is added as appropriate to improve the clarity of the drawing. The hatching added to the plan view is not necessarily related to the material or characteristics of the components to which the hatching is added. In the cross-sectional view, the illustration of the components is omitted as appropriate to improve the clarity of the drawing.

[0029] 1.1.4.1 Overall Planar Layout of Memory Cell Array Figure 3 is a plan view showing an example of the planar layout of a memory cell array in a memory device according to the embodiment. In Figure 3, regions corresponding to four blocks BLK0 to BLK3 are shown. As shown in Figure 3, the planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory region MA, adjustment regions AA1 and AA2, and extraction regions HA1 and HA2. The memory cell array 10 also includes a stacked wiring structure and a plurality of members SLT and SHE.

[0030] The stacked wiring structure has a configuration in which stacked wiring, including word lines WL0 to WL7 and selection gate lines SGD and SGS, is stacked in the Z direction. The stacked wiring structure is provided across the memory area MA, adjustment areas AA1 and AA2, and lead areas HA1 and HA2.

[0031] The memory region MA is located, for example, in the central part of the memory cell array 10. The memory region MA is a region containing multiple NAND strings NS.

[0032] Adjustment regions AA1 and AA2 are positioned to sandwich the memory region MA in the X direction. Similar to the memory region MA, multiple NAND strings NS are provided in adjustment regions AA1 and AA2. Adjustment regions AA1 and AA2 are areas that adjust the X-direction misalignment (described later) of the NAND strings NS that occurs between blocks BLK in the memory region MA. The misalignment of the NAND strings NS adjusted in adjustment regions AA1 and AA2 is resolved by the time they reach the extraction regions HA1 and HA2.

[0033] The lead-out regions HA1 and HA2 are arranged so as to sandwich the adjustment region AA1, the memory region MA, and the adjustment region AA2 in the X direction. The example in Figure 3 shows the case where the lead-out region HA1, the adjustment region AA1, the memory region MA, the adjustment region AA2, and the lead-out region HA2 are arranged in this order in the X direction. Each of the lead-out regions HA1 and HA2 is an area used for connection between the stacked wiring included in the stacked wiring structure (i.e., word lines WL0 to WL7, and selection gate lines SGD and SGS) and the row decoder module 15.

[0034] Multiple SLT components are aligned in the Y direction. Each of the SLT components extends in the X direction so as to cross the memory area MA, the adjustment areas AA1 and AA2, and the lead-out areas HA1 and HA2. Each of the SLT components has a structure in which, for example, an insulator or plate-shaped contact is embedded. Each of the SLT components divides the stacked wiring in the Y direction.

[0035] Multiple components SHE are aligned in the Y direction. In this example, three components SHE are positioned between two adjacent components SLT in the Y direction. Each of the multiple components SHE extends in the X direction so as to cross the memory area MA and the adjustment areas AA1 and AA2. The ends of each of the multiple components SHE are located in the lead-out areas HA1 and HA2, respectively. Each of the multiple components SHE also has a structure in which an insulator is embedded, for example. Each of the multiple components SHE selectively separates the selected gate line SGD of the stacked wiring.

[0036] In the planar layout of the memory cell array 10 described above, each portion of the stacked wiring structure separated by two adjacent members SLT in the Y direction corresponds to one block BLK. Furthermore, each portion of the stacked wiring structure separated by adjacent members SLT and SHE in the Y direction, or by two adjacent members SHE in the Y direction, corresponds to one string unit SU. The memory cell array 10 is arranged in the Y direction repeatedly, for example, the planar layout shown in Figure 3.

[0037] The planar layout of the memory cell array 10 in the memory device 3 according to this embodiment is not limited to the example described above. For example, the number of members SHE arranged between two adjacent members SLT in the Y direction can be designed to any number. The number of string units SU formed between two adjacent members SLT in the Y direction can be changed according to the number of members SHE arranged between two adjacent members SLT in the Y direction.

[0038] 1.1.4.2 Planar layout of the memory area Figure 4 is a plan view showing an example of a planar layout in the memory region of a memory cell array according to the embodiment. In Figure 4, one block BLKk (string units SU0 to SU3) and a portion of two adjacent blocks BLK(k-1) (string unit SU3) and a portion of block BLK(k+1) (string unit SU0) are shown. As shown in Figure 4, in the memory region MA, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV and VY, and a plurality of bit lines BL. In addition, each of the plurality of members SLT includes a contact LI and a spacer SP.

[0039] Contact LI is a conductor extending in the XZ plane. Spacer SP is an insulator located on the side of contact LI. In other words, contact LI is surrounded by spacer SP in a plan view.

[0040] Each memory pillar MP functions, for example, as one NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern of, for example, 20 rows in the region between two adjacent members SLT in the Y direction. Of the 20 rows of memory pillar MPs, the first to fifth rows correspond to string unit SU0. The sixth to tenth rows correspond to string unit SU1. The eleventh to fifteenth rows correspond to string unit SU2. The sixteenth to twentieth rows correspond to string unit SU3. For example, the first member SHE overlaps the fifth and sixth rows of memory pillar MPs from the top of the page. The second member SHE overlaps the tenth and eleventh rows of memory pillar MPs from the top of the page. The third component SHE is superimposed on the memory pillars MP in the 15th and 16th columns, counting from the top of the page.

[0041] Multiple bit lines BL are aligned in the X direction. Each of the multiple bit lines BL extends in the Y direction. Each of the multiple bit lines BL is positioned to overlap in plan view with at least one memory pillar MP for each string unit SU. Each of the multiple bit lines BL is then electrically connected to a corresponding one of the at least one memory pillar MP that overlaps in plan view for each string unit SU via a pair of contacts CV and VY.

[0042] The example in Figure 4 shows a case where five adjacent bit lines BL in the X direction are electrically connected to five rows of memory pillars MP within the same string unit SU. More specifically, for example, in block BLKk, of the five bit lines BL blacked out in Figure 4, the first bit line BL is electrically connected to the memory pillars MP in the 1st, 9th, 11th, and 19th rows. The second bit line BL is electrically connected to the memory pillars MP in the 3rd, 7th, 13th, and 17th rows. The third bit line BL is electrically connected to the memory pillars MP in the 5th, 10th, 15th, and 20th rows. The fourth bit line BL is electrically connected to the memory pillars MP in the 2nd, 8th, 12th, and 18th rows. The fifth bit line BL is electrically connected to the memory pillars MP in the 4th, 6th, 14th, and 16th rows.

[0043] The layout of the memory pillar MPs described above is shifted in the X direction by a pitch Δ between bit lines BLs between adjacent blocks BLKs. In the example in Figure 4, the layout of the memory pillar MPs in block BLK(k-1) is shifted in the -X direction by a pitch Δ compared to the layout of the memory pillar MPs in block BLKk. That is, the amount of shift in the layout of the memory pillar MPs in block BLK(k-1) relative to block BLKk is -Δ. Therefore, in block BLK(k-1), the first bit line BL of the five bit lines BLs blacked out in Figure 4 is electrically connected to the memory pillar MPs in the 3rd, 7th, 13th, and) 17th columns. The second bit line BL is electrically connected to the memory pillar MPs in the 5th, 10th, 15th, and) 20th columns. The third bit line BL is electrically connected to the memory pillar MPs in the 2nd, 8th, 12th, and) 18th columns. The fourth bit line BL is electrically connected to the memory pillars MP of the 4th, 6th, 14th, and 16th columns. The fifth bit line BL is electrically connected to the memory pillars MP of the 19th column (1st, 9th, 11th, and 19th columns).

[0044] Furthermore, the layout of the memory pillar MPs in block BLK(k+1) is shifted by a pitch Δ in the +X direction compared to the layout of the memory pillar MPs in block BLKk. That is, the amount of shift in the layout of the memory pillar MPs in block BLK(k+1) relative to block BLKk is +Δ. For this reason, in block BLK(k+1), the first bit line BL of the five bit lines BL blacked out in Figure 4 is electrically connected to the memory pillar MPs in the 4th row (6th, 14th, and 16th rows). The second bit line BL is electrically connected to the memory pillar MPs in the 1st row (9th, 11th, and 19th rows). The third bit line BL is electrically connected to the memory pillar MPs in the 3rd row (7th, 13th, and 17th rows). The fourth bit line BL is electrically connected to the memory pillar MP of the 5th column (and the 10th, 15th, and 20th columns). The fifth bit line BL is electrically connected to the memory pillar MP of the 2nd column (and the 8th, 12th, and 18th columns).

[0045] 1.1.4.3 Cross-sectional structure of the memory area Figure 5 is a cross-sectional view along the VV line in Figure 4, showing an example of the cross-sectional structure in the memory region of the memory cell array according to the embodiment. As shown in Figure 5, the memory cell array 10 further includes a semiconductor layer 21, conductive layers 22, 23, 24, and 25, conductive films 26, 27, and 51, insulating layers 30, 31, 32, 33, and 34, a core film 41, a semiconductor film 42, a laminated film 43, and insulating films 52 and 53.

[0046] A semiconductor layer 21 is provided on the upper surface of the insulating layer 30. The semiconductor layer 21 includes, for example, three semiconductor layers 21a, 21b, and 21c. A semiconductor layer 21b is provided on the upper surface of semiconductor layer 21a. A semiconductor layer 21c is provided on the upper surface of semiconductor layer 21b. Semiconductor layer 21b is formed, for example, by replacing the insulating layer provided between semiconductor layer 21a and semiconductor layer 21c. Semiconductor layers 21a to 21c include, for example, polysilicon. Semiconductor layers 21a to 21c also include, for example, phosphorus (P) as a semiconductor impurity.

[0047] On the upper surface of the semiconductor layer 21, an insulating layer 31 and a conductive layer 22 are alternately stacked one layer at a time. The conductive layer 22 is formed, for example, in the shape of a plate extending in the XY plane. The conductive layer 22 is used as a selected gate line (SGS). The conductive layer 22 contains, for example, tungsten.

[0048] On the upper surface of the conductive layer 22, eight insulating layers 32 and eight conductive layers 23 are alternately stacked one layer at a time. Each of the conductive layers 23 is formed in a plate shape, for example, extending in the XY plane. Each of the conductive layers 23 is used as a word line WL0 to WL7. Each of the conductive layers 23 contains, for example, tungsten.

[0049] On the upper surface of the top conductive layer 23, an insulating layer 33 and a conductive layer 24 are alternately stacked one layer at a time. The conductive layer 24 is formed, for example, in the shape of a plate extending in the XY plane. The conductive layer 24 is used as a selected gate wire SGD. The conductive layer 24 contains, for example, tungsten.

[0050] A conductive layer 25 is provided above the conductive layer 24 via an insulating layer 34. The conductive layer 25 is formed in a line shape extending in the Y direction. The conductive layer 25 is used as a bit line BL. In other words, in a region not shown, multiple conductive layers 25 are aligned in the X direction. The conductive layer 25 contains, for example, copper.

[0051] The component SLT includes a conductive film 51 and an insulating film 52. The conductive film 51 is formed in a plate shape extending in the XZ plane. The conductive film 51 contains, for example, tungsten and is used as a contact LI. The lower end of the conductive film 51 is located within the semiconductor layer 21b. The upper end of the conductive film 51 is located above the conductive layer 24.

[0052] The insulating film 52 is formed in a plate-like shape extending in the XZ plane. The insulating film 52 contains, for example, silicon oxide and is used as a spacer SP. The insulating film 52 divides the plurality of conductive layers 22, 23, and 24 in the Y direction. The insulating film 52 is provided so as to cover the side surface of the conductive film 51 and electrically insulates the plurality of conductive layers 22, 23, and 24 from the conductive film 51.

[0053] Component SHE includes an insulating film 53. The insulating film 53 is formed in a plate-like shape extending in the XZ plane. The insulating film 53 includes, for example, silicon oxide. The insulating film 53 divides the conductive layer 24 in the Y direction. The lower end of the insulating film 53 is located within the insulating layer 33 between the conductive layer 24 and the uppermost conductive layer 23. The upper end of the insulating film 53 is located above the conductive layer 24.

[0054] The memory pillar MP has a substantially cylindrical shape extending in the Z direction. The memory pillar MP penetrates multiple conductive layers 22, 23, and 24. The bottom surface of the memory pillar MP reaches the semiconductor layer 21a. A conductive film 26 is provided on the upper surface of the semiconductor film 42 of the memory pillar MP. The conductive film 26 is formed in a columnar shape extending in the Z direction and is used as a contact CV.

[0055] A conductive film 27 is provided on the upper surface of the conductive film 26. The conductive film 27 is formed in a columnar shape extending in the Z direction and is used as a contact VY. In Figure 5, two contacts VY are shown corresponding to two of the six memory pillars MP arranged in the Y direction (the first and sixth memory pillars MP from the right side of the page in Figure 5). For memory pillars MP that do not have contacts VY connected in Figure 5, the corresponding contacts VY are connected in areas not shown.

[0056] One conductive layer 25, i.e., one bit line BL, is in contact with the upper surface of contact VY. The one conductive layer 25 is in contact with one contact VY in each of the spaces separated by members SLT and SHE, and in the spaces separated by the two members SHE.

[0057] Next, the structure of the memory pillar MP will be described. The memory pillar MP includes a core film 41, a semiconductor film 42, and a stacked film 43.

[0058] The core film 41 extends in the Z direction. The core film 41 includes an insulator, such as silicon oxide. The upper end of the core film 41 reaches the insulator layer 34, and the lower end of the core film 41 reaches the semiconductor layer 21a.

[0059] The semiconductor film 42 surrounds the core film 41. The semiconductor film 131 contains, for example, silicon. At the lower end of the memory pillar MP, a portion of the semiconductor film 42 is in contact with the semiconductor layer 21b.

[0060] The laminated film 43 covers the sides and bottom edge of the semiconductor film 42, except for the portion where the semiconductor film 42 and the semiconductor layer 21b are in contact.

[0061] Figure 6 is a cross-sectional view along the line VI-VI in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a memory cell array according to the embodiment. Figure 6 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the XY plane and including the bottom conductive layer 23. As shown in Figure 6, the laminated film 43 includes, for example, a tunnel insulating film 44, a charge storage film 45, and a block insulating film 446.

[0062] In a cross-section including the conductive layer 23, the core film 41 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 42 surrounds the sides of the core film 41. The tunnel insulating film 44 surrounds the sides of the semiconductor film 42. The charge storage film 45 surrounds the sides of the tunnel insulating film 44. The block insulating film 46 surrounds the sides of the charge storage film 45. The conductive layer 23 surrounds the sides of the block insulating film 46. Each of the tunnel insulating film 44 and the block insulating film 46 contains, for example, silicon oxide. The charge storage film 45 has the function of storing charge and contains, for example, silicon nitride.

[0063] Memory cell transistors MT0 to MT7 are formed by combining a memory pillar MP with a conductive layer 23 that functions as word lines WL0 to WL7. Similarly, a selection transistor ST1 is formed by combining a memory pillar MP with a conductive layer 24 that functions as a selection gate line SGD. A selection transistor ST2 is formed by combining a memory pillar MP with a conductive layer 22 that functions as a selection gate line SGS. Thus, each memory pillar MP can function as a single NAND string NS.

[0064] Of the multiple memory pillars MP, the memory pillars MP that are in contact with member SHE (the 5th and 6th memory pillars MP from the right side of the page in Figure 5) will have a shape in which a portion of the memory pillar MP is missing due to member SHE.

[0065] Figure 7 is a cross-sectional view along line VII-VII in Figure 5, showing an example of the cross-sectional structure of a memory pillar in a memory cell array according to the embodiment. Figure 7 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the XY plane and including the conductive layer 24. As shown in Figure 7, in the layer including the conductive layer 24, the semiconductor film 42 surrounds the portion of the core film 41's side surface excluding the contact surface with the insulating film 53. The tunnel insulating film 44 surrounds the portion of the semiconductor film 42's side surface excluding the contact surface with the insulating film 53. The charge storage film 45 surrounds the portion of the tunnel insulating film 44's side surface excluding the contact surface with the insulating film 53. The block insulating film 46 surrounds the portion of the charge storage film 45's side surface excluding the contact surface with the insulating film 53. The conductive layer 24 surrounds the portion of the block insulating film 46's side surface excluding the contact surface with the insulating film 53.

[0066] 1.1.4.4 Planar layout of the adjustment area Figure 8 is a plan view showing an example of a planar layout in the adjustment region of a memory cell array according to the embodiment. Figure 8 shows the adjustment region AA2, a part of the memory region MA adjacent to adjustment region AA2 in the X direction, and a part of the extraction region HA2. Although not shown in Figure 8, the planar layout of adjustment region AA1, the memory region MA adjacent to adjustment region AA1 in the X direction, and the extraction region HA1 is equivalent to the planar layout of adjustment region AA2, memory region MA, and extraction region HA2.

[0067] First, let's describe the planar layout of the drawer area HA2.

[0068] In the extraction region HA2, each of the selected gate line SGS, word lines WL0 to WL7, and selected gate line SGD has a portion (terrace portion) that does not overlap with the upper wiring layer (conductor layer) of the stacked wiring. In addition, the memory cell array 10 in the extraction region HA2 includes multiple contacts CC.

[0069] In the lead-out area HA2, the shape of the portion that does not overlap with the upper wiring layer is similar to a step, terrace, rimstone, etc. Specifically, steps are provided between the selection gate line SGS and word line WL0, between word line WL0 and word line WL1, ..., between word line WL6 and word line WL7, and between word line WL7 and selection gate line SGD. In the example in Figure 8, it is shown that steps are formed in a stepped shape in the X direction at the ends of the terrace portions of the selection gate line SGD and word lines WL0 to WL7.

[0070] In the drawout area HA2, multiple contacts CC are provided on the respective terrace portions of the selected gate line SGS, word lines WL0 to WL7, and selected gate lines SGD0 to SGD3.

[0071] Each of the selection gate line SGS, word lines WL0 to WL7, and selection gate lines SGD0 to SGD3 is electrically connected to the row decoder module 15 via the corresponding contact CC. In other words, each of the selection gate line SGS, word lines WL0 to WL7, and selection gate lines SGD0 to SGD3 is supplied with voltage from, for example, a contact CC located in at least one of the drawout regions HA1 and HA2.

[0072] Next, we will describe the planar layout of adjustment region AA2.

[0073] As described above, the planar layout of the memory pillar MP is shifted in the X direction by the pitch Δ between bit lines BL between adjacent blocks BLK. Therefore, at the boundary between the memory area MA and the adjustment area AA2, the displacement amounts of the memory pillar MP layouts of blocks BLK(k-1) and BLK(k+1) relative to block BLKk are -Δ and +Δ, respectively. In the adjustment area AA2, the memory pillar MP is arranged such that this displacement amount between blocks BLK becomes zero at the boundary with the extraction area HA2.

[0074] In other words, in the example shown in Figure 8, the memory pillars MP are arranged such that the distance between memory pillars MP aligned in the X direction in the adjustment region AA2 of block BLK(k-1) is longer than the distance between memory pillars MP aligned in the X direction in the adjustment region AA2 of block BLKk. As a result, the amount of displacement -Δ occurring at the boundary between the memory region MA and the adjustment region AA2 gradually approaches 0 as it approaches the extraction region HA2. At the boundary between the adjustment region AA2 and the extraction region HA2, the amount of displacement can be considered to be 0.

[0075] Similarly, in the adjustment region AA2 of block BLK(k+1), the memory pillars MP are arranged such that the distance between memory pillars MP aligned in the X direction is shorter than the distance between memory pillars MP aligned in the X direction in the adjustment region AA2 of block BLKk. As a result, the displacement amount +Δ occurring at the boundary between the memory region MA and the adjustment region AA2 gradually approaches zero as it approaches the extraction region HA2. Then, the displacement amount can be made zero at the boundary between the adjustment region AA2 and the extraction region HA2. With this layout, the starting position of the extraction region HA2 can be prevented from shifting in the X direction between blocks BLK.

[0076] Furthermore, the memory pillar MP located in adjustment region AA2 is not used as the NAND string NS. Therefore, contacts CV and VY are not provided on the upper surface of the memory pillar MP located in adjustment region AA2. In other words, the memory pillar MP located in adjustment region AA2 is electrically isolated from the bit line BL.

[0077] 1.2 Effects according to the embodiment According to this embodiment, the multiple memory pillars MP arranged in blocks BLK(k+1) and BLK(k-1) are offset in the X direction relative to the multiple memory pillars MP arranged in block BLKk. This makes it possible to equalize the parasitic capacitance for each bit line BL. This effect will be described in detail below using a comparative example.

[0078] Figure 9 schematically shows an example of the connection relationship between the bit lines and memory pillars of a memory device in a comparative example. The comparative example corresponds to a case where the multiple memory pillars MP arranged in blocks BLK(k+1) and BLK(k-1) are not offset in the X direction relative to the multiple memory pillars MP arranged in block BLKk. In Figure 9, the correspondence between the five bit lines BL arranged consecutively in the X direction and the row numbers of the memory pillars MP connected to the bit lines BL is indicated by circles. Among the memory pillars MP connected to the bit lines BL, those that are not in contact with member SHE and have a cylindrical shape are indicated by white circles. On the other hand, memory pillars MP that have a cylindrical shape with a part missing due to contact with member SHE are indicated by black circles.

[0079] As shown in Figure 9, if the arrangement of multiple memory pillars MPs between blocks BLK is not shifted in the X direction, the relationship between a memory pillar MP in contact with member SHE and the corresponding bit line BL does not change between blocks BLK. Therefore, the bit lines BL that connect to memory pillar MPs in contact with member SHE are concentrated in the 1st, 3rd, and 5th bit lines BL (especially the 3rd bit line BL) out of the 5 bit lines BL. In other words, the 2nd and 4th bit lines BL are not connected to memory pillar MPs in contact with member SHE. Thus, in the comparative example, there is a bias in the number of connections to memory pillar MPs having a cylindrical shape with a portion missing, among the bit lines BL.

[0080] When a portion of the memory pillar MP is missing, the parasitic capacitance caused by the memory pillar MP as seen from the corresponding bit line BL changes. Therefore, in the comparative example, a difference in parasitic capacitance occurs between bit lines BL due to the difference in the number of connections with the memory pillar MP having a missing cylindrical shape. This difference in parasitic capacitance is undesirable because it leads to increased variation in data read time between bit lines BL.

[0081] Figure 10 is a schematic diagram showing an example of the connection relationship between the bit lines and the memory pillar of a memory device according to the embodiment. Figure 10 is a diagram that corresponds Figure 9 in the comparative example to the embodiment. In Figure 10, the areas indicated by white or black circles in the comparative example of Figure 9 are indicated by dotted circles. In addition, the shift of the memory pillar MP in the X direction that occurs between the comparative example and the embodiment is indicated by an arrow.

[0082] As shown in Figure 10, when the arrangement of multiple memory pillars MP is shifted in the X direction between blocks BLK, the relationship between a memory pillar MP in contact with a member SHE and the corresponding bit line BL changes between blocks BLK. Specifically, for example, in block BLKk, the bit lines BL connected to the memory pillar MP in contact with member SHE are concentrated on the 1st, 3rd, and 5th bit lines BL out of the 5 bit lines BL. In this case, in block BLK(k-1), the bit lines BL connected to the memory pillar MP in contact with member SHE are concentrated on the 2nd, 4th, and 5th bit lines BL out of the 5 bit lines BL. In block BLK(k+1), the bit lines BL connected to the memory pillar MP in contact with member SHE are concentrated on the 1st, (2nd), and 4th bit lines BL out of the 5 bit lines BL. As a result, in this embodiment, the number of connections with memory pillar MP having a cylindrical shape with a portion missing can be equalized across the bit lines BL. Therefore, the difference in parasitic capacitance between bit lines BL caused by the difference in the number of connections with the memory pillar MP, which has a cylindrical shape with a portion missing, can be reduced. Consequently, variations in data read time between bit lines BL can be suppressed.

[0083] Furthermore, the memory cell array 10 has adjustment areas AA1 and AA2 between the memory area MA1 and the extraction areas HA1 and HA2. The X-direction misalignment of the arrangement of multiple memory pillars MP between blocks BLK that occurred in the memory area MA is eliminated in the adjustment areas AA1 and AA2. This prevents the starting position of the extraction area HA from shifting in the X-direction between blocks BLK. Therefore, it is possible to suppress the increase in the manufacturing load of the extraction area HA caused by the misalignment of the arrangement of multiple memory pillars MP between blocks BLK.

[0084] 2. Variant Furthermore, various modifications can be applied to the embodiments described above.

[0085] 2.1 First Variation In the above-described embodiment, the case in which the arrangement of multiple memory pillars MP between adjacent blocks BLK is shifted in the X direction by a pitch Δ of one bit line BL was explained, but it is not limited to this. For example, the arrangement of multiple memory pillars MP between adjacent blocks BLK may be an integer multiple of the pitch Δ of the bit line BL.

[0086] Figure 11 is a schematic diagram showing an example of the connection relationship between the bit lines and memory pillars of a memory device according to the first modified example. Figure 11 corresponds to Figure 10 in the embodiment. In the example of Figure 11, the arrangement of multiple memory pillars MP between adjacent blocks BLK is shown to be shifted in the X direction by a pitch 2Δ, which is the width of two bit lines BL.

[0087] As shown in Figure 11, for example, in block BLKk, the bit lines BL connecting to the memory pillar MP in contact with member SHE are concentrated in the 1st, 3rd, and 5th bit lines BL out of the 5 bit lines BL. In this case, in block BLK(k-1), the bit lines BL connecting to the memory pillar MP in contact with member SHE are concentrated in the 1st, 3rd, and 4th bit lines BL out of the 5 bit lines BL. In block BLK(k+1), the bit lines BL connecting to the memory pillar MP in contact with member SHE are concentrated in the 2nd, (3rd), and 5th bit lines BL out of the 5 bit lines BL. As a result, in the first modified example as in the embodiment, the number of connections to the memory pillar MP having a cylindrical shape with a portion missing can be equalized among the bit lines BL. Therefore, the difference in parasitic capacitance that occurs among the bit lines BL due to the difference in the number of connections to the memory pillar MP having a cylindrical shape with a portion missing can be reduced. Consequently, variations in data read time among the bit lines BL can be suppressed.

[0088] 2.2 Second Variation Furthermore, although the above-described embodiment described a case where the region between two adjacent SLT members in the Y direction is used as one block BLK, it is not limited to this. For example, the region between three or more consecutively adjacent SLT members in the Y direction may be used as one block BLK.

[0089] Figure 12 is a plan view showing an example of a planar layout of a memory cell array in a memory device according to a second modified example. Figure 12 corresponds to Figure 3 in the embodiment. In the example of Figure 12, the region between three continuously adjacent members SLT in the Y direction is used as a single block BLK.

[0090] As shown in Figure 12, each of the multiple SLT members is classified into members SLTa and SLTb.

[0091] Component SLTa extends in the X direction across the memory area MA, adjustment areas AA1 and AA2, and lead areas HA1 and HA2. That is, component SLTa has the same configuration as component SLT in the embodiment. Therefore, the stacked wiring structure is divided by component SLTa. In other words, component SLTa functions as a boundary of block BLK, electrically insulating the stacked wiring structures between blocks BLK.

[0092] The component SLTb extends in the X direction, but is interrupted in one of the memory region MA, adjustment regions AA1 and AA2, or lead regions HA1 and HA2 (in the example in Figure 12, lead regions HA1 and HA2). As a result, the stacked wiring structure is not completely divided by the component SLTb. Therefore, the stacked wiring structure has a partial JCT that connects in the Y direction at the point where the component SLTb is interrupted. That is, the stacked wiring structures flanking the component SLTb are electrically connected via the partial JCT and function as the same block BLK.

[0093] In the configuration of the memory cell array 10 having the members SLTa and SLTb described above, the multiple memory pillars MP located in one of two adjacent block BLKs separated by the member SLTa are positioned offset in the X direction relative to the multiple memory pillars MP located in the other block. Similarly, the multiple memory pillars MP located in one of two adjacent portions within the same block BLK separated by the member SLTb are positioned offset in the X direction relative to the multiple memory pillars MP located in the other block. This allows for the equalization of the connection relationship between the memory pillars MP and bit lines BL, using the members SLTa and SLTb as boundaries, regardless of whether they are block BLK boundaries or not. Therefore, parasitic capacitance between bit lines BL can be equalized, similar to the embodiment.

[0094] 2.3 Third Variation Furthermore, although the above-described embodiment described a case in which the memory cell array 10 has a planar layout in which two draw-out areas sandwich one memory area, it is not limited to this. For example, the memory cell array 10 may have a planar layout in which two memory areas sandwich one draw-out area.

[0095] Figure 13 is a plan view showing an example of a planar layout of a memory cell array in a memory device according to a third modified example. Figure 13 corresponds to Figure 3 in the embodiment. In the example of Figure 13, the memory cell array 10 is shown to be divided in the X direction into memory areas MA1 and MA2, adjustment areas AA1 and AA2, and extraction area HA.

[0096] As shown in Figure 13, the extraction area HA is located, for example, in the center of the memory cell array 10. The adjustment areas AA1 and AA2 are arranged so as to sandwich the extraction area HA in the X direction. The memory areas MA1 and MA2 are arranged so as to sandwich the adjustment area AA1, the extraction area HA, and the adjustment area AA2 in the X direction. In the example in Figure 13, the memory area MA1, adjustment area AA1, extraction area HA, adjustment area AA2, and memory area MA2 are shown in this order in the X direction.

[0097] In the planar layout of the memory cell array 10 as described above, the multiple memory pillars MP arranged in blocks BLK(k+1) and BLK(k-1) are offset in the X direction relative to the multiple memory pillars MP arranged in block BLKk. This makes it possible to equalize the parasitic capacitance for each bit line BL, similar to the embodiment.

[0098] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0099] 1…Memory system 2…Memory controller 3…Memory devices 10…Memory cell array 11... Command Register 12…Address Register 13… Sequencer 14…Driver module 15… Raw Decoder Module 16…Sense Amp Module 21, 21a, 21b, 21c… Semiconductor layers 22, 23, 24, 25… Conductive layer 26, 27… Conductive film 30, 31, 32, 33, 34… Insulating layer 41… Core film 42… Semiconductor film 43…Multilayer film 44...Tunnel insulating film 45...Charge storage film 46…Block Insulating Film 51... Conductive film 52, 53… Insulating film

Claims

1. A plurality of first conductive layers arranged apart from each other in a first direction, A first member extending in a second direction intersecting the first direction, dividing the plurality of first conductive layers into a first portion and a second portion aligned in a third direction intersecting the first and second directions, A plurality of first memory pillars, each extending in the first direction and intersecting each of the first portions of the plurality of first conductive layers, A plurality of second memory pillars, each extending in the first direction and intersecting each of the second portions of the plurality of first conductive layers, Equipped with, Viewed in the first direction, the plurality of second memory pillars are arranged offset in the second direction from the plurality of first memory pillars. Memory device.

2. The system further comprises a plurality of bit lines connected to each of the plurality of first memory pillars and the plurality of second memory pillars, The amount of the second-direction displacement of the arrangement of the plurality of second memory pillars relative to the arrangement of the plurality of first memory pillars is an integer multiple of the pitch of the plurality of bit lines in the second direction. The memory device according to claim 1.

3. The present invention further comprises a second member that extends in the second direction and divides the first portion of the third conductive layer, which is included in the plurality of first conductive layers, into a first sub-part and a second sub-part arranged in the third direction, The plurality of first memory pillars include a third memory pillar that contacts the second member and a fourth memory pillar that does not contact the second member. The memory device according to claim 2.

4. Viewed in the first direction, the shape of the third memory pillar differs from the shape of the fourth memory pillar at the position of the third conductive layer in the first direction. The memory device according to claim 3.

5. The present invention further comprises a third member that extends in the second direction and divides the second portion of the third conductive layer into a third sub-part and a fourth sub-part arranged in the third direction, The plurality of second memory pillars include a fifth memory pillar that contacts the third member and a fifth memory pillar that does not contact the third member. The third memory pillar and the fifth memory pillar are connected to different bit lines among the plurality of bit lines. The memory device according to claim 3.

6. The plurality of first conductive layers, when viewed in the first direction, The first region in which the plurality of first memory pillars and the plurality of second memory pillars are provided, Each has a terrace portion that does not overlap with the upper first conductive layer, and the first region and the second region aligned in the second direction, It has, In the boundary region between the first region and the second region, the misalignment in the second direction between the arrangement of the plurality of first memory pillars and the arrangement of the plurality of second memory pillars is eliminated. The memory device according to claim 5.

7. The first portion of the plurality of first conductive layers is electrically insulated from the second portion of the plurality of first conductive layers by the first member. The memory device according to claim 1.

8. The plurality of first conductive layers further have a third portion that electrically connects the first portion and the second portion. The memory device according to claim 1.

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