Memory system and method for controlling the memory system

Abstract

Improve the reliability of data retrieval. [Solution] The memory system of the embodiment includes a memory device including a plurality of memory cells connected to each of a plurality of word lines, and a memory controller, wherein the memory controller acquires first data relating to the threshold voltage of a plurality of selected cells connected to a selected word line, acquires second data from a plurality of first adjacent cells connected to a first adjacent word line, corrects the first data based on the second data to acquire first corrected data, acquires third data from a plurality of second adjacent cells connected to a second adjacent word line, corrects the first corrected data based on the third data to acquire second corrected data, and performs a soft judgment process on the second corrected data to generate read data from the plurality of selected cells.

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a method for controlling the memory system.

Background Art

[0002] As a memory system, a solid state drive (SSD) including a memory controller and a memory device is known. The memory device is, for example, a non-volatile memory. The non-volatile memory is, for example, a NAND type flash memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the reliability of data reading.

Means for Solving the Problems

[0005] The memory system of the embodiment includes a memory device including a plurality of word lines and a plurality of memory cells connected to each of the plurality of word lines, and a memory controller that controls the read operation of the memory device, wherein the memory controller acquires first data relating to the threshold voltage of a plurality of selected cells connected to a selected word line among the plurality of word lines, acquires second data from a plurality of first adjacent cells connected to a first adjacent word line adjacent to one end of the selected word line among the plurality of word lines, corrects the first data based on the second data to acquire first corrected data, acquires third data from a plurality of second adjacent cells connected to a second adjacent word line adjacent to the other end of the selected word line among the plurality of word lines, corrects the first corrected data based on the third data to acquire second corrected data, and performs a soft judgment process on the second corrected data to generate read data from the plurality of selected cells. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing an example configuration of the memory system according to the first embodiment. [Figure 2] A block diagram showing an example configuration of the memory device in the memory system of the first embodiment. [Figure 3] A circuit diagram showing the circuit configuration of a memory cell array in a memory device. [Figure 4] A cross-sectional view showing an example of the structure of a NAND string in a memory device. [Figure 5] A schematic diagram illustrating an example of the relationship between data and the threshold voltage of a memory cell. [Figure 6] A schematic diagram illustrating the overview of the memory system of the first embodiment. [Figure 7] A flowchart illustrating an example of the operation of the memory system according to the first embodiment. [Figure 8] A schematic diagram showing the data storage state in RAM during operation of the memory system of the first embodiment. [Figure 9]Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the first embodiment. [Figure 10] Schematic diagram showing an example of data correction in the operation example of the memory system of the first embodiment. [Figure 11] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the first embodiment. [Figure 12] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the first embodiment. [Figure 13] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the first embodiment. [Figure 14] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the first embodiment. [Figure 15] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the first embodiment. [Figure 16] Block diagram showing a configuration example of the memory system of the second embodiment. [Figure 17] Diagram showing an example of a histogram of the state of a selected cell in a certain state and the states of adjacent cells. [Figure 18] Diagram showing an example of the label value of a selected cell obtained from the histogram. [Figure 19] Diagram showing an example of a correction value table generated based on the histogram. [Figure 20] Flowchart showing an operation example of the memory system of the second embodiment. [Figure 21] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the second embodiment. [Figure 22] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the second embodiment. [Figure 23] Schematic diagram showing the data storage state in the RAM during the operation of the memory system of the second embodiment.

MODE FOR CARRYING OUT THE INVENTION

[0007] Referring to FIGS. 1 to 23, a memory system and a control method of the memory system according to an embodiment will be described. In the following description, elements having the same function and configuration are denoted by the same reference numerals. Also, in each of the following embodiments, when components (for example, circuits, wirings, various voltages and signals, etc.) with reference numerals accompanied by numbers / letters at the end for distinction do not need to be distinguished from each other, a description (reference numeral) in which the numbers / letters at the end are omitted is used. In the following description, data may also be referred to as data items.

[0008] (Embodiment) (1) First Embodiment Referring to FIGS. 1 to 15, a memory system and a control method of the memory system according to the first embodiment will be described.

[0009] (a) Configuration Example (a-1) Information Processing System Referring to FIG. 1, a configuration example of the memory system according to the present embodiment will be described.

[0010] FIG. 1 is a block diagram showing a configuration example of a device (for example, an information processing system) including the memory system 1 according to the present embodiment.

[0011] As shown in FIG. 1, the information processing system 9 includes the memory system 1 and the host 2 according to the present embodiment.

[0012] The memory system 1 according to the present embodiment is a device that stores data. The memory system 1 is, for example, an SSD (solid state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD TMIt is a card. Memory system 1 is connectable to host 2 via host bus HBS. Memory system 1 performs processing based on requests (commands or host commands) received from host 2 or spontaneous processing requests generated within memory system 1.

[0013] Host 2 is a computing device that controls memory system 1. Host 2 may be, for example, a personal computer, a server system, a mobile device, an in-vehicle device, or a digital camera.

[0014] (a-1-1) Internal configuration of the memory system The memory system 1 includes a memory controller 10 and a memory device 30. The memory device 30 is, for example, a non-volatile memory. The memory device 30 is a non-volatile semiconductor memory such as a NAND flash memory. Hereinafter, the memory device 30 will be referred to as non-volatile memory 30 or NAND memory 30.

[0015] The memory controller 10 is a device that controls the NAND memory 30. The memory controller 10 is connected to the host 2 via the host bus HBS. The memory controller 10 receives requests from the host 2 via the host bus HBS. The type of host bus HBS depends on the application applied to the memory system 1. If the memory system 1 is an SSD, the host bus HBS may be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM It conforms to the Peripheral Component Interconnect Express (CSI) standard. If memory system 1 is a UFS device, the host bus HBS conforms to the M-PHY standard. If memory system 1 is a USB memory device, the host bus HBS conforms to the USB standard. If memory system 1 is an MMC, the host bus HBS conforms to the eMMC (Embedded Multi Media Card) standard. If memory system 1 is an SD card... TMIf it is a card, the host bus HBS is SD TM To comply with standards.

[0016] The memory controller 10 controls the NAND memory 30 via the NAND bus NBS based on requests received from the host 2 or spontaneous processing requests generated within the memory system 1. The NAND bus NBS conforms to, for example, the Toggle NAND Flash Interface standard or the Open NAND Flash Interface standard.

[0017] The NAND memory 30 is a device for storing data. The NAND memory 30 includes multiple memory cells. Each of the multiple memory cells stores data nonvolatilously according to the threshold voltage of the memory cell. The NAND memory 30 stores the data received from the memory controller 10 nonvolatilously in the multiple memory cells. The NAND memory 30 outputs the data read from the multiple memory cells to the memory controller 10.

[0018] (a-1-2) Memory controller An example of the internal configuration of the memory controller 10 will be described below.

[0019] As shown in Figure 1, the memory controller 10 includes a host interface (I / F) circuit 11, a processor 12, a buffer memory 13, an ECC (error checking and correcting) circuit 14, a ROM (read-only memory) 15, a RAM (random access memory) 16, a NAND interface (I / F) circuit 17, and an ICI (inter-cell interference) correction circuit 18. The memory controller 10 may be configured, for example, as a SoC (system-on-a-chip).

[0020] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host 2. The host interface circuit 11 is connected to the host 2 via the host bus HBS.

[0021] The processor 12 is the control circuit of the memory controller 10. The processor 12 is, for example, a CPU (central processing unit). The processor 12 controls the operation of the entire memory controller 10 by executing the program (firmware) stored in the ROM 15. For example, when the processor 12 receives a write request from the host 2, it controls the write operation based on the received write request. The same applies to read and erase operations.

[0022] Buffer memory 13 is memory that temporarily stores data. Buffer memory 13 is, for example, SRAM (Static Random Access Memory). Buffer memory 13 temporarily stores written data and read data, etc. Written data is data written to NAND memory 30. Read data is data read from NAND memory 30.

[0023] The ECC circuit 14 is a circuit that performs ECC (error checking and correcting) processing for data error correction. During a data writing operation, the ECC circuit 14 generates an error correction code based on the data to be written. During a data reading operation, the ECC circuit 14 generates a syndrome based on the error correction code in predetermined units and detects errors. The ECC circuit 14 corrects the detected errors.

[0024] For example, the ECC circuit 14 performs hard-decision decoding and soft-decision decoding. The ECC circuit 14 can perform hard-decision decoding using RS (Reed-Solomon) codes or BCH (Bose-Chaudhuri-Hocquenghem) codes. The ECC circuit 14 can perform soft-decision decoding using LDPC (Low-density parity-check) codes of the data.

[0025] ROM15 is a non-volatile memory. ROM15 is, for example, an EEPROM. TM It is (Electrically Erasable Programmable Read-Only Memory). ROM15 stores programs such as firmware.

[0026] RAM16 is a volatile memory. RAM16 is, for example, SRAM or DRAM (Dynamic Random Access Memory). RAM16 is used as a work area for the processor 12. RAM16 stores firmware for managing the NAND memory 30 and various management information. RAM16 stores, for example, a table TBL0 containing various information. For example, table TBL0 contains information regarding the correction of data read from the NAND memory 30. RAM16 includes a memory area 160 for temporarily storing data read by the read operation of the NAND memory 30. Note that table TBL0 may be stored within the processor 12. Memory area 160 is an area with a predetermined storage capacity reserved for storing various data used in the soft judgment read operation described later.

[0027] The NAND interface circuit 17 is responsible for communication between the memory controller 10 and the NAND memory 30. The NAND interface circuit 17 is connected to the NAND memory 30 via the NAND bus NBS. For example, the NAND interface circuit 17 controls the transfer of data, commands, and addresses between the memory controller 10 and the NAND memory 30.

[0028] The ICI correction circuit 18 is a circuit that performs various processes to correct the read data according to the magnitude of interference occurring between memory cells, so that the effects of interference between memory cells in the read data are mitigated during data reading. The ICI correction circuit 18 may be provided as a functional block within the processor 12 or the ECC circuit 14.

[0029] (a-1-3) NAND flash memory Referring to Figure 2, the configuration of the NAND memory 30 will be explained.

[0030] Figure 2 is a block diagram showing an example configuration of the NAND memory 30. The NAND memory 30 includes a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register 35, a sequencer 36, a driver module 37, a row decoder module 38, a sense amplifier module 39, and a data latch 40.

[0031] The memory cell array 31 includes one or more blocks BLK (BLK0, BLK1, ..., BLKk-1), where k is an integer greater than or equal to 1. A block BLK is, for example, a collection of multiple memory cells whose data is erased all at once. For example, a block BLK is used as a unit of data erasure operation. Multiple bit lines and multiple word lines are provided within the memory cell array 31. Each memory cell is associated with, for example, one bit line and one word line. Details of the memory cell array 31 will be described later.

[0032] The input / output circuit 32 is a circuit that sends and receives signals and information to and from the memory controller 10. The input / output circuit 32 sends and receives input / output signals DQ (for example, 8-bit signals DQ0 to DQ7) and data strobe signals DQS to and from the memory controller 10. Signal DQ is the actual data that is sent and received between the NAND memory 30 and the memory controller 10. Signal DQ is, for example, a command CMD, an address ADD, status information STS, and data DAT. Signal DQS is a signal (clock signal) for controlling the timing of sending and receiving signals DQ. For example, when writing data, signal DQS is sent from the memory controller 10 to the NAND memory 30 along with signal DQ containing the data to be written. The NAND memory 30 receives signal DQ containing the data to be written in synchronization with signal DQS. When reading data, signal DQS is sent from the NAND memory 30 to the memory controller 10 along with signal DQ containing the data to be read. The memory controller 10 receives signal DQ, which contains the read data, in synchronization with signal DQS. Alternatively, the input / output circuit 32 may receive signal DQS from the memory controller 10 via the logic control circuit 33.

[0033] The input / output circuit 32 transmits the command CMD in signal DQ to the command register 35A. The input / output circuit 32 transmits the address ADD in signal DQ to the address register 35B. The input / output circuit 32 receives the status information STS from the status register 35C. The input / output circuit 32 transmits and receives the data DAT in signal DQ to and from the data latch 40.

[0034] The logic control circuit 33 is a circuit that controls the input / output circuit 32 and the sequencer 36 based on control signals. The logic control circuit 33 receives the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn from the memory controller 10. Signal CEn is a signal for enabling the chip of the NAND memory 30. Signal CLE is a signal that indicates to the NAND memory 30 that the signal DQ received is the command CMD. Signal ALE is a signal that indicates to the NAND memory 30 that the signal DQ received is the address ADD. Signal WEn is a signal that commands the NAND memory 30 to input signal DQ. Signal REn is a signal that commands the NAND memory 30 to output signal DQ. The NAND memory 30 generates signal DQS based on signal REn. The NAND memory 30 outputs signal DQ to the memory controller 10 based on the generated signal DQS.

[0035] The ready / busy control circuit 34 is a circuit that informs the memory controller 10 of the operating status of the sequencer 36. Based on the operating status of the sequencer 36, the ready / busy control circuit 34 sends a ready / busy signal RBn to the memory controller 10. Signal RBn is a signal that indicates whether the NAND memory 30 is in a ready state or a busy state. The signal level of signal RBn is, for example, set to a "High" level ("H" level) when the NAND memory 30 is in a ready state. The ready state is a state in which the NAND memory 30 can accept a command CMD from the memory controller 10. The signal level of signal RBn is, for example, set to a "Low" level ("L" level) when the NAND memory 30 is in a busy state. The busy state is a state in which the NAND memory 30 cannot accept a command CMD from the memory controller 10.

[0036] Register 35 is a circuit for temporarily storing information. Register 35 includes the command register 35A, the address register 35B, and the status register 35C.

[0037] Command register 35A is a circuit that stores command CMDs. Command CMDs include, for example, instructions that cause the sequencer 36 to perform a read operation, a write operation, or an erase operation.

[0038] Address register 35B is a circuit that stores address ADD. Address ADD includes, for example, row addresses and column addresses. Row addresses include block addresses and page addresses (word line addresses). Block addresses, page addresses, and column addresses are used, for example, for selecting block BLK, word lines, and bit lines, respectively.

[0039] The status register 35C is a circuit that temporarily stores status information STS during, for example, a read operation, write operation, or erase operation. The status information STS is used to notify the memory controller 10 whether or not the operation has been completed successfully.

[0040] The sequencer 36 is a circuit that controls the operation of other circuits according to a predetermined program. The sequencer 36 controls the operation of the entire NAND memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the raw decoder module 38, and the sense amplifier module 39 based on the command CMD stored in the command register 35A. For example, the sequencer 36 performs read operations, write operations, and erase operations.

[0041] The driver module 37 is a circuit that generates voltages used in read, write, and erase operations. Based on the page address stored in the address register 35B, the driver module 37 applies the generated voltage to the signal line corresponding to the selected word line.

[0042] The row decoder module 38 is a circuit that selects one block BLK in the memory cell array 31 based on the block address stored in the address register 35B. The row decoder module 38 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0043] During a write operation, the sense amplifier module 39 receives the write data DAT from the input / output circuit 32 via the data latch 40. The sense amplifier module 39 applies a voltage based on the received write data DAT to the bit line. During a read operation, the sense amplifier module 39 determines the data stored in the memory cell based on whether or not current is generated on the bit line or the voltage on the bit line. The sense amplifier module 39 transfers the determination result as read data DAT to the input / output circuit 32 via the data latch 40.

[0044] The data latch (data cache) 40 includes a plurality of latch circuits (not shown). Each latch circuit temporarily stores write data or read data. For example, during a write operation, the data latch 40 temporarily stores the write data received from the input / output circuit 32 and transmits it to the sense amplifier module 39. Similarly, during a read operation, the data latch 40 temporarily stores the read data received from the sense amplifier module 39 and transmits it to the input / output circuit 32.

[0045] <Example configuration of a memory cell array> The circuit configuration of the memory cell array 31 will be explained with reference to Figure 3. Figure 3 is a circuit diagram of the memory cell array 31. Figure 3 shows the circuit configuration of block BLK0 included in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31. Other blocks BLK have a similar configuration to that shown in Figure 3.

[0046] Block BLK0 includes, for example, five string units SU0, SU1, SU2, SU3, and SU4. Each string unit SU is a set of multiple NAND strings NS that are selected together in, for example, a write or read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, ..., BLm-1, respectively. m is an integer greater than or equal to 1.

[0047] A NAND string NS is a set of multiple memory cells connected in series. Each NAND string NS includes, for example, memory cells MC (MC0, MC1, ..., MCi-1, MCi, MCi+1, ..., MCn-2, MCn-1), select transistor ST1, and select transistor ST2. n is an integer greater than or equal to 1. i is an integer greater than or equal to 0 and less than or equal to n-1.

[0048] The memory cell (also called a memory cell transistor) MC is a field-effect transistor that includes a control gate and a charge storage layer. The select transistors ST1 and ST2 are switching elements. Each of the select transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0049] In each NAND string NS, multiple memory cells MC0,...,MCn-1 are connected in series. The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to one end of the series-connected memory cells MC0,...,MCn-1. The drain of select transistor ST2 is connected to the other end of the series-connected memory cells MC0,...,MCn-1. The source of select transistor ST2 is connected to the source line SL.

[0050] Within the same block BLK, the control gates of memory cells MC0, MC1, ..., MCi-1, MCi, MCi+1, ..., MCn-2, MCn-1 are commonly connected to word lines WL0, WL1, WL2, WL3, ..., WLi-1, WLi, WLi+1, ..., WLn-2, ​​WLn-1, respectively, across multiple NAND strings. The gates of select transistors ST1 within string units SU0, SU1, SU2, SU3, SU4 are commonly connected to select gate lines SGD0, SGD1, SGD2, SGD3, SGD4, respectively, across multiple NAND strings. The gate of select transistor ST2 included in the same block BLK is commonly connected to select gate line SGS across multiple NAND strings.

[0051] In the circuit configuration of the memory cell array 31 described above, the bit line BL is shared, for example, by NAND strings NS to which the same column address is assigned in each string unit SU. The source line SL is shared, for example, between multiple blocks BLK.

[0052] In the following, among the multiple word lines WL0,...,WLn-1, the word line WL0 located furthest to the source side of the NAND string NS is called the start word line WL0, and the word line WLn-1 located furthest to the drain side of the NAND string NS is called the end word line WLn-1. The word lines WL1,...,WLn-2 other than the start and end word lines WL0,WLn-1 are called the intermediate word lines WL1,...,WLn-2.

[0053] For example, if word line WLi is an intermediate word line, word line WLi-1 is located between word line WLi and source line SL. The address value of word line WLi-1 differs from the address value of word line WLi by 1. For example, the address value of word line WLi-1 (e.g., the physical address value) is 1 less than the address value of word line WLi. For example, if word line WLi is an intermediate word line, word line WLi+1 is located between word line WLi and bit line BL. The address value of word line WLi+1 (e.g., the physical address value) differs from the address value of word line WLi by 1. For example, the address value of word line WLi+1 is 1 greater than the address value of word line WLi. Note that, depending on the address settings, the address value of word line WLi-1 may be 1 greater than the address value of word line WLi, and the address value of word line WLi+1 may be 1 less than the address value of word line WLi.

[0054] A collection of multiple memory cells MC connected to a common word line WL within a single string unit SU is referred to, for example, as a cell unit CU. A block BLK contains multiple cell unit CUs. The data stored in a cell unit CU, which includes multiple memory cells MCs each storing 1-bit data according to a threshold voltage, corresponds to one page of data. A cell unit CU can store two or more pages of data, based on the number of bits of data stored in the memory cells MCs. In this embodiment, one memory cell MC can store 3 bits of data. That is, the memory cell MC in this embodiment is a TLC (triple level cell) that stores 3 bits of data. In this case, the data stored in one cell unit CU corresponds to three pages of data.

[0055] Furthermore, the number of bits of data that a memory cell MC can store can be any real number. For example, a memory cell MC may be an MLC (multi-level cell) that stores 2 bits of data, a QLC (quad-level cell) that stores 4 bits of data, or a PLC (penta-level cell) that stores 5 bits of data.

[0056] Furthermore, the circuit configuration of the memory cell array 31 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK, and the number of memory cells MC and select transistors ST1 and ST2 included in each NAND string NS, can be any number.

[0057] Referring to Figure 4, the structure of the NAND string NS of the memory cell array 31 will be explained.

[0058] Figure 4 is a cross-sectional view showing an example of the structure of a NAND string NS included in the memory cell array 31. In Figure 4, one NAND string NS is extracted and shown.

[0059] As shown in Figure 4, the NAND string NS includes a semiconductor layer 301. The semiconductor layer 301 is provided on an insulating layer 313. The semiconductor layer 301 includes, for example, three semiconductor layers 301a, 301b, and 301c. The three semiconductor layers 301a, 301b, and 301c function as a source line SL. The semiconductor layer 301a is provided on the insulating layer 313. The semiconductor layer 301b is provided on the semiconductor layer 301a. The semiconductor layer 301c is provided on the semiconductor layer 301b. The semiconductor layers 301a, 301b, and 301c include, for example, silicon. The semiconductor layers 301a, 301b, and 301c include, for example, phosphorus (P) as a semiconductor impurity.

[0060] The NAND string NS includes multiple insulating layers 302 and multiple conductive layers 303. The multiple insulating layers 302 and multiple conductive layers 303 are stacked on the semiconductor layer 301 in the Z direction. Above the semiconductor layer 301c, the multiple insulating layers 302 and multiple conductive layers 303 are stacked alternately one layer at a time. The conductive layers 303 have a plate-like structure that extends in the X and Y directions.

[0061] In the example shown in Figure 4, each of the conductive layers 303 functions, in order from the side closest to the semiconductor layer 301 (source line SL), as a select gate line SGS, word lines WL0, WL1, ..., WLi-1, WLi, WLi+1, ..., WLn-2, ​​WLn-1, and select gate line SGD. Note that each of the select gate lines SGS and SGD may be composed of multiple conductive layers 303.

[0062] When multiple conductive layers 303 are stacked in the Z direction, multiple word lines WL0, WL1, ..., WLi-1, WLi, WLi+1, ..., WLn-2, ​​WLn-1 are aligned in the Z direction. Word lines WL are adjacent to each other in the direction (Z direction) that intersects the extension direction (X and Y directions) of word lines WL. For example, word line WLi is located between two word lines WLi-1 and WLi+1 in the Z direction. Word line WL-i is adjacent to word line WLi on the source side of the NAND string NS (one end of word line WLi in the Z direction). Word line WL-i is located below word line WLi in the Z direction. Word line WL+i is adjacent to word line WLi on the drain side of the NAND string NS (the other end of word line WLi in the Z direction). Word line WL+i is located above word line WLi in the Z direction.

[0063] For example, a titanium nitride (TiN) / tungsten (W) laminated structure may be used for the conductive material of the conductive layer 303. In this case, the titanium nitride is formed to cover the tungsten. The titanium nitride functions as a barrier layer to suppress oxidation of tungsten and / or as an adhesion layer to improve the adhesion of tungsten, for example, when tungsten is formed by CVD (chemical vapor deposition). The conductive layer 303 may also contain a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed to cover the conductive material between the insulating layers 302.

[0064] The NAND string NS includes a memory pillar MP. The memory pillar MP extends in the Z direction. In the Z direction, the memory pillar MP penetrates multiple insulating layers 302 and multiple conductive layers 303. The bottom (one end) of the memory pillar MP reaches the semiconductor layer 301. The memory pillar MP may have a structure in which multiple pillars are connected in the Z direction.

[0065] The memory pillar MP includes a block insulating layer 340, a charge storage layer 341, a tunnel insulating layer 342, a semiconductor layer 343, a core layer 344, and a capping layer 345.

[0066] The charge storage layer 341 is a layer capable of storing electric charge. The charge storage layer 341 includes, for example, silicon nitride. The tunnel insulating layer 342 is a layer through which charge passes by tunneling when a voltage above a threshold is applied to the conductive layer 303. The block insulating layer 340 is a layer that blocks the movement of charge in the charge storage layer 341 to the conductive layer 303.

[0067] The semiconductor layer 343 is the region where the current paths (channels) of the memory cell MC and select transistors ST1 and ST2 are formed. The sides of the semiconductor layer 343 are covered in order from the outside of the memory pillar MP by the block insulating layer 340, the charge storage layer 341, and the tunnel insulating layer 342. The semiconductor layer 343 covers the sides and bottom of the core layer 344. The semiconductor layer 343 contains, for example, silicon.

[0068] In the same layer as semiconductor layer 301b and in the vicinity of semiconductor layer 301b, the block insulating layer 340, charge storage layer 341, and tunnel insulating layer 342 on the side surface of the memory pillar MP are removed. Semiconductor layer 343 is in contact with semiconductor layer 301b through the portion where the block insulating layer 340, charge storage layer 341, and tunnel insulating layer 342 have been removed.

[0069] The core layer 344 is the core material of the memory pillar MP. The core layer 344 is, for example, The cap layer 345 is provided at the upper (other end) of the memory pillar MP in the Z direction, so as to cover the ends of the semiconductor layer 343 and the core layer 344. The side surface of the cap layer 345 is in contact with the tunnel insulating layer 342. The cap layer 345 contains, for example, silicon.

[0070] A conductor 304 is provided on the cap layer 345. A conductor 305 is provided on the conductor 304. The conductor 305 is connected to a conductive layer 306 which serves as a bit line BL. The conductive layer 306 extends in the Y direction. Conductors 304, 305 and the conductive layer 306 are provided within the insulating layer 311.

[0071] Multiple conductive layers 303, acting as word lines WL, are aligned in the Z direction between the semiconductor layer 301 acting as source line SL and the conductive layer 306 acting as bit line BL.

[0072] A memory cell MC (MC0, MC1, ..., MCi-1, MCi, MCi+1, ..., MCn-2, MCn-1) is formed by combining a memory pillar MP with a conductive layer 303 acting as a word line WL (WL0, WL1, ..., WLi-1, WLi, WLi+1, ..., WLn-2, ​​WLn-1). A select transistor ST1 is formed by combining a memory pillar MP with a conductive layer 303 acting as a select gate line SGD. A select transistor ST2 is formed by combining a memory pillar MP with a conductive layer 303 acting as a select gate line SGS. Thus, each memory pillar MP can function as a single NAND string NS.

[0073] The data stored in the memory cell MC depends on the amount of charge stored in the charge storage layer 341.

[0074] Referring to Figure 5, the relationship between the data stored in the memory cell MC and the threshold voltage of the memory cell MC will be explained.

[0075] In this example, one memory cell (MC) can store 3 bits of data. Hereafter, these 3 bits of data will be referred to as the lower bit, middle bit, and upper bit, in order from the least significant bit. The set of lower bits stored by memory cells (MCs) belonging to the same cell unit (CU) will be called the lower page (or lower data), the set of middle bits will be called the middle page (or middle data), and the set of upper bits will be called the upper page (or upper data).

[0076] For example, three pages are allocated to a single word line WL (a single cell unit CU) within a single string unit SU. Alternatively, a "page" can be defined as a portion of the memory space formed within a cell unit CU. Data may be written to and read from each page or each cell unit CU.

[0077] Figure 5(a) is a diagram showing the data that each memory cell MC can handle, the threshold voltage distribution, and the voltage used when reading the data.

[0078] As shown in Figure 5(a), if a memory cell MC can store 3 bits of data, the memory cell MC can take on eight states depending on the threshold voltage. These eight states, in descending order of threshold voltage, are called the “Er” state T0, “A” state T1, “B” state T2, “C” state T3, “D” state T4, “E” state T5, “F” state T6, and “G” state T7.

[0079] In state T0, "Er," the threshold voltage of the memory cell MC is less than voltage VAR, corresponding to the data erasure state. In state T1, "A," the threshold voltage of the memory cell MC is greater than or equal to voltage VAR and less than voltage VBR (>VAR). In state T2, "B," the threshold voltage of the memory cell MC is greater than or equal to voltage VBR and less than voltage VCR (>VBR). In state T3, "C," the threshold voltage of the memory cell MC is greater than or equal to voltage VCR and less than voltage VDR (>VCR). In state T4, "D," the threshold voltage of the memory cell MC is greater than or equal to voltage VDR and less than voltage VER (>VDR). In state T5, "E," the threshold voltage of the memory cell MC is greater than or equal to voltage VER and less than voltage VFR (>VER). In state T6, "F," the threshold voltage of the memory cell MC is greater than or equal to voltage VFR and less than voltage VGR (>VFR). In state T7, "G," the threshold voltage of the memory cell MC is greater than or equal to voltage VGR and less than voltage VREAD (>VGR).

[0080] Of the eight states T0, ..., T7 distributed in this manner, the “G” state T7 is the state with the highest threshold voltage. Each state T0, ..., T7 has a range of voltage values ​​associated with the corresponding data. The “Er” state T0 is called the erase state. States T1, ..., T7 from “A” to “G” are called the program states.

[0081] In the following, each of the voltages VAR, ..., VGR will also be called the read level or decision level.

[0082] The readout levels VAR,...,VGR are used as reference voltages for hard-decision readouts. Additionally, the readout levels VAR,...,VGR are used as reference voltages for setting the voltage interval (shift voltage) for soft-decision readouts.

[0083] Voltage VREAD is, for example, the voltage applied to a word line (non-selected word line) WL that is not being read during a read operation. When voltage VREAD is applied to a memory cell MC, the memory cell MC turns on regardless of the data stored in the memory cell MC.

[0084] The threshold voltage distribution corresponding to each state T0, ..., T7 is realized by writing 3 bits (3 pages) of data, including the lower bit, middle bit, and upper bit mentioned above, to the memory cell MC in the memory cell array 31. An example of the relationship between the threshold voltage state and the lower / middle / upper bits is as follows. “Er” state: “111” (listed in the order of “Upper / Middle / Lower”) "A" State: "110" "B" State: "100" "C" state: "000" "D" State: "010" “E” State: “011” "F" State: "001" “G” State: “101” Thus, in the threshold voltage distribution, only one of the three bits changes between data corresponding to two adjacent states.

[0085] To read the lower bits, use the voltage corresponding to the boundary where the value of the lower bit ("0" or "1") changes. To read the upper bits, use the voltage corresponding to the boundary where the value of the upper bits changes. To read the middle bits, use the voltage corresponding to the boundary where the value of the middle bit changes.

[0086] As shown in Figure 5(a), lower pages are read using the voltage VAR, which distinguishes between the “Er” state T0 and the “A” state T1, and the voltage VER, which distinguishes between the “D” state T4 and the “E” state T5, as the read voltages.

[0087] The reading of the middle page is performed using the following reading voltages: VBR, which distinguishes between state "A" T1 and state "B" T2; VDR, which distinguishes between state "C" T3 and state "D" T4; and VFR, which distinguishes between state "E" T5 and state "F" T6.

[0088] The reading of the upper page is performed using the reading voltages VCR, which distinguishes between state "B" T2 and state "C" T3, and VGR, which distinguishes between state "F" T6 and state "G" T7.

[0089] By reading using voltage VAR, the erased memory cell MC can be identified.

[0090] In the following, reading (determination) using voltage VAR is also called AR reading. Similarly, reading using each voltage VBR, VCR, VDR, VER, VFR, and VGR is called BR reading, CR reading, DR reading, ER reading, FR reading, and GR reading, respectively.

[0091] Figure 5(b) is a diagram illustrating the state of the threshold voltage distribution of the memory cell.

[0092] The threshold voltages of adjacent memory cells (MCs) influence each other depending on the magnitude of the threshold voltage of the memory cell MC. The ICI between memory cell MCs causes a shift in the threshold voltage of the memory cell MCs. For example, if the threshold voltage of a memory cell adjacent to a memory cell selected for reading (hereinafter referred to as the selected cell) is lower than the threshold voltage of the selected cell MC (for example, if the state of the adjacent cell is the "Er" state), the threshold voltage of the selected cell MC shifts to the lower voltage side, as shown by the threshold voltage distribution indicated by the dotted line in Figure 5(b). If the threshold voltage of the adjacent cell is higher than the threshold voltage of the selected cell (for example, if the state of the adjacent cell is the "G" state), the threshold voltage of the selected cell MC shifts to the higher voltage side, as shown by the threshold voltage distribution indicated by the dashed line in Figure 5(b).

[0093] When the threshold voltage distribution changes due to fluctuations caused by ICI, adjacent threshold voltage distributions may overlap.

[0094] Due to the overlap of adjacent threshold voltage distributions, the hard detection read operation using the above voltages VAR, VBR, VCR, ..., VFR, VGR may fail to correctly read data from memory cells that have threshold voltages within the overlapping distribution region.

[0095] For example, if the threshold voltage distribution of state "A" T1 and the threshold voltage distribution of state "B" T2 overlap, memory cells with a threshold voltage greater than voltage VBR in the threshold voltage distribution of state "A" T1 may be mistakenly read as state "B" T2, and memory cells with a threshold voltage less than voltage VBR in the threshold voltage distribution of state "B" T2 may be mistakenly read as state "A" T1. In this way, if the number of bits that are mistakenly read (number of error bits) exceeds the number of correctable bits of the ECC circuit 14, the memory controller 10 will fail to read the correct data from the NAND memory 30.

[0096] In the memory system 1 of this embodiment, in order to reduce data errors caused by ICI during data reading by soft judgment, ICI cancellation correction is performed to correct the data read from the selected cell according to the threshold voltage (state) of the adjacent cell.

[0097] Referring to Figure 6, the overview of the memory system 1 of this embodiment will be described.

[0098] Figure 6 is a schematic diagram showing an overview of the memory system 1 of this embodiment.

[0099] In this embodiment, when the soft judgment read operation is performed, the memory system 1 in the memory controller 10 performs ICI cancellation correction on the data read from multiple selected cells MCi of the selected word line (hereinafter referred to as the selected word line) WLi.

[0100] In the soft-decision read operation, the threshold voltage of the selected cell MCi is estimated based on information obtained from the measurement operation of the threshold voltage of the selected cell MCi (for example, the distribution read described later). In the memory controller 10, the magnitude of the estimated threshold voltage of each selected cell MCi is indicated by a label value. The label value is a digital value.

[0101] In this embodiment, when performing ICI cancellation correction on data read from the selected cell MCi of the selected word line WLi, the memory system 1 performs a read operation to determine the threshold voltage of the memory cells (adjacent cells) MCi-1 and MCi+1 connected to the adjacent word lines WLi-1 and WLi+1, respectively, for the word line WLi-1 adjacent to the source side (source line side) of the NAND string NS with respect to the selected word line WLi (hereinafter referred to as the source-side adjacent word line) and the word line WLi+1 adjacent to the drain side (bit line side) of the NAND string NS with respect to the selected word line WLi (hereinafter referred to as the drain-side adjacent word line). This determines the state of the adjacent cells MCi-1 and MCi+1.

[0102] The memory system 1 of this embodiment corrects the label value corresponding to the data read from the selected cell MCi of the selected word line WLi by performing a first ICI cancellation correction based on the read result (state of the adjacent cell) for one of the adjacent word lines (for example, adjacent word line WLi-1).

[0103] Subsequently, the memory system 1 of this embodiment corrects the label value of the selected cell MCi of the selected word line WLi again by a second ICI cancellation correction based on the read result (state of the adjacent cell) for the other word line (e.g., adjacent word line WLi+1).

[0104] For example, if the memory cell MC is TLC, the threshold voltage of a certain adjacent cell MC on an adjacent word line WL belongs to one of eight threshold voltage distributions. Therefore, there are eight possible states (threshold voltage distributions) for a single adjacent cell MCi-1 on the source-side adjacent word line WLi-1.

[0105] In the first ICI cancellation correction, the label value (data, threshold voltage) of one selected cell MCi is corrected using one of eight correction values, depending on the threshold voltage distribution pattern of the adjacent cell MCi-1.

[0106] Similarly, there are eight possible states for one adjacent cell MCi+1 on the drain-side adjacent word line WLi+1.

[0107] In the second ICI cancellation correction, the corrected label value of one selected cell MCi is corrected again using one of eight correction values, depending on the state pattern of the adjacent cell MCi+1.

[0108] Thus, the data for each selected cell MCi on the selected word line WLi is corrected by ICI cancellation correction using 8 x 8 (=64) patterns of correction values.

[0109] As a result, the memory system 1 of this embodiment can improve the reliability of the data read out.

[0110] (b) Example of operation An example of the operation of the memory system 1 of this embodiment will be described with reference to Figures 7 to 15. Note that the example of the operation of the memory system 1 of this embodiment corresponds to the control method of the memory system 1 of this embodiment.

[0111] Figure 7 is a flowchart showing an example of the operation of the memory system 1 of this embodiment. Figures 8 to 15 are schematic diagrams illustrating an example of the operation of the memory system 1 of this embodiment.

[0112] In this embodiment, if data reading by hard judgment fails, the memory system 1 starts reading data by soft judgment.

[0113] <s11> Memory system 1 samples the threshold voltages (threshold voltage distributions) of multiple selected cells MCi connected to the selected word line WLi corresponding to the selected address.

[0114] The memory system 1 causes the NAND memory 30 to perform a distribution read on the selected word line WLi, via the ICI correction circuit 18 of the memory controller 10, in order to sample the threshold voltage of the selected cell MCi.

[0115] Distribution Lead is an operation that measures the distribution of threshold voltages of selected cells MCi connected to a selected word line WLi by shifting the voltage applied to the selected word line WLi in predetermined voltage increments and measuring the number of ON-state selected cells MCi or OFF-state selected cells MCi connected to the selected word line WLi.

[0116] In the distribution lead, the threshold voltage distribution of the selected cell MCi is measured for each of the multiple pages assigned to the selected word line WLi.

[0117] For example, if the memory cell MC is TLC, the threshold voltage distribution formed from the threshold voltages of multiple selected cells MCi of the selected word line WLi is measured for each lower page, middle page, and upper page, relative to the read level used to read the corresponding page.

[0118] In measuring the threshold voltage distribution on lower pages, multiple judgment processes (readouts) are performed for each of the AR readout (readout level VAR) and ER readout (readout level VER).

[0119] In AR readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the voltage applied to the selected word line WLi (hereinafter also called the selected word line voltage) is shifted to the lower and higher voltage sides within the range of readout level VBR from the lower end of the threshold voltage distribution of the "Er" state T0, relative to the readout level VAR. For example, for AR readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the word line voltage shifted by 1 DAC or 2 DACs at a time. The on and off states of the selected cell MCi are detected by each judgment process.

[0120] Voltage VREAD is applied to all unselected word lines except the selected word line WLi.

[0121] "DAC" refers to a setting value (digital value) used to set the voltage value (analog value) of the charge pump that generates the voltage applied to the word line WL, etc., inside the NAND memory 30. For example, 1 DAC corresponds to 10 mV.

[0122] In ER readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the selected word line voltage is shifted to the lower and higher voltage sides within the range from the readout level VDR to the upper limit of the threshold voltage distribution of the "G" state T7, with the readout level VER as the reference. For example, with respect to ER readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the selected word line voltage shifted by 1 DAC or 2 DACs at a time.

[0123] Furthermore, for distribution reads of lower pages, a CR read (determination process using read level VCR) is executed once as a level-separated read (also called a single-state read). The level-separated read detects whether the selected cell MCi is on or off. The level-separated read of the CR read classifies whether the state of the selected cell MCi is "B" state T2 or lower, or "C" state T3 or higher.

[0124] This provides the measurement results of the threshold voltage distribution of the selected cell MCi in the lower page. The data regarding the measurement results of the threshold voltage distribution of the selected cell MCi in the lower page is transferred from the NAND memory 30 to the memory controller 10. The memory controller 10 uses the ICI correction circuit 18 to calculate the label value of each selected cell MCi in the lower page based on the measurement results. The label value data of each selected cell MCi in the lower page (hereinafter referred to as label value data) is stored in the RAM 16 by the ICI correction circuit 18. The label value data is a set of label values ​​of multiple selected cell MCi.

[0125] In measuring the threshold voltage distribution of the middle page, multiple judgment processes (readouts) are performed for each of the following: BR readout (readout level VBR), DR readout (readout level VDR), and FR readout (readout level VFR).

[0126] In BR readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the selected word line voltage is shifted to the lower and higher voltage sides within the range of the readout level VCR, from the lower end of the threshold voltage distribution of the "Er" state, relative to the readout level VBR. For example, with respect to BR readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the selected word line voltage shifted by 1 DAC or 2 DACs at a time.

[0127] In DR readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the selected word line voltage is shifted to the lower and higher voltage sides within the range from readout level VCR to readout level VER, with readout level VDR as the reference. For example, with respect to DR readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the selected word line voltage shifted by 1 DAC or 2 DACs at a time.

[0128] In FR readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the selected word line voltage is shifted to the lower and higher voltage sides within the range from the readout level VER to the upper limit of the threshold voltage distribution of the "G" state, with the readout level VFR as the reference. For example, with respect to FR readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the selected word line voltage shifted by 1 DAC or 2 DACs at a time.

[0129] Furthermore, for distribution reads of mid-level pages, CR reads and ER reads (determination processing based on read level VER) are each executed once as level-separated reads. The level-separated read of the CR read classifies the state of the selected cell MCi as either "B" state T2 or lower, or "C" state T3 or higher. The level-separated read of the ER read classifies the state of the selected cell MCi as either "D" state T4 or lower, or "E" state T5 or higher.

[0130] This provides the measurement results of the threshold voltage distribution of selected cells MCi in the middle page. The data regarding the measurement results of the threshold voltage distribution of selected cells MCi in the middle page is transferred from the NAND memory 30 to the memory controller 10. The memory controller 10 uses the ICI correction circuit 18 to calculate the label value of each selected cell MCi in the middle page based on the measurement results. The label value data of each selected cell MCi in the middle page is stored in the RAM 16 by the ICI correction circuit 18.

[0131] In measuring the threshold voltage distribution on the higher-level page, multiple judgment processes (readouts) are performed for both CR readout (readout level VCR) and GR readout (readout level VGR).

[0132] In CR readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the selected word line voltage is shifted to the lower and higher voltage sides within the range of the readout level VDR from the lower end of the threshold voltage distribution of the "Er" state, relative to the readout level VCR. For example, with respect to CR readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the selected word line voltage shifted by 1 DAC or 2 DACs at a time.

[0133] In GR readout, the threshold voltage distribution of the selected cell MCi is measured while the magnitude of the selected word line voltage is shifted to the lower and higher voltage sides within a range from the readout level VER to the upper limit of the threshold voltage distribution of the "G" state, with the readout level VGR as the reference. For example, with respect to GR readout, 31 judgment processes are performed within the above voltage range, with the voltage value of the selected word line voltage shifted by 1 DAC or 2 DACs at a time.

[0134] Additionally, for distribution reads of higher-level pages, an ER read is performed once as a level-separated read. The level-separated read of the ER read classifies the state of the selected cell MCi as either a "D" state (T4 or lower) or an "E" state (T5 or higher).

[0135] This provides the measurement results of the threshold voltage distribution of the selected cell MCi in the upper page. The data regarding the measurement results of the threshold voltage distribution of the selected cell MCi in the upper page is transferred from the NAND memory 30 to the memory controller 10. The memory controller 10 uses the ICI correction circuit 18 to calculate the label value of each selected cell MCi in the upper page based on the measurement results. The label value data of each selected cell MCi in the upper page is stored in the RAM 16 by the ICI correction circuit 18.

[0136] As mentioned above, the number of reads for mid-level pages is greater than the number of reads for lower-level and higher-level pages. Therefore, the data size of the label value data for mid-level pages is larger than the data size of the label value data for lower-level pages and the data size of the label value data for higher-level pages.

[0137] Figure 8 is a schematic diagram showing the data storage state of memory area 160 in RAM 16 before and after the execution of a distribution read.

[0138] Figure 8(a) shows the data storage state of memory area 160 before the distribution read is performed. Figure 8(b) shows the data storage state of memory area 160 after the distribution read is performed.

[0139] In Figure 8, the memory area 160 of RAM 16 is a region reserved for storing various data used for soft-decision reading. For example, the memory area 160 has 10 data storage areas MEM(MEM0, MEM1, ..., MEM9).

[0140] As shown in Figure 8(a), before the distribution read is performed, each of the data storage areas MEM in memory area 160 is in a state where no data is stored.

[0141] As shown in Figure 8(b), after the distribution read is performed, the label value data DX1, DX2, and DX3 of the lower page, middle page, and upper page are stored in the data storage area MEM of the memory area 160, respectively.

[0142] The label value data DX1, DX2, and DX3 for each page span multiple data storage areas MEM. Each label value data DX1, DX2, and DX3 is stored in multiple data units LBUs within each data storage area MEM. <0> ,···,LBU <6> It is divided into.

[0143] Each of the data storage areas MEM0, ..., MEM5 contains the LBU data units for the lower, middle, and upper pages, respectively, which contain the label value data DX1, DX2, and DX3. <0> ,···,LBU <5> Remember this.

[0144] For example, each page's data unit LBU <0> This is stored in the data storage area MEM0. Each page's data unit LBU <1> The data is stored in the data storage area MEM1. Each page has a data unit LBU. <2> This is stored in the data storage area MEM2. Each page has a data unit LBU. <3> This is stored in the data storage area MEM3. Each page has a data unit LBU. <4> This is stored in the data storage area MEM4. Each page has a data unit LBU. <5> This is stored in the data storage area MEM5.

[0145] As described above, the data size of the label value data DX2 on the middle page is larger than the data size of the label value data DX1 on the lower page and the data size of the label value data DX3 on the upper page. Therefore, the data storage area MEM6 does not store the data units of the label value data DX1 and DX3 on the lower and upper pages, but stores the data unit LBU of the label value data DX2 on the middle page. <6> For example, in the data storage area MEM6, the "0" data is stored in the portion corresponding to the label value data DX1 and in the portion corresponding to the label value data DX1.

[0146] The set of data storage areas MEM0, ..., MEM6 corresponds to the first capacity of the memory area 160. This first capacity is substantially equal to the data size of the data read by the distribution data (label value data) DX1, DX2, DX3.

[0147] <s12> After the distribution read is performed, the memory system 1 uses the ICI correction circuit 18 of the memory controller 10 to determine whether the selected word line WLi targeted by the distribution read is the starting word line WL0 (the first word line dress).

[0148] If the selected word line WLi is the starting word line WL0 (YES in S12), the memory system 1 executes the process in S15 described below because there are no adjacent word lines on the source side of the selected word line WLi (WL0).

[0149] <s13> If the selected word line WLi is not the starting word line WL0 (NO in S12), the memory system 1, using the ICI correction circuit 18 of the memory controller 10, causes the NAND memory 30 to perform a read operation for ICI cancellation correction (hereinafter referred to as ICI cancellation read) for the adjacent word line WLi-1 adjacent to the source side of the selected word line WLi.

[0150] The NAND memory 30 performs a hard-determination read operation on all pages of the adjacent word line WLi-1 (in this case, the lower page, middle page, and upper page). As a result, read data for three pages is acquired for the adjacent word line WLi-1.

[0151] The read data for each page in the adjacent word line WLi-1 is transferred from the NAND memory 30 to the memory controller 10. The read data for ICI cancellation correction is stored in the memory area 160 of the RAM 16.

[0152] Figure 9 is a schematic diagram showing the data storage state of memory area 160 in RAM 16 after an ICI cancellation read is performed on the adjacent word line WLi-1.

[0153] As shown in Figure 9, the data read from the adjacent word line WLi-1 for three pages, RD1L, RD1M, and RD1U, is stored in the data storage area MEM of the memory area 160.

[0154] The data RD1L read from the lower page of the adjacent word line WLi-1 is stored in the data storage area MEM. <7> It is stored in the data storage area MEM. The read data RD1M of the middle page of the adjacent word line WLi-1 is stored in the data storage area MEM. <8> It is stored in the data storage area MEM. The read data RD1U of the middle page of the adjacent word line WLi-1 is stored in the data storage area MEM. <9> It is stored in [location].

[0155] The set of data storage areas MEM7, MEM8, and MEM9 corresponds to the second capacity of memory area 160, excluding the first capacity of the set of data storage areas MEM0, ..., MEM6. The second capacity is substantially equal to the data size of the read data RD1L, RD1M, and RD1U read from the adjacent word line WLi-1 (or adjacent word line WLi+1) by an ICI cancel read (for example, the data size of three pages of data).

[0156] <s14> After the ICI cancellation read is performed on the adjacent word line WLi-1, the memory system 1 uses the ICI correction circuit 18 of the memory controller 10 to perform ICI cancellation correction on the distribution read result (label value data) for the selected word line WLi, using the read data RD1L, RD1M, and RD1U from the adjacent word line WLi-1 obtained by the ICI cancellation read.

[0157] The memory controller 10 uses the read data RD1L, RD1M, and RD1U to determine the state of each adjacent cell MCi-1 on the adjacent word line WLi-1.

[0158] The memory controller 10 refers to the lookup table TBL0 for ICI cancellation correction. The memory controller 10 accesses the memory area 160 of RAM 16 and refers to the data in the data storage area MEM.

[0159] The memory controller 10 converts the label values ​​of multiple selected cells MCi connected to the selected word line WLi to values ​​corrected for interference from adjacent cells MCi-1, based on the state (threshold voltage distribution) of adjacent cells MCi-1 obtained from the read data RD1L, RD1M, and RD1U and the correction value in the lookup table TBL0. As a result, the label values ​​of each selected cell MCi are corrected by the first ICI cancellation correction corresponding to the read result for adjacent word line WLi-1.

[0160] Figure 10 is a schematic diagram illustrating ICI cancellation correction using the lookup table TBL0.

[0161] As shown in Figure 10, the lookup table TBL0 is a table containing multiple transformed label values ​​corresponding to the state of adjacent cells. The transformed label values ​​are the corrected label values ​​of the selected cell, pre-set based on the correspondence between the state of adjacent cells and their label values.

[0162] If the label value of the selected cell MCi at a certain address (bit) of the selected word line WLi is "10", and the state of the adjacent cell at the corresponding address of the adjacent word line is "A", the memory controller 10 increases the label value from "10" to "12" based on the lookup table TBL0. As a result, the corrected converted label value of the selected cell MCi is set to "12".

[0163] If the label value of the selected cell MC at a certain address in the selected word line WLi is "20", and the state of the adjacent cell at the corresponding address in the adjacent word line is "G", the memory controller 10 lowers the label value from "20" to "16" based on the lookup table TBL0. As a result, the converted label value is set to "16".

[0164] In this way, multiple label values ​​contained within the label value data DX1, DX2, and DX3 of each page are transformed. As a result, the first transformed label value data DY1, DY2, and DY3, which include the transformed label values, are obtained for the lower-level, middle-level, and upper-level pages.

[0165] Figure 11 is a schematic diagram showing the data storage state of memory area 160 in RAM 16 after ICI cancellation correction based on the reading result of adjacent word line WLi-1.

[0166] As shown in Figure 11, the data stored in each of the data storage areas MEM0, ..., MEM6 is updated.

[0167] The data storage areas MEM0, ..., MEM6 store the converted label value data DY1 for lower pages, the converted label value data DY2 for middle pages, and the converted label value data DY3 for upper pages. The converted label value data DY1, DY2, and DY3 each contain multiple data units yLBU that include the converted label values.

[0168] The data storage areas MEM7, MEM8, and MEM9 maintain the storage state of the read data RD1L, RD1M, and RD1U from the adjacent word line WLi-1.

[0169] <s15> The memory system 1 determines, using the ICI correction circuit 18 of the memory controller 10, whether the selected word line WLi is the word line WLin-1 at the end (last word line address).

[0170] If the selected word line WLi is the terminating word line WLn-1 (YES in S15), the memory system 1 executes the process in S18 described below because there are no adjacent word lines on the drain side of the selected word line WLi (WLn-1).

[0171] <s16> If the selected word line WLi is not the terminating word line WLn-1 (NO in S15), the memory system 1, through the ICI correction circuit 18 of the memory controller 10, causes the NAND memory 30 to perform an ICI cancellation correction read operation (ICI cancellation read) for the adjacent word line WLi+1 that is adjacent to the drain side of the selected word line WLi.

[0172] The NAND memory 30 performs a hard-determination read operation on all pages of the adjacent word line WLi+1 (in this case, the lower page, middle page, and upper page). As a result, read data for three pages is acquired for the adjacent word line WLi+1.

[0173] Read data for each page in the adjacent word line WLi+1 is transferred from the NAND memory 30 to the memory controller 10. Read data for ICI cancellation correction is stored in the memory area 160 of the RAM 16.

[0174] Figure 12 is a schematic diagram showing the data storage state of memory area 160 in RAM 16 after an ICI cancellation read is performed on the adjacent word line WLi+1 when the selected word line WLi is not the terminating word line WLn-1.

[0175] As shown in Figure 12, the read data RD2L, RD2M, and RD2U from the adjacent word line WLi+1 are stored in the data storage area MEM of the memory area 160. For example, the memory controller 10 overwrites the data storage areas MEM7, MEM8, and MEM9, which store the read data RD1L, RD1M, and RD1U, with the read data RD2L, RD2M, and RD2U. In this way, the memory controller 10 updates the data in the data storage areas MEM7, MEM8, and MEM9 with the read data RD2L, RD2M, and RD2U.

[0176] The data RD2L read from the lower page of the adjacent word line WLi+1 is stored in the data storage area MEM. <7> It is stored in the data storage area MEM. The read data RD2M of the middle page of the adjacent word line WLi+1 is stored in the data storage area MEM. <8> It is stored in the data storage area MEM. The read data RD2U of the middle page of the adjacent word line WLi+1 is stored in the data storage area MEM. <9> It is stored in [location].

[0177] The data storage areas MEM1, ..., MEM6 will continue to store the converted label value data DY1, DY2, and DY3.

[0178] Figure 13 is a schematic diagram showing the data storage state of memory area 160 in RAM 16 after an ICI cancellation read is performed on the adjacent word line WLi+1, when the selected word line WLi was the starting word line WL0.

[0179] If the selected word line WLi is the starting word line WL0, then the adjacent word line WLi-1 on the source side does not exist. Therefore, as in S12 above, the ICI cancellation read and ICI cancellation correction related to the adjacent word line WLi-1 are skipped.

[0180] Therefore, if the selected word line WLi is the starting word line WL0, the read data for the adjacent word line WLi-1 is not acquired, and the conversion (correction) of the label value by ICI cancellation correction is not performed.

[0181] As a result, as shown in Figure 13, when the selected word line WLi is the starting word line WL0, the unconverted label value data DX1, DX2, DX3 are stored, and the read data RD2L, RD2M, RD2U from each page of the adjacent word line WLi+1 are stored in the data storage areas MEM7, MEM8, MEM9.

[0182] <s17> After performing an ICI cancellation read on the adjacent word line WLi+1, the memory system 1 uses the ICI correction circuit 18 of the memory controller 10 to perform ICI cancellation correction on the converted label value data DY1, DY2, DY3 (or the label value data DX1, DX2, DX3 before correction) using the read data RD2L, RD2M, RD2U from the adjacent word line WLi+1 acquired by the ICI cancellation read.

[0183] The memory controller 10 uses the read data RD2L, RD2M, and RD2U to determine the state of each adjacent cell MCi+1 on the adjacent word line WLi+1.

[0184] The memory controller 10 refers to the lookup table TBL0 for ICI cancellation correction. The memory controller 10 accesses the memory area 160 of RAM 16 and refers to the data in the data storage area MEM.

[0185] The memory controller 10 converts the label values ​​of multiple selected cells MCi connected to the selected word line WLi based on the state (threshold voltage distribution) of the adjacent cell MCi+1 obtained from the read data RD2L, RD2M, and RD2U and the correction value in the lookup table TBL0. As a result, the label values ​​of the selected cells MCi are corrected by a second (or first) ICI cancellation correction corresponding to the read result for the adjacent word line WLi+1.

[0186] If ICI cancellation correction is performed using the read data RD1L, RD1M, RD1U from the adjacent word line WLi-1 on the source side, the converted label value data DY1, DY2, DY3 are corrected again using the read data RD2L, RD2M, RD2U from the adjacent word line WLi+1 on the drain side.

[0187] Memory system 1, in the same manner as the processing in S14 and Figure 10 described above, converts the converted label values ​​of the data units yLBU for each label value data DY1, DY2, and DY3 again.

[0188] Figure 14 is a schematic diagram showing the data storage state of memory area 160 in RAM 16 after ICI cancellation correction based on the reading result of adjacent word line WLi+1.

[0189] Figure 14 shows the data storage state of memory area 160 after two ICI cancellation corrections when the selected word line WLi is not the start word line WL0 or the end word line WLn-1 (i.e., the selected word line WLi is an intermediate word line).

[0190] As shown in Figure 14, the data stored in each of the data storage areas MEM0, ..., MEM6 is updated.

[0191] The data storage areas MEM0, ..., MEM6 store the second transformed label value data DZ1 for the lower page, the second transformed label value data DZ2 for the middle page, and the second transformed label value data DZ3 for the upper page. The transformed label value data DZ1, DZ2, and DZ3 each contain multiple data units zLBUs, which consist of transformed label values ​​that reflect the states of both adjacent word lines WLi-1 and WLi+1.

[0192] The data storage areas MEM7, MEM8, and MEM9 continue to store the data RD2L, RD2M, and RD2U read from the adjacent word line WLi+1.

[0193] Figure 15 shows the data storage state of the memory area 160 of RAM 16 after ICI cancellation correction based on the reading result of the adjacent word line WLi+1, when the selected word line WLi is the starting word line WL0.

[0194] As described above, when the selected word line WLi is the starting word line WL0, ICI cancellation read and ICI cancellation correction based on the read result of the source-side adjacent word line WLi-1 are not performed. Therefore, the label value is converted to a converted label value by a single conversion process based on the read data RD2L, RD2M, RD2U from the adjacent word line WLi+1. This generates converted label value data DA1, DA2, DA3 for each page of the selected word line WLi, corrected only by the read result of the adjacent word line WLi+1, and stores them in memory area 160. The converted label value data DA1, DA2, DA3 consists of multiple data units aLDU containing converted label values ​​that reflect only the influence of the state of the adjacent cell MCi+1 of the adjacent word line WLi+1.

[0195] If the selected word line WLi is the termination word line, the processes in S16 and S17 are not executed, and the memory system 1 executes the process in S18 while the memory area 160 continues to have the data storage state shown in Figure 11.

[0196] <s18> The memory system 1 generates read data (hereinafter also called soft bit read data) by performing a soft decision process on the converted label value data, which has been corrected by two (or one) ICI cancellation corrections using the ECC circuit 14 or ICI correction circuit 18 of the memory controller 10. For example, the read data is FSB (Full soft bit) read data.

[0197] Furthermore, the generation of read data by the soft judgment process may include various processes, including tracking and / or updating (generating) various tables, based on the results of distribution reads and ICI cancellation reads.

[0198] Memory system 1 transfers the generated read data to host 2.

[0199] As described above, the read operation of the soft judgment of the memory system 1 in this embodiment is completed.

[0200] Furthermore, after the ICI cancellation read and ICI cancellation correction of the adjacent word line WLi+1 adjacent to the drain side of the NAND string NS with respect to the selected word line WLi are performed, the ICI cancellation read and ICI cancellation correction of the adjacent word line WLi-1 adjacent to the source side of the NAND string NS with respect to the selected word line WLi may also be performed.

[0201] (c) Summary In a typical memory system, when generating read data through a soft judgment, various data related to the generation of the soft judgment read data are temporarily stored in RAM.

[0202] To generate highly reliable read data, information from memory cells in adjacent word lines is used in addition to information from memory cells in the selected word line being read. As a result, the amount of information stored in RAM tends to increase during soft-decision read operations.

[0203] Furthermore, in order to generate highly reliable soft-decision read data, it is desirable to use a lookup table with a large data size. However, increasing the data size of the lookup table increases the storage capacity of the memory area allocated in RAM to store that lookup table.

[0204] Increasing RAM storage capacity may be undesirable from the standpoint of reducing memory system specifications and costs.

[0205] In a typical memory system, to generate read data using soft judgment, read data is acquired from one or two adjacent word lines adjacent to the selected word line. To generate highly reliable read data, it is preferable to correct the data from the selected word line with the read data from the two adjacent word lines, taking into account the influence of ICI from the two adjacent word lines.

[0206] As the data size of page data increases, it may become difficult to simultaneously store both the data read from each of the two adjacent word lines in a memory area with a small storage capacity during a soft-decision read operation.

[0207] Therefore, typical memory systems correct data from a selected word line based on a correction value obtained by combining data read from two adjacent word lines. For example, if the memory cell is TLC, eight correction patterns are generated by combining data read from two adjacent word lines. The threshold voltage (label value) of the selected cell is corrected with correction values ​​corresponding to these eight correction patterns. As a result, typical memory systems may have low reliability in reading data for soft decisions.

[0208] In this embodiment, when read data is obtained from both adjacent word lines WLi-1 and WLi+1, the memory system 1 corrects the label value (threshold voltage) of the selected cell MCi of the selected word line WLi for each read data from adjacent word lines WLi-1 and WLi+1. Therefore, in this embodiment, the label value of the selected cell MCi is corrected twice.

[0209] As a result, the memory system 1 of this embodiment can correct the label value of the selected cell MCi by considering the eight possible state (threshold voltage) patterns of the adjacent cell MCi-1 of the adjacent word line WLi-1, and the eight possible state patterns of the adjacent cell MCi+1 of the adjacent word line WLi-1.

[0210] In other words, when the memory cell MC is TLC, 64 possible correction patterns, which can be obtained by combining the state of the adjacent cell of adjacent word line WLi-1 and the state of the adjacent cell of adjacent word line WLi+1, are reflected in each selected cell MCi of the selected word line WLi. In this way, the memory system 1 of this embodiment can correct the label value of the selected cell MCi with a more suitable correction value.

[0211] As a result, the memory system 1 of this embodiment can generate highly accurate read data by soft judgment.

[0212] As described above, the memory system 1 of this embodiment can improve the reliability of data reading.

[0213] (2) Second embodiment A memory system and a control method for the memory system according to a second embodiment will be described with reference to Figures 16 to 23.

[0214] (a) Configuration example Figure 16 is a block diagram illustrating an example configuration of the memory system of this embodiment.

[0215] As shown in Figure 16, the memory system 1 of this embodiment includes a histogram engine (also called a histogram generation circuit) 180. The histogram engine 180 is provided, for example, within the ICI correction circuit 18. The histogram engine 180 may be a circuit independent of the ICI correction circuit 18, or it may be a functional block of the processor 12.

[0216] The histogram engine 180 generates a histogram based on the results of the distribution read and the ICI cancellation read. In this embodiment, the histogram shows the distribution of the number of memory cells turned on in each voltage interval delimited by the selected word line voltage during the distribution read (hereinafter referred to as the number of interval cells) for each state of adjacent cells. The voltage intervals of the selected word line voltage are associated with the label values ​​of the memory cells MC.

[0217] The processor 12 maintains a table (hereinafter referred to as the correction value table) TBL1 (TBL1a, TBL1b) containing correction values ​​obtained based on the histogram. For example, the correction value table TBL1 is stored in the firmware 120 of the processor 12. Note that the firmware 120 and the correction value table TBL1 may be located in the RAM 16.

[0218] Figure 17 is a schematic diagram illustrating the histograms relating to the states of adjacent cells and the number of interval cells in the memory system 1 of this embodiment.

[0219] Figure 17 shows an example of a histogram generated based on the reading results of lower-level pages.

[0220] As described above, in memory system 1, when reading lower pages in distribution read, the voltage is shifted based on the read level VAR of AR read, and the number of ON-state memory cells in each voltage section of the selected word line is counted. This allows the number of section cells in each voltage section to be obtained with respect to the read level VAR. Also, when reading lower pages in distribution read, the voltage is shifted based on the read level VER of ER read, and the number of ON-state memory cells in each voltage section is counted. This allows the number of section cells in each voltage section to be obtained with respect to the read level VER.

[0221] As shown in Figure 17, the memory system 1, using the histogram engine 180 of the memory controller 10, generates a histogram for each state of adjacent cells MCi-1 and MCi+1 in adjacent word lines WLi-1 and WLi+1, based on the result of the ICI cancellation read, relating to the number of interval cells of the selected cell MCi.

[0222] Based on the generated histogram, memory system 1 obtains, for each state of adjacent cells, a label value corresponding to the minimum number of interval cells in the histogram (hereinafter referred to as the minimum cell count label value).

[0223] A correction value for ICI cancellation is calculated by performing a calculation (e.g., a differential calculation) on the acquired minimum cell count label value and the label value of the reference state (e.g., the "Er" state). The correction value table TBL1, which includes the calculated correction value, is stored in the firmware 120 of the processor 12.

[0224] Figure 18 shows an example of the minimum cell count label value obtained by processing using a histogram. In Figure 18, the minimum cell count label value for the reading results of lower pages obtained by the histogram is shown. In Figure 18(a), the minimum cell count label value of the selected cell MCi for AR reading for the state of adjacent cell MCi-1 and the minimum cell count label value of the selected cell MCi for ER reading for the state of adjacent cell MCi-1 are shown in the source-side adjacent word line WLi-1. Also, in Figure 18(b), the minimum cell count label value of the selected cell MCi for AR reading for the state of adjacent cell MCi+1 and the minimum cell count label value of the selected cell MCi for ER reading for the state of adjacent cell MCi+1 are shown in the drain-side adjacent word line WLi+1.

[0225] As shown in Figure 18(a), for adjacent word line WLi-1, in both AR and ER reading of the lower page, the minimum number of cell labels ARN-1, AAn-1, ..., AFn-1, AGn-1, ERN-1, EAN-1, ..., EFn-1, EGn-1 are obtained, respectively, depending on the state of the adjacent cell MCi-1.

[0226] Similarly, as shown in Figure 18(b), for adjacent word line WLi+1, in both AR and ER reading of the lower page, the minimum number of selected cell label values ​​ARN+1, AAn+1, ..., AFn+1, AGn+1, ERN+1, EAN+1, ..., EFn+1, EGn+1 are obtained, respectively, depending on the state of the adjacent cell MCi+1.

[0227] For example, the minimum number of cell label values ​​ARN-1, ARN+1, ERN-1, and ERN+1 when adjacent cells MCi-1 and MCi+1 are in the "Er" state are set as the reference label values ​​(hereinafter referred to as reference label values) for calculating the correction value.

[0228] Figure 19 is a schematic diagram showing an example of correction values ​​obtained by processing using a histogram. In Figure 19, an example of correction values ​​for lower pages is shown according to the states of adjacent cells MCi-1 and MCi+1 of adjacent word lines WLi-1 and WLi+1. In Figure 19(a), the correction values ​​for AR read and ER read for the state of adjacent cell MCi-1 are shown for the source-side adjacent word line WLi-1. Also, in Figure 19(b), the correction values ​​for AR read and ER read for the state of adjacent cell MCi+1 are shown for the drain-side adjacent word line WLi+1.

[0229] As shown in Figures 19(a) and (b), the difference between the minimum cell count label value and the reference label value is set as the correction value.

[0230] For example, as shown in the correction value table TBL1a for the source-side adjacent word line WLi-1 in Figure 19(a), when the adjacent cell MCi-1 is in the "Er" state in the selected cell MCi of the "A" state, the minimum cell number label value is "ARn-1", and the reference label value is "ARn-1". In this case, the correction value is "ARn-1" - "ARn-1".

[0231] Furthermore, as shown in the correction value table TBL1b for the drain-side adjacent word line WLi+1 in Figure 19(b), when the adjacent cell MCi+1 is in the "B" state in the selected cell MCi of the "E" state, the minimum cell number label value is "EBn+1" and the reference label value is "ERn+1". In this case, the correction value is "EBn+1" - "ERn+1".

[0232] In this way, the correction value table TBL1(TBL1a,TBL1b) for the lower pages is generated.

[0233] For example, memory system 1 generates a correction value table TBL1a for the source-side adjacent word line WLi-1 and a correction value table TBL1b for the drain-side adjacent word line WLi+1.

[0234] Similarly to the mid-level and upper-level pages, histograms are generated for each of the adjacent word lines WLi-1 and WLi+1, as in the examples shown in Figures 17 and 18, and the minimum cell count label value is obtained based on the generated histograms. Similar to the example shown in Figure 19, based on the obtained minimum cell count label value, correction values ​​for the selected cell MCi label value are calculated for the mid-level and upper-level pages, according to the state of adjacent cells MCi-1 and MCi+1. Based on the calculated correction values, correction value tables TBL1 (TBL1a, TBL1b) for the mid-level and upper-level pages are generated.

[0235] The memory system 1 of this embodiment dynamically calculates correction values ​​based on the results of read operations for the selected word line WLi and adjacent word lines WLi-1 and WLi+1, without using a lookup table that includes pre-calculated correction values.

[0236] This allows the memory system 1 of this embodiment to further improve the accuracy of ICI cancellation correction.

[0237] (b) Example of operation Referring to Figures 20 to 23, an example of the operation of the memory system 1 of this embodiment (a control method for the memory system 1) will be described.

[0238] Figure 20 is a flowchart showing an example of the operation of the memory system 1 in this embodiment. Figures 21 to 23 are schematic diagrams illustrating an example of the operation of the memory system 1 of this embodiment.

[0239] <S11,S12,S13> As shown in Figure 20, in this embodiment, after performing a distribution read on the selected word line WLi, if the selected word line WLi is not the starting word line WL0 (NO in S12), the memory system 1 performs a hard-determination read operation (ICI cancel read) on all pages of the adjacent word line WLi-1 on the source side.

[0240] The data obtained by distribution reads and ICI cancellation reads for adjacent word lines WLi-1 is stored in the memory area 160 of RAM 16, as shown in Figure 9 above.

[0241] Furthermore, if the selected word line WLi is the starting word line WL0, the memory system 1 executes the process in S15 after performing the distribution read.

[0242] <s21> The memory system 1 uses the histogram engine 180 of the memory controller 10 to generate a histogram (first histogram) relating to the state and number of interval cells of adjacent cell MCi-1 of adjacent word line WLi-1, as shown in Figure 17, using the distribution read data (label value data) DX1, DX2, DX3 and the ICI cancellation read data RD1L, RD1M, RD1U.

[0243] <s22> Memory system 1 obtains the minimum cell count label value and reference label value in the adjacent word line WLi-1 based on the histogram of the generated adjacent word line WL-1, as shown in Figure 18. Memory system 1 obtains multiple correction values ​​for each state of memory cell MC, according to the relationship between the state of the selected cell MCi (read result) and the state of the adjacent cell MCi-1 of the adjacent word line WLi-1, by performing a calculation process (e.g., differential processing) between the obtained minimum cell count label value and reference label value, as shown in Figure 19.

[0244] The memory system 1 stores the correction value for the adjacent word line WLi-1 in the firmware 120 of the processor 12. As a result, the correction value table TBL1 is stored in the firmware 120.

[0245] <S15,S16> If the selected word line WLi is not the terminating word line WLn-1 (NO in S15), the memory system 1 performs a hard-determination read operation (ICI cancel read) for all pages of the adjacent word line WLi+1 on the drain side. The data read from all pages of the adjacent word line WLi+1 is stored in the memory area 160 of RAM 16, as shown in Figure 13 above. Therefore, the data read from the adjacent word line WLi-1 is erased from the memory area 160.

[0246] <s23> The memory system 1 uses the histogram engine 180 of the memory controller 10 to generate a histogram (second histogram) relating to the state and number of interval cells of the adjacent cell MCi+1 of the adjacent word line WLi+1, as shown in Figure 17, using the distribution read data DX1, DX2, DX3 and the ICI cancellation read data RD2L, RD2M, RD2U for the adjacent word line WLi+1.

[0247] <s24> The memory system 1 acquires the minimum cell count label value and the reference label value in the adjacent word line WLi+1, as shown in Figure 18, based on the histogram generated by the ICI correction circuit 18 of the memory controller 10. The memory system 1 acquires multiple correction values ​​for each state of the memory cell MC, according to the relationship between the state of the selected cell MCi and the state of the adjacent cell MCi+1 of the adjacent word line WLi+1, by performing a calculation (difference processing) between the acquired minimum cell count label value and the reference label value, as shown in Figure 19.

[0248] The memory system 1 stores the correction value for the adjacent word line WLi+1 in the firmware 120 of the processor 12. As a result, the correction value table TBL1 is stored in the firmware 120.

[0249] <s25> The memory system 1, using the ICI correction circuit 18 of the memory controller 10, performs ICI cancellation correction on the read data (label value data) of the selected cell MCi obtained by distribution read, based on the correction values ​​in the correction value table TBL1 and the read data RD2L, RD2M, RD2M of the adjacent word line WLi+1. As a result, the label value of each selected cell MCi obtained by distribution read is corrected.

[0250] Figure 21 shows the data storage state of the memory area 160 of RAM 16 after ICI cancellation correction according to the state of the adjacent cell MCi+1 of the adjacent word line WLi+1.

[0251] As shown in Figure 21, the corrected label value data DP1, DP2, and DP3 are stored in memory area 160. The label values ​​in the data storage areas MEM0, ... MEM6 of memory area 160 are converted to corrected label values ​​based on the correction values ​​obtained from the histogram related to the adjacent word line WLi+1. As a result, the corrected data units pLBU in the converted label value data DP1, DP2, and DP3 are stored in the data storage areas MEM0, ... MEM6.

[0252] After this, the data read from the erased adjacent word line WLi-1 is read again.

[0253] <s26> Memory system 1 determines whether the selected word line WLi is an intermediate word line. If the selected word line WLi is not an intermediate word line (NO in S26), memory system 1 executes the process in S28 described below.

[0254] <s27> If the selected word line WLi is an intermediate word line (YES in S26), the memory system 1 performs an ICI cancellation read on all pages of the adjacent word line WLi-1, substantially the same as the process in S13. The data read from all pages of the adjacent word line WLi-1 is stored in the memory area 160.

[0255] Figure 22 shows the data storage state of memory area 160 of RAM 16 after an ICI cancellation read for adjacent word line WLi-1.

[0256] As shown in Figure 22, the data RD1L, RD1M, and RD1U read from the adjacent word line WLi-1 are stored in MEM7, MEM8, and MEM9 of memory area 160. The data read from the adjacent word line WLi+1 is erased from memory area 160.

[0257] Furthermore, if ICI cancellation correction is performed for the adjacent word line WLi+1, the corrected label value data DP1, DP2, DP3 are stored in the data storage areas MEM0, ... MEM6.

[0258] <s28> After the second ICI cancellation read for the adjacent word line WLi-1, the memory system 1, using the ICI correction circuit 18 of the memory controller 10, determines whether the selected word line WLi is the starting word line WL0.

[0259] If the selected word line WLi is the starting word line WL0 (YES in S28), the memory system 1 executes the process in S18.

[0260] <s29> When the selected word line WLi is not the starting word line WL0 (NO in S28), the memory system 1 uses the ICI correction circuit 18 of the memory controller 10 to perform ICI cancellation correction on the read data (corrected label value data or original label value data) of the selected cell MCi based on the correction value in the correction value table TBL1 and the re-acquired read data RD1L, RD1M, RD1U of the adjacent word line WLi-1. As a result, the label value of each selected cell MCi is corrected.

[0261] FIG. 23 shows the data storage state of the memory area 160 of the RAM 16 after ICI cancellation correction according to the state of the adjacent cell MCi-1 of the adjacent word line WLi-1.

[0262] As shown in FIG. 23, the corrected label value data DO1, DO2, DO3 are stored in the memory area 160. The label values in the data storage areas MEM0, ··· MEM6 of the memory area 160 are converted into corrected label values based on the correction values obtained from the histogram related to the adjacent word line WLi-1. As a result, the corrected data unit oLBU in the converted label value data DO1, DO2, DO3 is stored in the data storage areas MEM0, ··· MEM6.

[0263] For example, both the correction value according to the state of the adjacent cell MCi+1 of the adjacent word line WLi+1 and the correction value according to the state of the adjacent cell MCi-1 of the adjacent word line WLi-1 are reflected in the label values of the plurality of data units oLBU of the data DO1, DO2, DO3.

[0264] <s18> The memory system 1 generates soft bit readout data by performing a soft decision process on the converted label value data, which has been corrected by the ICI cancellation correction of one or both of the adjacent word lines WLi-1,i+1, using the ECC circuit 14 or ICI correction circuit 18 of the memory controller 10.

[0265] The memory controller 10 transfers the generated soft bit read data to the host 2.

[0266] As described above, the read operation of the soft judgment of the memory system 1 in this embodiment is completed.

[0267] (c) Summary The memory system 1 of this embodiment dynamically calculates correction values ​​based on the results of a read operation, without using a lookup table that includes pre-calculated correction values.

[0268] This allows the memory system 1 of this embodiment to further improve the accuracy of ICI cancellation correction.

[0269] Therefore, the memory system 1 of this embodiment can improve the reliability of data retrieval.

[0270] (4) Others In the memory system of this embodiment, the memory device 30 may be a memory device other than NAND flash memory. For example, the memory device 30 may be a volatile memory such as DRAM.

[0271] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0272] 1: Memory system, 10: Memory controller, 12: Processor, 120: Firmware, 18: ICI correction circuit, 180: Histogram engine, 30: Memory device, 31: Memory cell array, MC: Memory cell, WL: Word line, WLi: Selected word line, WLi-1, WLi+1: Adjacent word lines.

Claims

1. A memory device including multiple word lines and multiple memory cells connected to each of the multiple word lines, A memory controller that controls the read operation of the memory device, It is equipped with, The aforementioned memory controller First data is obtained regarding the threshold voltages of multiple selected cells connected to a selected word line among the multiple word lines. Second data is obtained from a plurality of first adjacent cells connected to a first adjacent word line adjacent to one end of the selected word line among the plurality of word lines. Based on the second data, the first data is corrected to obtain the first corrected data. From among the plurality of word lines, obtain third data from a plurality of second adjacent cells connected to a second adjacent word line adjacent to the other end of the selected word line. Based on the third data, the first correction data is corrected to obtain the second correction data. A soft judgment process is performed on the second correction data to generate read data from the plurality of selected cells. Memory system.

2. The first data includes a plurality of label values ​​corresponding to the threshold voltage of each of the plurality of selected cells, The memory controller includes a first table showing the relationship between the threshold voltage state of each of the plurality of first and second adjacent cells and the corrected label value, The memory controller corrects the plurality of label values ​​according to the threshold voltage state of each of the plurality of first and second adjacent cells based on the first table. The memory system according to claim 1.

3. The aforementioned memory controller A first histogram is generated that shows the relationship between the threshold voltage state of each of the plurality of first adjacent cells and a plurality of label values ​​corresponding to the threshold voltage of the plurality of selected cells. Based on the first histogram, a plurality of first correction values ​​corresponding to the threshold voltage state of each of the plurality of first adjacent cells are calculated. A second histogram is generated that shows the relationship between the threshold voltage state of each of the plurality of second adjacent cells and a plurality of label values ​​corresponding to the threshold voltage of the plurality of selected cells. Based on the second histogram, a plurality of second correction values ​​corresponding to the threshold voltage state of each of the plurality of second adjacent cells are calculated. Each of the plurality of label values ​​is corrected based on the plurality of first and second correction values. The memory system according to claim 1.

4. The memory controller generates a second table relating to the plurality of first and second correction values ​​based on the first and second histograms. The memory system according to claim 3.

5. The memory controller includes firmware that stores the second table, The memory system according to claim 4.

6. The aforementioned memory controller includes a memory area, The aforementioned memory controller The first data is stored in the first storage area of ​​the memory area. The second data is stored in the second storage area of ​​the memory area. The second data in the second storage area is updated with the third data, and the third data is stored in the second storage area. The memory system according to claim 1.

7. The aforementioned memory controller The first data in the first storage area is updated with the first correction data, and the first correction data is stored in the first storage area. The first correction data in the first storage area is updated with the second correction data, and the second correction data is stored in the first storage area. The memory system according to claim 6.

8. The aforementioned memory controller Based on the second data, the threshold voltage state of each of the plurality of first adjacent cells is determined. The first data is corrected according to the threshold voltage state of each of the plurality of first adjacent cells. Based on the third data, the threshold voltage state of each of the plurality of second adjacent cells is determined. The first correction data is corrected according to the threshold voltage state of each of the plurality of second adjacent cells. The memory system according to claim 1.

9. The memory controller corrects errors in the first data caused by a shift in the threshold voltage of the plurality of selected cells in response to interference between the plurality of selected cells and the plurality of first adjacent cells or interference between the plurality of selected cells and the plurality of second adjacent cells. The memory system according to claim 1.

10. A memory device including multiple word lines and multiple memory cells connected to each of the multiple word lines, A memory controller including a memory area for storing data acquired from the plurality of memory cells, It is equipped with, The aforementioned memory controller First data relating to the threshold voltages of multiple selected cells connected to a selected word line among the multiple word lines is stored in a first storage area of ​​the memory area. The second data obtained from a plurality of first adjacent cells connected to a first adjacent word line adjacent to one end of the selected word line among the plurality of word lines is stored in the second storage area of ​​the memory area. Based on the second data, the first data is corrected to generate the first corrected data. The first correction data is stored in the first storage area. The third data obtained from a plurality of second adjacent cells connected to a second adjacent word line adjacent to the other end of the selected word line among the plurality of word lines is stored in the second storage area. Based on the third data, the first correction data is corrected to generate the second correction data. The second correction data is stored in the first storage area. A soft judgment process is performed on the second correction data to generate read data from the plurality of selected cells. Memory system.

11. The first data includes a plurality of label values ​​corresponding to the threshold voltages of the plurality of selected cells, The memory controller includes a first table showing the relationship between the threshold voltage state of each of the plurality of first and second adjacent cells and the corrected label value, The memory controller corrects the plurality of label values ​​according to the threshold voltage state of each of the plurality of first and second adjacent cells based on the first table. The memory system according to claim 10.

12. The aforementioned memory controller A first histogram is generated that shows the relationship between the threshold voltage state of each of the plurality of first adjacent cells and a plurality of label values ​​corresponding to the threshold voltage of the plurality of selected cells. Based on the first histogram, a plurality of first correction values ​​corresponding to the threshold voltage state of each of the plurality of first adjacent cells are calculated. A second histogram is generated that shows the relationship between the threshold voltage state of each of the plurality of second adjacent cells and a plurality of label values ​​corresponding to the threshold voltage of the plurality of selected cells. Based on the second histogram, a plurality of second correction values ​​corresponding to the threshold voltage state of each of the plurality of second adjacent cells are calculated. Each of the plurality of label values ​​is corrected based on the plurality of first and second correction values. The memory system according to claim 10.

13. The memory controller generates a second table relating to the plurality of first and second correction values ​​based on the first and second histograms. The memory system according to claim 12.

14. The memory controller includes firmware that stores the second table, The memory system according to claim 13.

15. The aforementioned memory controller Based on the second data, the threshold voltage state of each of the plurality of first adjacent cells is determined. The first data is corrected according to the threshold voltage state of each of the plurality of first adjacent cells. Based on the third data, the threshold voltage state of each of the plurality of second adjacent cells is determined. The first correction data is corrected according to the threshold voltage state of each of the plurality of second adjacent cells. The memory system according to claim 10.

16. The memory controller corrects errors in the first data caused by a shift in the threshold voltage of the plurality of selected cells in response to interference between the plurality of selected cells and the plurality of first adjacent cells or interference between the plurality of selected cells and the plurality of second adjacent cells. The memory system according to claim 10.

17. First data is obtained regarding the threshold voltages of multiple selected cells connected to a selected word line among multiple word lines. Second data is obtained from a plurality of first adjacent cells connected to a first adjacent word line adjacent to one end of the selected word line among the plurality of word lines. Based on the second data, the first data is corrected to obtain the first corrected data. From among the plurality of word lines, obtain third data from a plurality of second adjacent cells connected to a second adjacent word line adjacent to the other end of the selected word line. Based on the third data, the first correction data is corrected to obtain the second correction data. A soft judgment process is performed on the second correction data to generate read data from the plurality of selected cells. A method for controlling a memory system.

18. The aforementioned first data is stored in the first storage area of ​​the memory area, The second data is stored in the second storage area of ​​the memory area. The second data in the second storage area is updated with the third data, and the third data is stored in the second storage area. A method for controlling a memory system according to claim 17.

19. The first data in the first storage area is updated with the first correction data, and the first correction data is stored in the first storage area. The first correction data in the first storage area is updated with the second correction data, and the second correction data is stored in the first storage area. A method for controlling a memory system according to claim 18.

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