Semiconductor memory

Abstract

To provide a semiconductor memory device that suppresses the deterioration of reliability. [Solution] The semiconductor memory device according to the present disclosure includes a semiconductor substrate including a first region which is a source region or a drain region, and a second region which is a source region or a drain region and is spaced apart from the first region in a first direction; a first contact connected to the first region; a second contact connected to the second region; a first memory cell connected to the first contact; a gate electrode formed between the first contact and the second contact; a first conductor of the same height as the gate electrode and electrically connected to the first contact; and a second conductor of the same height as the gate electrode, at least a portion of which is formed between the gate electrode and the second contact and is insulated from the gate electrode, the first contact, and the second contact.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device capable of storing data non-volatily, a NAND type flash memory is known. In a semiconductor memory device such as a NAND type flash memory, a three-dimensional memory structure is adopted for high integration and large capacity.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress a decrease in the reliability of the semiconductor memory device.

Means for Solving the Problems

[0005] This embodiment discloses a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate including a first region that is a source region or a drain region and a second region that is spaced apart from the first region in a first direction and is a source region or a drain region, a first contact connected to the first region, a second contact connected to the second region, a first memory cell connected to the first contact, a gate electrode formed between the first contact and the second contact, a first conductor having the same height as the gate electrode and being electrically connected to the first contact, and a second conductor having the same height as the gate electrode, at least a part of which is formed between the gate electrode and the second contact and is insulated from the gate electrode, the first contact, and the second contact. Furthermore, the term "a semiconductor substrate including a 'first region' and a 'second region'" includes known configurations such as one in which a source region or drain region, which is the first region or the second region, is formed within a P-type well region or N-type well region provided in a semiconductor layer stacked on a substrate such as a silicon substrate that constituted a semiconductor wafer. [Brief explanation of the drawing]

[0006] [Figure 1] This block diagram shows an example of the configuration of a memory system including a semiconductor storage device according to the embodiment. [Figure 2] This is a circuit diagram showing an example of the circuit configuration of a memory cell array included in a semiconductor memory device according to the embodiment. [Figure 3] This is a cross-sectional view showing an example of the cross-sectional structure of a semiconductor memory device according to the embodiment. [Figure 4] This is a circuit diagram showing an example of the configuration of a low decoder module, driver module, and memory cell array of a semiconductor memory device according to an embodiment. [Figure 5] This is a circuit diagram showing an example of the configuration of a block decoder included in a semiconductor memory device according to the embodiment. [Figure 6] This is a plan view showing an example of the planar structure of a low decoder module of a semiconductor memory device according to an embodiment. [Figure 7] This is a plan view showing an example of the planar structure of a transfer transistor in a semiconductor memory device according to the embodiment. [Figure 8A] This is a cross-sectional view along line AA in Figure 7, showing an example of the cross-sectional structure of a transfer transistor in a semiconductor memory device according to the embodiment. [Figure 8B] This is a cross-sectional view along line BB in Figure 7, showing an example of the cross-sectional structure of a transfer transistor in a semiconductor memory device according to the embodiment. [Figure 9A] This is a cross-sectional view showing the configuration of a transfer transistor related to a comparative example. [Figure 9B] This is a cross-sectional view showing the configuration of a transfer transistor according to an embodiment. [Figure 10]This is a plan view showing an example of the planar structure of a transfer transistor in a semiconductor memory device according to one embodiment. [Figure 11] This is a plan view showing an example of the planar structure of a transfer transistor in a semiconductor memory device according to one embodiment. [Figure 12] This is a plan view showing an example of the planar structure of a transfer transistor in a semiconductor memory device according to one embodiment. [Figure 13] This is a plan view showing an example of the planar structure of a transfer transistor in a semiconductor memory device according to one embodiment. [Figure 14] This is a plan view showing an example of the planar structure of a transfer transistor in a semiconductor memory device according to one embodiment. [Figure 15] This is a plan view showing an example of the planar structure of multiple transfer transistors in a semiconductor memory device according to one embodiment. [Figure 16A] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16B] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16C] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16D] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16E] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16F] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16G] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16H] This is a schematic diagram showing the manufacturing process of the transfer transistors included in the semiconductor memory device according to the embodiment. [Figure 16I]It is a schematic diagram showing a manufacturing process of a transfer transistor included in a semiconductor memory device according to an embodiment. [Figure 16J] It is a schematic diagram showing a manufacturing process of a transfer transistor included in a semiconductor memory device according to an embodiment. [Figure 16K] It is a schematic diagram showing a manufacturing process of a transfer transistor included in a semiconductor memory device according to an embodiment. [Figure 16L] It is a schematic diagram showing a manufacturing process of a transfer transistor included in a semiconductor memory device according to an embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, this embodiment will be described with reference to the accompanying drawings. The dimensions and ratios in the drawings are not necessarily the same as the actual ones. For ease of understanding the description, the same reference numerals are attached to the same components in each drawing as much as possible, and redundant descriptions are omitted.

[0008] 1. Embodiment 1.1 Configuration 1.1.1 Memory System FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0009] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0010] The memory system 3 is, for example, a memory card such as an SD card, UFS (Universal Flash Storage), and SSD (Solid State Drive). The memory system 3 is connected to an external host device not shown.

[0011] The memory controller 2 is composed of an integrated circuit, such as a System-on-a-Chip (SoC). The memory controller 2 controls the semiconductor memory device 1 based on requests from the host device. Specifically, for example, the memory controller 2 writes data requested to be written by the host device to the semiconductor memory device 1. The memory controller 2 also reads data requested to be read from the semiconductor memory device 1 and transmits it to the host device.

[0012] The semiconductor memory device 1 is, for example, a NAND flash memory. The semiconductor memory device 1 stores data non-volatilely. The semiconductor memory device 1 is connected to the memory controller 2 via the NAND bus B.

[0013] NAND bus B is, for example, a bus that conforms to an SDR (Single Data Rate) interface, a toggle DDR (Double Data Rate) interface, or ONFI (Open NAND Flash Interface).

[0014] 1.1.2 Semiconductor Memory Devices Next, the internal configuration of the semiconductor memory device 1 according to the embodiment will be described with reference to the block diagram shown in Figure 1. The semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0015] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cell transistors capable of storing data non-volatilely, and is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. One memory cell transistor is associated with, for example, one bit line and one word line.

[0016] The command register 11 holds the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, instructions that cause the sequencer 13 to perform read operations, write operations, and erase operations.

[0017] The address register 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, the page address PA, the block address BA, and the column address CA. For example, the page address PA, the block address BA, and the column address CA are used for selecting word lines, block lines BLK, and bit lines, respectively.

[0018] The sequencer 13 controls the operation of the entire semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD held in the command register 11, to perform read operations, write operations, erase operations, etc.

[0019] The driver module 14 generates voltages used in read, write, and erase operations. The driver module 14 then applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PA held in the address register 12.

[0020] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. The row decoder module 15 then transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0021] The sense amplifier module 16 transfers data DAT between the memory controller 2 and the memory cell array 10. The data DAT includes written data and read data. More specifically, during a write operation, the sense amplifier module 16 transfers the written data received from the memory controller 2 to the memory cell array 10. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell transistors based on the voltage of the bit line. The sense amplifier module 16 then transfers the result of this determination to the memory controller 2 as read data.

[0022] 1.1.3 Circuit configuration of memory cell array Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array in a semiconductor memory device according to the embodiment. In Figure 2, one of several block BLKs included in the memory cell array 10 is shown. In the example shown in Figure 2, the block BLK includes, for example, five string units SU0 to SU4.

[0023] Each string unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage layer to hold data non-volatilely. The selection transistors ST1 and ST2 are used to select the string unit SU during various operations. In the following description, memory cell transistors MT0 to MT7 are also referred to as memory cell transistors MT. Some of the memory cell transistors MT may include dummy cell transistors (not shown) that are not used to hold valid data.

[0024] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. One end of selection transistor ST1 is connected to the associated bit line BL, and the other end of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. One end of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The other end of selection transistor ST2 is connected to the source line SL.

[0025] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 in string units SU0 to SU4 are connected to selection gate lines SGD0 to SGD4, respectively. In contrast, the gates of multiple selection transistors ST2 are commonly connected to the selection gate line SGS. However, this is not limited to this configuration, and the gates of multiple selection transistors ST2 may each be connected to different selection gate lines for each string unit SU. In the following explanation, when word lines WL0 to WL7 are not distinguished, they will simply be referred to as word lines WL. Similarly, when selection gate lines SGD0 to SGD4 are not distinguished, they will simply be referred to as selection gate lines SGD.

[0026] Each of the bit lines BL0 to BLm connects a single NAND string NS contained in each string unit SU across multiple block BLKs. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, across multiple block BLKs.

[0027] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0028] The circuit configuration of the memory cell array 10 in the semiconductor memory device 1 according to this embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0029] 1.1.4 Cross-sectional structure of semiconductor memory devices Next, the cross-sectional structure of the semiconductor memory device 1 according to the embodiment will be described with reference to Figure 3. Figure 3 is a cross-sectional view showing an example of the cross-sectional structure of the semiconductor memory device according to the embodiment. Figure 3 shows a cross-sectional structure including two of the five string units SU included in one block BLK.

[0030] In the drawings referenced below, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate 20 on which the semiconductor memory device 1 is formed.

[0031] The memory cell array 10 includes conductive layers 21, 22, 24, and 25, a plurality of conductive layers 23, and a plurality of memory pillars MP (only two are shown in Figure 3), which are provided above the semiconductor substrate 20. In the following description, the direction in which the memory cell array 10 is provided relative to the semiconductor substrate 20 is referred to as the upward direction, and the opposite direction is referred to as the downward direction.

[0032] An insulating layer 30 is provided on the semiconductor substrate 20. The insulating layer 30 includes peripheral circuits PERI, such as a low decoder module 15.

[0033] A conductive layer 21 is laminated on the insulating layer 30. The conductive layer 21 is formed in a plate shape that extends along the XY plane, for example. The conductive layer 21 is used as a source wire SL. The conductive layer 21 is composed of a conductive material, and metallic materials such as an impurity-doped N-type semiconductor, or a compound containing nitrogen and titanium (TiN), a compound containing nitrogen and tantalum (TaN), aluminum (Al), a laminated film of a compound containing nitrogen and tantalum (TaN) and tantalum (Ta), a laminated film of titanium (Ti), a compound containing nitrogen and titanium (TiN) and tungsten (W), or a laminated film of a compound containing nitrogen and titanium (TiN), tungsten and silicon-containing silicide (WSi) can be used. Alternatively, the conductive layer 21 may have a laminated structure of a semiconductor and a metallic material, such as a laminated film of a compound containing nitrogen and titanium (TiN), tungsten and silicon-containing silicide (WSi) and polysilicon.

[0034] An insulating layer 31 is provided on the conductive layer 21. A conductive layer 22 is laminated on the insulating layer 31. The conductive layer 22 is formed in a plate shape that extends along the XY plane, for example. The conductive layer 22 is used as a selectable gate wire (SGS). The conductive layer 22 contains, for example, tungsten (W) or molybdenum (Mo).

[0035] An insulating layer 32 is provided on the conductive layer 22. Eight conductive layers 23 and eight insulating layers 33 are stacked on the insulating layer 32 in the order of conductive layer 23, insulating layer 33, ... conductive layer 23, insulating layer 33. The conductive layer 23 is formed in a plate shape that extends along the XY plane, for example. The eight stacked conductive layers 23 are used as word lines WL0 to WL7, in order from the conductive layer 21 side. The conductive layer 23 contains, for example, tungsten (W) or molybdenum (Mo).

[0036] A conductive layer 24 and another conductive layer 34 are stacked in this order on the uppermost insulating layer 33. The conductive layer 24 is formed in a plate shape that extends along the XY plane, for example. The stacked conductive layers 24 are used as a selection gate wire SGD. The conductive layer 24 contains, for example, tungsten (W) or molybdenum (Mo). The conductive layer 24 is electrically isolated for each string unit SU by, for example, a slit SHE.

[0037] An insulating layer 34 is provided on the conductive layer 24. A conductive layer 25 is provided on the insulating layer 34. The conductive layer 25 is formed, for example, in the shape of a line extending in the Y direction and functions as a bit line BL. The conductive layer 25 contains, for example, copper (Cu).

[0038] Multiple memory pillars MP are provided extending along the Z direction below the conductive layer 25, penetrating conductive layers 22 and 24, as well as multiple conductive layers 23. The bottom of each memory pillar MP is located below the insulating layer 31 and is in contact with the conductive layer 21.

[0039] Each of the memory pillars MP includes, for example, a core member 35, a semiconductor film 36, a tunnel insulating film 37, a charge storage film 38, a block insulating film 39, and a semiconductor portion 26.

[0040] The core member 35 is provided, for example, extending along the Z direction. The upper end of the core member 35 is included in a layer above the conductive layer 24, and the lower end of the core member 35 is included in a layer below the conductive layer 22. The core member 35 contains, for example, a compound (SiO2) containing oxygen and silicon.

[0041] The semiconductor film 36 is provided so as to cover the side and bottom surfaces of the core member 35. The upper end of the semiconductor film 36 reaches the same position as the upper end of the core member 35. The lower end of the semiconductor film 36 is in contact with the conductive layer 21. The semiconductor film 36 contains, for example, polysilicon.

[0042] The tunnel insulating film 37 covers the sides of the semiconductor film 36. The tunnel insulating film 37 includes, for example, a compound containing oxygen and silicon (SiO2).

[0043] The charge storage film 38 covers the side surface of the tunnel insulating film 37. The charge storage film 38 includes, for example, an insulator capable of storing charge. This insulator is, for example, a compound containing nitrogen and silicon (SiN).

[0044] The block insulating film 39 covers the sides of the charge storage film 38. The block insulating film 39 contains, for example, a compound (SiO2) containing oxygen and silicon.

[0045] The semiconductor portion 26 is provided in contact with the semiconductor film 36 and covering the upper end of the core member 35. A conductive layer 27, which functions as a columnar contact CV, is provided at the upper end of the semiconductor portion 26. The upper end of the conductive layer 27 is in contact with the conductive layer 25.

[0046] In the structure of the memory pillar MP described above, the portion where the memory pillar MP intersects with the conductive layer 22 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with the conductive layer 23 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 24 functions as a selection transistor ST1. The semiconductor film 36 functions as the channels for the memory cell transistors MT0 to MT7, and the selection transistors ST1 and ST2. The charge storage film 38 functions as the charge storage layer for the memory cell transistor MT.

[0047] 1.1.5 Raw Decoder Module Next, we will describe an example configuration of the low decoder module 15 included in the peripheral circuit PERI.

[0048] 1.1.5.1 Overall Structure The overall configuration of the row decoder module 15 will be explained using Figure 4. Figure 4 is a circuit diagram illustrating an example of the configuration of the row decoder module, driver module, and memory cell array of a semiconductor memory device according to the embodiment.

[0049] The row decoder module 15 includes row decoders RD0 to RDn. Row decoders RD0 to RDn are used for selecting block BLK. Each row decoder RD0 to RDn is associated with block BLK0 to BLKn.

[0050] Each row decoder RD includes, for example, a block decoder BD, and transfer transistors TW0-TW7, TS, and TD0-TD4. Transfer transistors TW0-TW7, TS, and TD0-TD4 are, for example, high-voltage N-channel MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). Transfer transistors TW0-TW7 are associated with word lines WL0-WL7, respectively. In the following description, when transfer transistors TW0-TW7 are not distinguished, they will simply be referred to as transfer transistors TW. Transfer transistors TS and TD0-TD4 are associated with select gate lines SGS and SGD0-SGD4, respectively. In the following description, when transfer transistors TD0-TD4 are not distinguished, they will simply be referred to as transfer transistors TD. Furthermore, a high-voltage MOSFET is a MOSFET with a gate insulating film thickness of 10 nm or more. The gate-source voltage of a high-voltage N-channel MOSFET can be, for example, 10 V or more.

[0051] The block decoder BD decodes the block address BA. Based on the result of this decoding, the block decoder BD applies a "H (High)" level voltage and a "L (Low)" level voltage to the transfer gate line BLKSEL, for example.

[0052] The transfer transistors TW0-TW7, TS, and TD0-TD4 connect the driver module 14 and the corresponding block BLK via signal lines CG0-CG7, CGS, and CGD0-CGD4, respectively. In the following description, when signal lines CG0-CG7, CGS, and CGD0-CGD4 are not distinguished, they will simply be referred to as signal lines CG.

[0053] More specifically, in each row decoder RD, the gate of the transfer transistor TD is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TD is connected to the driver module 14 via the corresponding signal line CG from among the signal lines CGD0 to CGD4. The second end of the transfer transistor TD is connected to the corresponding selected gate line SGD from among the selected gate lines SGD0 to SGD4.

[0054] Each gate of the transfer transistor TW is connected to the transfer gate line BLKSEL. The first end of each transfer transistor TW is connected to the driver module 14 via the corresponding signal line CG from among the signal lines CG0 to CG7. The second end of each transfer transistor TW is connected to the corresponding word line WL from among the word lines WL0 to WL7.

[0055] The gate of the transfer transistor TS is connected to the transfer gate line BLKSEL. The first end of the transfer transistor TS is connected to the driver module 14 via the signal line CGS. The second end of the transfer transistor TS is connected to the selection gate line SGS.

[0056] When a high voltage is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD turn ON. As a result, the voltages of each signal line CG0-CG7, CGS, and CGD0-CGD4 are transferred to the word lines WL0-WL7, the select gate lines SGS, and the select gate lines SGD0-SGD4, respectively, via the transfer transistors TW0-TW7, TS, and TD0-TD4. When a low voltage is applied to the transfer gate line BLKSEL, the transfer transistors TW, TS, and TD turn OFF.

[0057] 1.1.5.2 Block Decoder The configuration of the block decoder BD included in each row decoder RD will be explained with reference to Figure 5. Figure 5 is a circuit diagram illustrating an example of the configuration of a block decoder included in a semiconductor memory device according to the embodiment.

[0058] As shown in Figure 5, the block decoder BD includes a logic circuit LC, a logic AND circuit, inverters INV1 and INV2, and transistors T1, T2, T3, and T4. Transistors T1, T2, and T4 are N-channel MOSFETs. Transistor T3 is a P-channel MOSFET. Transistors T2, T3, and T4 are high-voltage MOSFETs with a thicker gate insulating film than transistor T1. The physical thickness of the gate insulating film of each of transistors T2, T3, and T4 is, for example, 10 nm or more. Also, the gate-source voltage of each of transistors T2, T3, and T4 can be, for example, 10 V or more. On the other hand, the physical thickness of the gate insulating film of transistor T1 is, for example, less than 10 nm. Also, the gate-source voltage of transistor T1 is, for example, lower than 10 V.

[0059] The first terminal of logic circuit LC receives the block address BA from address register 12. The second terminal of logic circuit LC receives, for example, the power supply voltage VDD. Logic circuit LC is driven by the power supply voltage VDD. A signal based on the block address BA is output from the third terminal of logic circuit LC. If the block address BA input to logic circuit LC is the block address BA assigned to block BLK corresponding to logic circuit LC, a "H" level signal is output from the second terminal of logic circuit LC. If the block address BA input to logic circuit LC is not the block address BA assigned to block BLK corresponding to logic circuit LC, a "L" level signal is output from the second terminal of logic circuit LC.

[0060] The first terminal of the AND gate is connected to the third terminal of the LC logic circuit. For example, the power supply voltage VDD is applied to the second terminal of the AND gate. The AND gate is driven by the power supply voltage VDD. The third terminal of the AND gate outputs a signal based on the logical AND operation of the signals output from the third terminal of the LC logic circuit.

[0061] The first terminal of inverter INV1 is connected to the third terminal of the AND gate. For example, the power supply voltage VDD is applied to the second terminal of inverter INV1. Inverter INV1 is driven by the power supply voltage VDD. The third terminal of inverter INV1 is connected to node N1. The third terminal of inverter INV1 outputs the inverted signal of the signal output from the third terminal of the AND gate.

[0062] The first terminal of inverter INV2 is connected to node N1. For example, the power supply voltage VDD is applied to the second terminal of inverter INV2. Inverter INV2 is driven by the power supply voltage VDD. The third terminal of inverter INV2 outputs an inverted signal of the signal output from the third terminal of inverter INV1.

[0063] The first terminal of transistor T1 is connected to the third terminal of inverter INV2. The power supply voltage VDD is applied to the gate of transistor T1. The second terminal of transistor T1 is connected to transistor T2.

[0064] The first terminal of transistor T2 is connected to the second terminal of transistor T1. The power supply voltage VDD is applied to the gate of transistor T2. The second terminal of transistor T2 is connected to the transfer gate line BLKSEL.

[0065] The first end of transistor T3 is connected to the transfer gate line BLKSEL. The gate of transistor T3 is connected to node N1. The second end of transistor T3, along with the back gate of transistor T3, is connected to transistor T4.

[0066] The first terminal of transistor T4 is connected to the second terminal of transistor T3 and the back gate of transistor T3. The gate of transistor T4 is connected to the transfer gate line BLKSEL. The second terminal of transistor T4 is connected to node VRDEC. A high voltage is applied to node VRDEC, which is transferred to the transfer gate line BLKSEL via transistors T3 and T4, thereby enabling transfer transistors TW, TS, and TD to transfer the voltage supplied to their corresponding signal lines CG to the word line WL, the select gate line SGS, and the select gate line SGD, respectively.

[0067] With the above configuration, the block decoder BD outputs an "H" level signal to the transfer gate line BLKSEL when the corresponding block BLK is selected. The block decoder BD outputs an "L" level signal to the transfer gate line BLKSEL when the corresponding block BLK is not selected.

[0068] 1.1.5.3 Planar configuration of the low decoder module The planar structure of the row decoder module 15 of the semiconductor memory device 1 according to the embodiment will be described with reference to Figure 6. Figure 6 is a plan view showing an example of the planar structure of the row decoder module of the semiconductor memory device according to the embodiment. In the following description, the transfer transistors TW0 to TW7, TS, and TD0 to TD4 included in the row decoder RDi, and the block decoder BD will also be referred to as transfer transistors TW0_i to TW7_i, TS_i, and TD0_i to TD4_i, and block decoder BD_i, respectively. i is an integer between 0 and n, inclusive.

[0069] The low decoder module 15 is provided on the semiconductor substrate 20.

[0070] The semiconductor substrate 20 is provided with an N-type well region 40. The N-type well region 40 is a region containing N-type impurities. The N-type well region 40 is provided in a rectangular shape, for example.

[0071] A P-type well region 41 is provided in the N-type well region 40. The P-type well region 41 is a region containing P-type impurities. The P-type well region 41 is provided in, for example, a rectangular region.

[0072] The pair of raw decoders RD(2j) and RD(2j+1) is arranged, for example, in a rectangular region. j is an integer between 0 and (n-1) / 2 (inclusive).

[0073] The pairs of low decoders RD0 and RD1, RD2 and RD3, RD4 and RD5, and so on are arranged in this order along the Y direction, for example.

[0074] In the pair of low decoders RD(2j) and RD(2j+1), the transfer transistors TS_(2j) and TS_(2j+1), TW0_(2j) and TW0_(2j+1), ..., TW7_(2j) and TW7_(2j+1), TD0_(2j) and TD0_(2j+1)..., and TD4_(2j) and TD4_(2j+1) are each provided, for example, in the P-type well region 41.

[0075] In a pair of row decoders RD(2j) and RD(2j+1), the block decoders BD_(2j) and BD_(2j+1) are provided, for example, outside the N-type well region 40.

[0076] The sets of multiple transfer transistors TW_(2j) and TW_(2j+1), TS_(2j) and TS_(2j+1), and TD_(2j) and TD_(2j+1) are arranged in a matrix configuration, for example, in the X and Y directions.

[0077] 1.1.5.4 Transfer Transistor The configurations of the transfer transistors TW, TS, and TD included in the semiconductor memory device 1 according to the embodiment will be described.

[0078] The planar structures of the transfer transistors TW, TS, and TD will be explained using Figures 7, 8A, and 8B. Figure 7 is a planar view showing an example of the planar structure of the transfer transistors in the semiconductor memory device according to the embodiment; Figure 8A is a cross-sectional view AA cut by a virtual plane perpendicular to the X direction and parallel to the Z direction, passing through contacts 61 and 62 in Figure 7; and Figure 8B is a cross-sectional view BB cut by a virtual plane perpendicular to the X direction and parallel to the Z direction, passing through contacts 67 and 69 in Figure 7. In the example shown in Figure 7, the planar structure including the transfer transistors TW0_0 and TW0_1 from the configuration shown in Figure 6 is mainly shown. The structures of the transfer transistor pairs TW_(2j) and TW_(2j+1), TS_(2j) and TS_(2j+1), and TD_(2j) and TD_(2j+1) have substantially equivalent structures. Below, the structures of the transfer transistors TW0_0 and TW0_1 will be mainly described.

[0079] An insulating layer 50 is formed on the P-type well region 41 (sometimes called the "element region") shown in Figure 6, for example, as an element isolation region formed in a grid pattern. In this embodiment, a portion of the P-type well region 41, which is formed over the entire surface of the low decoder module 15, is called the P-type well region 41B, and is shown as the region enclosed by the dashed line in the plan view shown in Figure 7. Each region surrounded by the grid-like insulating layer 50 formed on the P-type well region 41B corresponds to an active region AA. Multiple transfer transistors TW, TS, TD, etc., may be formed in each active region AA.

[0080] As shown in Figure 7, the transfer transistors TW0_0 and TW0_1 are arranged in this order along the Y direction. In the following description, the end of the transfer transistors TW0_0 and TW0_1 on which transfer transistor TW0_0 is located may be referred to as one end, and the end of the transfer transistors TW0_0 and TW0_1 on which transfer transistor TW0_1 is located may be referred to as the other end.

[0081] As shown in Figure 7, N-impurity diffusion regions 42, 43, and 44 are arranged in the Y direction (an example of the "first direction"), separated from each other in this order. N-impurity diffusion regions 42, 43, and 44 are N-type impurity diffusion regions in which dopants such as phosphorus (P) or arsenic (As) are diffused.

[0082] Electrode 201 is provided within N-impurity diffusion region 42, electrode 202 is provided within N-impurity diffusion region 43, and electrode 203 is provided within N-impurity diffusion region 44. The regions where electrodes 201, 202, and 203 are provided are the regions enclosed by dashed lines in Figure 7.

[0083] Electrode 201 functions as the first end of transfer transistor TW0_0. Electrode 203 functions as the first end of transfer transistor TW0_1. Electrode 202 functions as the second end of transfer transistor TW0_0 and the second end of transfer transistor TW0_1. Thus, transfer transistors TW0_0 and TW0_1 share electrode 202.

[0084] Electrode 201 corresponds to the region connected to the lower end of contact 61 and is the source region or drain region (an example of the "first region") of the transfer transistor TW0_0. Electrode 201 includes a region with a higher impurity concentration than the N-impurity diffusion region 42 (and is therefore sometimes called the "N+ impurity diffusion region 201"). In other words, the N-impurity diffusion region 42 (an example of the "first high-resistance diffusion layer") surrounds electrode 201, which is the source region or drain region, and is a high-resistance diffusion layer with a lower concentration than the N+ impurity diffusion region that forms electrode 201, resulting in relatively higher resistance. In this embodiment, electrode 201 may include a conductive layer 221 containing silicide connected to the lower end of contact 61 and the N+ impurity diffusion region 211 (Figure 8A). However, it is not limited to this, and for example, electrode 201 may not include silicide.

[0085] Electrode 202 corresponds to the region connected to the lower end of contact 62 and is the drain region or source region (an example of the "second region") of transfer transistors TW0_0 and TW0_1. Electrode 202 includes a region with a higher impurity concentration than the N-impurity diffusion region 43 (and is therefore sometimes called the "N+ impurity diffusion region 202"). In other words, the N-impurity diffusion region 43 (an example of the "second high-resistance diffusion layer") surrounds electrode 202, which is the source region or drain region, and is a high-resistance diffusion layer with a lower concentration than the N+ impurity diffusion region that forms electrode 202, resulting in relatively higher resistance. In this embodiment, electrode 202 may include a conductive layer 222 containing silicide connected to the lower end of contact 62 and the N+ impurity diffusion region 212 (Figure 8A). However, it is not limited to this, and for example, electrode 202 may not include silicide.

[0086] Electrode 203 corresponds to the region connected to the lower end of contact 63 and is the source region or drain region (an example of the "first region") of the transfer transistor TW0_1. Electrode 203 includes a region with a higher impurity concentration than the N-impurity diffusion region 44 (and is therefore sometimes called the "N+ impurity diffusion region 203"). In other words, the N-impurity diffusion region 44 (an example of the "second high-resistance diffusion layer") surrounds electrode 203, which is the source region or drain region, and is a high-resistance diffusion layer with a lower concentration than the N+ impurity diffusion region that forms electrode 203, resulting in relatively higher resistance. In this embodiment, electrode 203 may include a conductive layer 223 containing silicide connected to the lower end of contact 63 and the N+ impurity diffusion region 213 (Figure 8A). However, it is not limited to this, and for example, electrode 203 may not include silicide.

[0087] As shown in Figure 8A, a cross-sectional view of AA in Figure 7, a contact 61 (an example of a "first contact") is formed on electrode 201, which is connected to a conductive layer 66A (an example of a "first wiring layer") at its lower end, extends upward from electrode 201, and extends in the X direction at its upper end. The conductive layer 66A is connected to the word line WL0 of block BLK0, which is connected to the control gate of the memory cell transistor MT0 (an example of a "first memory cell") of block BLK0.

[0088] Furthermore, a contact 62 (an example of a "second contact") is formed on the electrode 202, which connects to the electrode 202 at its lower end, extends upward from the electrode 202, and connects to a conductive layer 66C that extends in the X direction at its upper end. The conductive layer 66C is connected to the signal line CG0.

[0089] Furthermore, a contact 63 (an example of a "first contact") is formed on the electrode 203, which connects to a conductive layer 66E (an example of a "first wiring layer") at its lower end, extends upward from the electrode 203, and extends in the X direction at its upper end. The conductive layer 66E connects to the word line WL0 of block BLK1, which is connected to the control gate of the memory cell transistor MT0 (an example of a "first memory cell") of block BLK1.

[0090] Note that while Figure 7 shows an example where each electrode 201, electrode 202, and electrode 203 has two contacts, this is not the only option. The number of contacts on each electrode 201, electrode 202, and electrode 203 may be one, three, or more.

[0091] As shown in Figure 8A, in the Z direction, above the semiconductor substrate 20, that is, above electrodes 201, 202, and 203 which include the N+ impurity diffusion region formed on the semiconductor substrate 20, and below the conductive layer 66A (and the upper end of the contact 61 connected thereto), conductive layer 66C (and the upper end of the contact 62 connected thereto), and conductive layer 66E (and the upper end of the contact 63 connected thereto), seven conductors, electrodes 101, 105, 103, 107, 104, 106, and 102, are formed. Electrodes 101, 105, 103, 107, 104, 106, and 102 are arranged in this order, for example, along the Y direction.

[0092] Furthermore, in the Z direction, at least a portion of each of electrodes 101, 105, 103, 107, 104, 106, and 102 includes portions that are formed at the same height as each other. Therefore, the conductive layers 66A to 66E are formed above each of these electrodes. In this embodiment, in order to achieve this configuration, each electrode is formed on an insulating film 51 having the same thickness and composition by being deposited using the same process, and the electrodes themselves also have the same thickness and composition by being formed using the same process. Furthermore, in this embodiment, sidewalls having the same composition are formed on the side walls constituting the outer and inner surfaces of each electrode. However, the sidewalls of each electrode do not necessarily have to be formed. The configuration of each electrode will be described below.

[0093] Electrode 101 (an example of the "first conductor") is a conductor formed at the same height as electrode 105, which is the gate electrode, in the Z direction, and at least a portion of it is provided between contact 61 and electrode 105 in the Y direction. Electrode 101 is formed on an insulating film 51. The upper surface of electrode 101 is connected to the lower end of contact 67 (an example of a "third contact"). The upper ends of contact 67 and contact 61 are each connected to the conductive layer 66A. Therefore, electrode 101 is electrically connected to contact 61 via contact 67 and the conductive layer 66A, and is configured to be at approximately the same potential as contact 61 and electrode 201. On the other hand, electrode 101 is insulated from electrode 105, and is electrically connected to contact 62 when the transfer transistor TW0_0 is on, and insulated when it is off.

[0094] With this configuration, for example, when a high voltage is applied to a conductive layer such as the conductive layer 66B, the electrode 101, which is located above the semiconductor substrate 20 and below the conductive layer such as the conductive layer 66B, functions as a shield, thereby suppressing potential fluctuations in the diffusion layer including the electrode 201 within the semiconductor substrate 20. The electrode 101 may include a conductive layer 111 containing polysilicon or the like, and a conductive layer 121 formed on the upper surface of the conductive layer 111, which may include, for example, a silicide containing nickel and silicon (NiSi), a silicide containing nickel, platinum, and silicon (NiPtSi), and a silicide containing cobalt and silicon (CoSi).

[0095] In this embodiment, the electrode 101 faces the N-impurity diffusion region 42 in the Z direction via the insulating film 51, as shown in Figure 8A, for example. In other words, the insulating film 51 is provided between the electrode 101 and the N-impurity diffusion region 42, which is a high-resistance diffusion layer.

[0096] With this configuration, when voltages are applied to electrode 201 and gate electrode 105 to turn on the transfer transistor TW0_0, a voltage is also applied to electrode 101. This makes it possible to apply an electric field from electrode 101 to the N-impurity diffusion region 42 facing the Z direction via the insulating film 51. As a result, it is possible to reduce the ON resistance of the transfer transistor TW0_0.

[0097] As shown in Figure 7, the electrode 101 in this embodiment further has an opening that surrounds the contact 61. In other words, the contact 61 extends in the Z direction so as to penetrate the opening formed in the electrode 101 and is formed to connect to the electrode 201 at its lower end. With this configuration, the electrode 101 is formed so as to surround the contact 61 connected to the electrode 201, making it possible to further suppress potential fluctuations in the diffusion layer within the semiconductor substrate 20 containing the electrode 201 caused by the conductive layer 66B, etc. Furthermore, sidewalls 521 are provided on each side wall constituting the outer circumferential surface of the electrode 101, and sidewalls 522 are provided on the side walls constituting the inner circumferential surface.

[0098] Electrode 105 (an example of a "gate electrode") is the gate electrode of the transfer transistor TW0_0. Electrode 105 is located between contact 61, which is connected to electrode 201 (which is either the source or drain region in the Y direction), and contact 62, which is connected to electrode 202 (which is either the drain or source region). Electrode 105 is formed on an insulating film 51 (sometimes referred to as the "gate insulating film 51"). The upper surface of electrode 105 is connected to the lower end of contact 64. The upper end of contact 64 is connected to a conductive layer 66B which forms part of the transfer gate line BLKSEL for supplying the gate signal to transfer transistor TW0_0.

[0099] The electrode 105 may comprise a conductive layer 115 containing polysilicon or the like, and a conductive layer 125 formed on the upper surface of the conductive layer 115, which may contain, for example, a silicide containing nickel and silicon (NiSi), a silicide containing nickel, platinum, and silicon (NiPtSi), or a silicide containing cobalt and silicon (CoSi). Furthermore, each side wall constituting the outer circumferential surface of the electrode 105 may be provided with a sidewall 541 (an example of a "gate electrode sidewall").

[0100] As shown in Figure 7, a narrow slit extending in the X direction (perpendicular to the channel direction of the transfer transistor TW0_0) is formed between electrode 105 and electrode 101. Therefore, except for the opening through which contact 61 passes and the slit, most of the surface area of ​​the semiconductor substrate 20 located below the conductive layer 66A and conductive layer 66B is covered by electrodes 101 and 105. With this configuration, for example, when a high voltage is applied to a conductive layer such as the conductive layer 66A, at least one of the electrodes 101 and 105, which are located above the semiconductor substrate 20 and below the conductive layer such as the conductive layer 66A, functions as a shield, thereby making it possible to suppress potential fluctuations in the diffusion layer including the electrode 201 within the semiconductor substrate 20.

[0101] As shown in Figure 8A, a portion of the sidewall 521 formed on the side wall of electrode 101 and a portion of the sidewall 541 formed on the side wall of electrode 105 are in contact in at least the lower region of the slit. As a result, at least a portion of the slit is closed. With this configuration, it is possible to close off many areas within the slit and expose areas within the opening, such as the electrode 101. Therefore, by using a self-alignment process, it is possible to selectively provide a conductive layer 221 containing silicide in these areas within the opening.

[0102] The electrode 103 shown in Figure 7 (an example of the "second conductor") is formed at the same height as the electrode 105, which is the gate electrode, in the Z direction, and in the Y direction, at least a portion of it is formed between the electrode 105, which is the gate electrode, and the contact 62, which is the second contact, and is a conductor that is insulated from all of the electrodes 105, contact 61, and contact 62.

[0103] In this embodiment, electrode 103 is a floating electrode (sometimes called a "floating electrode") and is surrounded by an insulator. In this embodiment, since electrode 107 is provided with an opening that surrounds contact 62, electrode 103 can also be said to be provided between electrode 105, which is the gate electrode, and electrode 107.

[0104] As described later, the inventors of this application have found that by providing an electrode 103, which is a conductor insulated from electrode 105, contact 61, and contact 62, between electrode 105, which is the gate electrode, and contact 62, which is the second contact, it is possible to increase the breakdown voltage when a large potential difference occurs between electrode 105 and electrode 202 (and contact 62 connected thereto), compared to the case in which such an electrode 103 is not present.

[0105] However, electrode 103 does not necessarily have to be a floating electrode as long as it is insulated from electrode 105, contact 61, and contact 62; for example, it may be configured to have a constant potential. To realize such a configuration, electrode 103 may be connected to a conductive layer for applying a constant potential (an example of a "constant potential wiring layer").

[0106] This configuration also makes it possible to increase the voltage withstand capability even when a large potential difference occurs between electrode 105 and electrode 202 (and the contact 62 connected thereto).

[0107] The potential applied to electrode 103 may be higher than the potential of one electrode and lower than the potential of the other when a large potential difference occurs between them. For example, when 0V is applied to electrode 105 and a voltage of 20V or more is applied to electrode 202, the potential applied to electrode 103 may be, for example, 5 to 15V.

[0108] Electrode 103, like electrode 105, may comprise a conductive layer 113 containing polysilicon or the like, and a conductive layer 123 containing silicide formed on the upper surface of conductive layer 113. Sidewalls 542 (an example of a "second sidewall") may be provided on each side wall constituting the outer circumferential surface. As shown in Figure 7, a narrow slit extending in the X direction (perpendicular to the channel direction of the transfer transistor TW0_0) is formed between electrode 105 and electrode 103. Also, as shown in Figure 8A, a portion of the sidewall 542 formed on the side wall of electrode 103 and a portion of the sidewall 541 formed on the side wall of electrode 105 are in contact in at least the lower region of the slit. As a result, at least a portion of the slit is closed.

[0109] With this configuration, it is possible to close off many areas within the slit and expose areas within the opening, such as the electrode 101. Therefore, by using a self-alignment process, it is possible to selectively provide a conductive layer 221 containing silicide in these areas within the opening.

[0110] Electrode 107 (an example of the "third conductor") is formed at the same height as electrodes 105 and 106, which are gate electrodes, in the Z direction, and is a conductor provided between electrodes 105 and 106, which are the two gate electrodes, in the Y direction. Therefore, electrode 103 is formed between electrode 107 and electrode 105. Electrode 107 is formed on the insulating film 51.

[0111] The upper surface of electrode 107 is connected to the lower end of contact 69 (an example of a "fourth contact"). The upper ends of contact 69 and contact 62 are each connected to the conductive layer 66C. Therefore, electrode 107 is electrically connected to contact 62 via contact 69 and the conductive layer 66C, and is configured to be at approximately the same potential as contact 62 and electrode 202. On the other hand, electrode 107 is insulated from electrode 105, and is electrically connected to contact 63 when transfer transistor TW0_1 is ON, and insulated when it is OFF. With this configuration, for example, when a high voltage is applied to a conductive layer such as the conductive layer 66B, the electrode 107, which is located above the semiconductor substrate 20 and below the conductive layer such as the conductive layer 66B, functions as a shield, thereby suppressing potential fluctuations in the diffusion layer including the electrode 202 within the semiconductor substrate 20. The electrode 107 may comprise a conductive layer 117 containing polysilicon or the like, and a conductive layer 127 formed on the upper surface of the conductive layer 117, which may contain, for example, a silicide containing nickel and silicon (NiSi), a silicide containing nickel, platinum, and silicon (NiPtSi), or a silicide containing cobalt and silicon (CoSi).

[0112] In this embodiment, the electrode 107 faces the N-impurity diffusion region 43 (an example of a "second high-resistance diffusion layer") in the Z direction via the insulating film 51, as shown in Figure 8A, for example. In other words, the insulating film 51 is provided between the electrode 107 and the N-impurity diffusion region 43, which is a high-resistance diffusion layer.

[0113] With this configuration, when voltages are applied to electrode 202 and gate electrode 105 to turn on the transfer transistor TW0_0, a voltage is also applied to electrode 107. This makes it possible to apply an electric field from electrode 107 to the N-impurity diffusion region 43 facing the Z direction via the insulating film 51. As a result, it is possible to reduce the ON resistance of the transfer transistor TW0_0.

[0114] As shown in Figure 7, the electrode 107 in this embodiment further has an opening that surrounds the contact 62. In other words, the contact 62 extends in the Z direction so as to penetrate the opening formed in the electrode 107 and is formed to connect to the electrode 202 at its lower end. With this configuration, the electrode 107 is formed so as to surround the contact 62 connected to the electrode 202, making it possible to further suppress potential fluctuations in the diffusion layer within the semiconductor substrate 20 containing the electrode 202 caused by the conductive layer 66B, etc. Furthermore, each side wall constituting the outer circumferential surface of the electrode 107 is provided with a side wall 543 (an example of a "third side wall"), and a side wall 544 is provided on the side wall constituting the inner circumferential surface facing the contact 62.

[0115] As shown in Figure 7, a narrow slit extending in the X direction (perpendicular to the channel direction of the transfer transistor TW0_0) is formed between electrode 103 and electrode 107. Also, as shown in Figure 8A, a portion of the sidewall 542 formed on the side wall of electrode 103 and a portion of the sidewall 543 formed on the side wall of electrode 107 are in contact, at least in the lower region within the slit. As a result, at least a portion of the slit is closed. With this configuration, it is possible to close off many areas within the slit and expose areas within the opening, such as the electrode 101. Therefore, by using a self-alignment process, it is possible to selectively provide a conductive layer 221 containing silicide in these areas within the opening.

[0116] As shown in Figure 7 and other figures, in this embodiment, transfer transistors TW0_0 and TW0_1 are formed symmetrically with respect to a conductive layer 66C extending in the X direction. Therefore, the explanation of the configuration of transfer transistor TW0_1 will be simplified.

[0117] Electrode 104 (an example of a "second conductor") has the same configuration as electrode 103, is formed at the same height as electrode 106, which is the gate electrode, in the Z direction, and in the Y direction, at least a portion of it is formed between electrode 106, which is the gate electrode, and contact 62, which is the second contact, and is a conductor that is insulated from electrode 106, contact 63, and contact 62. Similar to electrode 103, electrode 104 may be configured as a floating electrode ("floating electrode") or may be configured to have a constant potential by being connected to a conductive layer for applying a constant potential (an example of a "constant potential wiring layer"). The other configurations, including the sidewall 545 formed on electrode 104, and the technical effects associated with providing electrode 104 are the same as those of electrode 103, as will be understood by those skilled in the art, and therefore will not be described.

[0118] Electrode 106 (an example of a "gate electrode") is the gate electrode of the transfer transistor TW0_1, having a similar configuration to electrode 105. Electrode 106 is provided between contact 63, which is connected to electrode 203, which is the source or drain region in the Y direction, and contact 62, which is connected to electrode 202, which is the drain or source region. Electrode 106 is also formed on an insulating film 51 (sometimes called a "gate insulating film 51"). The upper surface of electrode 106 is connected to the lower end of contact 65, and the upper end of contact 65 is connected to a conductive layer 66D, which forms part of the transfer gate line BLKSEL for supplying the gate signal of the transfer transistor TW0_1. Electrode 106 may also include a conductive layer 116 and a conductive layer 126, and sidewalls 546 (an example of a "gate electrode sidewall") may be provided on each side wall constituting the outer circumferential surface of electrode 106.

[0119] The electrode 102 (an example of the "first conductor") shown in Figure 7 has the same configuration as electrode 101, is formed at the same height as electrode 106, which is the gate electrode, in the Z direction, and is a conductor in which at least a portion is provided between contact 63 and electrode 106 in the Y direction. Electrode 102 is formed on the insulating film 51, the upper surface of electrode 102 is connected to the lower end of contact 68 (an example of the "third contact"), and the upper ends of contact 68 and contact 63 are connected to the conductive layer 66E, respectively. Therefore, electrode 102 is configured to be at approximately the same potential as contact 63 and electrode 203. On the other hand, electrode 102 is insulated from electrode 106, and is electrically connected to contact 62 when the transfer transistor TW0_1 is ON, and insulated when it is OFF. The other configurations of electrode 102 and the technical effects associated with providing electrode 102 are the same as those of electrode 101 and will be understood by those skilled in the art, so a detailed explanation is omitted.

[0120] Similar to the transfer transistor TW0_0, a narrow slit extending in the X direction (perpendicular to the channel direction of the transfer transistor TW0_1) is formed between each electrode constituting the transfer transistor TW0_1. A portion of the sidewall formed on the side wall of each electrode is in contact with a portion of the sidewall formed on the side wall of the opposing electrode in at least the lower region within the slit. As a result, at least a portion of the slit is closed, making it possible to selectively provide silicide or the like in the region within the opening of electrode 106.

[0121] Furthermore, a shielding conductive layer, for example containing polysilicon, may be provided on the insulating layer 50, for example, surrounding the active region AA. The shielding conductive layer may be provided in a grid pattern similar to the insulating layer 50, and sidewalls may be provided on the inner and outer periphery sides. In addition, the space above the semiconductor substrate 20 is filled with an insulator (not shown) composed of an oxide insulating film or the like to insulate conductive layers such as the conductive layer 66A from each other and from each electrode.

[0122] With the above configuration, in the transfer transistor TW0_0, the electrode 101, which is the first conductor, is provided at the same height as the gate electrode 105, above the semiconductor substrate 20 and below the conductive layer 66A, and the electrode 101 is electrically connected to the contact 61, which is the first contact connected to the source region or drain region. As a result, the electrode 101 acts as a shield, making it possible to suppress voltage fluctuations in the source region or drain region caused by conductive layers such as the conductive layer 66B above it.

[0123] In addition, since electrode 103, which is insulated from all of the gate electrode 105, contact 61, and contact 62, is provided above the semiconductor substrate 20, below the conductive layer 66A, and between the gate electrode 105 and contact 62, it is possible to increase the breakdown voltage against the potential difference between the electrodes. This point will be explained below.

[0124] Figure 9A is a schematic diagram showing the electric field lines at cutoff in a transfer transistor C according to a comparative example, and Figure 9B is a schematic diagram showing the electric field lines at cutoff in a transfer transistor TW0_0 according to this embodiment. For the purpose of simplifying the explanation, common or similar components are denoted by the same reference numerals and their descriptions are omitted. Furthermore, the fact that they are approximately the same potential is schematically shown by the wires connecting the contacts and electrodes, and the wiring is omitted, and other components are simplified as appropriate.

[0125] As shown in the figure, the transfer transistor C in the comparative example differs from the transfer transistor TW0_0 in that it does not have a configuration corresponding to electrode 103, and instead electrode 107 extends to a position opposite electrode 105.

[0126] When a predetermined transfer transistor is cut off during programming of NAND flash memory, a high voltage (e.g., 20-25V) is applied to the signal line CG, and a low voltage (e.g., 0-0.5V) is applied to the word line WL and the gate electrode 105. Therefore, a potential difference of 20V or more is generated between the contact 62 and electrode 202 connected to the signal line CG and the gate electrode 105. This raises concerns about the breakdown voltage between the two electrodes.

[0127] As shown in Figure 9A, the inventors of this application have found that in the comparative example transfer transistor C, equipotential lines are concentrated at the lower end of the slit formed between electrode 107 and electrode 105, creating a region where the electric field change is steep, which is a factor in breakdown voltage degradation.

[0128] On the other hand, as shown in Figure 9B, the transfer transistor TW0_0 according to this embodiment includes an electrode 103 between the gate electrode 105 and the contact 62 that is insulated from the gate electrode 105, contact 61, and contact 62, is floating, or has a constant potential (where "constant potential" includes a potential within a certain range; preferably an intermediate potential such as 5 to 15V) applied to it. With this configuration, both ends of electrode 103 in the Y direction are insulated from other adjacent electrodes, thus mitigating the concentration of equipotential lines and, consequently, increasing the breakdown voltage.

[0129] Furthermore, multiple configurations corresponding to electrode 103 may be provided. Also, a configuration corresponding to electrode 103 may be provided on the electrode 201 side. In addition, although this embodiment shows an example of application to transfer transistor TW0_0, it can be applied to other transfer transistors such as TS and TD. It can also be applied to other transistors requiring high voltage resistance. Moreover, the shape of electrodes such as electrode 103 can be varied in various ways. Furthermore, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. Other embodiments will be described below. Components common to or similar to these embodiments will be denoted by the same or similar reference numerals, and their descriptions will be simplified or omitted as appropriate, with the focus being on the differences.

[0130] [Second Embodiment] Figure 10 shows the transfer transistors TW0_0 and TW1_1 according to this embodiment. The transfer transistors of this embodiment differ from the transfer transistor according to the first embodiment in that they do not have an electrode 107 and the shape of the electrode 1032 corresponding to electrode 103 is different.

[0131] In this embodiment, the electrode 1032 (an example of a "second conductor") of the transfer transistors TW0_0 and TW1_1 is provided so as to surround the contact 62, which is the second contact. Here, the electrode 1032 is insulated from the first contacts, contact 61 and 62, and the electrode 105, which is the gate electrode. The electrode 1032 may be floating, or a certain range of potential (preferably an intermediate potential between the potentials that can be applied to both electrodes) may be applied to it.

[0132] With this configuration, the outer circumference of electrode 1032 and the inner circumference in the Y direction facing contact 62 are insulated from other adjacent electrodes, thereby mitigating the concentration of equipotential lines and thus increasing the breakdown voltage.

[0133] [Third Embodiment] Figure 11 shows the transfer transistors TW0_0 and TW1_1 according to this embodiment. The transfer transistors of this embodiment differ from the transfer transistor according to the first embodiment in that they are equipped with an electrode 108 (an example of a "fourth conductor") and the shape of the electrode 1012 (an example of a "first conductor") corresponding to electrode 101 is different.

[0134] The electrode 108 is at the same height as the gate electrode 105, and at least a portion of it is formed between the gate electrode 105 and the first contact, contact 61, and is insulated from the gate electrode 105, contact 61, and the second contact, contact 62. With this configuration, both ends of electrode 108 in the Y direction are insulated from other adjacent electrodes, thus mitigating the concentration of equipotential lines, and therefore making it possible to increase the breakdown voltage based on the potential difference between the second end and the gate electrode 105.

[0135] Alternatively, by forming the first conductor as electrode 1012, the contact 61 may be configured to be provided between electrode 1012 and electrode 108. Specifically, electrode 108 may be formed between gate electrode 105 and the first contact, contact 61, and electrode 1012 may be formed to surround contact 61 with electrode 108 and electrode 1012 which is insulated from electrode 108. With this configuration, it is possible to suppress the increase in dimensions in the Y direction compared to the case where the contact 61 is surrounded by the electrode 101.

[0136] Furthermore, electrode 107 may be formed in a shape similar to electrode 1012. With such a configuration, it is possible to suppress the increase in dimensions in the Y direction compared to the case where electrode 107 surrounds the contact 62.

[0137] [Fourth Embodiment] Figure 12 shows the transfer transistors TW0_0 and TW1_1 according to this embodiment. The transfer transistor of this embodiment differs from the transfer transistor according to the first embodiment in that the electrode 107 has two electrodes 107A (an example of the "first conductor") and 107B (an example of the "fifth conductor"), has an electrode 108 (an example of the "fourth conductor"), and the shape of the electrode 1012 (an example of the "first conductor") corresponding to electrode 101 is different.

[0138] Electrode 107 comprises two electrodes 107A and 107B. Both electrodes are positioned at a distance from the second contact, contact 62, in the X direction perpendicular to the channel direction of the transfer transistor TW0_0, and are positioned so as to sandwich contact 62. In other words, contact 62 is formed between electrode 107A and electrode 107B. At this time, a portion of electrode 103, which is the second conductor, is formed between electrode 105, which is the gate electrode, and electrode 107A, and the other portion of electrode 103 is formed between electrode 105 and electrode 107B.

[0139] Furthermore, electrode 107A, which constitutes electrode 107, is connected to contact 69A, and electrode 107B is connected to contact 69B. Contacts 69A and 69B are electrically connected to contact 62 via the conductive layer 66C. As a result, electrodes 107A and 107B are electrically connected to contact 62 so that they are at approximately the same potential as contact 62.

[0140] With this configuration, both ends of electrode 103 in the Y direction are insulated from other adjacent electrodes, thus mitigating the concentration of equipotential lines, and therefore making it possible to increase the breakdown voltage based on the potential difference between the second end and the gate electrode 105. In addition, electrodes 107A and 107B each face the N-impurity diffusion region 43 via the insulating film 51. Therefore, when the transfer transistor TW0_0 according to this embodiment is turned ON, a voltage is also applied to electrode 107, making it possible to apply an electric field from electrodes 107A and 107B to the N-impurity diffusion region 43 facing each other in the Z direction via the insulating film 51. This makes it possible to reduce the ON resistance of the transfer transistor TW0_0. The effects related to the configuration of electrodes 108 and 1012 have been described in the third embodiment, etc., so their explanation is omitted here.

[0141] [Fifth Embodiment] Figure 13 shows the transfer transistors TW0_0 and TW1_1 according to this embodiment. The transfer transistor of this embodiment differs from the transfer transistor of the first embodiment in that the electrode 107 has two electrodes 107A (an example of the "first conductor") and 107B (an example of the "fifth conductor"). With this configuration, both ends of electrode 103 in the Y direction are insulated from other adjacent electrodes, thus mitigating the concentration of equipotential lines, and therefore making it possible to increase the breakdown voltage based on the potential difference between the second end and the gate electrode 105. Furthermore, when the transfer transistor TW0_0 is turned ON, a voltage is also applied to electrode 107, so an electric field is applied from electrodes 107A and 107B to the N-impurity diffusion region 43 facing in the Z direction via the insulating film 51, making it possible to reduce the ON resistance.

[0142] [Sixth Embodiment] Figure 14 shows the transfer transistors TW0_0 and TW1_1 according to this embodiment. The transfer transistors of this embodiment differ from the transfer transistor according to the first embodiment in that the electrode 1032 (an example of the "second conductor") corresponding to electrode 103 is formed in a ring shape, and the shape of the electrode 1072 (an example of the "third conductor") corresponding to electrode 107 is different from that of electrode 107. In this embodiment, electrode 1072 is formed to surround contact 62, and electrode 1032 is formed to further surround electrode 1072.

[0143] With this configuration, the outer circumference of electrode 1032 in the Y direction and the inner circumference in the Y direction facing electrode 1072 are insulated from other adjacent electrodes, thereby mitigating the concentration of equipotential lines and thus increasing the breakdown voltage. Alternatively, sidewalls may be formed on electrodes 1072 and 1032, so that the sidewalls of electrode 1072 and 1032 come into contact in part within the slit formed between electrode 1072 and electrode 1032, thereby partially closing the slit.

[0144] With this configuration, it is possible to close off many areas within the slit and expose areas within the opening, such as the electrode 101. Therefore, by using a self-alignment process, it is possible to selectively provide a conductive layer 221 containing silicide in these areas within the opening. The embodiments have been described above with reference to specific examples. According to the transistors of each embodiment, it is possible to suppress voltage fluctuations in the source region or drain region caused by the upper conductive layer. Furthermore, it is possible to increase the breakdown voltage.

[0145] [Seventh Embodiment] Figure 15 shows an example in which 12 transfer transistors are arranged to illustrate a modified example of the gate electrode 105 and gate electrode 106 according to the first embodiment. Each transfer transistor in this embodiment has the same configuration as the transfer transistor according to the second embodiment (Figure 10), but is not limited to this and may be applied to transfer transistors according to other embodiments. In this embodiment, common or similar components among multiple transfer transistors are denoted by the same or similar reference numerals, and their descriptions are appropriately simplified or omitted.

[0146] The figure shows a total of six active regions AA of the semiconductor memory device 1, three in the X direction and two in the Y direction. Each active region AA is provided with an electrode 201 which will be a source region or drain region (an example of a "first region"), an electrode 202 which will be a drain region or source region (an example of a "second region"), an electrode 203 which will be a drain region or source region (an example of a "first region"), a contact 61 connected to electrode 201 and a contact 63 connected to electrode 203, a contact 62 connected to electrode 202, a gate electrode 105 and a gate electrode 106, electrodes 101 and 102, and an electrode 1032.

[0147] Furthermore, the semiconductor memory device 1 includes element isolation regions having an insulator such as STI to electrically isolate each active region AA from one another. In this embodiment, the semiconductor memory device 1 includes two connecting conductors 105C that connect the gate electrodes 105 of three adjacent active regions AA in the X direction, and two connecting conductors 106C that connect the gate electrodes. The connecting conductors 105C and 106C are each formed above the element isolation region.

[0148] With this configuration, for example, connecting conductors 105C and 106C are provided between the electrode 202 formed in one active region AA and the conductive layers 66A and 66E provided in other active regions AA adjacent to each other in the X direction. Therefore, when a high voltage is applied to a conductive layer such as the conductive layer 66A provided in another adjacent active region AA, for example, it becomes possible to suppress potential fluctuations in the diffusion layer including the electrode 202 formed in one active region AA. The lengths of the connecting conductors 105C and 106C in the Y direction may be smaller than the length of electrode 105 (or electrode 106) in the Y direction. Alternatively, a configuration may be adopted in which the gate electrodes 105 of the three adjacent active regions AA in the X direction are not connected to each other, without providing the connecting conductors 105C and 106C.

[0149] [Manufacturing method] Next, a method for manufacturing the transfer transistor of the semiconductor memory device 1 according to the first embodiment will be described. Figures 16A to 16L are schematic diagrams of the AA cross-section in Figure 7, illustrating the manufacturing process of the transfer transistor. Figure 16A shows a P-type semiconductor substrate 20. Figure 16B shows how N-type wells 40 are formed in the semiconductor substrate 20 by injecting N-type and P-type impurities (dopants), and how a P-type well region 41 is formed above the N-type well region 40. Figure 16C shows how a photoresist PH coated on a semiconductor substrate 20, in which an N-type well region 40 and a P-type well region 41 are formed above the N-type well region 40, is patterned, and N-type impurities are selectively implanted to form N-impurity diffusion regions 42 and N-impurity diffusion regions 43 in the selected regions.

[0150] Figure 16D shows the state after the photoresist PH has been removed, with an insulating film 51 and a polysilicon film POLY deposited on the surface of the semiconductor substrate 20. Figure 16E shows the semiconductor substrate 20, on which an insulating film 51 and a polysilicon film POLY are deposited on the insulating film 51, further depositing a silicon nitride film SIN as a mask, then applying a resist RES, and subsequently performing processing for STI formation. Figure 16F shows a process in which, for example, an oxide insulating film is deposited to form an insulating layer 50, followed by CMP polishing using a silicon nitride film SIN as a mask, then etching back to remove the silicon nitride film SIN, and finally etching the polysilicon film POLY with RIE until the upper surface of the insulating layer 50 and the upper surface of the polysilicon film POLY are at approximately the same height.

[0151] Figure 16G shows the process after which a polysilicon film (POLY) is deposited, a resist (RES) is applied, and then the surface is patterned to form slits and openings. Figure 16H shows how multiple electrode configurations are formed by etching a polysilicon film (POLY) using RIE. Figure 16I shows how, after removing the resist RES, an oxide insulating film is deposited on the inner and outer sides of each electrode (electrodes 101, 105, 103, 107, 104, and 106, etc.) to create sidewalls (sidewalls 522, 521, 541, 542, 544, 545, and 546, etc.), and how the sidewalls of adjacent electrodes are brought into contact at their lower ends.

[0152] Figure 16J shows how N+ impurities are injected into the openings of electrodes 101 and 107 to form self-aligned N+ impurity diffusion regions 211 and 212. Figure 16K shows how a metal film is deposited in the openings of electrodes 101 and 107, for example by CVD, and then heat-treated to form self-aligned conductive layers 221 and 222 containing silicide. As mentioned above, the silicide may be, for example, a nickel-silicon silicide (NiSi), a nickel-platinum-silicon silicide (NiPtSi), or a cobalt-silicon silicide (CoSi). In this case, since the slit is closed by the sidewall, conductive layers 221 and 222 containing silicide are selectively formed in the opening. Figure 16L shows the formation of contacts 61, 62, and 64 after the deposition of an interlayer insulating film (not shown).

[0153] Through the process described above, it becomes possible to manufacture the transfer transistors shown in Figures 7, 8A, and 8B. This disclosure is not limited to these specific examples. Modifications made to these examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned examples are not limited to those exemplified and can be modified as appropriate. The elements of each of the aforementioned examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of Symbols]

[0154] 1. Semiconductor memory 2 Memory Controller 3. Memory System 10 memory cell arrays 11 Command Registers 12 Address Registers 13 Sequencer 14 Driver Modules 15 Low Decoder Module 16 Sense Amp Module 20 Semiconductor substrates 21-25 Conductive layer 26 Semiconductor Division 27 Conductive layer 30-34 Insulating layer 35 Core members 36 Semiconductor film 37 Tunnel insulating film 38 Charge storage film 39 Block insulating film 40 N-type well region 41 P-type well area 42 N-impurity diffusion region 43 Impurity diffusion region 44 Impurity diffusion region 50 Insulating layer 51 Insulating Film 51 Gate insulating film 61-65 Contact 66A~66E Conductor layer 67-69 Contact 101~108 electrode 111, 113, 115, 116, 117 Conductive layer 121, 123, 125-127 Conductive layer 201 Electrode 202 Electrode 203 Electrode 221 Conductive layer 222 Conductive layer 400 Shielding conductive layer 521, 522, 541-546 Sidewall

Claims

1. A semiconductor substrate comprising a first region which is a source region or drain region, and a second region which is a source region or drain region and is spaced apart from the first region in a first direction, A first contact connected to the first region, A second contact connected to the second region, A first memory cell connected to the first contact, A gate electrode formed between the first contact and the second contact, A first conductor, which includes a portion that is the same height as the gate electrode and is electrically connected to the first contact, A second conductor, which includes a portion of the same height as the gate electrode, is formed at least in part between the gate electrode and the second contact, and is insulated from the gate electrode, the first contact, and the second contact; A semiconductor memory device equipped with the following features.

2. The semiconductor memory device according to claim 1, wherein the first conductor surrounds the first contact.

3. A first wiring layer connected to the first contact, The semiconductor memory device according to claim 2, further comprising a third contact connecting the first wiring layer and the first conductor.

4. The semiconductor substrate includes a first high-resistivity diffusion layer that surrounds the first region and has a higher resistance than the first region. The semiconductor memory device according to claim 3, further comprising an insulating film provided between the first conductor and the first high-resistance diffusion layer.

5. The present invention further comprises a third conductor surrounding the second contact, At least a portion of the second conductor is formed between the gate electrode and the third conductor. The semiconductor memory device according to claim 1.

6. The semiconductor memory device according to claim 5, further comprising a fourth contact connected to the third conductor for electrically connecting the second contact and the third conductor.

7. The semiconductor substrate includes a second high-resistivity diffusion layer that surrounds the second region and has a higher resistance than the second region. The semiconductor memory device according to claim 5, further comprising an insulating film provided between the third conductor and the second high-resistance diffusion layer.

8. A gate electrode sidewall formed on at least two side walls of the gate electrode, A second sidewall formed on at least two side walls of the second conductor, The third conductor further comprises a third sidewall formed on at least two side walls, A portion of the gate electrode sidewall and a portion of the second sidewall are in contact with each other. A portion of the second sidewall and a portion of the third sidewall are in contact. The semiconductor memory device according to claim 5.

9. A slit is formed between the gate electrode and the second conductor, and within this slit, a part of the gate electrode sidewall and a part of the second sidewall are in contact. A slit is formed between the second conductor and the third conductor, and within this slit, a portion of the second sidewall and a portion of the third sidewall are in contact. The semiconductor memory device according to claim 8.

10. The semiconductor memory device according to claim 1, wherein the second conductor is floating.

11. The semiconductor memory device according to claim 1, further comprising a constant potential wiring layer for applying a constant potential to the second conductor.

12. The first memory cell constitutes a memory cell of a NAND flash memory, The semiconductor memory device according to claim 1, further comprising a first wiring layer formed above the first conductor for connecting the word line of the first memory cell to the first contact.

13. The semiconductor memory device according to claim 1, wherein the second conductor surrounds the second contact.

14. The semiconductor memory device according to claim 1, further comprising a fourth conductor having the same height as the gate electrode, at least a portion of which is formed between the gate electrode and the first contact, and which is insulated from the gate electrode, the first contact, and the second contact.

15. The semiconductor memory device according to claim 14, wherein the first contact is formed between at least a portion of the first conductor and the fourth conductor.

16. The present invention further comprises a fifth conductor electrically connected to the second contact, The semiconductor memory device according to claim 1, wherein at least a portion of the second conductor is formed between the gate electrode and the fifth conductor.

17. The present invention further comprises a sixth conductor electrically connected to the second contact, The semiconductor memory device according to claim 16, wherein the second contact is formed between the fifth conductor and the sixth conductor.

18. The semiconductor memory device according to claim 5, wherein the second conductor surrounds the third conductor.

19. A plurality of active regions, each provided with the first region, the second region, the first contact, the second contact, the gate electrode, the first conductor, and the second conductor, An element isolation region that electrically separates one of the aforementioned active regions from the other aforementioned active region, The element isolation region is provided on the element isolation region that separates one of the active regions from another active region adjacent in a second direction intersecting the first direction, and further comprises the gate electrode of the one active region and a connecting conductor that connects the gate electrode of the other active region. The semiconductor memory device according to claim 1.

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