Memory device

Abstract

The present invention provides a storage device with reduced component length. [Solution] The memory device includes a first semiconductor 61_1, a first pillar CGP_1, a first conductor 67_1, a first transistor T, and a second conductor 67_2. The first semiconductor extends in the Z direction. The first pillar extends in the X direction intersecting the Z direction and is in contact with the first semiconductor. The first conductor is connected to the X-side end of the first pillar and extends in the Y direction intersecting the Z and X directions. The first transistor is provided in the -X direction from the first conductor and is connected to the first conductor. The second conductor is provided in the +X direction from the first conductor, extends in the Y direction, and is connected to the first transistor.

Description

Technical Field

[0001] Embodiments generally relate to a memory device.

Background Art

[0002] Memory devices including three-dimensionally arranged memory cells are known. In order to increase the integration degree of the memory device, the number of components of the memory device may increase or the dimensions (length) may become excessively large.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a memory device with a suppressed length of components.

Means for Solving the Problems

[0005] A memory device according to an embodiment includes a first semiconductor, a first pillar, a first conductor, a first transistor, and a second conductor. The first semiconductor extends in a first direction. The first pillar extends in a second direction intersecting the first direction and is in contact with the first semiconductor. The first conductor is connected to an end of the first pillar on the side in the second direction and extends in a third direction intersecting the first direction and the second direction. The first transistor is provided in the second direction from the first conductor and is connected to the first conductor. The second conductor is provided in the second direction from the first conductor, extends in the third direction, and is connected to the first transistor.

Brief Description of the Drawings

[0006] [Figure 1]Figure 1 shows an example of the components of the storage device according to the first embodiment and the connections between the components. [Figure 2] Figure 2 shows the components and connections of one block of the storage device according to the first embodiment. [Figure 3] Figure 3 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 4] Figure 4 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 5] Figure 5 shows an example of the cross-sectional structure of a part of the storage device of the first embodiment. [Figure 6] Figure 6 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 7] Figure 7 shows the structure of a cross-section of a part of the storage device of the first embodiment. [Figure 8] Figure 8 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 9] Figure 9 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 10] Figure 10 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 11] Figure 11 shows a layout of a portion of the storage device of the first embodiment along the xy plane. [Figure 12] Figure 12 shows an example of the structure of a cross-section of a part of the storage device of the first embodiment. [Figure 13] Figure 13 shows some of the components of the block and the connections between the components. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Multiple components having substantially the same function and configuration in one embodiment or a different embodiment may be denoted by additional numbers or letters at the end of their reference numerals to distinguish them from one another.

[0008] The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may differ from reality. Furthermore, there may be differences in dimensional relationships and ratios between drawings.

[0009] In this specification and in the claims, "connected" to another second element means that the first element is connected to the second element directly, or via an element that is always or selectively conductive.

[0010] The following embodiments are described using a three-dimensional Cartesian coordinate system. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, with upwards pointing in the Z direction. The direction opposite to the Z direction is referred to as the -Z direction, with downwards pointing in the -Z direction.

[0011] 1. First Embodiment 1.1.Configuration (Structure) Figure 1 shows an example of the components of a storage device according to the first embodiment and the connections of those components. Storage device 1 is a device that stores data using memory cells. Storage device 1 is controlled by an external memory controller. Storage device 1 operates based on commands CMD and address information ADD received from the memory controller, for example. Storage device 1 receives data DAT to be written and outputs the data stored in storage device 1. Storage device 1 is configured, for example, as a single semiconductor chip.

[0012] As shown in Figure 1, the memory device 1 includes components such as a memory cell array 10, a row decoder 11, a register 12, a sequencer 13, a driver 14, and a sense amplifier 15.

[0013] The memory cell array 10 is a set of memory cell transistors and a set of components connected to the memory cell transistors. The memory cell array 10 includes a plurality of memory blocks (blocks) BLK (BLK_0, BLK_2, …). Each block BLK includes a plurality of memory cell transistors MT (not shown). In the memory cell array 10, wirings such as word lines WL (not shown) and bit lines BL (not shown), and wirings connected to the memory cell transistors MT are also located.

[0014] The row decoder 11 is a circuit for selecting a block BLK. The row decoder 11 transfers the voltage supplied from the driver 14 to one selected block BLK based on the block address received from the register 12.

[0015] The register 12 is a circuit that holds the command CMD and the address information ADD received by the storage device 1. The command CMD instructs various operations including data read, data write, and data erase to the sequencer 13. The address information ADD specifies the target of access in the memory cell array 10.

[0016] The sequencer 13 is a circuit that controls the overall operation of the storage device 1. The sequencer 13 controls the row decoder 11, the driver 14, and the sense amplifier 15 based on the command CMD received from the register 12, and executes various operations including data read, data write, and data erase.

[0017] The driver 14 is a circuit that generates a plurality of voltages of different magnitudes and applies the generated voltages to some components. The driver 14 supplies, to the row decoder 11, one of the plurality of generated voltages selected based on the control by the sequencer 13 and the address information ADD.

[0018] The sense amplifier 15 is a circuit that outputs a signal based on the data stored in the memory cell array 10. The sense amplifier 15 senses the state of the memory cell transistor MT, generates read data based on the sensed state, and also transfers write data to the memory cell transistor MT.

[0019] Figure 2 shows the components and connections of one block BLK of the storage device in the first embodiment. Multiple block BLKs, for example, all block BLKs, include the components and connections shown in Figure 2.

[0020] A single block BLK contains multiple string units SU. Figure 2 shows an example of five string units SU_0 to SU_4.

[0021] As shown in Figure 2, each of the m bit lines BL_0 to BL_m-1 is connected in each block BLK to one NAND string NS from each of the string units SU_0 to SU_4, where m is a positive integer.

[0022] Each NAND string NS contains one selection gate transistor ST, n-1 memory cell transistors MT, and one selection gate transistor DT (DT0, DT1, DT2, DT3, or DT4), where n is a positive integer. The memory cell transistor MT includes a control gate electrode and a charge storage film isolated from the surroundings, and is an element that non-volatilely stores data based on the amount of charge in the charge storage film. The selection gate transistor ST, memory cell transistor MT, and selection gate transistor DT are connected in this order in series between the source line SL and one bit line BL.

[0023] Multiple NAND strings NS, each connected to a different bit line BL, constitute a single string unit SU. In each string unit SU, the control gate electrodes of memory cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of memory cell transistors MT sharing a word line WL within a single string unit SU is referred to as a cell unit CU.

[0024] The selection gate transistors DT0 to DT4 belong to string units SU_0 to SU_4, respectively. In Figure 2, the selection gate transistors DT2, DT3, and DT4 are not shown. The gate of each selection gate transistor DT0 in the multiple NAND strings NS of string unit SU_0 is connected to the selection gate line SGDL0. Similarly, the gates of each selection gate transistor DT1, DT2, DT3, and DT4 in the multiple NAND strings NS of string units SU_2, SU_2, SU_3, and SU_4 are connected to the selection gate lines SGDL1, SGDL2, SGDL3, and SGDL4.

[0025] The gate of the selection gate transistor ST is connected to the selection gate line SGSL.

[0026] Figure 3 shows a layout of a portion of the storage device of the first embodiment along the xy plane. Figure 3 shows the structure of a certain layer of the storage device 1. As shown in Figure 3, the storage device 1 includes a plurality of memory cell regions (or MC regions) MCRs, a plurality of CP regions, and a plurality of conductors 21.

[0027] The MC region (MCR) is a region within which memory cell transistors (MT) and related structures are provided. Multiple MC regions (MCRs) are arranged with spacing in the Y direction, forming a column. Multiple columns of MC regions (MCRs) are arranged with spacing in the X direction.

[0028] The conductor 21 connects some conductors in a plurality of MC regions MCRs to each other. Each conductor 21 includes one first portion 21P1 and a plurality of second portions 21P2. The first portion 21P1 extends in the Y direction. The first portion 21P1 aligns with one row of MC regions MCRs. The first portion 21P1 is adjacent to one of the two edges aligned in the X direction of one row of MC regions MCRs. Figure 3 shows an example where the first portion 21P1 is located on the left side of the row of MC regions MCRs.

[0029] The second parts 21P2 extend in the X direction and are spaced apart in the Y direction. Each second part 21P2 is located between two MC regions MCR aligned in the Y direction. Between two MC regions MCR aligned in the Y direction, there may be one second part 21P2, or two or more spaced second parts 21P2. Figure 3 shows an example where two second parts 21P2 are located. Each second part 21P2 is connected to the first part 21P1 at one of its two sides aligned in the X direction. Figure 3 shows an example where each second part 21P2 is connected to the first part 21P1 at its left end. In one example, the right end of the second part 21P2 coincides with or is located near the right end of the MC region MCR.

[0030] Examples of conductor 21 include tungsten (W) and titanium nitride (TiN).

[0031] The CP region CPRs extend in the X direction and are spaced apart in the Y direction. Each CP region CPR is located between two MC region MCRs aligned in the Y direction. In one example, each CP region CPR is located between two second parts 21P2 aligned in the Y direction. In one example, the right edge of a CP region CPR overlaps with or is located near the right edge of an MC region MCR.

[0032] Figure 4 shows a layout along the xy plane of a portion of the storage device of the first embodiment. Figure 4 shows the layout near the boundary between the MC region (MCR) and the CP region (CPR). Figure 4 shows one of several layers aligned in the Z direction.

[0033] As shown in Figure 4, each MC region (MCR) includes multiple semiconductors 22 and multiple electrode pillars CGP and SGP in a single layer. Each CP region (CPR) includes multiple contacts CP.

[0034] In one example, the semiconductor 22 is silicon (Si) containing impurities. The impurities include elements that give the semiconductor 22 n-type or p-type conductivity, and in one example include boron (B) or arsenic (As). The semiconductors 22 extend in the Y direction and are spaced apart in the X direction. On the Y-direction side, the semiconductors 22 are in contact with the second portion 21P2 of the conductor 21. One of the sets of semiconductors 22 aligned in the X direction, located at the end, faces the conductor 21.

[0035] Multiple sets of one conductor 21 and multiple semiconductors 22 shown in Figure 4 are provided in each of multiple layers. That is, the structure of one conductor 21 and multiple semiconductors 22 shown in Figure 4 is repeatedly provided in the Z direction.

[0036] The electrode pillars CGP are arranged along the xy-plane. In one example, several electrode pillars CGP form a row aligned in the Y direction. Two rows of electrode pillars CGP sandwich one semiconductor 22. The two rows of electrode pillars CGP sandwiching one semiconductor 22 are located at different positions (coordinates) on the y-axis. Therefore, each electrode pillar CGP in one row is not aligned in the X direction with any electrode pillar CGP in the other row. In one example, two adjacent rows of electrode pillars CGP are symmetrical with respect to the y-axis. With this arrangement, one electrode pillar CGP is aligned diagonally with another electrode pillar CGP. The electrode pillars CGP may also be arranged in a matrix.

[0037] Each electrode pillar CGP overlaps with one semiconductor 22 on either the -X direction side or the +X direction side, and is in contact with one semiconductor 22 on its side.

[0038] Each electrode pillar CGP, as omitted in Figure 4 and described later, includes an insulator, a conductor, and a semiconductor. Each electrode pillar CGP has a columnar shape and extends in the Z direction. A portion of each electrode pillar CGP and the portion of the semiconductor 22 in contact with this electrode pillar CGP function as a single memory cell transistor MT.

[0039] The electrode pillars SGP are arranged along the xy-plane. Each electrode pillar SGP lies on the extension of one column of electrode pillars SGP. That is, multiple electrode pillars SGP and one electrode pillar SGP form one column in the Y direction. The two columns of electrode pillars CGP and SGP sandwich one semiconductor 22. The two electrode pillars SGP that sandwich one semiconductor 22 are located at different positions (coordinates) on the y axis. Therefore, the two (one pair) of electrode pillars SGP that sandwich one semiconductor 22 are not aligned in the X direction. In one example, two adjacent pairs of electrode pillars SGP have a line-symmetric relationship with respect to the y axis. The electrode pillars CGP and SGP may be arranged in a matrix.

[0040] Each electrode pillar SGP overlaps with one semiconductor on either the -X or +X side and is in contact with one semiconductor on its side.

[0041] Each electrode pillar SGP, which is omitted in Figure 4 and will be described later with reference to Figure 5, includes an insulator, a conductor, and a semiconductor. Each electrode pillar SGP has a columnar shape and extends in the Z direction. A portion of each electrode pillar SGP and the portion of the semiconductor 22 in contact with this electrode pillar SGP functions as a single selection gate transistor DT.

[0042] In the MC region MCR, areas where semiconductor 22 and electrode pillars CGP and SGP are not provided are provided with an insulator 23 (not shown) or are embedded with an insulator 23. In one example, the insulator 23 contains silicon oxide or consists of silicon oxide.

[0043] Each contact CP includes a first portion CPP1, a second portion CPP2, and an insulator CPI. The first portion CPP1 and the second portion CPP2 contain or consist of a conductor. In each contact CP, the first portion CPP1 and the second portion CPP2 overlap, and the first portion CPP1 and the insulator CPI overlap. The second portion CPP2 has a larger area along the xy plane than the area of ​​the first portion CPP1 along the xy plane. The first portion CPP1 has the shape of a column extending in the Z direction and is in contact with the second portion CPP2. Multiple different second portions CPP2 are located in different layers. The side surface of each second portion CPP2 is in contact with the side surface of the second portion 21P2 of the conductor 21 in the layer in which the second portion CPP2 is located. The insulator CPI surrounds the side surface of the second portion CPP2, i.e., the outer perimeter in Figure 4.

[0044] In the CP region, areas within the CPR where contact CP is not provided are insulated. In one example, the insulator contains or consists of silicon oxide.

[0045] Figure 5 shows an example of the cross-sectional structure of a part of the memory device of the first embodiment. Figure 5 shows an example of the cross-sectional structure of an electrode pillar CGP. As shown in Figure 5, the electrode pillar CGP includes an insulator 31, a conductor 32, a block insulator 33, a block insulator 34, a charge storage film 35, and a tunnel insulator 36.

[0046] The insulator 31 has a columnar shape extending in the Z direction. The conductor 32 surrounds the sides of the insulator 31. In one example, the conductor 32 includes or consists of a semiconductor containing a metal or impurities. Examples of metals include tungsten (W) and titanium nitride (TiN). Examples of semiconductors include silicon. Examples of impurities include elements that give the semiconductor n-type or p-type conductivity.

[0047] The block insulator 33 surrounds the sides of the conductor 32. In one example, the block insulator 33 includes or is made of an oxide or nitride of aluminum (Al), hafnium (Hf), titanium (Ti), zirconium (Zr), or lanthanum (La), or silicon oxide or silicon oxynitride (SiON). The block insulator 33 protrudes toward the semiconductor 22 on the side where the electrode pillar CGP is in contact with the semiconductor 22.

[0048] Each block insulator 34 surrounds at least a portion of the side surface of the block insulator 33 and is located between the block insulator 33 and a single semiconductor 22. The block insulator 34 is located in a region between multiple portions of the semiconductor 22. In one example, the block insulator 34 contains or consists of silicon oxide.

[0049] The charge storage film 35 surrounds the side surface of the block insulator 34 and is located between the block insulator 34 and a single semiconductor 22. The charge storage film 35 is located in the region between multiple parts of the semiconductor 22. The charge storage film 35 stores (holds) the injected charge (electrons). In one example, the charge storage film 35 contains or consists of silicon nitride.

[0050] The tunnel insulator 36 surrounds the side surface of the charge storage film 35 and is located between the charge storage film 35 and one semiconductor 22. The tunnel insulator 36 is located in the region between multiple parts of the semiconductor 22. The tunnel insulator 36 is in contact with one semiconductor 22. In one example, the tunnel insulator 36 contains or consists of silicon oxide.

[0051] The electrode pillar CGP in contact with the semiconductor 22 on the left side has a structure that is inverted with respect to the y-axis from the structure shown in Figure 5.

[0052] The electrode pillar SGP has the same structure as the electrode pillar CGP.

[0053] Figure 6 shows a layout of a portion of the memory device of the first embodiment along the xy plane. Figure 6 shows the layout near the boundary between the MC region (MCR) and the CP region (CPR), and for the region along the xy plane, it shows the same region as shown in Figure 4. Figure 6 shows the region on the Z side of the region shown in Figure 4, and the conductor 21 located furthest in the Z direction.

[0054] As shown in Figure 6, the storage device 1 includes a plurality of conductors 41 and a plurality of conductors 42.

[0055] The conductors 41 have a linear shape extending in the Y direction and are aligned in the X direction. Examples of conductors 41 include tungsten and titanium nitride. Each conductor 41 functions as at least part of one bit line BL. The conductors 41 are aligned in the X direction in ascending order of the identifiers (addresses) of the bit line BL in which the conductor 41 functions as part. That is, the conductors 41 aligned in the X direction function as at least part of bit line BL_0, bit line BL_1, bit line BL_2, ...

[0056] The conductor 42 has a columnar shape and extends in the Z direction. Each conductor 42 overlaps with one conductor 41 and one contact CP. The conductor 42 is in contact with one conductor 41 and the second portion CPP2 of one contact CP.

[0057] Figure 7 shows the structure of a cross-section of a part of the memory device of the first embodiment. Figure 7 shows the structure along the line VII-VII in Figure 4.

[0058] As shown in Figure 7, the memory device 1 further includes a semiconductor 51 and insulators 52, 54, 55, and 57.

[0059] In one example, the semiconductor 51 contains or consists of silicon.

[0060] The insulator 52 is located on the upper surface of the semiconductor 51. In one example, the insulator 52 contains silicon oxide or is made of silicon oxide.

[0061] The insulators 54 and 55 are positioned alternately, one at a time, on the upper surface of the semiconductor 51. The number of insulators 54 is equal to the number of bit lines BL, i.e., m+1. Figure 7 shows only four insulators 54. In one example, the insulators 54 and 55 contain silicon nitride, silicon oxide, or nitrogen-containing silicon oxide, or consist of silicon nitride, silicon oxide, or nitrogen-containing silicon oxide. Each layer of insulator 54 contains the semiconductor 22 and the second portion 21P2 of the conductor 21.

[0062] The insulator 57 is located on the upper surface of the top insulator 54. In one example, the insulator 57 contains or consists of silicon oxide.

[0063] Each contact CP includes a second portion CPP2 located in a layer of one insulator 54, and a first portion CPP1 having a lower surface in contact with the upper surface of the second portion CPP2. The first portion CPP1 penetrates insulator 57, one or more insulators 54, and one or more insulators 55. Each second portion CPP2 is in contact with one second portion 21P2 on its side. Each contact CP is in contact with only the second portion 21P2 of the layer in which its lower end is located, out of a plurality of second portions 21P2 located in a plurality of layers, respectively. Each second portion 21P2 may contain a different material in the portion including the edge on the side in the Y direction from the rest of the portion. An example of such a material is the material of the second portion CPP2 of the contact CP.

[0064] Figure 8 shows a layout of a portion of the storage device of the first embodiment along the xy plane. Figure 8 shows a portion of the MC region MCR, and a portion of the region between the first portion 21P1 of two adjacent conductors 21.

[0065] As shown in Figure 8, the memory device 1 further includes a conductor 44 and contacts 45. Each contact 45 overlaps with one electrode pillar CGP.

[0066] The conductors 44 extend in the X direction and are aligned in the Y direction. Two conductors 44 aligned in the X direction are located between the first parts 21P1 of two adjacent conductors 21. Therefore, multiple conductors 44 aligned in the Y direction form a set, and two sets aligned in the X direction are located between the first parts 21P1 of two adjacent conductors 21.

[0067] Each conductor 44 overlaps with multiple electrode pillars CGP aligned in the X direction and multiple contacts 45 that overlap with each of them. Each conductor 44 is located more in the Z direction relative to the electrode pillars CGP. Each conductor 44 functions as at least part of one subword line SWL.

[0068] The spacing between the conductors 44 aligned in the X direction is arbitrary. In one example, the spacing is located at the center of the set of electrode pillars CGP aligned in the X direction.

[0069] Figure 9 shows a layout of a portion of the memory device of the first embodiment along the xy plane. Figure 9 shows a portion of the MC region MCR. As shown in Figure 9, the memory device 1 further includes semiconductors 61, contacts 64, 65, and 68, and a conductor 67. Hereinafter, each of a certain electrode pillar CGP aligned in the X direction will be referred to as electrode pillar CGP_1, and each of another electrode pillar CGP aligned in the X direction will be referred to as electrode pillar CGP_2. Some electrode pillars CGP_1 are aligned in the Y direction, and some electrode pillars CGP_2 are aligned in the Y direction. On the other hand, each electrode pillar CGP_1 is not aligned in the Y direction with any of the electrode pillars CGP_2, and is located at a different position (coordinate) on the x axis. The sets of electrode pillars CGP_1 aligned in the X direction and the sets of electrode pillars CGP_2 aligned in the X direction alternately align in the Y direction one by one. A conductor 44 that overlaps with electrode pillar CGP_1 may be referred to as conductor 44_1, and a conductor 44 that overlaps with electrode pillar CGP_2 may be referred to as conductor 44_2.

[0070] The semiconductors 61_1 extend in the X direction and are aligned in the Y direction. Each semiconductor 61_1 overlaps with one conductor 44_1. The semiconductors 61_1 include source / drain regions 62_1 and 63_1. The source / drain region 62_1 is located in the region that includes the -X side edge of the semiconductor 61_1. The source / drain region 63_1 is located in the region that includes the X side edge of the semiconductor 61_1.

[0071] Contact 64_1 overlaps with the source / drain region 63_1 and one conductor 44_1. Contact 64_1 is in contact with the source / drain region 63_1 and one conductor 44_1.

[0072] Contact 65_1 overlaps with the source / drain region 62_1. Contact 65_1 is in contact with the source / drain region 62_1.

[0073] The conductor 67_1 extends in the Y direction and overlaps with multiple semiconductors 61_1. The conductor 67_1 is located on a gate insulator (not shown) on the semiconductors 61_1.

[0074] The contacts 68_1 are aligned in the Y direction. Each contact 68_1 overlaps with one semiconductor 61_1 and one conductor 67_1.

[0075] Each semiconductor 61_1, the source / drain regions 62_1 and 63_1 within this semiconductor 61_1, the gate insulator, and the portion of the conductor 67_1 that overlaps with this semiconductor 61_1 function as a single transistor T.

[0076] Each semiconductor 61_2 extends in the X direction and is aligned in the Y direction. Each semiconductor 61_2 overlaps with one conductor 44_2. The semiconductor 61_2 includes source / drain regions 62_2 and 63_2. The source / drain region 62_2 is located in the region that includes the -X side edge of the semiconductor 61_2. The source / drain region 63_2 is located in the region that includes the X side edge of the semiconductor 61_2.

[0077] Contact 64_2 overlaps with the source / drain region 63_2 and one conductor 44_2. Contact 64_2 is in contact with the source / drain region 63_2 and one conductor 44_2.

[0078] Contact 65_2 overlaps with the source / drain region 62_2. Contact 65_2 is in contact with the source / drain region 62_2.

[0079] The conductor 67_2 extends in the Y direction and overlaps with multiple semiconductors 61_2. The conductor 67_2 is located on a gate insulator (not shown) on the semiconductor 61_2.

[0080] The contacts 68_2 are aligned in the Y direction. Each contact 68_2 overlaps with one semiconductor 61_2 and one conductor 67_2.

[0081] Each semiconductor 61_2, the source / drain regions 62_2 and 63_2 within this semiconductor 61_2, the gate insulator, and the portion of the conductor 67_2 that overlaps with this semiconductor 61_2 function as a single transistor T.

[0082] As described above, two types of conductors 44_1 and 44_2 are provided alternately, one of each. Based on this, two types of semiconductors 61_1 and 61_2 are provided. If we define the distance D1 between two conductors 44 aligned in the Y direction as the distance between the center of one conductor 44 on the y axis and the center of the other conductor 44 on the y axis, and define the distance D2 between two semiconductors 61_1 aligned in the Y direction as the distance between the center of one semiconductor 61_1 on the y axis and the center of the other semiconductor 61_1 on the y axis, then the distance D2 is twice the distance D1. Similarly, if we define the distance D3 between two semiconductors 61_2 aligned in the Y direction as the distance between the center of one semiconductor 61_2 on the y axis and the center of the other semiconductor 61_1 on the y axis, then the distance D3 is twice the distance D2.

[0083] When sets of n conductors 44 aligned in the Y direction are repeatedly aligned in the Y direction, the spacing D2 and spacing D3 are n times the spacing D1.

[0084] Hereinafter, a transistor T connected to one of two conductors 44 aligned in the X direction may be referred to as transistor T_0, and a transistor T connected to the other may be referred to as transistor T_1. More specifically, it is as follows:

[0085] Figure 10 shows a layout of a portion of the memory device of the first embodiment along the xy plane. As shown in Figure 10, one of the two conductors 44 aligned in the X direction (e.g., the conductor 44 located on the -X side) is referred to as conductor 44_L, and the other of the two conductors 44 aligned in the X direction (e.g., the conductor 44 located on the X side) is referred to as conductor 44_R. The region between the first portion 21P1 of the two conductors 21 aligned in the X direction includes region A_0 and region A_1. Regions A_0 and A_1 are aligned in the X direction and do not overlap each other.

[0086] Region A_0 includes conductor 44_L but does not include conductor 44_R. Region A_0 includes transistor T_0 but does not include transistor T_1.

[0087] Region A_1 includes conductor 44_R but does not include conductor 44_L. Region A_1 includes transistor T_1 but does not include transistor T_0.

[0088] Figure 11 shows a layout of a portion of the storage device of the first embodiment along the xy plane. Figure 11 shows a portion of the MC region MCR, and the region along the xy plane is the same region as shown in Figure 8. Figure 11 shows the region on the Z side of the region shown in Figure 8.

[0089] As shown in Figure 11, the memory device 1 further includes conductors 46. Each conductor 46 extends in the X direction and is aligned in the Y direction. Each conductor 46 extends across the first portion 21P1 of two conductors 21 aligned in the X direction. Each conductor 46 overlaps with a set of electrode pillars CGP aligned in the X direction (i.e., a set of electrode pillars CGP_1 or a set of electrode pillars CGP_2). Therefore, the spacing of the conductors 46 along the y-axis is the same as the spacing D1 of the conductors 44 along the y-axis.

[0090] Figure 12 shows an example of the structure of a cross-section of a part of the memory device of the first embodiment. Figure 12 shows the structure along the line XII-XII in Figure 9.

[0091] As shown in Figure 12, the memory device 1 further includes a semiconductor 70, insulators 71, 72, 74, 75, and 78, and contacts 77. In one example, the insulators 71, 72, 74, 75, and 78 contain or consist of silicon oxide.

[0092] The electrode pillar CGP penetrates the insulators 57, 54, and 55, as well as the semiconductor 22. A portion of the underside of the electrode pillar CGP lies within the insulator 52. In one example, the undersides of the block insulator 33, the conductor 32, and the insulator 31 are each located within the insulator 52.

[0093] Each semiconductor 70 is located in a region that includes the upper surface of one electrode pillar CGP. In one example, the semiconductor 70 contains or is made of silicon. The semiconductor 70 is doped with impurities and is conductive.

[0094] The upper surface of each electrode pillar CGP is in contact with the lower surface of one contact 45. The upper surface of each contact 45 is in contact with the lower surface of one conductor 44.

[0095] The insulator 71 is located in a region within the layer where the contact 45 is located, where the contact 45 is not provided.

[0096] The conductor 44 is located on the upper surface of the insulator 71 and the contact 45, respectively.

[0097] The contact 64 is in contact with the upper surface of the conductor 44 on its lower surface.

[0098] The insulator 72 is located in a region within the layer where the contact 64 is located, where the contact 64 is not provided.

[0099] The source / drain region 63 is in contact with the upper surface of the contact 64 on its lower surface.

[0100] The insulator 74 is located in a region within the layer where the semiconductor 61 is located, where the semiconductor 61 is not provided.

[0101] The conductor 67 is located above the upper surface of the semiconductor 61. A gate insulator is provided between the conductor 67 and the semiconductor 61.

[0102] The contact 68 is in contact with the upper surface of the conductor 67 on its lower surface.

[0103] The contact 65 is in contact with the upper surface of the source / drain region 62 on its lower surface.

[0104] The insulator 75 is located in a region within the layer where the conductor 67 and the contacts 65 and 68 are located, where the conductor 67 and the contacts 65 and 68 are not provided.

[0105] The conductor 46 is located on the upper surface of the insulator 75 and the contact 65, respectively.

[0106] The contact 77 is in contact with the upper surface of the conductor 46 on its lower surface. In one example, the contact 77 contains tungsten or is made of tungsten.

[0107] The insulator 78 is located in a region within the layer where the contact 77 is located, where the contact 77 is not provided.

[0108] Figure 13 shows the division of the memory device into blocks according to the first embodiment, and shows some of the components of the blocks and the connections of the components. As shown in Figure 13, each block BLK contains two subblocks SBLK (SBLK_0 and SBLK_1). The number of subblocks SBLK corresponds to the number of conductors 44 aligned in the X direction between two adjacent conductors 21. Subblock SBLK_0 contains bit lines BL_0 to BL_k, where k is an integer greater than or equal to 1. k depends on the position of the boundary of the conductors 44 aligned in the X direction. Based on the example where the boundary is located at the center of a pair of electrode pillars CGP aligned in the X direction, k is p / 2, where p is the number of conductors 44 aligned along the x-axis between two adjacent conductors 21. Subblock SBLK_1 contains bit lines BL_k+1 to BL_p-1.

[0109] The word line WL_0 is connected to the subword line SWL_0_0 via transistor T_0. The subword line SWL_0_0 is connected to the memory cell transistor MT_0 of the subblock SBLK_0. Transistor T_0 receives the signal SN0 at its gate.

[0110] The word line WL_0 is connected to the subword line SWL_0_1 via transistor T_1. The subword line SWL_0_1 is connected to the memory cell transistor MT_0 of the subblock SBLK_1. Transistor T_1 receives the signal SN1 at its gate.

[0111] The word line WL_1 is connected to the subword line SWL_1_0 via transistor T_0. The subword line SWL_1_0 is connected to the memory cell transistor MTMT_1 of the subblock SBLK_0.

[0112] The word line WL_1 is connected to the subword line SWL_1_1 via transistor T_1. The subword line SWL_1_1 is connected to the memory cell transistor MT_1 of the subblock SBLK_1.

[0113] Similarly, for each integer case where Q is between 2 and n, the word line WL_Q is connected to the subword line SWL_Q_0 via transistor T_0. For each integer case where Q is between 2 and n-1, the subword line SWL_Q_0 is connected to the memory cell transistor MT_Q of subblock SBLK_0.

[0114] For each integer case where Q is between 2 and n, the word line WL_Q is connected to the subword line SWL_Q_1 via transistor T_1. For each integer case where Q is between 2 and n-1, the subword line SWL_Q_1 is connected to the memory cell transistor MT_Q of subblock SBLK_1.

[0115] Bit lines BL0 to BL_k share a common value in a specific bit of the assigned column address, in one example, the most significant bit. In one example, bit lines BL0 to BL_k have the value "0" in the most significant bit of the column address.

[0116] Bit lines BL_k+1 to BL_p-1 share a common value in a specific bit of the assigned column address, for example, the most significant bit. Bit lines BL_k+1 to BL_p-1 have a different value in the most significant bit of the column address from bit lines BL0 to BL_k. For example, bit lines BL_k+1 to BL_p-1 have a value of "1" in the most significant bit of the column address.

[0117] Signal SN0 has a high level when the column address to be accessed has a value of "0" in its most significant bit. Signal SN1 has a high level when the column address to be accessed has a value of "1" in its most significant bit.

[0118] 1.3. Advantages (Effects) According to the first embodiment, as described below, it is possible to provide a storage device in which conductors can be easily arranged and which has a reduced size block.

[0119] The memory device 1 may have many layers as described above, with reference to Figure 4, in order to have a large storage capacity. The more layers there are, the more contact CPs are required to be arranged. To double the number of layers in a certain comparative structure, twice the number of contact CPs are required to be arranged. To arrange twice the number of contact CPs, in the example of Figure 4, where two contact CPs are provided in the Y direction, it is conceivable that four contact CPs may be provided in the Y direction. In the example where two contact CPs are provided in the Y direction, as shown in Figure 6, the conductors 41 only need to be arranged so that two conductors 41 overlap in the row of two contact CPs aligned in the Y direction. However, when four contact CPs are provided in the Y direction, the conductors 41 need to be arranged so that four conductors 41 overlap in the row of four contact CPs aligned in the Y direction. This makes the arrangement of the conductors 41 difficult.

[0120] In contrast, it is conceivable to maintain the number of contact CPs aligned in the Y direction at 2, while laying twice the number of contact CPs as the number of layers in the comparison structure, by arranging the increased number of contact CPs in the X direction from the comparison configuration. In this case, the number of electrode pillars CGP connected to the conductor functioning as a single word line WL is twice the number of electrode pillars CGP connected in the comparison structure. This means that the size of the block BLK is twice the size of the block BLK in the comparison structure. If the block BLK is used as a unit for erasing data, an excessively large block BLK size would impair the usability of the storage device 1.

[0121] According to the first embodiment, the memory device 1 includes only two contacts CP in the Y direction in the CP region CPR. This facilitates the arrangement of conductors 41 that function as at least part of the bit line BL. The memory device 1 also includes a transistor T connected to a word line WL and a subword line SWL connected to transistor T. Conductors 44 that function as at least part of the subword line SWL are connected to fewer electrode pillars CGP than conductors 46 that function as at least part of the word line WL. Therefore, the size of block BLK is smaller than in the case where electrode pillars CGP are connected to conductors 46.

[0122] 1.4. Variations The description so far concerns an example in which two conductors 44 are aligned along the x-axis between the first parts 21P1 of two conductors 21 aligned along the x-axis. There may be three or more conductors 44 aligned along the x-axis between the first parts 21P1 of two conductors 21 aligned along the x-axis.

[0123] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0124] 1...Storage device, 10…Memory cell array, 11... Raw decoder, 12... Register, 13... Sequencer, 14... Driver, 15...Sense amp, BLK... Block, MT...Memory cell transistor, WL... Word line, BL... bit line, SU... String unit, NS...NAND string, ST...Selection gate transistor, DT...Selection gate transistor, CU... Cell unit, 21... Conductor, MCR…MC area, CPR…CP area, CGP... Electrode pillar, SGP... Electrode pillar, 22... Semiconductors, 42... Conductor, 44... Conductors, 46... Conductor

Claims

1. A first semiconductor extending in the first direction, A first pillar extending in a second direction intersecting the first direction and in contact with the first semiconductor, A first conductor connected to the end of the first pillar on the second direction side and extending in a third direction intersecting the first and second directions, A first transistor is provided in the second direction from the first conductor and connected to the first conductor, A second conductor is provided in the second direction from the first conductor, extends in the third direction, and is connected to the first transistor. A storage device equipped with the following features.

2. The first conductor and the second conductor are arranged in the second direction. The storage device according to claim 1.

3. The first conductor is shorter than the second conductor. The storage device according to claim 1.

4. The first semiconductor is in contact with the first pillar, and the second pillar is aligned in a fourth direction that intersects the first direction, the second direction, and the third direction. A third conductor is connected to the end of the second pillar on the second direction and extends in the third direction, A second transistor is provided in the second direction from the third conductor and connected to the third conductor, A fourth conductor is provided in the second direction from the third conductor, extends in the third direction, and is connected to the second transistor. Furthermore, The storage device according to claim 1.

5. The first transistor includes a second semiconductor, The aforementioned second transistor includes a third semiconductor, The sum of the length of the second semiconductor along the third direction and the length of the third semiconductor along the third direction is shorter than the length of the first conductor. The storage device according to claim 4.

6. The first semiconductor is in contact with the second pillar, extends in the second direction, and is aligned with the first pillar in the first direction, A third conductor is connected to the end of the second pillar on the second direction and extends in the third direction, A second transistor is provided in the second direction from the third conductor and connected to the third conductor, A fourth conductor is provided in the second direction from the third conductor, extends in the third direction, and is connected to the second transistor. Furthermore, The storage device according to claim 1.

7. The first conductor and the second conductor are arranged in the second direction, The third conductor and the fourth conductor are arranged in the second direction, The storage device according to claim 6.

8. The present invention further comprises a fifth conductor provided between the first conductor and the third conductor and extending in the third direction, The first transistor and the second transistor are arranged adjacent to each other in the first direction. The storage device according to claim 7.

9. Further comprising a sixth conductor, The first transistor includes a first portion of the sixth conductor, The second transistor includes the second portion of the sixth conductor, The storage device according to claim 8.

10. The first conductor and the third conductors aligned in the third direction, A second transistor is provided in the second direction from the third conductor and connected between the third conductor and the second conductor, Furthermore, The storage device according to claim 1.

11. The first pillar is in contact with the first semiconductor on a plane facing the third direction or the opposite direction of the third direction. The storage device according to claim 1.

12. The invention comprises a plurality of first semiconductors, including the first semiconductor, The plurality of first semiconductors extend in the first direction and are arranged with spacing in the second direction. The first pillar is in contact with the plurality of first semiconductors. The storage device according to claim 1.

13. The first pillar includes a film that holds the injected electrons, The storage device according to claim 1.

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