Semiconductor memory

Abstract

To provide a semiconductor memory device that enables high integration. [Solution] The semiconductor memory device comprises a bonded first chip CM and a second chip CP, the second chip comprising a first wiring layer and a second wiring layer provided between the semiconductor substrate and the first chip. The second wiring layer comprises a plurality of word line voltage supply line groups and a plurality of block selection line (BLKSEL) groups arranged alternately in a second direction, each of the plurality of word line voltage supply line groups extending in a first direction and comprising a plurality of word line voltage supply lines arranged in a second direction, and each of the plurality of block selection line groups comprises a first block selection line and a second block selection line. The first block selection line is the first block selection line from one side in the second direction among the plurality of block selection lines, and comprises a curved portion 402 that bends in a direction away from the adjacent word line conductive layer in the second direction. The second block selection line comprises a connection portion 401 that electrically connects to the first wiring layer at its end in the first direction.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a substrate, a plurality of conductive layers stacked in a direction intersecting the surface of the substrate, semiconductor layers facing these plurality of conductive layers, and a gate insulating layer provided between the conductive layers and the semiconductor layers. The gate insulating layer includes a memory portion capable of storing data, such as an insulating charge storage layer made of silicon nitride (SiN) or a conductive charge storage layer such as a floating gate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2018-026518 [Patent Document 2] Japanese Patent Publication No. 2015-041743 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that enables high integration. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a first chip having a plurality of memory blocks arranged in a first direction and extending in a second direction intersecting the first direction, and a second chip bonded to the first chip via bonding electrodes. Each of the plurality of memory blocks comprises a plurality of word line conductive layers stacked in the stacking direction, semiconductor pillars extending in the stacking direction and facing the plurality of word line conductive layers, and a charge storage film provided between the plurality of word line conductive layers and the semiconductor pillars. The second chip includes a semiconductor substrate, a plurality of transistor groups provided on the semiconductor substrate corresponding to the plurality of memory blocks and each including a plurality of transistors arranged in a first direction and a second direction, a block decoder provided on the semiconductor substrate that decodes a block address and selects one of the plurality of memory blocks, a first wiring layer provided between the semiconductor substrate and the first chip, and a second wiring layer provided between the first wiring layer and the first chip. The second wiring layer comprises a plurality of word line voltage supply line groups and a plurality of block selection line groups, each of which extends in the first direction and comprises a plurality of word line voltage supply line lines arranged in the second direction. Each of the plurality of word line voltage supply line lines is electrically connected in common to a corresponding word line conductive layer included in each of the plurality of memory blocks via a corresponding transistor included in each of the plurality of transistor groups, and each of the plurality of block selection line groups comprises a plurality of block selection line lines extending in the first direction and arranged in the second direction. Each of the plurality of block selection line lines is electrically connected in common to the gate electrodes of n transistors included in a corresponding transistor in one of the plurality of transistor groups, and each of the plurality of block selection line groups includes a first block selection line and a second block selection line.

[0006] The first block selection line is the first block selection line from one side in the second direction among a plurality of block selection lines, and has a first curved portion that bends away from the adjacent word line conductive layer in the second direction. The second block selection line has a first connection portion that electrically connects to the first wiring layer at its end in the first direction, and the position of the first curved portion in the first direction differs for each of the alternately arranged groups of word line voltage supply lines and groups of block selection lines. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 2] This is a schematic circuit diagram showing a portion of the peripheral circuit configuration of the PC. [Figure 3] This is a schematic circuit diagram showing a portion of the peripheral circuit configuration of the PC. [Figure 4] This is a schematic circuit diagram showing a portion of the peripheral circuit configuration of the PC. [Figure 5] This is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. [Figure 6] This is a schematic bottom view showing an example of the configuration of a chip CM. [Figure 7] This is a schematic cross-sectional view showing a portion of the configuration of a memory die (MD). [Figure 8] This is a schematic cross-sectional view showing a portion of the configuration of a memory die (MD). [Figure 9] This is a schematic bottom view showing a portion of the configuration of the chip CM. [Figure 10] This is a schematic cross-sectional view showing a portion of the structure of the chip CM. [Figure 11] This is a schematic plan view showing an example of the configuration of a chip CP. [Figure 12] This is a schematic plan view showing an example configuration of a word line switch (WLSW). [Figure 13] This is a schematic enlarged view of the area indicated by B in Figure 11. [Figure 14]This figure shows an example of a wiring pattern for block selection lines BLKSEL in wiring layer D4. [Figure 15] This figure shows an example of a wiring pattern for block selection lines BLKSEL in wiring layer D3. [Figure 16] This figure shows an example of a wiring pattern, such as a block selection line BLKSEL, in the wiring layer D4 according to the second embodiment. [Figure 17] This is a schematic plan view showing some configuration examples of the chip CP according to the third embodiment. [Figure 18] This figure illustrates some configuration examples of chip CM and chip CP according to the fourth embodiment. [Figure 19] This figure shows an example of a wiring pattern for block selection lines BLKSEL in wiring layer D4 according to the fourth embodiment. [Figure 20] This is a schematic diagram showing the positional relationship between the word line switch WLSW and the memory block BLK according to the first embodiment. [Figure 21] This is a schematic diagram showing the positional relationship between the word line switch WLSW and the memory block BLK according to another embodiment. [Figure 22] This is a schematic diagram showing the positional relationship between the word line switch WLSW and the memory block BLK according to another embodiment. [Modes for carrying out the invention]

[0008] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0009] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0010] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0011] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0012] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0013] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0014] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0015] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0016] Furthermore, in this specification, when we refer to the "width," "length," or "thickness" of a component, member, etc., in a predetermined direction, it may mean the width, length, or thickness of a cross-section observed by SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy), etc.

[0017] Furthermore, in this specification, the term "wiring" may include wiring, contact electrodes, connectors for connecting wiring and contact electrodes, bonded electrodes, etc.

[0018] [First Embodiment] [Circuit configuration of the memory die MD] Figure 1 is a schematic circuit diagram showing a portion of the configuration of the memory die MD. Figures 2 to 4 are schematic circuit diagrams showing a portion of the configuration of the peripheral circuit PC.

[0019] As shown in Figure 1, the memory die MD comprises a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC comprises a voltage generation circuit VG and a low decoder RD, as shown in Figures 2 and 4.

[0020] [Circuit configuration of memory cell array MCA] As shown in Figure 1, the memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0021] A memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory transistors), and a source-side selection transistor STS. The drain-side selection transistor STD, the multiple memory cells MC, and the source-side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors (STD, STS).

[0022] A memory cell MC is a field-effect transistor. A memory cell MC comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. A memory cell MC stores one or more bits of data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are commonly connected to all memory string MS in one memory block BLK.

[0023] Selection transistors (STD, STS) are field-effect transistors. A selection transistor (STD, STS) comprises a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may include a charge storage film. A drain-side selection gate line SGD is connected to the gate electrode of the drain-side selection transistor STD, and a source-side selection gate line SGS is connected to the gate electrode of the source-side selection transistor STS. One drain-side selection gate line SGD is commonly connected to all memory strings MS in one string unit SU. One source-side selection gate line SGS is commonly connected to all memory strings MS in one memory block BLK.

[0024] [Circuit configuration of the voltage generation circuit VG] The voltage generation circuit VG comprises multiple voltage generation units vg1 to vg4, as shown in Figures 2 and 4, for example.

[0025] The voltage generation units vg1 to vg3 (Figure 2) generate a voltage of a predetermined magnitude during read, write, and erase operations, and supply voltage to the voltage supply line L VG1 ~L VG3 It outputs via [a specific method]. For example, the voltage generation unit vg1 outputs the program voltage V during the writing operation. PGM The voltage generation unit vg2 outputs the read path voltage during read operations. The voltage generation unit vg2 also outputs the write path voltage V during write operations. USEL The voltage generation unit vg3 outputs the read voltage during read operations. Furthermore, the voltage generation unit vg3 outputs the verify voltage V during write operations. CGR Outputs.

[0026] The voltage generation unit vg4 (Figure 4) generates a voltage of a predetermined magnitude and supplies voltage to the voltage supply line L VG4 The output is generated via [a specific device]. For example, the voltage generation unit vg4 outputs a voltage to turn on the drain-side selected gate line SGD.

[0027] The voltage generation units vg1 to vg3 may be, for example, a boosting circuit such as a charge pump circuit, or a bucking circuit such as a regulator. These bucking circuits and boosting circuits are each connected to a voltage supply line L P . The voltage supply line L P is supplied with a ground voltage V SS . These voltage supply lines L P are connected to, for example, a pad electrode P. The operating voltage output from the voltage generation circuit VG is appropriately adjusted according to a control signal from a sequencer not shown in the figure.

[0028] In addition, FIG. 2 illustrates a configuration for generating a program voltage, a read path voltage, a write path voltage, a read voltage, and a verify voltage that are applied to the word line WL via the voltage supply line CGI in the voltage generation circuit VG. Further, FIG. 4 illustrates a configuration for generating a voltage applied to the drain side select gate line SGD via the voltage supply line CGI in the voltage generation circuit VG. However, the voltage generation circuit VG includes a configuration for generating a plurality of operating voltages applied to the bit line BL, the source line SL, and the select gate lines (SGD, SGS) during a read operation, a write operation, and an erase operation on the memory cell array MCA, in addition to the operating voltages applied to the word line WL and the drain side select gate line SGD, and outputting them to a plurality of voltage supply lines. These operating voltages are appropriately adjusted according to a control signal from a sequencer not shown in the figure.

[0029] [Circuit configuration of row decoder RD] The row decoder RD includes, for example, as shown in FIGS. 2 and 4, a row control circuit RowC, a word line decoder WLD, a select gate line decoder SGDD, a driver circuit DRV, and an address decoder not shown in the figure. The row control circuit RowC includes, for example, as shown in FIG. 3, a plurality of block decoder units blkd and a block decoder BLKD.

[0030] Multiple block decoder units blkd correspond to multiple memory blocks BLK in the memory cell array MCA. Each block decoder unit blkd comprises multiple word line switches WLSW and multiple selection gate line switches SGSW, SGSWP. Multiple word line switches WLSW correspond to multiple word lines WL in the memory block BLK. Multiple selection gate line switches SGSW, SGSWP correspond to the drain-side selection gate line SGD and the source-side selection gate line SGS in the memory block BLK.

[0031] The word line switch WLSW is, for example, a field-effect NMOS transistor. The drain electrode of the word line switch WLSW is connected to the word line WL. The source electrode of the word line switch WLSW is connected to the voltage supply line CGI. The gate electrode of the word line switch WLSW is connected to the block selection line BLKSEL.

[0032] The selective gate line switch SGSW is, for example, a field-effect NMOS transistor. The drain electrode of the selective gate line switch SGSW is connected to the drain-side selective gate line SGD and the source-side selective gate line SGS. The source electrode of the selective gate line switch SGSW is connected to the voltage supply line CGI. The gate electrode of the selective gate line switch SGSW is connected to the block selective line BLKSEL.

[0033] A selective gate line switch (SGSWP) is, for example, a field-effect NMOS transistor. The drain electrode of the selective gate line switch (SGSWP) is connected to the drain-side selective gate line (SGD) and the source-side selective gate line (SGS). The source electrode of the selective gate line switch (SGSWP) is connected to the pad electrode. The gate electrode of the selective gate line switch (SGSWP) is connected to the block selective line (BLKSELn).

[0034] Multiple block selection lines, BLKSEL and BLKSELn, are provided to correspond to all block decoder units, blkd. Furthermore, the block selection lines BLKSEL and BLKSELn are connected to all word line switches (WLSW) and selection gate line switches (SGSW) within the block decoder unit blkd.

[0035] The block decoder BLKD (Figure 3) decodes the block address and supplies a high voltage to one block selection line BLKSEL corresponding to the block address, and a low voltage to another block selection line BLKSEL corresponding to that. It also supplies low voltages to other block selection lines BLKSEL and supplies high voltages to the corresponding block selection lines BLKSELn.

[0036] The word line decoder WLD (Figure 2) comprises multiple word line decoding units wld. Each of the multiple word line decoding units wld corresponds to multiple memory cells MC in the memory string MS. In the example in Figure 2, the word line decoding unit wld comprises two transistors T WLS ,T WLU It is equipped with a transistor T WLS ,T WLU For example, a field-effect NMOS transistor. Transistor T WLS ,T WLU The drain electrode of transistor T is connected to the voltage supply line CGI. WLS The source electrode is the voltage supply line CGI S It is connected to transistor T. WLU The source electrode is the voltage supply line CGI U It is connected to transistor T. WLS The gate electrode is the signal line WLSEL S It is connected to transistor T. WLU The gate electrode is the signal line WLSEL U It is connected to the signal line WLSEL. S This is one of the transistors T included in all word line decoding units (wld). WLS Multiple units are provided to accommodate this. Signal line WLSELU This is the other transistor T included in all word line decoding units wld. WLU Multiple versions are provided to accommodate this.

[0037] In read and write operations, for example, a signal line WLSEL corresponds to a word line decoding unit wld that corresponds to a page address. S The signal line WLSEL enters the "H" state. U This enters the "L" state. In addition, the signal line WLSEL corresponds to the other word line decoding unit wld. S The signal line WLSEL enters the "L" state. U This enters the "H" state. Also, the voltage supply line CGI S A voltage corresponding to the selected word line WL is supplied to it. Also, the voltage supply line CGI U A voltage corresponding to the unselected word line WL is supplied to this.

[0038] The selected gate line decoder SGDD (Figure 4) comprises multiple selected gate line decoding units sgd. These multiple selected gate line decoding units sgd correspond to multiple string units SU in the memory block BLK. In the example in Figure 4, the selected gate line decoding unit sgd comprises two transistors T SGDS ,T SGDU It is equipped with a transistor T SGDS ,T SGDU For example, a field-effect NMOS transistor. Transistor T SGDS ,T SGDU The drain electrode of transistor T is connected to the voltage supply line CGI. SGDS The source electrode is the voltage supply line CGI S It is connected to transistor T. SGDU The source electrode is the voltage supply line CGI U It is connected to transistor T. SGDS The gate electrode is the signal line SGSEL S It is connected to transistor T. SGDU The gate electrode is the signal line SGSEL U It is connected to the signal line SGSEL.S This is one of the transistors T included in all selected gate line decode units (SGD). SGDS Multiple units are provided to accommodate this. Signal line SGSEL U This is the other transistor T included in all selected gate line decode units (sgd). SGDU Multiple versions are provided to accommodate this.

[0039] In read and write operations, for example, a single selected gate line corresponding to a page address corresponds to a decode unit sgd, and a signal line SGSEL corresponds to that gate line. S The signal line SGSEL enters the "H" state. U This enters the "L" state. In addition, the signal line SGSEL corresponds to the other selected gate line decode unit SGD. S The signal line SGSEL enters the "L" state. U This enters the "H" state. Also, the voltage supply line CGI S The voltage corresponding to the drain-side selection gate line SGD in the selection string unit SU is supplied to this line. Also, the voltage supply line CGI U A voltage corresponding to the drain-side selected gate line SGD in the non-selected string unit SU is supplied to this.

[0040] The driver circuit DRV is, for example, as shown in Figure 2, a transistor T DRV1 ~T DRV6 It is equipped with a transistor T DRV1 ~T DRV6 For example, a field-effect NMOS transistor. Transistor T DRV1 ~T DRV4 The drain electrode is connected to the voltage supply line CGI. S It is connected to transistor T. DRV5 ,T DRV6 The drain electrode is connected to the voltage supply line CGI. U It is connected to transistor T. DRV1 The source electrode is connected to the voltage supply line L. VG1 It is connected to the output terminal of the voltage generation unit vg1 via transistor T. DRV2 ,T DRV5 The source electrode is connected to the voltage supply line L.VG2 is connected to the output terminal of the voltage generation unit vg2 via the transistor T DRV3 The source electrode of is connected to the output terminal of the voltage generation unit vg3 via the voltage supply line L VG3 is connected to the output terminal of the voltage generation unit vg3 via the transistor T DRV4 ,T DRV6 The source electrode of is connected to the pad electrode P via the voltage supply line L P is connected to the pad electrode P via the transistor T DRV1 ~T DRV6 The gate electrodes of are respectively connected to the signal lines VSEL1~VSEL6

[0041] In the read operation, write operation, etc., for example, one of the plurality of signal lines VSEL1~VSEL4 corresponding to the voltage supply line CGI S becomes the “H” state, and the others become the “L” state. Also, one of the two signal lines VSEL5, VSEL6 corresponding to the voltage supply line CGI U becomes the “H” state, and the other becomes the “L” state

[0042] Also, the driver circuit DRV, for example, as shown in FIG. 4, includes the transistor T DRV7 ,T DRV8 is provided. The transistor T DRV7 ,T DRV8 is, for example, a field effect type NMOS transistor. The transistor T DRV7 ,T DRV8 The drain electrode of is connected to the voltage supply line CGI S is connected to the voltage supply line CGI DRV7 ,T DRV8 The drain electrode of is connected to the voltage supply line CGI U is connected to the voltage supply line CGI DRV7 The source electrode of is connected to the output terminal of the voltage generation unit vg4 via the voltage supply line L VG4 is connected to the output terminal of the voltage generation unit vg4 via the transistor T DRV8 The source electrode of is connected to the pad electrode P DRV7 ,T DRV8 The gate electrodes of are respectively connected to the signal lines VSEL7, VSEL8

[0043] In read operations, write operations, etc., for example, voltage supply line CGI S One of the multiple signal lines VSEL1 to VSEL4 corresponding to this will be in the "H" state, and the others will be in the "L" state. Also, the voltage supply line CGI U Of the two corresponding signal lines VSEL5 and VSEL6, one will be in the "H" state and the other in the "L" state.

[0044] In the examples shown in Figures 2 to 4, the row decoder RD is provided with one block decoder unit blkd for each memory block BLK. However, this configuration can be changed as appropriate. For example, one block decoder unit blkd may be provided for each of two or more memory blocks BLK.

[0045] [Memory die MD structure] Figure 5 is a schematic exploded perspective view showing an example configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 5, the memory die MD is located on the chip C on the memory cell array MCA side. M And, the peripheral circuit PC side chip C P It is equipped with the following.

[0046] Chip C M On the upper surface are multiple external pad electrodes P (not shown) that can be connected to bonding wires. X A chip C is provided. M On the lower surface, there are multiple bonded electrodes P I1 A chip C is provided. P On the upper surface, there are multiple bonded electrodes P I2 A chip C is provided below. M Regarding this, multiple bonded electrodes P I1 The surface on which the multiple external pad electrodes P are provided is called the surface, and X The side on which this is provided is called the back side. Also, chip C P Regarding this, multiple bonded electrodes P I2 The surface on which the chip is provided is called the front surface, and the surface opposite the front surface is called the back surface. In the illustrated example, chip C P The surface is chip C PIt is located above the back surface, and chip C M The back side is chip C M It is positioned above the surface.

[0047] Chip C M and chip C P This is chip C M Surface and chip C P Multiple bonded electrodes P are arranged so as to face each other on the surface. I1 This is a plurality of bonded electrodes P I2 Multiple adhesive electrodes P are provided, corresponding to each of them. I2 It is positioned in a location where it can be bonded. Bonding electrode P I1 and bonded electrode P I2 This refers to chip C M and chip C P It functions as a bonding electrode for bonding two materials together and for electrical conductivity.

[0048] Furthermore, in the example in Figure 5, chip C M The corners a1, a2, a3, and a4 are, respectively, chip C P These correspond to corners b1, b2, b3, and b4.

[0049] Figure 6 shows chip C M This is a schematic bottom view showing an example of the configuration. In Figure 6, the bonded electrode P I1 Some components, such as those shown, have been omitted. Figures 7 and 8 are schematic cross-sectional views showing some components of the memory die MD. Figure 9 shows chip C M This is a schematic bottom view showing a part of the configuration. In Figure 9, the left region shows the XY cross-section at the position of the word line WL, and the right region shows the XY cross-section at the position of the drain-side selection gate line SGD. In addition, in the right region of Figure 9, the contact electrodes ch,Vy and the bit line BL are also shown to represent the connection between the semiconductor layer 120 and the bit line BL. In the left region of Figure 9, the contact electrodes ch,Vy and the bit line BL are also provided. Figure 10 shows chip C MThis is a schematic cross-sectional view showing part of the structure. Figure 10 shows a YZ cross-section, but a similar structure to that in Figure 10 can be observed when observing cross-sections other than the YZ cross-section along the central axis of the semiconductor layer 120 (for example, the XZ cross-section). Figure 11 shows chip C P This is a schematic plan view showing an example of the configuration. Figure 11 shows the bonded electrode P I2 Some of the components have been omitted.

[0050] [Chip C M [Structure] In the example in Figure 6, chip C M It comprises four memory planes MP0 to MP3 aligned in the X direction. These four memory planes MP0 to MP3 are sometimes simply referred to as memory plane MP. Furthermore, each of these four memory planes MP0 to MP3 comprises multiple memory blocks BLK aligned in the Y direction. In the example in Figure 6, each of these four memory planes MP0 to MP3 comprises a memory hole region R. MH (Memory area) and memory hole area R MH A hook-up region R is provided on one side in the X direction relative to it. HU It also includes chip C M This is a peripheral region R located on one end in the Y direction of the four memory planes MP0 to MP3. P It is equipped with.

[0051] Note that in the illustrated example, the hookup region R HU The memory hole region R MH It is provided on one side in the X direction. However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, the hookup region R HU This is the memory hole region R MH It may also be provided on both sides in the X direction. Furthermore, the hookup region R HU It may be located at the center or near the center of the memory plane MP in the X direction.

[0052] Chip C M For example, as shown in Figure 7, the substrate layer L SBand the base layer L SB Memory cell array layer L located below MCA and memory cell array layer L MCA It comprises a contact electrode layer CH provided below, a plurality of wiring layers M0, M1 provided below the contact electrode layer CH, and a chip bonding electrode layer MB provided below the wiring layers M0, M1.

[0053] [Chip C M The base layer L SB [Structure] For example, as shown in Figure 7, the substrate layer L SB The memory cell array layer L MCA It comprises a conductive layer 100 provided on the upper surface, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back wiring layer MA.

[0054] The conductive layer 100 may contain, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may contain a metal such as tungsten (W), or it may contain a silicide such as tungsten silicide (WSi).

[0055] The conductive layer 100 functions as part of the source line SL (Figure 1). Four conductive layers 100 are provided, corresponding to the four memory planes MP0 to MP3 (Figure 6). Regions VZ, which do not include the conductive layer 100, are provided at the X and Y ends of the memory plane MP.

[0056] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0057] The back wiring layer MA includes multiple wirings ma. These multiple wirings ma may include, for example, aluminum (Al).

[0058] Some of the multiple wirings ma function as part of the source line SL (Figure 1). There are four of these wirings ma, corresponding to the four memory planes MP0 to MP3 (Figure 6). Each of these wirings ma is electrically connected to the conductive layer 100.

[0059] Furthermore, some of the multiple wirings ma are external pad electrodes P X This function is achieved by this wiring ma in the surrounding region R. P It is provided in the region VZ that does not include the conductive layer 100, and the memory cell array layer L MCA It is connected to the contact electrode CC inside. In addition, a portion of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0060] The insulating layer 102 is a passivation layer made of an insulating material such as polyimide.

[0061] [Chip C M Memory cell array layer L MCA Memory hole region R MH [Structure in] As explained with reference to Figure 6, the memory cell array layer L MCA Multiple memory blocks BLK are provided, aligned in the Y direction. As shown in Figure 7, an interblock insulating layer ST made of silicon oxide (SiO2) or the like is provided between two adjacent memory blocks BLK in the Y direction.

[0062] The memory block BLK comprises, for example, a plurality of conductive layers 110 aligned in the Z direction and a plurality of semiconductor layers 120 extending in the Z direction, as shown in Figure 7. Furthermore, as shown in Figure 10, a gate insulating film 130 is provided between each of the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0063] The conductive layer 110 has a substantially plate-like shape that extends in the X direction. The conductive layer 110 may also contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). Furthermore, the conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between a plurality of conductive layers 110 arranged in the Z direction.

[0064] Of the multiple conductive layers 110, one or more of the uppermost conductive layers 110 function as the gate electrode and source-side selection gate line SGS of the source-side selection transistor STS (Figure 1) (see Figure 7). These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0065] Furthermore, the multiple conductive layers 110 located below this function as the gate electrodes and word lines WL of the memory cell MC (Figure 1). Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0066] Furthermore, one or more conductive layers 110 located below this function as the gate electrode and drain-side selected gate line SGD of the drain-side selected transistor STD. For example, as shown in Figure 9, the width Y in the Y direction of these multiple conductive layers 110 SGD The width Y in the Y direction of the conductive layer 110, which functions as a word line WL. WL It is smaller than that. In addition, an inter-string unit insulating layer SHE made of silicon oxide (SiO2) or the like is provided between two adjacent conductive layers 110 in the Y direction.

[0067] The semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions, as shown in Figure 9, for example. Each semiconductor layer 120 functions as a channel region for multiple memory cells MC and selection transistors (STD, STS) contained in one memory string MS (Figure 1). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 made of silicon oxide or the like is provided in the central portion. The outer surface of the semiconductor layer 120 is surrounded by multiple conductive layers 110 and faces these conductive layers 110.

[0068] Furthermore, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. This impurity region is connected to the conductive layer 100 (see Figure 7). This impurity region contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0069] Furthermore, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. This impurity region is connected to the bit line BL via contact electrodes ch and Vy. This impurity region contains, for example, N-type impurities such as phosphorus (P).

[0070] The gate insulating film 130 has a substantially cylindrical shape, as shown in Figure 9, for example, and covers the outer circumferential surface of the semiconductor layer 120. The gate insulating film 130 comprises a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133, which are laminated between the semiconductor layer 120 and the conductive layer 110, as shown in Figure 10, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2), silicon nitride (SiON), etc. The charge storage film 132 includes, for example, a charge-storing film such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor layer 120, excluding the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0071] Figure 10 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0072] [Chip C M Memory cell array layer L MCA Hookup region R HU [Structure in] As shown in Figure 8, the hookup region R HU Multiple contact electrodes CC are provided in the device. Each of these contact electrodes CC extends in the Z direction and is connected to the conductive layer 110 (WL, SGD, SGS) at its upper end.

[0073] [Chip C M Memory cell array layer L MCA The surrounding region R P [Structure in] Surrounding region R P For example, as shown in Figure 7, the external pad electrode P X In response, multiple contact electrodes CC are provided. These multiple contact electrodes CC have an external pad electrode P at their upper end. X Connected.

[0074] [Chip C M [Structure of the contact electrode layer CH] Multiple contact electrodes ch included in the contact electrode layer CH are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0075] The contact electrode layer CH includes multiple contact electrodes ch as multiple wirings. These multiple contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The contact electrodes ch are provided corresponding to the multiple semiconductor layers 120 and are connected to the lower ends of the multiple semiconductor layers 120.

[0076] [Chip C M [Structure of wiring layers M0, M1] Multiple wirings included in wiring layers M0 and M1 are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0077] The wiring layer M0 includes multiple wirings m0. These multiple wirings m0 may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a laminate of tantalum nitride (TaN) and tantalum (Ta), and a laminate of metal films such as copper (Cu). Some of the multiple wirings m0 function as bit lines BL. The bit lines BL are aligned in the X direction and extend in the Y direction, for example, as shown in Figure 9.

[0078] The wiring layer M1 includes a plurality of wirings m1, as shown in Figure 7, for example. These plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Furthermore, these plurality of wirings m1 are electrically connected to wiring m0 via contact electrodes V1, as shown in Figures 7 and 8, for example.

[0079] [Structure of the chip-bonded electrode layer MB] Multiple wirings included in the chip bonding electrode layer MB are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0080] The chip-bonded electrode layer MB consists of multiple bonded electrodes P I1 (Includes adhesive pads). These multiple adhesive electrodes P I1 Examples include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and multilayer films of tantalum nitride (TaN) and tantalum (Ta). I1B and metal films such as copper (Cu) p I1M It may also contain a multilayer film, etc.

[0081] [Chip C P [Structure] Chip C P As shown in Figure 11, for example, it comprises four planes FP0' to FP3' arranged in two pairs in the X direction and two pairs in the Y direction, in the region overlapping with the four memory planes MP0 to MP3 arranged in the X direction. The central region R in the X direction of the two planes FP0', FP2' and planes FP1', FP3' arranged in the Y direction. CEN Each of these is provided with multiple word line switches WLSW and multiple selection gate line switches SGSW, SGSWP, and multiple voltage supply lines CGI are provided at both ends in the X direction. In addition, the central region R in the X direction of the four planes FP0'~FP3' CEN The region excluding the peripheral circuit region R PC A system is in place.

[0082] The peripheral circuit region R of each of the four planes FP0' to FP3' PC The central region R in the X direction CEN Multiple block decoder regions R are arranged on both sides, spaced apart in the Y direction. BD Multiple block decoder regions R are provided. BD This unit is equipped with a block decoder BLKD, as explained with reference to Figure 3.

[0083] Block decoder region R near the boundary between two planes FP0' and FP2' aligned in the Y direction. BD It is located in a position close to the Y direction. Similarly, block decoder region R is located near the boundary between two planes FP1' and FP3' aligned in the Y direction. BD It is located in a position close to the Y direction.

[0084] Furthermore, the peripheral circuit region R of each of the four planes FP0' to FP3' PC It has four column control circuit regions R aligned in the X direction. CC A is provided. Also, although not shown in the diagram, the peripheral circuit region R PC Circuits are also located in other areas inside. M The surrounding region RP (Figure 6) Opposite chip C P The region is the circuit region R C A system is in place.

[0085] Column control circuit region R CC A sense amplifier module SAM is provided. The sense amplifier module SAM detects the ON / OFF state of the memory cell MC and acquires data indicating the state of the memory cell MC. The sense amplifier module SAM comprises multiple sense amplifier units. The multiple sense amplifier units correspond to multiple bit lines BL. Each of the multiple sense amplifier units comprises a sense amplifier circuit and a latch circuit.

[0086] Circuit area R C An input / output circuit (not shown) is provided. This input / output circuit connects to an external pad electrode P via a contact electrode CC, etc., as explained with reference to Figure 7. X Connected.

[0087] Also, chip C P As shown in Figure 7, for example, the device comprises a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, D4 provided above the electrode layer GC, and a chip-bonded electrode layer DB provided above the wiring layers D0, D1, D2, D3, D4.

[0088] [Chip C P [Structure of semiconductor substrate 200] The semiconductor substrate 200 contains, for example, p-type silicon (Si) containing p-type impurities such as boron (B). The surface of the semiconductor substrate 200 is provided with, for example, an N-type well region 200N containing an N-type impurity such as phosphorus (P), a p-type well region 200P containing a p-type impurity such as boron (B), a semiconductor substrate region 200S where the N-type well region 200N and the p-type well region 200P are not provided, and an insulating region STI. A portion of the p-type well region 200P is provided in the semiconductor substrate region 200S, and a portion of the p-type well region 200P is provided in the N-type well region 200N. The N-type well region 200N, the p-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S each function as part of a plurality of transistors Tr and a plurality of capacitors that constitute a peripheral circuit PC. The insulating region STI includes, for example, silicon oxide (SiO2) and is stretched in the Z direction.

[0089] [Chip C P [Structure of the electrode layer GC] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200. Furthermore, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a contact electrode CS.

[0090] Each of the multiple electrodes gc contained in the electrode layer GC functions as a gate electrode or the like of multiple transistors Tr that constitute the peripheral circuit PC.

[0091] The contact electrode CS extends in the Z direction and is connected at its lower end to the semiconductor substrate 200 or the upper surface of electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection point between the contact electrode CS and the semiconductor substrate 200. The contact electrode CS may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0092] [Chip C P[Structure of wiring layers D0, D1, D2, D3, D4] For example, as shown in Figure 7, the multiple connections and multiple wirings included in D0, D1, D2, D3, and D4 are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0093] Each wiring layer D0, D1, and D2 includes multiple connection points d0, d1, and d2, and multiple wirings. These multiple connection points d0, d1, and d2, and the multiple wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0094] Each wiring layer D3 and D4 includes multiple connection parts d3 and d4 and multiple wirings. These multiple connection parts d3 and d4 and multiple wirings may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of metal films such as copper (Cu).

[0095] [Structure of the chip-bonded electrode layer DB] Multiple wirings included in the chip bonding electrode layer DB are, for example, in the memory cell array layer L MCA Internal components and chip C P It is electrically connected to at least one of the internal components.

[0096] The chip-bonded electrode layer DB consists of multiple bonded electrodes P I2 This includes multiple bonded electrodes P. I2 Examples include barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and multilayer films of tantalum nitride (TaN) and tantalum (Ta). I2B and metal films such as copper (Cu) p I2M It may also contain a multilayer film, etc.

[0097] In addition, the bonded electrode P I1 and bonded electrode P I2 and a metal film such as copper (Cu) p I1M ,p I2MUsing this method, the metal film p I1M and metal film p I2M The two become integrated, making it difficult to confirm their boundaries. However, the bonded electrode P may be misaligned during bonding. I1 and bonded electrode P I2 Distortion of the shape when the two are bonded together, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the misalignment (occurrence of discontinuities on the side). Also, bonded electrode P I1 and bonded electrode P I2 When formed by the damascene method, each side has a tapered shape. Therefore, the bonded electrode P I1 and bonded electrode P I2 The cross-sectional shape along the Z-direction at the point where the two are bonded together is not a straight line, but rather a non-rectangular shape. Furthermore, the bonded electrode P I1 and bonded electrode P I2 When these are bonded together, the barrier metal covers the bottom, sides, and top surfaces of each Cu component forming them. In contrast, in a typical Cu wiring layer, an insulating layer (such as SiN or SiCN) with an oxidation prevention function for Cu is provided on the top surface of the Cu, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0098] [Structure of a word line switch (WLSW)] Figure 12 is a schematic plan view showing an example configuration of a word line switch (WLSW). Note that Figure 12 corresponds to, for example, the part indicated as A in Figure 11.

[0099] Figure 12 shows two word line switches (transistors) with a common source region. Hereafter, these two word line switches (transistors) will be referred to as "transistor group TG3".

[0100] As shown in Figure 12, the transistor group TG3 includes semiconductor regions (diffusion regions) 203 extending in the Y direction. The semiconductor regions 203 are aligned in both the Y and X directions. An insulating region STI is formed around the semiconductor regions 203. Contact electrodes CS2, which function as drain terminals of word line switches WLSW, are provided at both ends of the semiconductor region 203 in the Y direction. A contact electrode CS1, which functions as a common source terminal of the two word line switches WLSW, is provided between these contact electrodes CS2. A gate insulating film 205 and a gate electrode 206 are provided between the contact electrodes CS2, which function as drain terminals, and the contact electrodes CS1, which function as source terminals, respectively.

[0101] As shown in Figure 12, the position of the midline equidistant from the negative Y-direction end of one semiconductor region 203 and the positive Y-direction end of the other semiconductor region 203 coincides with the position of the interblock insulating layer ST (Figures 7 and 9) when viewed from the Z direction. Also, the position of the center line of the semiconductor region 203 in the Y direction coincides with the position of the interblock insulating layer ST (Figures 7 and 9) when viewed from the Z direction. The spacing between the interblock insulating layers ST aligned in the Y direction is the pitch of the word line switch WLSW in the Y direction (Ypitch in Figure 12). That is, in this embodiment, the pitch of the word line switch WLSW in the Y direction is the same as the pitch of the memory block BLK in the Y direction. The fact that the pitches of the word line switch WLSW and the memory block BLK are the same in the Y direction is sometimes expressed as 1Tr / 1BLK.

[0102] Although Figure 12 shows the structure of the word line switch WLSW, the structure of the selection gate line switch SGSW may be the same as that of the word line switch WLSW.

[0103] [Chip C P [Paths of block selection lines BLKSEL and block selection lines BLKSELn] Figure 13 is a schematic enlarged view of the area shown as B in Figure 11. In Figure 13, the block decoder region R BD Figure 13 shows how the block selection lines BLKSEL and BLKSELn of the block decoder BLKD included in the diagram are electrically connected to the word line switch WLSW and the selection gate line switch SGSW via wiring layers D3 and D4. Note that Figure 13 is a schematic diagram illustrating the connection relationships between multiple block decoders BLKD and multiple word line switches WLSW, and between multiple block decoders BLKD and multiple selection gate line switches SGSW, and does not show the specific number, shape, arrangement, etc. of the configuration.

[0104] As shown in Figure 13, the central region R CEN The unit is provided with multiple word line switches (WLSW) and multiple selection gate line switches (SGSW), and the electrode layers GC (WLSW GC) of the multiple word line switches (WLSW) are provided. Block decoder region R BD The block decoder BLKD contained within and the electrode layer GC of multiple word line switches WLSW are electrically connected by block selection lines BLKSEL passing through wiring layers D3 and D4. Block decoder region R BD The block decoder BLKD and the selection gate wire switch SGSW included in the circuit are electrically connected by block selection wires BLKSEL and BLKSELn, which pass through wiring layers D3 and D4. In wiring layer D4, block selection wires BLKSEL and BLKSELn extend in the Y direction.

[0105] [Wiring pattern of block selection line BLKSEL in wiring layer D4] Figure 14 shows an example of a wiring pattern for block selection lines BLKSEL in wiring layer D4. In Figure 14, the 1st to 7th memory blocks BLK, counting from the negative side in the Y direction, are designated as memory blocks BLK(2n) to BLK(2n+6). The bundles of multiple voltage supply lines CGI (consisting of two voltage supply lines CGI in the figure) from the 1st to 6th side in the negative side in the X direction are designated as voltage supply line group CGG(1) to voltage supply line group CGG(6). In addition, the bundles of multiple block selection lines BLKSEL (consisting of seven block selection lines BLKSEL in the figure) from the 1st to 5th side in the negative side in the X direction are designated as block selection line group BLKSELG(1) to block selection line group BLKSELG(5).

[0106] As shown in Figure 14, the voltage supply line groups CGG(1) to CGG(6) are spaced apart in the X direction. The block selection line group BLKSELG(1) is located between the voltage supply line groups CGG(1) and CGG(2). The block selection line group BLKSELG(2) is located between the voltage supply line groups CGG(2) and CGG(3), the block selection line group BLKSELG(3) is located between the voltage supply line groups CGG(3) and CGG(4), the block selection line group BLKSELG(4) is located between the voltage supply line groups CGG(4) and CGG(5), and the block selection line group BLKSELG(5) is located between the voltage supply line groups CGG(5) and CGG(6).

[0107] In the block selection line group BLKSELG(1), as shown in Figure 14, the fourth block selection line BLKSEL from the negative side in the X direction is connected to the connection part 401 at a position in the Y direction corresponding to the memory block BLK(2n), and does not extend beyond this connection part 401 to the positive side in the Y direction. The connection part 401 electrically connects the block selection line BLKSEL of the D4 wiring layer to the gate electrode of the word line switch WLSW via wiring d3 in the D3 wiring layer. The connection part 401 consists of two contacts c4, but it may also consist of one contact c4.

[0108] Furthermore, in the block selection line group BLKSELG(1), the 1st to 3rd block selection lines BLKSEL from the negative side in the X direction are provided with a curved portion 402 that bends away from the voltage supply line group CGG(1) (positive side in the X direction) at a position in the Y direction corresponding to the memory block BLK(2n+1). The 1st block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 2nd block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 (changing the wiring path). The 2nd block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 3rd block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 (changing the wiring path). The 3rd block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 4th block selection line BLKSEL on the negative side in the Y direction from the connection portion 401 (changing the wiring path).

[0109] Furthermore, in the block selection line group BLKSELG(1), the third block selection line BLKSEL from the negative side in the X direction is connected to the connection part 401 at a position in the Y direction corresponding to the memory block BLK(2n+1), and does not extend beyond this connection part 401 to the positive side in the Y direction.

[0110] Furthermore, in the block selection line group BLKSELG(1), the 5th to 7th block selection lines BLKSEL from the negative side in the X direction are provided with a curved portion 402 that bends away from the voltage supply line group CGG(2) (negative side in the X direction) at a position in the Y direction corresponding to the memory block BLK(2n+2). The 5th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 2nd block selection line BLKSEL on the negative side in the Y direction from the connection portion 401 due to the curved portion 402. The 6th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 5th block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 due to the curved portion 402. The 7th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 6th block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 due to the curved portion 402.

[0111] In the block selection line group BLKSELG(2), similar to the block selection line group BLKSELG(1), the fourth block selection line BLKSEL from the negative side in the X direction is connected to the connection part 401 at a position in the Y direction corresponding to the memory block BLK(2n+2), and does not extend beyond this connection part 401 to the positive side in the Y direction.

[0112] Furthermore, in the block selection line group BLKSELG(2), the 1st to 3rd block selection lines BLKSEL from the negative side in the X direction are provided with a curved portion 402 that bends away from the voltage supply line group CGG(2) (positive side in the X direction) at a position in the Y direction corresponding to the memory block BLK(2n+3). The 1st block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 2nd block selection line BLKSEL on the negative side in the Y direction from the curved portion 402. The 2nd block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 3rd block selection line BLKSEL on the negative side in the Y direction from the curved portion 402. The 3rd block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 4th block selection line BLKSEL on the negative side in the Y direction from the connection portion 401.

[0113] Furthermore, in the block selection line group BLKSELG(2), the third block selection line BLKSEL from the negative side in the X direction is connected to the connection part 401 at a position in the Y direction corresponding to the memory block BLK(2n+3), and does not extend beyond this connection part 401 to the positive side in the Y direction.

[0114] Furthermore, in the block selection line group BLKSELG(1), the 5th to 7th block selection lines BLKSEL from the negative side in the X direction are provided with a curved portion 402 that bends away from the voltage supply line group CGG(3) (negative side in the X direction) at a position in the Y direction corresponding to the memory block BLK(2n+4). The 5th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 4th block selection line BLKSEL on the negative side in the Y direction from the connection portion 401 due to the curved portion 402. The 6th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 5th block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 due to the curved portion 402. The 7th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 6th block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 due to the curved portion 402.

[0115] In the block selection line group BLKSELG(3), similar to the block selection line groups BLKSELG(1) and (2), the fourth block selection line BLKSEL from the negative side in the X direction is connected to the connection part 401 at a position in the Y direction corresponding to the memory block BLK(2n+4), and does not extend beyond this connection part 401 to the positive side in the Y direction.

[0116] Furthermore, in the block selection line group BLKSELG(3), the 1st to 3rd block selection lines BLKSEL from the negative side in the X direction are provided with a curved portion 402 that bends away from the voltage supply line group CGG(3) (positive side in the X direction) at a position in the Y direction corresponding to the memory block BLK(2n+5). The 1st block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 2nd block selection line BLKSEL on the negative side in the Y direction from the curved portion 402. The 2nd block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 3rd block selection line BLKSEL on the negative side in the Y direction from the curved portion 402. The 3rd block selection line BLKSEL from the negative side in the X direction is positioned by the curved portion 402 in the direction of extension of the 4th block selection line BLKSEL on the negative side in the Y direction from the connection portion 401.

[0117] Furthermore, in the block selection line group BLKSELG(3), the third block selection line BLKSEL from the negative side in the X direction is connected to the connection part 401 at a position in the Y direction corresponding to the memory block BLK(2n+5), and does not extend beyond this connection part 401 to the positive side in the Y direction.

[0118] Furthermore, in the block selection line group BLKSELG(3), the 5th to 7th block selection lines BLKSEL from the negative side in the X direction are provided with a curved portion 402 that bends away from the voltage supply line group CGG(4) (negative side in the X direction) at a position in the Y direction corresponding to the memory block BLK(2n+6). The 5th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 4th block selection line BLKSEL on the negative side in the Y direction from the connection portion 401 due to the curved portion 402. The 6th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 5th block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 due to the curved portion 402. The 7th block selection line BLKSEL from the negative side in the X direction is positioned in the direction of extension of the 6th block selection line BLKSEL on the negative side in the Y direction from the curved portion 402 due to the curved portion 402.

[0119] Furthermore, the block selection line groups BLKSELG(4) to BLKSELG(5) are the same as block selection line groups BLKSELG(1) and BLKSELG(3), so their explanations are omitted. Similarly, the block selection line groups BLKSELnG(1) to BLKSELnG(5) are also the same, so their explanations are omitted.

[0120] Furthermore, the number of block selection lines BLKSEL that make up block selection line groups BLKSELG(1) to BLKSELG(5) is not limited to seven. Also, the number of voltage supply lines CGI that make up voltage supply line groups CGG(1) to CGG(6) is not limited to two; for example, there could be four.

[0121] Furthermore, the positions in the block selection line groups BLKSELG(1) to BLKSELG(5) where the connection portion 401 and the curved portion 402 are provided are not limited to the positions in the Y direction corresponding to the memory block BLK described above. Any position is acceptable as long as the total length of the block selection line BLKSEL adjacent to the voltage supply line groups CGG(1) to CGG(6) is reduced.

[0122] [Connection configuration of wiring layer D4 and wiring layer D3 of block selection line BLKSEL] Figure 15 shows an example of a wiring pattern for block selection lines BLKSEL in wiring layer D3.

[0123] Figure 15 shows the BLKSEL region R, where multiple block selection lines (BLKSELs) are provided in wiring layer D3. BLKSEL The adhesive pad region R is provided with multiple adhesive pad electrodes 301 and wiring d31. PI This is shown. Also, Figure 15 shows a hookup wiring area R where multiple hookup wires are provided. WLHU And a pass-through wiring area R where multiple pass-through wirings are provided. PERI The image also shows the interblock insulating layer ST, which indicates the boundary of the memory block BLK, and the shield wiring Shield.

[0124] Shielded wiring is hook-up wiring area R WLHU Hook-up wiring is provided in the area, and the through wiring area R PERI This is wiring that shields the pass-through wiring provided in the system. During read, write, and erase operations, high voltages such as read path voltage, write voltage, and erase voltage are applied to the hook-up wiring, whereas many of the pass-through wirings are shielded with the ground voltage V SS From the power supply voltage V CC A relatively low voltage up to a certain level is applied. Wiring adjacent to wiring to which a high voltage is applied is prone to unintentional voltage increases due to capacitive coupling. To suppress voltage fluctuations in through wiring, shielded wiring has a hook-up wiring area R WLHU and the wiring area R PERI It is installed between them and shields the hook-up wiring and the through wiring.

[0125] The block selection line BLKSEL of wiring layer D3 and the block selection line BLKSEL of wiring layer D4 are in the BLKSEL region R. BLKSEL It is connected via contact c4 of connection region Rc4 located in the BLKSEL region RBLKSEL Hook-up wiring area R WLHU It is provided in the BLKSEL region R where the bonding pad electrode 301 is not provided. In other words, the contact c4 of the connection region Rc4 is provided in the BLKSEL region R BLKSEL In this area, a pass-through wiring region R is provided where power supplies and the like are installed. PERI Avoid hookup wiring area R WLHU It will be established in [location].

[0126] [effect] As explained with reference to Figures 11 and 13, the multiple block decoders BLKD are located in the central region R CEN Central region R on both sides in the X direction CEN (The word line switch WLSW and the selection gate line switch SGSW are not arranged along the circuit (extending in the Y direction), and the peripheral circuit area R PC Central region R CEN They are spaced apart on both sides in the X direction. This allows for the block decoder region R BD The position in the Y direction is in the column control circuit region R CC This makes it possible to reduce the chip size in the X direction. However, the block selection line BLKSEL and block selection line BLKSELn will pass between the voltage supply line CGI, and the voltage supply line CGI and block selection line BLKSEL, or the voltage supply line CGI and block selection line BLKSELn will be adjacent to each other. Since high voltage is applied to both the voltage supply line CGI and the block selection line BLKSEL, if the distance (space) between the voltage supply line CGI and block selection line BLKSEL, or the voltage supply line CGI and block selection line BLKSELn, is small, or if the voltage supply line CGI and block selection line BLKSEL, or the voltage supply line CGI and block selection line BLKSELn, face each other over a long distance, then the chip C will be affected by TDDB (Duration-Dependent Dielectric Breakdown withstand voltage) failure due to the high voltage difference, wiring short circuits due to dust during manufacturing, etc. P Yield may be reduced. Also, when high voltage is applied to the voltage supply line CGI, the block selection line BLKSEL and block selection line BLKSELn are affected by noise, and chip C P This can sometimes lead to undesirable behavior.

[0127] On the other hand, if the block selection line BLKSEL and block selection line BLKSELn extend beyond the area where the word line switch WLSW and the selection gate line switch SGSW are located when viewed from the Z direction, the size of the chip Cp will increase. For this reason, it may be difficult to leave a space equivalent to one wire of the block selection line BLKSEL in the area adjacent to the voltage supply line CGI.

[0128] Therefore, in this embodiment, as explained with reference to Figure 14, a portion of the multiple block selection lines BLKSEL that pass between the voltage supply line group CGG, which are spaced apart in the X direction in the D4 wiring layer, are connected to the D3 wiring layer. The space freed up by this is used to change the wiring path of the remaining block selection lines BLKSEL so that it is moved away from the voltage supply line CGI of the voltage supply line group CGG. As a result, even though many block selection lines BLKSEL can be provided between the voltage supply line group CGG, at least the length of one block selection line BLKSEL can be secured between adjacent block selection lines BLKSEL and the voltage supply line CGI in the voltage supply line group CGG, and furthermore, the total length of block selection lines BLKSEL that are close to the voltage supply line CGI can be shortened. As a result, the possibility of short-circuiting the voltage supply line CGI and the block selection lines BLKSEL due to the effects of dust during manufacturing can be suppressed, so chip C P This can suppress a decrease in yield. Furthermore, by securing space between the adjacent block selection line BLKSEL and the voltage supply line CGI in the voltage supply line group CGG, even if a high voltage is applied to the voltage supply line CGI, the impact of noise on the block selection line BLKSEL and block selection line BLKSELn can be suppressed, thus improving chip C P This can prevent the system from performing undesirable actions.

[0129] [Second Embodiment] [Wiring patterns for block selection lines such as BLKSEL in wiring layer D4] Figure 16 shows an example of a wiring pattern including block selection line BLKSEL in wiring layer D4 according to the second embodiment. Figure 16 shows the block selection line BLKSEL, voltage supply line CGI, and ground voltage V in wiring layer D4 according to the second embodiment. SS and power supply voltage V CC This diagram is intended to illustrate a schematic wiring pattern and does not show the specific number, shape, or arrangement of components.

[0130] Of the multiple memory blocks BLK shown in Figure 16, the 1st to 4th memory blocks BLK counting from the negative side in the Y direction are designated as memory blocks BLK(n) to BLK(o). The bundles of multiple voltage supply lines CGI (consisting of two voltage supply lines CGI in the figure) counting from the negative side in the X direction are designated as voltage supply line groups CGG(n) to CGG(n+2) and CGG(l) to CGG(l+2). In addition, the bundles of multiple block selection lines BLKSEL (consisting of seven block selection lines BLKSEL in the figure) counting from the negative side in the X direction are designated as block selection line groups BLKSELG(n) to (n+2) and (l) to (l+2).

[0131] As shown in Figure 16, the voltage supply line group CGG(n) to the voltage supply line group CGG(l+2) are spaced apart in the X direction. The block selection line group BLKSELG(n) is provided between the voltage supply line group CGG(n) and the voltage supply line group CGG(n+1). The wiring paths of the multiple block selection lines BLKSEL of the block selection line group BLKSELG(n) are changed in the direction away from the voltage supply line group CGG(n) and the voltage supply line group CGG(n+1) (positive and negative sides in the X direction) by curved or connected parts (not shown). As a result, in the block selection line group BLKSELG(n), a space equal to the wiring width of one block selection line BLKSEL is freed up from the voltage supply line groups CGG(n) and CGG(n+1) at the Y-direction position corresponding to memory block BLK(m), a space equal to the wiring width of two block selection lines BLKSEL is freed up from the voltage supply line groups CGG(n) and CGG(n+1) at the Y-direction position corresponding to memory block BLK(l), and a space equal to the wiring width of three block selection lines BLKSEL is freed up from the voltage supply line groups CGG(n) and CGG(n+1) at the Y-direction position corresponding to memory block BLK(o).

[0132] Furthermore, in the block selection line group BLKSELG(n), in the space equal to the wiring width of the two block selection lines BLKSEL that are empty at the Y-direction position corresponding to memory block BLK(l), the space adjacent to the 3rd to 5th block selection lines BLKSEL (the space in the extension direction of the 2nd and 6th block selection lines BLKSEL) is used, for example, for the ground voltage V SS A power line 501 is provided. This allows noise to be blocked between the voltage supply line group CGG(n) and the block selection line group BLKSELG(n), and between the voltage supply line group CGG(n+1) and the block selection line group BLKSELG(n). In addition, in the block selection line group BLKSELG(n), of the space equal to the wiring width of the three block selection lines BLKSEL that are empty at the Y-direction position corresponding to the memory block BLK(o), the space of two wirings adjacent to the fourth block selection line BLKSEL (the space in the extension direction of the second, third, fifth, and sixth block selection lines BLKSEL) is used, for example, for the ground voltage V SSA power line 501 is provided. This allows noise to be blocked between the voltage supply line group CGG(n) and the block selection line group BLKSELG(n), and between the voltage supply line group CGG(n+1) and the block selection line group BLKSELG(n).

[0133] The block selection line group BLKSELG(n+1) is located between the voltage supply line group CGG(n+1) and the voltage supply line group CGG(n+2). Multiple block selection lines BLKSEL of the block selection line group BLKSELG(n+1) have their wiring paths changed in the direction away from the voltage supply line group CGG(n+1) and the voltage supply line group CGG(n+2) (positive and negative sides in the X direction) by curved or connected sections not shown. As a result, in block selection line group BLKSELG(n+1), a space equal to the width of one block selection line BLKSEL is freed up from voltage supply line group CGG(n+1) and voltage supply line group CGG(n+2) at the Y-direction position corresponding to memory block BLK(m), a space equal to the width of two block selection lines BLKSEL is freed up from voltage supply line group CGG(n+1) and voltage supply line group CGG(n+2) at the Y-direction position corresponding to memory block BLK(l), and a space equal to the width of three block selection lines BLKSEL is freed up from voltage supply line group CGG(n+1) and voltage supply line group CGG(n+2) at the Y-direction position corresponding to memory block BLK(o).

[0134] Furthermore, in the block selection line group BLKSELG(n+1), in the space equal to the wiring width of the two block selection lines BLKSEL that are empty at the Y-direction position corresponding to memory block BLK(l), the space adjacent to the 3rd to 5th block selection lines BLKSEL is used, for example, for the ground voltage V SSA power line 501 is provided. This allows noise to be blocked between the voltage supply line group CGG(n+1) and the block selection line group BLKSELG(n+1), and between the voltage supply line group CGG(n+2) and the block selection line group BLKSELG(n+1). In addition, in the block selection line group BLKSELG(n+1), of the space equal to the wiring width of the three block selection lines BLKSEL that are empty at the Y-direction position corresponding to the memory block BLK(o), the space of the two wirings adjacent to the fourth block selection line BLKSEL is used, for example, for the ground voltage V SS A power line 501 is provided. This allows noise to be blocked between the voltage supply line group CGG(n+1) and the block selection line group BLKSELG(n+1), and between the voltage supply line group CGG(n+2) and the block selection line group BLKSELG(n+1).

[0135] The block selection line group BLKSELnG(l) is located between the voltage supply line group CGG(l) and the voltage supply line group CGG(l+1). Multiple block selection lines BLKSELn of the block selection line group BLKSELnG(l) have their wiring paths changed in the direction away from the voltage supply line group CGG(l) and the voltage supply line group CGG(l+1) (positive and negative sides in the X direction) by curved sections or connection sections not shown. As a result, in the block selection line group BLKSELnG(l), a space equal to the width of one block selection line BLKSELn is created between the voltage supply line group CGG(l) and voltage supply line group CGG(l+1) at the Y-direction position corresponding to memory block BLK(m), a space equal to the width of two block selection lines BLKSELn is created between the voltage supply line group CGG(l) and voltage supply line group CGG(l+1) at the Y-direction position corresponding to memory block BLK(l), and a space equal to the width of three block selection lines BLKSELn is created between the voltage supply line group CGG(l) and voltage supply line group CGG(l+1) at the Y-direction position corresponding to memory block BLK(o).

[0136] Furthermore, in the block selection line group BLKSELnG(l), a power supply line 502 with a voltage of Vdd is provided in the space adjacent to the 3rd to 5th block selection lines BLKSELn (the space in the extension direction of the 2nd and 6th block selection lines BLKSELn), which is the width of the wiring of the two block selection lines BLKSELn that are available at the Y-direction position corresponding to the memory block BLK(l). The voltage Vdd is the power supply voltage used by the block decoder BLKD.

[0137] This allows noise to be blocked between the voltage supply line group CGG(l) and the block selection line group BLKSELnG(l), and between the voltage supply line group CGG(l+1) and the block selection line group BLKSELnG(l). In addition, in the block selection line group BLKSELnG(l), of the space equal to the wiring width of the three block selection lines BLKSELn that are empty at the Y-direction position corresponding to the memory block BLK(o), a power supply line 502 with voltage Vdd is provided in the space of one wiring adjacent to the fourth block selection line BLKSELn (the space in the extension direction of the third and fifth block selection lines BLKSELn), and a power supply line 501 with ground voltage VSS is provided in the space of one wiring adjacent to the power supply line 502 (the space in the extension direction of the second and sixth block selection lines BLKSELn). This allows noise to be blocked between the voltage supply line group CGG(l) and the block selection line group BLKSELnG(l), and between the voltage supply line group CGG(l+1) and the block selection line group BLKSELnG(l).

[0138] Furthermore, if a short circuit occurs between power line 502 and block selection line group BLKSELnG(l), the drain-side selection gate line SGD and source-side selection gate line SGS in memory block BLK(l) will always have a ground voltage V SSThis results in a state where a current is applied. As a result, in the memory block BLK(l), the drain-side selection transistor STD and the source-side selection transistor STS are always turned off. In this case, even if the memory block BLK(l) cannot be operated, it is possible to suppress the possibility that, for example, the memory cell MC in the memory block BLK(l) may be electrically connected to the memory cell MC in other memory blocks. In other words, even if a short-circuit failure occurs between the power line 502 and the block selection line group BLKSELnG(l), the failure can be limited to only the memory block BLK(l) or only the memory block BLK(o).

[0139] The block selection line group BLKSELnG(l+1) is located between the voltage supply line group CGG(l+1) and the voltage supply line group CGG(l+2). Multiple block selection lines BLKSELn of the block selection line group BLKSELnG(l+1) have their wiring paths changed in the direction away from the voltage supply line group CGG(l+1) and the voltage supply line group CGG(l+2) (positive and negative sides in the X direction) by curved or connecting parts not shown. As a result, in block selection line group BLKSELnG(l+1), a space equal to the width of one block selection line BLKSELn is created between voltage supply line group CGG(l+1) and voltage supply line group CGG(l+2) at the Y-direction position corresponding to memory block BLK(m), a space equal to the width of two block selection lines BLKSELn is created between voltage supply line group CGG(l+1) and voltage supply line group CGG(l+2) at the Y-direction position corresponding to memory block BLK(l), and a space equal to the width of three block selection lines BLKSELn is created between voltage supply line group CGG(l+1) and voltage supply line group CGG(l+2) at the Y-direction position corresponding to memory block BLK(o).

[0140] Furthermore, in the block selection line group BLKSELnG(l+1), a power supply line 502 with a voltage of Vdd is provided in the space adjacent to the 3rd to 5th block selection lines BLKSELn (the space in the extension direction of the 2nd and 6th block selection lines BLKSELn), which is the width of the wiring of the two block selection lines BLKSELn that are available at the Y-direction position corresponding to the memory block BLK(l). This makes it possible to block noise between the voltage supply line group CGG(l+1) and the block selection line group BLKSELnG(l+1), and between the voltage supply line group CGG(l+2) and the block selection line group BLKSELnG(l+1). Furthermore, in the block selection line group BLKSELnG(l+1), a power supply line 502 with voltage Vdd is provided in the space of one wiring width adjacent to the fourth block selection line BLKSELn (the space in the extension direction of the third and fifth block selection lines BLKSELn) at the Y-direction position corresponding to the memory block BLK(o), and a power supply line 501 with ground voltage VSS is provided in the space of one wiring width adjacent to the power supply line 502 (the space in the extension direction of the second and sixth block selection lines BLKSELn). This makes it possible to block noise between the voltage supply line group CGG(l+1) and the block selection line group BLKSELnG(l+1), and between the voltage supply line group CGG(l+2) and the block selection line group BLKSELnG(l+1). Furthermore, even if a short circuit occurs between the power line 502 and the block selection line group BLKSELnG(l+1), the failure can be limited to only one memory block BLK, such as only memory block BLK(l) or only memory block BLK(o).

[0141] With this configuration, in the wiring pattern of the second embodiment, similar to the wiring pattern of the first embodiment, the wiring path of block selection lines BLKSEL or BLKSELn adjacent to the voltage supply line CGI is changed so that they are moved away from the voltage supply line CGI, and a space equivalent to one wiring is secured next to the voltage supply line CGI. Furthermore, in the second embodiment, if it is possible to provide space equivalent to two or more wirings next to the voltage supply line CGI, the power line can be placed in the wiring space that is not adjacent to the voltage supply line CGI, thereby reducing noise between it and the block selection line BLKSEL or BLKSELn.

[0142] In the configuration shown in Figure 16, the ground voltage V is applied to the power line 501. SS Instead, a negative voltage V BB A short circuit may be supplied. In this case, for example, if a short circuit occurs between the power line 501 and the block selection line group BLKSELG(n), the drain-side selection gate line SGD and the source-side selection gate line SGS in the memory block BLK(l) will always be disconnected from the voltage supply line CGI. This prevents the drain-side selection transistor STD and the source-side selection transistor STS from unintentionally turning on in the memory block BLK(l). In this case, even if the memory block BLK(l) becomes inoperable, it is possible to suppress the possibility that, for example, the memory cell MC in the memory block BLK(l) will be electrically connected to the memory cell MC in other memory blocks. That is, even if a short circuit occurs between the power line 501 and the block selection line group BLKSELG(n), the failure can be limited to only the memory block BLK(l) or only the memory block BLK(o).

[0143] [Third Embodiment] Figure 17 shows the chip C according to the third embodiment. PThis is a schematic plan view showing some configuration examples. Note that Figure 17 corresponds to a portion of, for example, plane FP1' among the four planes FP0' to FP3' shown in Figure 11. In Figure 17, components identical to those in Figure 11 are denoted by the same reference numerals, and redundant explanations are omitted.

[0144] In the configuration of the first embodiment, the block decoder region R is provided with the block decoder BLKD. BD The central region R CEN Three were provided on both sides in the X direction, spaced apart in the Y direction (Figure 11). In contrast, in the configuration of the third embodiment, the block decoder region R BD This is the central region R CEN On both sides in the X direction, and in the column control circuit region R CC They are provided spaced apart on parts of both sides in the Y direction. Furthermore, in the configuration of the third embodiment, the block decoder region R BD This is the column control circuit region R CC In the positive and negative Y directions, the central region R CEN It is provided extending in the Y direction, along both sides in the X direction.

[0145] Thus, the block decoder region R BD In the configuration of the third embodiment, where the arrangement differs from that of the first embodiment, the portion of E in Figure 17 (central region R) CEN For areas including the above, a wiring pattern can be adopted in which the wiring path of block selection line BLKSEL or block selection line BLKSELn adjacent to the voltage supply line CGI is changed to move away from the voltage supply line CGI, thereby securing space for one wiring next to the voltage supply line CGI.

[0146] Note that the central region R other than part E in Figure 17 CEN For regions including the above, it is not necessary to adopt the wiring pattern described in the first embodiment. However, even in such cases, it is preferable to secure space for one wiring next to the voltage supply line CGI.

[0147] Furthermore, the block decoder region R can employ the wiring pattern described in the first embodiment.BD Configurations in which the arrangement differs from that of the first embodiment are not limited to those described in the third embodiment.

[0148] [Fourth Embodiment] Figure 18 shows the chip C according to the fourth embodiment. M and chip C P This is a diagram illustrating some configuration examples. In the example in Figure 18, chip C M The memory plane MP0' shown as part of the diagram corresponds, for example, to the memory plane MP0 in Figure 6. P The plane MP0'' shown as part of the diagram corresponds to the region that overlaps with, for example, the memory plane MP0 in Figure 6. Figure 19 shows an example of the wiring pattern of the block selection line BLKSEL of the wiring layer D4 according to the fourth embodiment. In Figures 18 and 19, the same reference numerals are used for components identical to those in Figures 11 and 14, etc., and redundant explanations are omitted.

[0149] In memory plane MP0', as shown in Figure 18, the physical plane (memory block BLK) is divided into two logical planes of 8KB each, and a pair of blocks is used for 16KB of logical operation. In a pair of blocks, one memory block BLK on the positive Y side from the center (upper side in the figure) and one memory block BLK on the negative Y side from the center (lower side in the figure) (referred to as the upper and lower memory block BLKs) are selected simultaneously.

[0150] In plane MP0'', as shown in Figure 18, the block decoder region R BD This is on one side in the X direction of the region where the word line switch WLSW and the selection gate line switch SGSW are provided, and in the column control circuit region R CC They are provided spaced apart on parts of both sides in the Y direction.

[0151] Furthermore, along one side of the X direction of the area where the word line switch WLSW and the selection gate line switch SGSW are located, there is a block decoder area R. BDIt is also possible to provide a block decoder region R on the negative side (left side) of the X direction, counting from the positive side in the Y direction, from the 1st to the 3rd block decoder region in the X direction. BD The block decoder region R BD (L1) ~ Block Decoder Region R BD (L3) is assumed to be the same. Similarly, in Figure 18, the 1st to 3rd block decoder regions on the positive X side (right side), counting from the positive Y side, are R BD The block decoder region R BD (R1) ~ Block Decoder Region R BD (R3)

[0152] These block decoder regions R BD The block decoder BLKD provided there can simultaneously drive the upper and lower memory blocks BLK (8kb) of the memory plane MP0'. Specifically, the block decoder region R BD Block decoder BLKD and block decoder region R are located in (L1). BD The block decoder BLKD located in (L3) operates simultaneously, and the block decoder region R BD Block decoder BLKD and block decoder region R are located in (R1). BD The block decoder BLKD located in (R3) operates simultaneously to drive the upper and lower memory blocks BLK (8kb) at the same time. Block decoder region R BD The block decoder BLKD located in (L2), or the block decoder region R BD The block decoder BLKD located at (R2) simultaneously drives the upper and lower memory blocks BLK (8kb) near the center. This configuration allows for a reduction in the number of block decoders BLKD required.

[0153] Furthermore, when using such a drive method, for example, as shown in Figure 19, the block decoder region R BDThe block decoder BLKD located in (R2) electrically connects the block selection line BLKSEL to the memory blocks BLKa located on the positive and negative sides of the Y direction by branching it into the block selection line BLKSEL(a1) on the positive side of the Y direction and the block selection line BLKSEL(a2) on the negative side of the Y direction. This allows the memory blocks BLKa located on the positive and negative sides of the Y direction to be driven simultaneously. Similarly, the block decoder region R BD The block decoder BLKD located at (R2) electrically connects the block selection line BLKSEL to the memory blocks BLKb located on the positive and negative sides of the Y direction by branching it into the block selection line BLKSEL(b1) on the positive side of the Y direction and the block selection line BLKSEL(b2) on the negative side of the Y direction. This allows the memory blocks BLKb located on the positive and negative sides of the Y direction to be driven simultaneously.

[0154] Thus, in the configuration of the fourth embodiment, even if the block selection line BLKSEL is branched, for example, into a block selection line BLKSEL(b1) on the positive side of the Y direction and a block selection line BLKSEL(b2) on the negative side of the Y direction, the wiring pattern of the block selection line BLKSEL in the wiring layer D4 according to the first embodiment, i.e., the wiring path of the block selection line BLKSEL or block selection line BLKSELn that is close to the voltage supply line CGI, can be changed to move away from the voltage supply line CGI, and a wiring pattern can be adopted that secures space for one wiring next to the voltage supply line CGI.

[0155] [Other embodiments] The semiconductor memory devices according to the first to fourth embodiments have been described above. However, the configurations described above are merely examples, and the specific configurations can be adjusted as appropriate.

[0156] Figure 20 is a schematic diagram showing the positional relationship between the word line switch WLSW and the memory block BLK according to the first embodiment. Figures 21 and 22 are schematic diagrams showing the positional relationship between the word line switch WLSW and the memory block BLK according to other embodiments. In Figures 20 to 22, dotted lines indicating the boundaries of the memory block BLK are shown to explain the correspondence between the word line switch WLSW and the memory block BLK. In Figures 20 to 22, the first and second memory block BLKs counting from the negative side in the Y direction are designated as memory block BLK(1) and BLK(2). The first and second voltage supply lines CGIs counting from the negative side in the X direction are designated as CGI(1) and CGI(2).

[0157] As shown in Figure 20, for example, in the first embodiment, the voltage supply line group CGG consists of two lines, CGI(1) and CGI(2). Figure 20 shows two word line switches WLSW(1L) and WLSW(1R) located in the Y direction corresponding to memory block BLK(1). Also, Figure 20 shows two word line switches WLSW(2L) and WLSW(2R) located in the Y direction corresponding to memory block BLK(2).

[0158] Furthermore, the source electrodes of each word line switch WLSW are electrically connected to one voltage supply line CGI. Specifically, at the Y-direction position corresponding to memory block BLK(1), word line switch WLSW(1L) and CGI(1) are electrically connected, and word line switch WLSW(1R) and CGI(2) are electrically connected. Also, at the Y-direction position corresponding to memory block BLK(2), word line switch WLSW(2L) and CGI(1) are electrically connected, and word line switch WLSW(2R) and CGI(2) are electrically connected. When the voltage supply line group CGG is composed of two voltage supply lines CGI in this way, the wiring layout becomes easier. However, if, for example, the voltage supply line group CGG is composed of one voltage supply line CGI, the number of adjacent locations between the block selection line BLKSEL and the voltage supply line CGI increases.

[0159] As shown in FIG. 21, the voltage supply line group CGG may be composed of four voltage supply lines CGI(1), CGI(2), CGI(3), and CGI(4).

[0160] Even in this case, the source electrodes of the word line switches WLSW are each electrically connected to one voltage supply line CGI. Specifically, at the position in the Y direction corresponding to the memory block BLK(1), the word line switch WLSW(1L) and CGI(1) may be electrically connected, and the word line switch WLSW(1R) and CGI(4) may be electrically connected. Also, at the position in the Y direction corresponding to the memory block BLK(2), the word line switch WLSW(2L) and CGI(2) may be electrically connected, and the word line switch WLSW(2R) and CGI(3) may be electrically connected.

[0161] In the examples shown in FIGS. 20 and 21, the pitch of the word line switches WLSW in the Y direction is the same as the pitch of the memory blocks BLK in the Y direction, so it is 1Tr / 1BLK. On the other hand, in the example shown in FIG. 22, since three times the pitch of the word line switches WLSW in the Y direction is the same as twice the pitch of the memory blocks BLK in the Y direction, it becomes 3Tr / 2BLK.

[0162] As shown in FIG. 22, the voltage supply line group CGG may be composed of four voltage supply lines CGI(1), CGI(2), CGI(3), and CGI(4) and may be 3Tr / 2BL.

[0163] In this case, at the position in the Y direction corresponding to the memory block BLK(1), the word line switches WLSW(1L) and the word line switch WLSW(2L) may be electrically connected to CGI(1), and the word line switches WLSW(1R) and the word line switch WLSW(2R) may be electrically connected to CGI(4). Also, at the position in the Y direction corresponding to the memory block BLK(2), the word line switch WLSW(3L) may be electrically connected to CGI(2), and the word line switch WLSW(3R) may be electrically connected to CGI(3).

[0164] In the above embodiments, an example of application to a NAND flash memory has been described. However, the technology described in this specification is applicable to configurations other than NAND flash memories, such as, for example, three-dimensional NOR flash memories. Further, the technology described in this specification is applicable to configurations other than flash memories, such as, for example, three-dimensional DRAMs.

[0165] [Others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0166] 110... Conductive layer, 120... Semiconductor layer (semiconductor pillar), 200, 500... Semiconductor substrate, C M … Chip (first chip), C P … Chip (second chip), BL... Bit line, WL... Word line, SG... Select gate line, CC... Contact electrode, CGI... Wiring (voltage supply wiring), MC... Memory cell, M0, M1, D0, D1, D2, D3, D4, D100, D101, D102, D103... Wiring layer, MB, DB... Chip bonding electrode layer, WLSW... Word line switch (transistor), SGSW... Select gate line switch (transistor), P I1 , P I2 … Bonding electrode, R MH , R MH2 … Memory hole region (memory region)

Claims

1. A first chip comprising a plurality of memory blocks arranged in a first direction and extending in a second direction intersecting the first direction, A second chip bonded to the first chip via a bonding electrode and Equipped with, The aforementioned multiple memory blocks are, Multiple word-wire conductive layers stacked in the stacking direction, A semiconductor column extending in the lamination direction and facing the plurality of word line conductive layers, A charge storage film is provided between the plurality of word wire conductive layers and the semiconductor column. Equipped with, The second chip is Semiconductor substrate and The semiconductor substrate is provided with a plurality of transistor groups, each including a plurality of transistors arranged in a first direction and a plurality of transistors arranged in a second direction, corresponding to the plurality of memory blocks. A block decoder is provided on the semiconductor substrate and decodes a block address to select one of the plurality of memory blocks, A first wiring layer is provided between the semiconductor substrate and the first chip, A second wiring layer provided between the first wiring layer and the first chip Equipped with, The aforementioned second wiring layer is The system comprises a plurality of word line voltage supply lines arranged alternately in the second direction, and a plurality of block selection lines, Each of the aforementioned groups of word line voltage supply lines comprises a plurality of word line voltage supply lines extending in the first direction and aligned in the second direction. Each of the plurality of word line voltage supply lines is electrically connected in common to a corresponding word line conductive layer included in each of the plurality of memory blocks via a corresponding transistor included in each of the plurality of transistor groups. Each of the aforementioned group of block selection lines comprises a plurality of block selection lines extending in the first direction and aligned in the second direction. Each of the aforementioned block selection lines is electrically connected in common to the gate electrodes of n transistors included in one of the corresponding groups of transistors. Each of the aforementioned group of block selection lines includes a first block selection line and a second block selection line. The first block selection line is the first block selection line among the plurality of block selection lines, counting from one side in the second direction, and has a first curved portion that bends in a direction away from the adjacent word line conductive layer in the second direction. The second block selection line includes a first connection portion that electrically connects to the first wiring layer at its end in the first direction, A semiconductor memory device in which the positions of the first curved portion in the first direction are different in each of the multiple word line voltage supply line groups and the multiple block selection line groups that are arranged alternately.

2. In each of the aforementioned group of block selection lines, the position of the first curved portion in the first direction is such that, with reference to the position of the first connection portion in the first direction, there is no second block selection line. The semiconductor memory device according to claim 1.

3. Each of the aforementioned group of block selection lines includes a third block selection line and a fourth block selection line, The third block selection line is the first block selection line from the other side in the second direction among the plurality of block selection lines, and has a second curved portion that bends in a direction away from the adjacent word line conductive layer in the second direction. The fourth block selection line is electrically connected to the first wiring layer at its end in the first direction and includes a second connection portion that is different in position from the first connection portion in the first direction. The positions of the first curved portion and the second curved portion in the first direction are different in each of the multiple word line voltage supply line groups and the multiple block selection line groups that are arranged alternately. The semiconductor memory device according to claim 1.

4. The first connection portion is electrically connected to the first wiring layer at its end in the first direction via two contacts. The semiconductor memory device according to claim 1.

5. The first connection portion is electrically connected to the first position of the first wiring layer. The first position is located in a position that does not overlap with the bonded electrode when viewed from the stacking direction. The semiconductor memory device according to claim 1.

6. The first position is located in the hook-up wiring area. The semiconductor memory device according to claim 5.

7. Each of the aforementioned group of block selection lines includes a third block selection line. The third block selection line is electrically connected to the first wiring layer at its end in the first direction and includes a second connection portion that is different in position from the first connection portion in the first direction. The first block selection line further includes a second curved portion that bends in a direction away from the adjacent word line conductive layer in the second direction, A power supply is located in a region adjacent to the first block selection line that extends in the first direction after bending at the second curved portion, in a portion of the region where there is no first block selection line in the first direction after bending at the first curved portion. The semiconductor memory device according to claim 1.

8. Each of the aforementioned group of block selection lines includes a fourth block selection line, a fifth block selection line, and a sixth block selection line. The fourth block selection line is the first block selection line from the other side in the second direction among the plurality of block selection lines, and comprises a third curved portion that bends in a direction away from the adjacent word line conductive layer in the second direction, and a fourth curved portion that bends in a direction further away from the adjacent word line conductive layer in the second direction. The fifth block selection line is electrically connected to the first wiring layer at its end in the first direction and includes a third connection portion that is different in position from the first connection portion in the first direction. The sixth block selection line is electrically connected to the first wiring layer at its end in the first direction and includes a fourth connection portion that is different in position from the first connection portion in the first direction. A power supply is located in a region adjacent to the fourth block selection line that extends in the first direction after bending at the fourth curved portion, and in a portion of the region where the fourth block selection line does not exist in the first direction after bending at the third curved portion. The semiconductor memory device according to claim 7.

9. The aforementioned multiple word line voltage supply lines consist of two lines. The semiconductor memory device according to claim 1.

10. The aforementioned multiple word line voltage supply lines consist of four lines. The semiconductor memory device according to claim 1.

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