Semiconductor memory

Abstract

To provide a semiconductor memory device that enables high integration. [Solution] The semiconductor memory device comprises a plurality of semiconductor layers stacked in a first direction and aligned in a second and third direction, a plurality of via connections electrically connected to the plurality of semiconductor layers stacked in the first direction, a plurality of memory sections electrically connected to the plurality of semiconductor layers, a plurality of gate electrodes facing the plurality of semiconductor layers, and a plurality of wiring members positioned between two adjacent gate electrodes in the third direction. The plurality of gate electrodes include a plurality of first gate electrodes provided at a first position in the first direction and aligned in the third direction. The plurality of wiring members include a plurality of first wiring members provided at a first position in the first direction and aligned in the third direction. The plurality of first wiring members are electrically connected to each other via the plurality of first gate electrodes.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device.

Background Art

[0002] With the increasing integration of semiconductor memory devices, research on the three-dimensionalization of semiconductor memory devices has been underway.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device capable of high integration.

Means for Solving the Problems

[0005] A semiconductor memory device according to one embodiment comprises: a plurality of semiconductor layers stacked in a first direction and aligned in a second direction intersecting the first direction, and in a third direction intersecting the first and second directions; a plurality of via connections aligned in the second and third directions, extending in the first direction, and electrically connected to the plurality of semiconductor layers stacked in the first direction; a plurality of memory sections stacked in the first direction, aligned in the second and third directions, and electrically connected to the plurality of semiconductor layers; a plurality of gate electrodes stacked in the first direction, aligned in the second and third directions, and facing the plurality of semiconductor layers; and a plurality of wiring members stacked in the first direction, aligned in the second and third directions, and positioned between two adjacent gate electrodes in the third direction. The plurality of gate electrodes include a plurality of first gate electrodes provided at a first position in the first direction and aligned in the third direction. The plurality of wiring members include a plurality of first wiring members provided at a first position in the first direction and aligned in the third direction. The plurality of first wiring members are electrically connected to each other via the plurality of first gate electrodes. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic perspective view showing a part of the configuration of the semiconductor memory device. [Figure 3] This is a schematic perspective view showing a part of the configuration of the semiconductor memory device. [Figure 4] This is a schematic XY cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 5] This is a schematic XY cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 6] This is a schematic XZ cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 7] This is a schematic XY cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 8] This is a schematic XZ cross-sectional view showing a portion of the configuration of the memory layer ML. [Figure 9]It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor memory device according to the first embodiment. [Figure 10] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 11] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 12] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 13] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 14] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 15] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 16] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 17] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 18] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 19] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 20] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 21] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 22] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 23] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 24] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 25] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 26] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 27] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 28] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 29] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 30] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 31] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 32] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 33] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 34] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 35] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 36] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 37] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 38] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 39] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 40] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 41] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 42] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 43] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 44] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 45] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 46]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 47] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 48] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 49] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 50] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 51] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 52] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 53] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 54] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 55] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 56] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 57] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 58] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 59] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 60] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 61] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 62] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 63] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 64] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 65] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 66] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 67] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 68] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 69] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 70] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 71] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 72] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. [Figure 73] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. [Figure 74] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 75] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 76] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 77] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 78] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 79] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the fifth embodiment. [Figure 80] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 81]This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 82] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 83] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 84] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 85] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 86] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 87] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 88] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 89] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 90] This is a schematic cross-sectional view illustrating the manufacturing method. [Figure 91] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. [Figure 92] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the seventh embodiment. [Figure 93] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the seventh embodiment. [Figure 94] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the eighth embodiment. [Figure 95] This is a schematic XZ cross-sectional view showing a part of the configuration of a semiconductor memory device according to the eighth embodiment. [Figure 96] This is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the ninth embodiment. [Figure 97] This is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the ninth embodiment. [Figure 98]This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction intersecting a predetermined surface may be referred to as the first direction. The direction intersecting the first direction along this surface may be referred to as the second direction, and the direction intersecting the second direction along this surface may be referred to as the third direction. The first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0015] Furthermore, in this specification, when we refer to the "center position" of a certain configuration, it may mean, for example, the center of the circumscribed circle of the configuration, or it may mean the centroid of the configuration on the image.

[0016] [First Embodiment] [Circuit Configuration] Figure 1 is a schematic circuit diagram showing the configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML, a plurality of bit lines BL connected to these plurality of memory layers ML, and plate lines PL connected to the plurality of memory layers ML.

[0017] Each memory layer ML comprises multiple word lines WL and multiple memory cells MC connected to these multiple word lines WL. Each memory cell MC comprises a transistor TrC and a capacitor CpC. One electrode of transistor TrC is connected to the bit line BL. The other electrode of transistor TrC is connected to the capacitor CpC. Note that one and the other electrode of transistor TrC function as a source electrode or a drain electrode depending on the voltage supplied to transistor TrC. The gate electrode of transistor TrC is connected to one of the word lines WL. One electrode of capacitor CpC is connected to the other electrode of transistor TrC. The other electrode of capacitor CpC is connected to the plate line PL.

[0018] Furthermore, each bit line BL is connected to multiple memory cells MC corresponding to multiple memory layers ML.

[0019] [structure] Figures 2 and 3 are schematic perspective views showing a part of the configuration of a semiconductor memory device according to this embodiment. Figure 4 is a schematic XY cross-sectional view showing a part of the configuration of the memory layer ML. Figure 5 is a schematic XY cross-sectional view showing a part of the configuration of the memory layer ML. Figure 6 is a schematic XZ cross-sectional view showing a part of the configuration of the memory layer ML. Figure 7 is a schematic XY cross-sectional view showing a part of the configuration of the memory layer ML. Figure 8 is a schematic XZ cross-sectional view showing a part of the configuration of the memory layer ML. Figure 5 is an enlarged view of a part of Figure 4. Figure 6 shows a cross-section of the structure shown in Figures 5 and 7, cut along line AA' and viewed in the direction of the arrow. Figure 7 shows an XY cross-section corresponding to a different height position than in Figure 5. For example, Figure 7 shows the upper surface of the conductive layer 113, the barrier conductive film 121, and the conductive layer 134, which will be described later. Figure 8 shows a cross-section of the structure shown in Figures 5 and 7, cut along line BB' and viewed in the direction of the arrow.

[0020] Figures 2 and 3 show a portion of the semiconductor substrate Sub and the memory cell array MCA located above the semiconductor substrate Sub.

[0021] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer (not shown), and the electrode layer constitute a control circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in the region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the bit line BL. In a read operation, the sense amplifier circuit can read data stored in the selected memory cell MC by detecting fluctuations in the voltage or current of the bit line BL.

[0022] The memory cell array MCA comprises multiple memory layers ML stacked in the Z direction, as shown in Figures 2 and 3, for example. An insulating layer 103, such as silicon oxide (SiO2), is provided between each of the multiple memory layers ML.

[0023] Furthermore, the memory cell array MCA comprises, for example, a plurality of insulating layers 101 and a plurality of conductive layers 102 arranged alternately in the X direction, as shown in Figure 4. The insulating layers 101 and conductive layers 102 extend in the Y and Z directions, as shown in Figures 2 and 3, for example, dividing the plurality of memory layers ML in the X direction.

[0024] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0025] The conductive layer 102 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 102 may also contain, for example, a conductive oxide. Alternatively, the conductive layer 102 may contain ruthenium (Ru), iridium (Ir), or other metals instead of conductive oxides. Furthermore, the conductive layer 102 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals. The conductive layer 102 functions, for example, as a plate wire PL (Figure 1).

[0026] In this specification, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0027] Multiple via connections 104 are provided in the region between the insulating layer 101 and the conductive layer 102, respectively, aligned in the Y direction. These multiple via connections 104 extend in the Z direction, penetrating multiple memory layers ML, as shown in Figures 2 and 3, for example.

[0028] As shown in Figures 5 and 6, the via wiring 104 includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive member 104c such as tungsten (W). The via wiring 104 may also contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. Furthermore, the via wiring 104 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0029] The conductive member 104c has a substantially cylindrical shape that extends in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape that extends in the Z direction along the outer circumferential surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape that extends in the Z direction along the outer circumferential surface of the barrier conductive film 104b.

[0030] The via wiring 104 functions, for example, as a bit line BL (Figure 1). Multiple bit lines BL are provided, corresponding to multiple transistors TrC included in the memory layer ML, as shown in Figure 1.

[0031] The memory layer ML comprises, for example, as shown in Figure 4, a plurality of transistor structures 110 provided at positions corresponding to a plurality of via wirings 104, a plurality of wiring members 120 provided between two adjacent transistor structures 110 in the Y direction and connected to these two transistor structures 110, and a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102.

[0032] The transistor structure 110 includes, for example, a semiconductor layer 111 connected to the outer surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (the insulating layer 101 side) of the semiconductor layer 111, and a conductive layer 113 provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (the insulating layer 101 side) of the insulating layer 112.

[0033] The semiconductor layer 111 and the insulating layer 112 are provided across a region between two adjacent insulating layers 115 (described later) in the Y direction, a pair of regions between the insulating layer 115 and the insulating layer 101, and a region located between these pairs of regions and provided along a circle centered on the center of the via wiring 104. The conductive layer 113 is provided across the above region between two adjacent insulating layers 115 in the Y direction and the above pair of regions between the insulating layer 115 and the insulating layer 101.

[0034] In the XY cross-section as illustrated in Figure 5, in the region provided between two adjacent insulating layers 115 in the Y direction, the side surface of the semiconductor layer 111 on one side in the X direction (the side with the conductive layer 102) may be formed along a circle centered on the center position of the via wiring 104. Furthermore, both sides of the semiconductor layer 111, insulating layer 112, and conductive layer 113 in the Y direction may be formed linearly along the side surface of the insulating layer 115.

[0035] Furthermore, in the XY cross-section as illustrated in Figure 5, in the pair of regions provided between the insulating layer 115 and the insulating layer 101, both sides of the conductive layer 113 in the X direction may be in contact with the sides of the insulating layer 115 and the insulating layer 101 in the X direction, respectively. Also, both sides of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the X direction may be formed linearly along the sides of the insulating layer 115 and the insulating layer 101 in the X direction, respectively. In addition, both ends of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the Y direction may be formed along the circle centered on the center position of the via wiring 104.

[0036] In this embodiment, the conductive layer 113 and the side surface of the wiring member 120 on one side in the X direction (the insulating layer 101 side) are located on the other side in the X direction (the conductive layer 102 side) of the via wiring 104 (the insulating layer 101 side). Also, the side surface of the wiring member 120 on the other side in the X direction (the conductive layer 102 side) is located on one side in the X direction (the insulating layer 101 side) of the via wiring 104 (the conductive layer 102 side). In other words, in this embodiment, the entire wiring member 120 is located in a position that overlaps with the via wiring 104 when viewed from the Y direction.

[0037] Furthermore, in the region provided along a circle centered on the central position of the via wiring 104 in the XY cross-section as illustrated in Figure 5, the side surface of the semiconductor layer 111 and the insulating layer 112 on one side in the X direction (the insulating layer 101 side) may be formed along the circle centered on the central position of the via wiring 104. In the illustrated example, the side surface of the insulating layer 112 formed along this circle on one side in the X direction (the insulating layer 101 side) is not covered by the conductive layer 113 and is in contact with the insulating layer 101.

[0038] The semiconductor layer 111 functions, for example, as the channel region of a transistor TrC (Figure 1). The semiconductor layer 111 may be a semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or it may be another oxide semiconductor. Multiple semiconductor layers 111 aligned in the Z direction are commonly connected to via wiring 104 extending in the Z direction.

[0039] The insulating layer 112 functions, for example, as a gate insulating film of the transistor TrC (Figure 1). The insulating layer 112 includes, for example, silicon oxide (SiO2).

[0040] The conductive layer 113 functions, for example, as part of the gate electrode and word line WL of a transistor TrC (Figure 1). The conductive layer 113 contains, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). Multiple conductive layers 113 aligned in the Y direction are commonly connected to a wiring member 120 extending in the Y direction (see Figure 4). The conductive layer 113 faces the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (the side facing the insulating layer 101) of the semiconductor layer 111 via the insulating layer 112.

[0041] An insulating layer 115 made of silicon oxide (SiO2) or the like is provided between two adjacent semiconductor layers 111 in the Y direction. The insulating layer 115 extends in the Z direction, penetrating multiple memory layers ML.

[0042] Both sides of the wiring member 120 in the Y direction are in contact with the Y-direction sides of two adjacent conductive layers 113 in the Y direction. One side of the wiring member 120 in the X direction (the insulating layer 101 side) is in contact with the insulating layer 101, and the other side (the conductive layer 102 side) is in contact with the insulating layer 115. Multiple wiring members 120 arranged in the Y direction are electrically connected to each other via multiple conductive layers 113 arranged in the Y direction. Multiple wiring members 120 and multiple conductive layers 113 arranged alternately in the Y direction function, for example, as a word line WL. The wiring member 120 comprises, for example, a barrier conductive film 121 made of titanium nitride (TiN) and a conductive film 122 made of tungsten (W). The barrier conductive film 121 is provided on the top surface, bottom surface, both sides in the Y direction, and the other side in the X direction (the conductive layer 102 side) of the conductive film 122.

[0043] The capacitor structure 130, as shown in Figures 5 and 6, for example, comprises a conductive layer 131, a barrier conductive layer 132, an insulating layer 133, and a conductive layer 134, which are sequentially provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 110) of the conductive layer 131, and an insulating layer 135, a barrier conductive layer 136, and a conductive layer 137, which are sequentially provided on the top surface, bottom surface, and both sides in the Y direction of the conductive layer 134. The insulating layer 135 and the barrier conductive layer 136 are continuous with the insulating layer 133 and the barrier conductive layer 132, respectively.

[0044] The conductive layer 131, barrier conductive layer 132, barrier conductive layer 136, and conductive layer 137 function as one electrode of the capacitor CpC (Figure 1). The conductive layers 131 and 137 may contain, for example, tungsten (W), ruthenium (Ru), iridium (Ir), or other metals. The barrier conductive layers 132 and 136 may contain, for example, titanium nitride (TiN). The barrier conductive layers 132 and 136 may also be omitted. The conductive layer 131, barrier conductive layer 132, barrier conductive layer 136, and conductive layer 137 are continuous with the conductive layer 102.

[0045] The insulating layers 133 and 135 function as insulating layers of the capacitor CpC (Figure 1). The insulating layers 133 and 135 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxides. Alternatively, the insulating layers 133 and 135 may be, for example, a multilayer film of multiple insulating metal oxides (e.g., a multilayer film of zirconia and alumina).

[0046] The conductive layer 134 functions, for example, as the other electrode of a capacitor CpC (Figure 1). The conductive layer 134 contains a conductive oxide such as indium tin oxide (ITO). The conductive layer 134 is insulated from the barrier conductive layers 132 and 136 via the insulating layers 133 and 135. The conductive layer 134 is connected to one side of the semiconductor layer 111 in the X direction (the side with the conductive layer 102).

[0047] [Manufacturing method] Figures 9 to 64 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0048] Figures 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, and 63 show cross-sections corresponding to Figure 5.

[0049] Figures 10, 12, 14, 16, 18, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, and 64 show cross-sections corresponding to Figure 6.

[0050] Figures 20, 22, 24, and 26 show cross-sections corresponding to Figure 8.

[0051] In this manufacturing method, for example, as shown in Figure 10, multiple insulating layers 103 and multiple sacrificial layers MLA are formed alternately. The sacrificial layer MLA contains, for example, silicon nitride (Si3N4). This process is carried out by, for example, CVD (Chemical Vapor Deposition).

[0052] Next, as shown in Figures 9 and 10, for example, a sacrificial layer 101A and an insulating layer 115 are formed. In this step, for example, an opening is formed at a position corresponding to the insulating layers 101 and 115. This opening extends in the Z direction and penetrates multiple insulating layers 103 and multiple sacrificial layers MLA that are stacked in the Z direction. This step is performed, for example, by RIE. After the opening is formed, the sacrificial layer 101A and the insulating layer 115 are formed. This step is performed, for example, by CVD.

[0053] Next, as shown in Figures 11 and 12, for example, an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A extends in the Z direction and penetrates multiple insulating layers 103 and multiple sacrificial layers MLA, as well as the sacrificial layer 101A, which are stacked in the Z direction. This process is carried out, for example, by RIE.

[0054] Next, as shown in Figures 13 and 14, for example, an opening 111A is formed at a position corresponding to the transistor structure 110. Part of the opening 111A is provided in the region between two adjacent insulating layers 115 in the Y direction. In this region, a portion of the upper and lower surfaces of the insulating layer 103, a portion of the X-direction side surface of the sacrificial layer MLA, and a portion of the Y-direction side surface of the insulating layer 115 are exposed inside the opening 111A. Another portion of the opening 111A is provided in the region between the insulating layer 115 and the sacrificial layer 101A. In this region, a portion of the upper and lower surfaces of the insulating layer 103, a portion of the Y-direction side surface of the sacrificial layer MLA, a portion of the X-direction side surface of the insulating layer 115, and a portion of the X-direction side surface of the sacrificial layer 101A are exposed inside the opening 111A. In this step, a sacrificial layer MLA is left between two adjacent openings 111A in the Y direction so that the two adjacent openings 104A in the Y direction do not communicate through the opening 111A. In this step, a portion of the sacrificial layer MLA is selectively removed, for example, through the opening 104A. This step is performed, for example, by wet etching.

[0055] Next, as shown in Figures 15 and 16, for example, sacrificial layers 104B and 111B made of silicon (Si) or the like are embedded in the openings 104A and 111A. This process is carried out by, for example, CVD.

[0056] Next, as shown in Figures 17 and 18, for example, the sacrificial layer 101A is removed to form the opening 101B. This step is performed, for example, by wet etching.

[0057] Next, as shown in Figures 19 and 20, for example, an opening 121A is formed at a position corresponding to the wiring member 120. Inside the opening 121A, a portion of the upper and lower surfaces of the insulating layer 103, both Y-sides of the sacrificial layer 111B, and a portion of the X-side of the insulating layer 115 are exposed. In this step, for example, a portion of the sacrificial layer MLA is removed through the opening 101B. This step is performed, for example, by wet etching.

[0058] Next, as shown in Figures 21 and 22, for example, a barrier conductive film 121B and a conductive film 122B are formed on a portion of the upper surface, a portion of the lower surface, and the X-direction side surface of the insulating layer 103 (the surface exposed to the openings 101B and 120A of the insulating layer 103), both Y-direction side surfaces and one X-direction side surface of the sacrificial layer 111B (the surface exposed to the openings 101B and 120A of the sacrificial layer 111B), and a portion of the X-direction side surface of the insulating layer 115 (the surface exposed to the opening 121A of the insulating layer 115). In this process, the opening 121A is filled with the conductive film 122B. On the other hand, the opening 101B is not filled with the conductive film 122B. This process is carried out by, for example, CVD.

[0059] Next, the wiring member 120 is formed, for example, as shown in Figures 23 and 24. For example, the portion of the barrier conductive film 121B and conductive film 122B formed inside the opening 121A is left intact, and the portion formed inside the opening 101B is selectively removed to expose the X-direction side of the insulating layer 103 and one X-direction side of the sacrificial layer 111B, thereby dividing the barrier conductive film 121B and conductive film 122B in the Y and Z directions. This process is carried out, for example, by wet etching.

[0060] For example, as shown in Figures 25 and 26, an insulating layer 101 is formed inside the opening 101B. This process is carried out, for example, by CVD.

[0061] Next, the sacrificial layers 104B and 111B are removed. This step is performed, for example, by wet etching.

[0062] Next, as shown in Figures 27 and 28, for example, the conductive layer 113A and the sacrificial layer 111B are formed on a portion of the upper surface, a portion of the lower surface (the surface of the insulating layer 103 exposed to the opening 111A), a portion of the side surface (the surface of the insulating layer 103 exposed to the opening 104A), the X-direction side surface of the sacrificial layer MLA (the surface of the sacrificial layer MLA exposed to the opening 111A), a portion of the X-direction and Y-direction side surfaces of the insulating layer 115 (the surface of the insulating layer 115 exposed to the opening 111A), the barrier conductive film 121B, and a portion of the X-direction side surface of the insulating layer 101 (the surface of the insulating layer 101 exposed to the opening 111A). In this process, the opening 111A is filled by the sacrificial layer 111B. On the other hand, the opening 104A is not filled by the sacrificial layer 111B. This process is carried out by, for example, CVD.

[0063] Next, an insulating layer (not shown) is formed above the opening 104A to close the opening 104A.

[0064] Next, as shown in Figures 29 and 30, for example, an opening 102A is formed at a position corresponding to the conductive layer 102. The opening 102A extends in the Y and Z directions, penetrating the multiple insulating layers 103 and multiple sacrificial layers MLA, as well as the multiple insulating layers 115, which are stacked in the Z direction, and dividing these structures in the X direction. This process is carried out, for example, by RIE.

[0065] Next, as shown in Figures 31 and 32, for example, an opening 131A is formed at a position corresponding to the capacitor structure 130. In this step, the sacrificial layer MLA is removed through the opening 102A, exposing the X-direction side surface of the conductive layer 113A. This step is performed, for example, by wet etching.

[0066] Next, a portion of the conductive layer 113A is removed through the opening 131A, exposing the X-direction side of the sacrificial layer 111B. This step is performed, for example, by wet etching.

[0067] Next, as shown in Figures 33 and 34, for example, an oxide film MLB is formed on the X-direction side surface of the sacrificial layer 111B. This step is carried out, for example, by oxidation treatment. Then, sacrificial layers 131B and 102B made of silicon (Si) or the like are embedded in the openings 131A and 102A. This step is carried out, for example, by CVD.

[0068] Next, a conductive layer 113 is formed, for example, as shown in Figures 35 and 36. In this step, for example, a portion of the sacrificial layer 111B and a portion of the conductive layer 113A are removed through the opening 104A, exposing the insulating layer 103 and the insulating layer 101, and the conductive layer 113A is divided in the Z direction. This step is performed, for example, by wet etching.

[0069] Next, the sacrificial layer 111B is removed, for example, as shown in Figures 37 and 38. This step is performed, for example, by wet etching.

[0070] Next, the oxide film MLB is removed, for example, as shown in Figures 39 and 40. This step is performed, for example, by wet etching. Also, a portion of the sacrificial layer 131B is removed. This step is also performed, for example, by wet etching.

[0071] Next, as shown in Figures 41 and 42, for example, the insulating layer 112 and the sacrificial layer 111B are formed on the exposed surface of the conductive layer 113 to the opening 111A, a part of the upper surface of the insulating layer 103, a part of the lower surface (the exposed surface of the insulating layer 103 to the opening 111A), a part of the side surface in the X direction (the exposed surface of the insulating layer 103 to the opening 104A), the side surface of the sacrificial layer 131B in the X direction (the exposed surface of the sacrificial layer 131B to the opening 111A), a part of the side surface of the insulating layer 115 in the Y direction (the exposed surface of the insulating layer 115 to the opening 111A), and a part of the side surface of the insulating layer 101 in the X direction (the exposed surface of the insulating layer 101 to the opening 104A). In this process, the opening 111A is filled by the sacrificial layer 111B. On the other hand, the opening 104A is not filled by the sacrificial layer 111B. This process is carried out by, for example, CVD.

[0072] Next, an insulating layer (not shown) is formed above the opening 104A to close the opening 104A.

[0073] Next, the sacrificial layers 131B and 102B are removed, for example, as shown in Figures 43 and 44. This step is performed, for example, by wet etching.

[0074] Next, as shown in Figures 45 and 46, for example, a portion of the insulating layer 112 is removed through the opening 131A to expose the X-direction side of the sacrificial layer 111B. This step is performed, for example, by wet etching.

[0075] Next, as shown in Figures 47 and 48, for example, a conductive layer 134A is formed on one side of the sacrificial layer 111B in the X direction (the surface exposed to opening 131A), the upper and lower surfaces of the insulating layer 103 (the surfaces exposed to opening 131A), and one side of the insulating layer 103 in the X direction (the surface exposed to opening 102A), as well as a part of the side of the insulating layer 115 in the Y direction (the surface exposed to opening 131A) and the side in the X direction (the surface exposed to opening 102A), through openings 102A and 131A. This process is carried out, for example, by ALD (Atomic Layer Deposition).

[0076] Next, as shown in Figures 49 and 50, for example, a sacrificial layer 131B made of silicon (Si) or the like is formed in the openings 131A and 102A. Opening 131A is filled by the sacrificial layer 131B. On the other hand, opening 102A is not filled by the sacrificial layer 131B. This process is carried out by, for example, CVD.

[0077] Next, as shown in Figures 51 and 52, for example, portions of the sacrificial layer 131B provided on the X-direction sides of the insulating layer 115 and insulating layer 103 are removed to expose a portion of the conductive layer 134A. This step is performed, for example, by wet etching.

[0078] Next, a conductive layer 134 is formed, for example, as shown in Figures 53 and 54. For example, portions of the conductive layer 134A provided on the X-direction sides of the insulating layer 115 and insulating layer 103 are removed, and the conductive layer 134A is divided in the Y-direction and Z-direction. This step is performed, for example, by wet etching.

[0079] Next, the sacrificial layer 131B is removed, for example, as shown in Figures 55 and 56. This step is performed, for example, by wet etching.

[0080] Next, as shown in Figures 57 and 58, for example, a portion of the insulating layers 103 and 115 is removed. This step is performed, for example, by wet etching.

[0081] Next, a capacitor structure 130 is formed, for example, as shown in Figures 59 and 60. In this step, insulating layers 133, 135, barrier conductive layer 132, barrier conductive layer 136, and conductive layers 131 and 137 are formed on the upper surface, lower surface, one side in the X direction (the side on the side of opening 102A) and both sides in the Y direction of the conductive layer 134, and on the X-direction side of the insulating layer 115 and insulating layer 103, for example, through openings 131A and 102A. This step is performed, for example, by CVD.

[0082] Next, the sacrificial layer 111B is removed, for example, as shown in Figures 61 and 62. This step is performed, for example, by wet etching.

[0083] Next, as shown in Figures 63 and 64, for example, a semiconductor layer 111 is formed inside the openings 111A and 104A. The opening 111A is filled with the semiconductor layer 111. On the other hand, the opening 104A is not filled with the semiconductor layer 111. This process is carried out, for example, by ALD.

[0084] Subsequently, as shown in Figures 5 and 6, for example, a conductive oxide film 104a, a barrier conductive film 104b, and a conductive member 104c are formed inside the opening 104A. This process is carried out by methods such as ALD and CVD. This forms the structure described with reference to Figures 2 to 8.

[0085] [effect] As described with reference to Figures 9 to 64, the number of memory layers ML included in the memory cell array MCA can be increased simply by increasing the number of sacrificial layers MLA and insulating layers 101 stacked in the process described with reference to Figures 9 and 10. Therefore, high integration of the memory cell array MCA can be achieved relatively easily without significantly increasing manufacturing costs.

[0086] The semiconductor memory device manufactured by this method comprises multiple memory layers ML aligned in the Z direction and via wiring 104 extending in the Z direction. Furthermore, the configurations within the multiple memory layers ML (transistor structure 110, wiring member 120, capacitor structure 130, etc.) are all in different positions when viewed from the Z direction. In addition, the configurations within the memory layers ML have a vertically symmetrical structure.

[0087] In such a semiconductor memory device, for example, wiring extending in the Y direction can be provided between the transistor structure 110 and the insulating layer 101, and this can be used as a word line WL.

[0088] However, the X-direction length of each memory cell MC includes half the X-direction length of the opening 101B (Figure 23), half the X-direction length of the opening 102A (Figure 29), the X-direction length of the transistor structure 110, and the X-direction length of the capacitor structure 130. Here, the openings 101B and 102A need to be formed relatively deep because they extend in the Z-direction, penetrating multiple insulating layers 103 and multiple sacrificial layers MLA stacked in the Z-direction. For this reason, the X-direction lengths of the openings 101B and 102A tend to increase as the number of sacrificial layers MLA and insulating layers 101 stacked in the Z-direction increases, and it may be difficult to reduce them. Also, the X-direction lengths of the transistor structure 110 and the capacitor structure 130 are determined according to the channel length of the transistor TrC and the capacitance of the capacitor CpC, and it may be difficult to reduce them.

[0089] Therefore, for example, if wiring extending in the Y direction is provided between the transistor structure 110 and the insulating layer 101 as described above, and this is used as a word line WL, the length in the X direction for each memory cell MC may become relatively large.

[0090] Therefore, in the semiconductor memory device according to this embodiment, a plurality of conductive layers 113 arranged in the Y direction are connected via a plurality of wiring members 120, and this is used as a word line WL.

[0091] With this configuration, there is no need to provide wiring extending in the Y direction between the transistor structure 110 and the insulating layer 101. Therefore, it is possible to reduce the length in the X direction per memory cell MC and achieve high integration of semiconductor memory devices.

[0092] Furthermore, in such semiconductor memory devices, for example, the conductive layer 113 and the wiring member 120 may be positioned on one side in the X direction (the insulating layer 101 side) further than the end of the via wiring 104 on one side in the X direction (the insulating layer 101 side).

[0093] However, in such a configuration, the length of the via wiring 104 in the X direction is included in the length of each memory cell MC, which may result in an increased length of each memory cell MC in the X direction.

[0094] Therefore, in the semiconductor memory device according to this embodiment, the conductive layer 113 and the side surface of the wiring member 120 on one side in the X direction (the insulating layer 101 side) are located on the other side in the X direction (the conductive layer 102 side) of the via wiring 104 (the insulating layer 101 side).

[0095] With this configuration, it is possible to further reduce the length in the X direction of each memory cell MC, thereby achieving higher integration of semiconductor memory devices.

[0096] [Second Embodiment] Figure 65 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the second embodiment. Figure 66 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the second embodiment. Figure 67 is a schematic XZ cross-sectional view showing a part of the configuration of the semiconductor memory device according to the second embodiment. Figure 66 is an enlarged view of a part of Figure 65. Figure 67 shows a cross-section of the structure shown in Figure 66, cut along line AA' and viewed in the direction of the arrow. In the following description, parts the same as in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0097] The semiconductor memory device according to the second embodiment is basically configured in the same way as the semiconductor memory device according to the first embodiment. However, the structure of the memory cell array according to the second embodiment is different from the structure of the memory cell array MCA according to the first embodiment.

[0098] The memory cell array according to the second embodiment comprises a plurality of memory layers ML2 stacked in the Z direction, as shown in Figure 67, for example. An insulating layer 103, such as silicon oxide (SiO2), is provided between each of the plurality of memory layers ML2.

[0099] Furthermore, the memory cell array according to the second embodiment includes a plurality of conductive layers 102 arranged in the X direction, as shown in Figure 65, for example. In addition, a plurality of insulating layers 201 and a plurality of via wirings 204 are provided in the region between two adjacent conductive layers 102 in the X direction, arranged alternately in the Y direction. The plurality of insulating layers 201 and the plurality of via wirings 204 extend in the Z direction, penetrating the plurality of memory layers ML.

[0100] The insulating layer 201 includes, for example, silicon oxide (SiO2).

[0101] The via wiring 204 is basically configured similarly to the via wiring 104. However, in the first embodiment, when considering two via wirings 104 adjacent to each other in the X direction via the insulating layer 101, one via wiring 104 is spaced apart from the other via wiring 104 via the insulating layer 101. Furthermore, these two via wirings 104 are each electrically connected to different semiconductor layers 111. On the other hand, the via wiring 204 is electrically connected in common to two semiconductor layers 211 adjacent to each other in the X direction. The via wiring 204 may have, for example, a substantially elliptical or substantially oblong shape when viewed from the Z direction. Also, the length of the via wiring 204 in the X direction may be greater than the length of the via wiring 204 in the Y direction. In this embodiment, the entire wiring member 120 is provided in a position that overlaps with the via wiring 204 when viewed from the Y direction.

[0102] The memory layer ML2 comprises a plurality of transistor structures 210 provided between a plurality of via wirings 204 and a plurality of conductive layers 102, a plurality of wiring members 120 provided between two adjacent transistor structures 210 in the Y direction and connected to these two transistor structures 210, and a plurality of capacitor structures 130 provided between the plurality of transistor structures 210 and the conductive layers 102.

[0103] The transistor structure 210 includes, for example, a semiconductor layer 211 connected to the X-direction end of the via wiring 204 and extending in the X-direction, an insulating layer 212 provided on the top surface, bottom surface, both Y-direction sides, and one X-direction side (insulating layer 201 side) of the semiconductor layer 211, and a conductive layer 113 provided on the top surface, bottom surface, both Y-direction sides, and one X-direction side (insulating layer 201 side) of the insulating layer 212.

[0104] The semiconductor layer 211 and the insulating layer 212 are basically configured in the same way as the semiconductor layer 111 and the insulating layer 112. However, the semiconductor layer 211 and the insulating layer 212 have portions provided on the outer surface of the via wiring 204, as illustrated in Figure 66, for example, and are continuous with the semiconductor layer 211 and insulating layer 212 of other adjacent transistor structures 210 in the X direction via these portions.

[0105] For example, in the semiconductor memory device according to the first embodiment, if the length of the via wiring 104 in the X direction is about half the length of the insulating layer 101 in the X direction, by adopting such a configuration, it is possible to further reduce the length in the X direction per memory cell MC and achieve higher integration of the semiconductor memory device.

[0106] [Third Embodiment] Figure 68 is a schematic XY cross-sectional view showing a partial configuration of a semiconductor memory device according to the third embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0107] The semiconductor memory device according to the third embodiment is basically configured in the same way as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the third embodiment includes a transistor structure 310 and a wiring member 320 instead of the transistor structure 110 and wiring member 120.

[0108] The transistor structure 310 is basically configured in the same way as the transistor structure 110. However, the transistor structure 310 includes a conductive layer 313 instead of the conductive layer 113. The conductive layer 313 is basically configured in the same way as the conductive layer 113. However, one side of the conductive layer 313 in the X direction (the side facing the insulating layer 101) is spaced apart from the insulating layer 101.

[0109] The wiring member 320 is basically configured in the same way as the wiring member 120. However, the other side of the wiring member 320 in the X direction (the conductive layer 102 side) is in contact with one side of the insulating layer 115 in the X direction (the insulating layer 101 side) and has a portion that extends in the Y direction along this side, and is in contact with one side of the conductive layer 313 in the X direction (the insulating layer 101 side) and has a portion that extends in the Y direction along this side. In addition, both sides of the conductive layer 313 in the Y direction are in contact with the insulating layer 112. In this embodiment, the entire wiring member 320 is provided in a position that overlaps with the via wiring 104 when viewed from the Y direction.

[0110] Figures 69 to 71 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the third embodiment. Figures 69 to 71 show cross-sections corresponding to Figure 68.

[0111] The semiconductor memory device according to the third embodiment is basically manufactured in the same manner as the semiconductor memory device according to the first embodiment.

[0112] However, in the manufacturing of the semiconductor memory device according to the third embodiment, in the process described with reference to Figures 15 and 16, as shown in Figure 69, a sacrificial layer 111B of silicon (Si) or the like is embedded in the opening 111A, and another sacrificial layer 304B is embedded in the opening 104A. This process is carried out, for example, by CVD.

[0113] Furthermore, after performing the steps described with reference to Figures 19 and 20, and before performing the steps described with reference to Figures 21 and 22, a portion of the sacrificial layer 111B is removed as shown in Figure 70. This step is performed, for example, by wet etching.

[0114] Next, by performing the steps described with reference to Figures 21 to 24, the wiring member 320 is formed as shown in Figure 71.

[0115] In the semiconductor memory device according to the third embodiment, the length of the opening 121A in the Y direction is increased by removing a portion of the sacrificial layer 111B in the process described with reference to Figure 70. Therefore, the proportion of wiring members 320 in the word line WL in the third embodiment is greater than the proportion of wiring members 120 in the word line WL in the first embodiment. This makes it possible to reduce the resistance of the word line WL.

[0116] Furthermore, the semiconductor memory device according to the second embodiment may include a wiring member 320 instead of the wiring member 120.

[0117] [Fourth Embodiment] In the first embodiment, the conductive layer 113 and the wiring member 120 have one side in the X direction (the insulating layer 101 side) positioned further to the other side in the X direction (the conductive layer 102 side) than the end of the via wiring 104 on the X direction (the insulating layer 101 side). However, this configuration is merely illustrative, and the specific configuration can be adjusted as appropriate. For example, the conductive layer 113 and the wiring member 120 have one side in the X direction (the insulating layer 101 side) positioned further to the other side in the X direction (the insulating layer 101 side) than the end of the via wiring 104 on the X direction (the insulating layer 101 side). The second and third embodiments are similar.

[0118] The following describes an example of a semiconductor memory device according to the fourth embodiment.

[0119] Figure 72 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the fourth embodiment. Figure 73 is a schematic XZ cross-sectional view showing a part of the configuration of the semiconductor memory device according to the fourth embodiment. Figure 73 shows a cross-section of the structure shown in Figure 72, cut along line AA' and viewed in the direction of the arrow. In the following description, parts the same as in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0120] The semiconductor memory device according to the fourth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fourth embodiment includes a transistor structure 410 instead of the transistor structure 110.

[0121] The transistor structure 410 is basically configured in the same way as the transistor structure 110. However, the transistor structure 410 includes a semiconductor layer 411, an insulating layer 412, and a conductive layer 413 instead of the semiconductor layer 111, insulating layer 112, and conductive layer 113.

[0122] The semiconductor layer 411, the insulating layer 412, and the conductive layer 413 are basically constructed in the same way as the semiconductor layer 111, the insulating layer 112, and the conductive layer 113. However, the entire surface of one side in the X direction (the side facing the insulating layer 101) of the semiconductor layer 411, the insulating layer 412, and the conductive layer 413 is formed in a straight line along the X-direction surface of the insulating layer 101.

[0123] Furthermore, in this embodiment, the conductive layer 413 and one side of the wiring member 120 in the X direction (the insulating layer 101 side) are located further to the X direction (the insulating layer 101 side) than the end of the via wiring 104 in the X direction (the insulating layer 101 side). Also, the other side of the wiring member 120 in the X direction (the conductive layer 102 side) is located further to the X direction (the insulating layer 101 side) than the end of the via wiring 104 in the X direction (the conductive layer 102 side). In other words, in this embodiment, a portion of the wiring member 120 is located in a position that overlaps with the via wiring 104 when viewed from the Y direction.

[0124] Furthermore, the semiconductor memory device according to the fourth embodiment may include a wiring member 320 (Figure 68) instead of the wiring member 120.

[0125] [Fifth Embodiment] Figure 74 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the fifth embodiment. Figure 75 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the fifth embodiment. Figures 76 to 78 are schematic XZ cross-sectional views showing a part of the configuration of the semiconductor memory device according to the fifth embodiment. Figure 75 is an enlarged view of a part of Figure 74. Figure 76 shows a cross-section of the structure shown in Figure 75, cut along line AA' and viewed in the direction of the arrow. Figure 77 shows a cross-section of the structure shown in Figure 75, cut along line BB' and viewed in the direction of the arrow. Figure 78 shows a cross-section of the structure shown in Figure 75, cut along line CC' and viewed in the direction of the arrow. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0126] The semiconductor memory device according to the fifth embodiment is basically configured in the same way as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fifth embodiment includes a memory layer ML5 instead of the memory layer ML. The memory layer ML5 is basically configured in the same way as the memory layer ML. However, the memory layer ML5 includes a transistor structure 510, a wiring member 520, and an insulating member 521 instead of the transistor structure 110 and the wiring member 120.

[0127] The transistor structure 510 is basically configured in the same way as the transistor structure 110. However, the transistor structure 510 includes a semiconductor layer 511, an insulating layer 512, and a conductive layer 513 instead of the semiconductor layer 111, insulating layer 112, and conductive layer 113. The semiconductor layer 511, insulating layer 512, and conductive layer 513 are basically configured in the same way as the semiconductor layer 111, insulating layer 112, and conductive layer 113. However, the semiconductor layer 511, insulating layer 512, and conductive layer 513 are not provided in the region between the insulating layer 115 and the insulating layer 101.

[0128] The wiring member 520 extends in the Y direction and is continuous with two adjacent conductive layers 513 in the Y direction. One side of the wiring member 520 in the X direction (the side with the insulating layer 101) is in contact with the insulating layer 101, and the other side (the side with the conductive layer 102) is in contact with the insulating layer 115. Multiple wiring members 520 arranged in the Y direction are electrically connected to each other via multiple conductive layers 113 arranged in the Y direction. Multiple wiring members 520 and multiple conductive layers 513 arranged alternately in the Y direction function, for example, as a word line WL. The wiring member 520 includes a barrier conductive film, for example, titanium nitride (TiN).

[0129] The insulating member 521 extends in the Y direction and is continuous with two adjacent insulating layers 512 in the Y direction. The wiring member 520 is in contact with the top surface, bottom surface, and both sides in the X direction of the insulating member 521. Multiple insulating members 521 are arranged alternately in the Y direction together with multiple transistor structures 510. The insulating member 521 contains, for example, the same material as the insulating layers 512.

[0130] For example, as shown in Figure 78, the length of the wiring member 520 in the Z direction is Z 520 The length of the conductive layer 513 in the Z direction is Z 513 It is smaller than. Also, the length of the insulating member 521 in the Z direction is Z 521 This is the length of the insulating layer 512 in the Z direction Z 512 It is smaller than that.

[0131] In this embodiment, one side of the wiring member 520 in the X direction (the insulating layer 101 side) is located further to the other side in the X direction (the conductive layer 102 side) than the other end of the via wiring 104 in the X direction (the insulating layer 101 side). Also, the other side of the wiring member 520 in the X direction (the conductive layer 102 side) is located further to one side in the X direction (the insulating layer 101 side) than the other end of the via wiring 104 in the X direction (the conductive layer 102 side). In other words, in this embodiment, the entire wiring member 520 is located in a position that overlaps with the via wiring 104 when viewed from the Y direction.

[0132] Figures 79 to 90 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the fifth embodiment. Figures 79, 81, 83, 85, 87, and 89 show cross-sections corresponding to Figure 75. Figures 80, 82, 84, 86, 88, and 90 show cross-sections corresponding to Figure 78.

[0133] In manufacturing the semiconductor memory device according to the fifth embodiment, for example, the steps up to those described with reference to Figures 9 and 10 of the manufacturing method according to the first embodiment are performed.

[0134] Next, as shown in Figures 79 and 80, the sacrificial layer 101A is removed to form the opening 101B. Additionally, a portion of the insulating layer 103 is removed to expose the upper and lower surfaces of the sacrificial layer MLA corresponding to the wiring member 520. This step is performed, for example, by wet etching.

[0135] Next, as shown in Figures 81 and 82, a portion of the sacrificial layer MLA is removed through the opening 101B. This reduces the Z-direction length of the portion of the sacrificial layer MLA corresponding to the wiring member 520. This process is carried out, for example, by wet etching.

[0136] Next, as shown in Figures 83 and 84, an insulating layer 101 is formed inside the opening 101B. This process is carried out, for example, by CVD.

[0137] Next, as shown in Figures 85 and 86, the process described with reference to Figures 11 to 14 is performed. In this process, no sacrificial layer MLA remains between two adjacent openings 111A in the Y direction. As a result, an opening 111A is formed at a position corresponding to the transistor structure 110. Also, an opening 520A is formed at a position corresponding to the wiring member 520. The length of the opening 520A in the Z direction is smaller than the length of the opening 111A in the Z direction. At the stage when this process is performed, the multiple openings 111A aligned in the Y direction communicate with each other via the opening 520A.

[0138] Next, the process described with reference to Figures 27 and 28 is carried out as shown in Figures 87 and 88.

[0139] Next, as shown in Figures 89 and 90, the process described with reference to Figures 29 to 42 is carried out. In the process shown in Figures 41 and 42, an insulating layer 512 and an insulating member 521 are formed instead of the insulating layer 112. In this process, the opening 520A is filled with the insulating member 521. On the other hand, the opening 111A is not filled with the insulating layer 512. As a result, the multiple openings 111A aligned in the Y direction are spatially separated via the insulating member 521.

[0140] Subsequently, the semiconductor memory device according to the fifth embodiment is manufactured by performing the steps following the steps described with reference to Figures 43 and 44 of the manufacturing method according to the first embodiment.

[0141] With this configuration, as in the first embodiment, it is possible to reduce the length in the X direction of each memory cell MC and achieve high integration of semiconductor memory devices.

[0142] Furthermore, the semiconductor memory device according to the fifth embodiment does not require the steps described with reference to Figures 21 to 24 in the manufacturing process of the semiconductor memory device according to the first embodiment. Therefore, it can be manufactured at a lower cost compared to the semiconductor memory device according to the first embodiment.

[0143] [Sixth Embodiment] Figure 91 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. In the following description, parts similar to those in the fifth embodiment or the second embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0144] The semiconductor memory device according to the sixth embodiment is basically configured in the same way as the semiconductor memory device according to the fifth embodiment. However, the structure of the memory cell array according to the sixth embodiment is different from the structure of the memory cell array according to the fifth embodiment.

[0145] The memory cell array according to the sixth embodiment includes, for example, a plurality of conductive layers 102 arranged in the X direction, as shown in Figure 91. In addition, a plurality of insulating layers 201 and a plurality of via wirings 204 are provided in the region between two adjacent conductive layers 102 in the X direction, arranged alternately in the Y direction. The plurality of insulating layers 201 and the plurality of via wirings 204 extend in the Z direction, penetrating the plurality of memory layers ML.

[0146] Furthermore, the memory layer according to the sixth embodiment includes a plurality of transistor structures 610 provided between a plurality of via wirings 204 and a plurality of conductive layers 102, a plurality of wiring members 520 provided between two adjacent transistor structures 610 in the Y direction and connected to these two transistor structures 610, and a plurality of capacitor structures 130 provided between the plurality of transistor structures 610 and the conductive layers 102.

[0147] The transistor structure 610 is basically configured in the same way as the transistor structure 510. However, the configurations corresponding to the semiconductor layer 511 and insulating layer 512 in the transistor structure 610 include portions provided on the outer surface of the via wiring 204, and these portions are continuous with the configurations corresponding to the semiconductor layer 511 and insulating layer 512 in other adjacent transistor structures 610 in the X direction.

[0148] For example, in the semiconductor memory device according to the fifth embodiment, if the length of the via wiring 104 in the X direction is about half the length of the insulating layer 101 in the X direction, by adopting such a configuration, it is possible to further reduce the length in the X direction per memory cell MC and achieve higher integration of the semiconductor memory device.

[0149] [Seventh Embodiment] Figure 92 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the seventh embodiment. Figure 93 is a schematic XZ cross-sectional view showing a part of the configuration of the semiconductor memory device according to the seventh embodiment. Figure 93 shows a cross-section of the structure shown in Figure 92, cut along line AA' and viewed in the direction of the arrow. In the following description, parts similar to those in the fifth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0150] The semiconductor memory device according to the seventh embodiment is basically configured in the same way as the semiconductor memory device according to the fifth embodiment.

[0151] However, in the seventh embodiment, one side of the wiring member 520 in the X direction (the insulating layer 101 side) is located further to the X direction (the insulating layer 101 side) than the end of the via wiring 104 in the X direction (the insulating layer 101 side). Also, the other side of the wiring member 520 in the X direction (the conductive layer 102 side) is located further to the X direction (the insulating layer 101 side) than the end of the via wiring 104 in the X direction (the conductive layer 102 side). In other words, in this embodiment, a portion of the wiring member 520 is located in a position that overlaps with the via wiring 104 when viewed from the Y direction.

[0152] Furthermore, in the seventh embodiment, multiple wiring members 520 arranged in the Y direction are continuous with each other. Similarly, multiple insulating members 521 arranged in the Y direction are continuous with each other.

[0153] [Eighth Embodiment] Figure 94 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to the eighth embodiment. Figure 95 is a schematic XZ cross-sectional view showing a part of the configuration of the semiconductor memory device according to the eighth embodiment. Figure 95 shows a cross-section of the structure shown in Figure 94, cut along line AA' and viewed along the direction of the arrow. In the following description, parts similar to those in the seventh embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0154] The semiconductor memory device according to the eighth embodiment is basically configured the same as the semiconductor memory device according to the seventh embodiment. However, the semiconductor memory device according to the eighth embodiment does not include an insulating member 521.

[0155] The semiconductor memory device according to the eighth embodiment can be manufactured, for example, by filling the opening 520A with a wiring member 520 in the process described with reference to Figures 87 and 88.

[0156] Furthermore, in the semiconductor memory device according to the eighth embodiment, the side surface of the wiring member 520 on one side in the X direction (the insulating layer 101 side) may be located on the other side in the X direction (the conductive layer 102 side) of the via wiring 104 (the insulating layer 101 side). That is, even in the eighth embodiment, the entire wiring member 520 may be located in a position that overlaps with the via wiring 104 when viewed from the Y direction.

[0157] Furthermore, the semiconductor memory device according to the sixth embodiment does not need to include the insulating member 521, similar to the semiconductor memory device according to the eighth embodiment.

[0158] [Ninth Embodiment] In the first to eighth embodiments, an example was described in which one memory cell MC comprises one transistor TrC and one capacitor CpC. However, such a configuration is merely illustrative and can be adjusted as appropriate. Below, an example of a semiconductor memory device according to the ninth embodiment, in which one memory cell comprises multiple transistors, will be described.

[0159] [Circuit Configuration] Figure 96 is a schematic circuit diagram showing a partial configuration of a semiconductor memory device according to the ninth embodiment.

[0160] As shown in Figure 96, the semiconductor memory device according to this embodiment includes a memory cell array MCA9. The memory cell array MCA9 includes a plurality of memory layers ML9, a plurality of write bit lines WBL connected to these plurality of memory layers ML9, a plurality of voltage supply lines VDD connected to the plurality of memory layers ML9, and a plurality of read bit lines RBL connected to the plurality of memory layers ML9. The voltage supply line VDD may supply a power supply voltage Vdd or a ground voltage Vss.

[0161] Each memory layer ML9 comprises a write word line WWL, a read word line RWL, and a plurality of memory cells MC9 connected to the write word line WWL and the read word line RWL. Each memory cell MC9 comprises a write transistor WTr, a sense node SN, a read transistor RTr, a connection node CN, and a switch transistor STr.

[0162] The write transistor WTr is, for example, a field-effect NMOS transistor. One electrode of the write transistor WTr is connected to the write bit line WBL. The other electrode of the write transistor WTr is connected to the sense node SN. Both electrodes of the write transistor WTr function as source or drain electrodes depending on the voltage supplied to the write transistor WTr. The gate electrode of the write transistor WTr is connected to the write word line WWL.

[0163] The readout transistor RTr is, for example, a field-effect NMOS transistor. One electrode of the readout transistor RTr is connected to the voltage supply line VDD. The other electrode of the readout transistor RTr is connected to the connection node CN. Both electrodes of the readout transistor RTr function as source electrodes or drain electrodes depending on the voltage supplied to the readout transistor RTr. The gate electrode of the readout transistor RTr is connected to the sense node SN.

[0164] The switch transistor STr is, for example, a field-effect NMOS transistor. One electrode of the switch transistor STr is connected to the readout bit line RBL. The other electrode of the switch transistor STr is connected to the connection node CN. Both electrodes of the switch transistor STr function as source electrodes or drain electrodes depending on the voltage supplied to the switch transistor STr. The gate electrode of the switch transistor STr is connected to the readout word line RWL.

[0165] [structure] Figure 97 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the ninth embodiment. Figure 98 is a schematic cross-sectional view showing a part of the configuration of the same semiconductor memory device, showing the structure shown in Figure 97 cut along line AA' and viewed along the direction of the arrow.

[0166] The memory cell array MCA9 comprises multiple memory layers ML9 arranged in the Z direction. An insulating layer 103, such as silicon oxide (SiO2), is provided between each of the multiple memory layers ML9.

[0167] Furthermore, the memory cell array MCA9 includes a plurality of insulating layers 101 that are arranged alternately in the X direction and extend in the Y and Z directions.

[0168] Furthermore, vias 901, 902, and 903 are provided in the memory cell array MCA9. Via 901 functions as a write bit line (WBL). Via 902 functions as a voltage supply line (VDD). Via 903 functions as a read bit line (RBL). Vias 901, 902, and 903 are arranged sequentially in the X direction between two adjacent insulating layers 101 in the X direction, and extend in the Z direction, penetrating multiple memory layers ML9.

[0169] The via wiring 901 includes, for example, a conductive oxide film 901a containing a conductive oxide, a barrier conductive film 901b such as titanium nitride (TiN), and a conductive member 901c such as tungsten (W). The via wiring 901 may also contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 901a. Furthermore, the via wiring 901 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0170] The conductive member 901c has a substantially cylindrical shape that extends in the Z direction. The barrier conductive film 901b has a substantially cylindrical shape that extends in the Z direction along the outer surface of the conductive member 901c. The conductive oxide film 901a has a substantially cylindrical shape that extends in the Z direction along the outer surface of the barrier conductive film 901b.

[0171] The via wiring 902 includes, for example, a conductive oxide film 902a containing a conductive oxide, a barrier conductive film 902b such as titanium nitride (TiN), and a conductive member 902c such as tungsten (W). The via wiring 902 may also contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 902a. Furthermore, the via wiring 902 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0172] The conductive member 902c has a substantially cylindrical shape that extends in the Z direction. The barrier conductive film 902b has a substantially cylindrical shape that extends in the Z direction along the outer circumferential surface of the conductive member 902c. The conductive oxide film 902a has a substantially cylindrical shape that extends in the Z direction along the outer circumferential surface of the barrier conductive film 902b.

[0173] The via wiring 903 includes, for example, a conductive oxide film 903a containing a conductive oxide, a barrier conductive film 903b such as titanium nitride (TiN), and a conductive member 903c such as tungsten (W). The via wiring 903 may also contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 903a. Furthermore, the via wiring 903 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0174] The conductive member 903c has a substantially cylindrical shape that extends in the Z direction. The barrier conductive film 903b has a substantially cylindrical shape that extends in the Z direction along the outer surface of the conductive member 903c. The conductive oxide film 903a has a substantially cylindrical shape that extends in the Z direction along the outer surface of the barrier conductive film 903b.

[0175] The memory layer ML9 includes a transistor structure 910 located at a position corresponding to via wiring 901, a transistor structure 920 located at a position corresponding to via wiring 902, and a transistor structure 930 located at a position corresponding to via wiring 903. In the illustrated example, the transistor structures 910, 920, and 930 are aligned in the X direction. The memory layer ML9 also includes a plurality of wiring members 120 provided between two adjacent transistor structures 910 in the Y direction and connected to these two transistor structures 910, and a plurality of wiring members 120 provided between two adjacent transistor structures 930 in the Y direction and connected to these two transistor structures 930.

[0176] The transistor structure 910 is basically configured similarly to the transistor structure 110. However, the semiconductor layer 111, insulating layer 112, and conductive layer 113 in the transistor structure 910 function as the channel region, gate insulating film, and gate electrode of the write transistor WTr, respectively. The conductive layer 113 also functions as part of the write word line WWL.

[0177] The transistor structure 920 comprises a semiconductor portion 921 connected to the outer surface of the via wiring 902 and extending in the X direction, an insulating portion 922 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 910) of the semiconductor portion 921, and a conductive layer 923 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 910) of the insulating portion 922.

[0178] The transistor structure 930 comprises a semiconductor portion 931 connected to the outer surface of the via wiring 903 and extending in the X direction; an insulating portion 932 provided on the upper surface, lower surface, both sides in the Y direction, and the other side in the X direction (opposite to the transistor structure 910) of the semiconductor portion 931; and a conductive layer 933 provided on the upper surface, lower surface, both sides in the Y direction, and the other side in the X direction (opposite to the transistor structure 910) of the insulating portion 932.

[0179] Semiconductor portion 921 is continuous with semiconductor portion 931 and is directly connected to it. Semiconductor portion 921 and semiconductor portion 931 are each part of a single semiconductor layer extending in the X direction. Similarly, insulating portion 922 is continuous with insulating portion 932 and is directly connected to it. Insulating portion 922 and insulating portion 932 are each part of a single insulating layer.

[0180] In the XY cross-section illustrated in Figure 97, the side surface of the semiconductor portion 921, the insulating portion 922, and the conductive layer 923 on one side in the X direction (the side facing the transistor structure 910) may be formed along a circle centered on the center position of the via wiring 901. The other side surface of the semiconductor portion 931, the insulating portion 932, and the conductive layer 933 on the other side in the X direction (the side opposite to the transistor structure 910) may comprise a portion formed linearly along the side surface of the insulating layer 101 in the X direction, and a portion formed along a circle centered on the center position of the via wiring 903. Furthermore, both sides of the semiconductor portion 921, the insulating portion 922, the conductive layer 923, the semiconductor portion 931, the insulating portion 932, and the conductive layer 933 in the Y direction may be formed linearly along the side surface of the insulating layer 115 in the Y direction.

[0181] Semiconductor portion 921 functions, for example, as the channel region of a readout transistor RTr (Figure 96). Semiconductor portion 931 functions, for example, as the channel region of a switch transistor STr (Figure 96). Semiconductor portions 921 and 931 may be semiconductors containing, for example, at least one element from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or they may be other oxide semiconductors. Multiple semiconductor portions 921 aligned in the Z direction are commonly connected to via wiring 902 extending in the Z direction. Multiple semiconductor portions 931 aligned in the Z direction are commonly connected to via wiring 903 extending in the Z direction.

[0182] The insulating portion 922 functions, for example, as a gate insulating film of the readout transistor RTr (Figure 96). The insulating portion 932 functions, for example, as a gate insulating film of the switch transistor STr (Figure 96). The insulating portions 922 and 932 include, for example, silicon oxide (SiO2).

[0183] The conductive layer 923 functions, for example, as the gate electrode and sense node SN (Figure 96) of the readout transistor RTr (Figure 96). The conductive layer 933 functions, for example, as the gate electrode of the switch transistor STr (Figure 96) and as part of the readout word line RWL (Figure 96). The conductive layers 923 and 933 contain, for example, a conductive material such as titanium nitride (TiN) or a conductive oxide such as indium tin oxide (ITO). The conductive layer 923 faces the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (the side facing the transistor structure 910) of the semiconductor portion 921 via the insulating portion 922. The conductive layer 933 faces the upper surface, lower surface, both sides in the Y direction, and the other side in the X direction (the side opposite to the transistor structure 910) of the semiconductor portion 931 via the insulating portion 932.

[0184] Furthermore, the semiconductor memory device according to the ninth embodiment may include a wiring member 320 (Figure 68) or a wiring member 520 (Figures 74 and 75) instead of the wiring member 120.

[0185] Furthermore, the semiconductor memory device according to the ninth embodiment may include via wiring 204 and a transistor structure 210 or a transistor structure 610 instead of via wiring 901 and transistor structure 910. Also, the semiconductor memory device according to the ninth embodiment may include via wiring having a structure similar to via wiring 204 and a transistor structure having a structure similar to transistor structure 210 or a transistor structure 610 instead of via wiring 903 and transistor structure 930.

[0186] Furthermore, in the ninth embodiment, the conductive layer 113 and the wiring member 120 connected thereto on one side in the X direction (the negative X direction side in Figure 97) are located on the other side in the X direction (the positive X direction side in Figure 97) of the via wiring 901 than on the other end in the X direction (the negative X direction side in Figure 97). However, the conductive layer 113 and the wiring member 120 connected thereto on one side in the X direction (the negative X direction side in Figure 97) may also be located on the other side in the X direction (the negative X direction side in Figure 97) of the via wiring 901 than on the other end in the X direction (the negative X direction side in Figure 97).

[0187] Similarly, in the ninth embodiment, the other side of the conductive layer 933 and the wiring member 120 connected thereto in the X direction (positive side in the X direction in Figure 97) is located on one side in the X direction (negative side in the X direction in Figure 97) than the other end of the via wiring 903 in the X direction (positive side in the X direction in Figure 97). However, the other side of the conductive layer 933 and the wiring member 120 connected thereto in the X direction (positive side in the X direction in Figure 97) may be located on the other side of the X direction (positive side in the X direction in Figure 97) than the other end of the via wiring 903 in the X direction (positive side in the X direction in Figure 97).

[0188] [Other embodiments] The semiconductor memory devices according to the first to ninth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations can be adjusted as appropriate.

[0189] For example, in the semiconductor memory devices according to the first to ninth embodiments, via wiring 104, etc., which function as bit lines BL, etc., contain a conductive oxide such as indium tin oxide (ITO). However, such conductive oxides may be included in the transistor structure 110, etc., rather than in the via wiring 104, etc., which extends in the Z direction. Furthermore, the via wiring 104, etc. and the transistor structure 110, etc., may also contain other materials.

[0190] Furthermore, in the semiconductor memory devices according to the first to ninth embodiments, the conductive layer 113, which functions as a gate electrode of a transistor such as a TraC, may face only one of the upper or lower surfaces of the semiconductor layer 111, which functions as a channel region of a transistor such as a TraC.

[0191] Furthermore, in the first to eighth embodiments, examples were described in which a capacitor CpC is used as the memory section connected to the transistor structure 110, etc. In the ninth embodiment, an example was described in which a sense node SN is used as the memory section connected to the transistor structure 910. However, the memory section does not have to be a capacitor CpC. For example, the memory section may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and record data by utilizing the properties of these materials. For example, in any of the structures described above, one of these materials may be included in the insulating layer between the electrodes forming the capacitor CpC.

[0192] Furthermore, the semiconductor memory manufacturing method described above can be adjusted as appropriate. For example, the order of any two of the above steps can be changed, or any two of the above steps can be performed simultaneously.

[0193] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0194] Sub...semiconductor substrate, ML...memory layer, BL...bit line, PL...plate line, TraC...transistor, CpC...capacitor, 101...insulating layer, 102...conductive layer, 103...insulating layer, 104...via wiring, 110...transistor structure, 111...semiconductor layer, 112...insulating layer, 113...conductive layer, 120...wiring component, 130...capacitor structure.

Claims

1. A plurality of semiconductor layers stacked in a first direction, arranged in a second direction intersecting the first direction, and in a third direction intersecting the first and second directions, Multiple via connections electrically connected to multiple semiconductor layers arranged in the second and third directions, extending in the first direction, and stacked in the first direction, A plurality of memory units stacked in the first direction, arranged in the second and third directions, and electrically connected to each of the plurality of semiconductor layers, Multiple gate electrodes stacked in the first direction, arranged in the second and third directions, and facing each of the multiple semiconductor layers, A plurality of wiring members stacked in the first direction, arranged in the second and third directions, and each positioned between two adjacent gate electrodes in the third direction among the plurality of gate electrodes, Equipped with, The plurality of gate electrodes include a plurality of first gate electrodes arranged in the third direction and provided at a first position in the first direction. The plurality of wiring members include a plurality of first wiring members provided at the first position in the first direction and arranged in the third direction, The plurality of first wiring members are electrically connected to each other via the plurality of first gate electrodes. Semiconductor memory device.

2. The facility comprises insulating layers extending in the first and third directions, The plurality of via connections include first via connections and second via connections that are adjacent to each other in the second direction via the insulating layer, The first via wiring is spaced apart from the second via wiring via the insulating layer. The semiconductor memory device according to claim 1.

3. One of the plurality of semiconductor layers is electrically connected to the first via wiring, One of the plurality of gate electrodes faces one of the plurality of semiconductor layers, One of the plurality of wiring members is connected to one of the plurality of gate electrodes, The side surface of one of the plurality of gate electrodes and one of the plurality of wiring members facing the insulating layer in the second direction is provided on the side opposite to the insulating layer in the second direction, compared to the end of the first via wiring facing the insulating layer in the second direction. The semiconductor memory device according to claim 2.

4. One of the plurality of semiconductor layers is electrically connected to the first via wiring, One of the plurality of gate electrodes faces one of the plurality of semiconductor layers, One of the plurality of wiring members is connected to one of the plurality of gate electrodes, The side surface of one of the plurality of gate electrodes and one of the plurality of wiring members on the insulating layer side in the second direction is provided on the insulating layer side in the second direction, more so than the end of the first via wiring on the insulating layer side in the second direction. The semiconductor memory device according to claim 2.

5. Each of the aforementioned via connections is electrically connected to two adjacent semiconductor layers in the second direction. The semiconductor memory device according to claim 1.

6. Each of the plurality of wiring members is in contact with two of the plurality of gate electrodes that are adjacent to each other in the third direction. The semiconductor memory device according to claim 1.

7. Each of the plurality of wiring members is in contact with two adjacent sides in the third direction of the plurality of gate electrodes in the third direction. The semiconductor memory device according to claim 1.

8. Each of the plurality of wiring members is in contact with two adjacent sides in the second direction of the plurality of gate electrodes in the third direction. The semiconductor memory device according to claim 1.

9. Each of the aforementioned plurality of wiring members is continuous with two of the plurality of gate electrodes that are adjacent to each other in the third direction. The semiconductor memory device according to claim 1.

10. A plurality of gate insulating films are stacked in the first direction and arranged in the second and third directions, and each is provided between one of the plurality of semiconductor layers and one of the plurality of gate electrodes, Multiple insulating members are stacked in the first direction, arranged in the second and third directions, and each is continuous with two adjacent gate insulating films in the third direction. Equipped with, Each of the plurality of wiring members is in contact with one side and the other side in the first direction, and both sides in the second direction, of any of the plurality of insulating members. The semiconductor memory device according to claim 9.

11. Each of the aforementioned semiconductor layers contains at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 1.

12. The aforementioned multiple memory units are multiple capacitors. The semiconductor memory device according to claim 1.

13. A plurality of other gate electrodes stacked in the first direction, arranged in the second and third directions, and electrically connected to each of the plurality of semiconductor layers, A plurality of other semiconductor layers stacked in the first direction, arranged in the second and third directions, and facing the plurality of other gate electrodes, Multiple other via connections are arranged in the second and third directions, extend in the first direction, and are electrically connected to multiple other semiconductor layers stacked in the first direction. Equipped with, The plurality of memory units are the plurality of other gate electrodes. The semiconductor memory device according to claim 1.

14. At least a portion of one of the plurality of first wiring members overlaps with one of the plurality of via wirings when viewed from the third direction. The semiconductor memory device according to claim 1.

15. A plurality of semiconductor layers stacked in a first direction and aligned in a second direction intersecting the first direction, Multiple via connections electrically connected to multiple semiconductor layers arranged in the second direction, extending in the first direction, and stacked in the first direction, A plurality of memory units stacked in the first direction, arranged in the second direction, and electrically connected to each of the plurality of semiconductor layers, A plurality of gate electrodes stacked in the first direction and aligned in the second direction, each facing the plurality of semiconductor layers, Multiple wiring members are stacked in the first direction, arranged in the second direction, and extending in a third direction intersecting the first and second directions, each connected to a plurality of gate electrodes. Equipped with, The lengths of the plurality of wiring members in the first direction are smaller than the lengths of the plurality of gate electrodes in the first direction. Semiconductor memory device.

16. The insulating layer extends in the first direction, The plurality of via connections include first via connections and second via connections that are adjacent to each other in the second direction via the insulating layer, The first via wiring is spaced apart from the second via wiring via the insulating layer. The semiconductor memory device according to claim 15.

17. One of the plurality of semiconductor layers is electrically connected to the first via wiring, One of the plurality of gate electrodes faces one of the plurality of semiconductor layers, One of the plurality of wiring members is continuous with one of the plurality of gate electrodes, The side surface of one of the plurality of gate electrodes and one of the plurality of wiring members facing the insulating layer in the second direction is provided on the side opposite to the insulating layer in the second direction, compared to the end of the first via wiring facing the insulating layer in the second direction. The semiconductor memory device according to claim 16.

18. One of the plurality of semiconductor layers is electrically connected to the first via wiring, One of the plurality of gate electrodes faces one of the plurality of semiconductor layers, One of the plurality of wiring members is continuous with one of the plurality of gate electrodes, The side surface of one of the plurality of gate electrodes and one of the plurality of wiring members on the insulating layer side in the second direction is provided on the insulating layer side in the second direction, more so than the end of the first via wiring on the insulating layer side in the second direction. The semiconductor memory device according to claim 16.

19. Each of the aforementioned via connections is electrically connected to two adjacent semiconductor layers in the second direction. The semiconductor memory device according to claim 15.

20. A plurality of gate insulating films are stacked in the first direction and arranged in the second direction, and each is provided between one of the plurality of semiconductor layers and one of the plurality of gate electrodes, Multiple insulating members are stacked in the first direction, aligned in the second direction, and extended in the third direction, each continuous with one of the multiple gate insulating films. Equipped with, Each of the plurality of wiring members is in contact with one side and the other side in the first direction, and both sides in the second direction, of any of the plurality of insulating members. The semiconductor memory device according to claim 15.

21. At least a portion of one of the plurality of wiring members overlaps with one of the plurality of via wirings when viewed from the third direction. The semiconductor memory device according to claim 15.

22. Each of the aforementioned semiconductor layers contains at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 15.

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