Semiconductor equipment

Abstract

To provide a semiconductor device that consumes low power and operates optimally. [Solution] The semiconductor device comprises: a first transistor of a first conductivity type, whose source electrode is electrically connected to a first voltage supply line, its drain electrode to a first node, and its gate electrode to a signal input terminal; a second transistor of a second conductivity type, whose source electrode is electrically connected to a second voltage supply line, its drain electrode to a second node, and its gate electrode to a signal input terminal; a third transistor of a second conductivity type, whose source electrode is electrically connected to a second node, its drain electrode to a first node, and its gate electrode to a signal input terminal; and a fourth transistor of a second conductivity type, whose source electrode is electrically connected to a second node, its drain electrode to a first voltage supply line, and whose gate electrode receives a signal from the first node. The current capability of the second transistor and the third transistor are higher than the current capability of the first transistor.

Description

Technical Field

[0001] This embodiment relates to a semiconductor device.

Background Art

[0002] A semiconductor device including a signal input terminal capable of inputting a signal and an inverter circuit whose input terminal is connected to the signal input terminal is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor device that operates preferably with low power consumption.

Means for Solving the Problems

[0005] A semiconductor device according to one embodiment includes a signal input terminal capable of receiving a signal, a first transistor of a first conductivity type, a second transistor of a second conductivity type, a third transistor of a second conductivity type, and a fourth transistor of a second conductivity type. The first transistor has its source electrode electrically connected to a first voltage supply line, its drain electrode electrically connected to a first node, and its gate electrode electrically connected to the signal input terminal. The second transistor has its source electrode electrically connected to a second voltage supply line, its drain electrode electrically connected to a second node, and its gate electrode electrically connected to the signal input terminal. The third transistor has its source electrode electrically connected to a second node, its drain electrode electrically connected to a first node, and its gate electrode electrically connected to the signal input terminal. The fourth transistor has its source electrode electrically connected to a second node, its drain electrode electrically connected to a first voltage supply line, and the signal from the first node is input to its gate electrode. The current capability of the second transistor and the third transistor are higher than the current capability of the first transistor. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic block diagram showing the configuration of the memory system 10. [Figure 2] This is a schematic side view showing an example configuration of the memory system 10. [Figure 3] This is a schematic plan view illustrating the same configuration example. [Figure 4] This is a schematic block diagram showing the configuration of the memory die MD. [Figure 5] This is a schematic circuit diagram showing a part of the configuration of the memory die MD. [Figure 6] This is a schematic perspective view showing a portion of the configuration of the memory die MD. [Figure 7] This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit. [Figure 8] This is a schematic graph illustrating the operation of the chip enable signal detection circuit. [Figure 9]This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit. [Figure 10] This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit. [Figure 11] This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit. [Figure 12] This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit. [Figure 13] This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit according to the second embodiment. [Figure 14] This is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit according to the third embodiment. [Modes for carrying out the invention]

[0007] Next, a semiconductor device according to an embodiment will be described in detail with reference to the drawings. It should be noted that the following embodiments are merely examples and are not intended to limit the scope of the present invention.

[0008] Furthermore, in this specification, the term "semiconductor device" may refer to a semiconductor memory device or other semiconductor devices. Also, in this specification, the term "semiconductor memory device" may refer to a memory die (memory chip), or to a memory system including a controller die, such as a memory card or SSD. It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer. In this specification, NAND flash memory is used as an example of a semiconductor memory device. However, a semiconductor memory device may be a memory other than NAND flash memory.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] [First Embodiment] [Memory System 10] Figure 1 is a schematic block diagram showing the configuration of the memory system 10.

[0013] The memory system 10 reads, writes, erases, etc., user data in response to signals transmitted from the host computer 20. The memory system 10 is, for example, a memory card, SSD, or other system capable of storing user data. The memory system 10 comprises a plurality of memory dies MD for storing user data, and a controller die CD connected to these plurality of memory dies MD and the host computer 20. The controller die CD includes, for example, a processor, RAM, etc., and performs processing such as logical address-to-physical address conversion, bit error detection / correction, garbage collection (compaction), and wear leveling.

[0014] Figure 2 is a schematic side view showing an example configuration of the memory system 10 according to this embodiment. Figure 3 is a schematic top view showing the same configuration example. For the sake of explanation, some components are omitted in Figures 2 and 3.

[0015] As shown in Figure 2, the memory system 10 according to this embodiment comprises a mounting substrate MSB, a plurality of memory dies MD stacked on the mounting substrate MSB, and a controller die CD stacked on the memory dies MD. Pad electrodes P are provided on the upper surface of the mounting substrate MSB at the Y-direction end region, and some other regions are bonded to the lower surface of the memory dies MD via adhesive or the like. Pad electrodes P are provided on the upper surface of the memory dies MD at the Y-direction end region, and other regions are bonded to the lower surface of other memory dies MD or controller die CD via adhesive or the like. Pad electrodes P are provided on the upper surface of the controller die CD at the Y-direction end region.

[0016] As shown in Figure 3, the mounting substrate MSB, the multiple memory dies MD, and the controller die CD each have multiple pad electrodes P arranged in the X direction. The multiple pad electrodes P on the mounting substrate MSB, the multiple memory dies MD, and the controller die CD are each connected to one another via bonding wires B.

[0017] Note that the configurations shown in Figures 2 and 3 are merely examples, and the specific configuration can be adjusted as appropriate. For example, in the examples shown in Figures 2 and 3, controller dies CD are stacked on multiple memory dies MD, and these components are connected by bonding wires B. In such a configuration, multiple memory dies MD and controller dies CD are contained within a single package. However, the controller die CD may be contained in a separate package from the memory dies MD. Also, multiple memory dies MD and controller dies CD may be connected to each other via through-electrodes or the like, instead of bonding wires B.

[0018] [Memory die MD configuration] Figure 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. Figure 5 is a schematic circuit diagram showing a part of the configuration of the memory die MD. Figure 6 is a schematic perspective view showing a part of the configuration of the memory die MD.

[0019] Figure 4 illustrates multiple control terminals. These control terminals may be represented as terminals corresponding to high-active signals (positive logic signals), as terminals corresponding to low-active signals (negative logic signals), or as terminals corresponding to both high-active and low-active signals. In Figure 4, the symbols for control terminals corresponding to low-active signals include an overline. In this specification, the symbols for control terminals corresponding to low-active signals include a slash (" / "). Note that the description in Figure 4 is illustrative, and the specific configuration can be adjusted as appropriate. For example, some or all high-active signals may be treated as low-active signals, or some or all low-active signals may be treated as high-active signals.

[0020] Furthermore, arrows indicating input / output directions are illustrated next to the multiple control terminals shown in Figure 4. In Figure 4, control terminals with arrows pointing from left to right can be used for inputting data or other signals from the controller die CD to the memory die MD. In Figure 4, control terminals with arrows pointing from right to left can be used for outputting data or other signals from the memory die MD to the controller die CD. In Figure 4, control terminals with arrows pointing in both directions can be used for both inputting data or other signals from the controller die CD to the memory die MD, and outputting data or other signals from the memory die MD to the controller die CD.

[0021] As shown in Figure 4, the memory die MD comprises a memory cell array MCA for storing user data and a peripheral circuit PC connected to the memory cell array MCA.

[0022] [Memory Cell Array (MCA) Configuration] As shown in Figure 5, the memory cell array MCA comprises multiple memory blocks BLK. Each of these memory blocks BLK comprises multiple string units SU. Each of these string units SU comprises multiple memory strings MS. One end of each of these memory strings MS is connected to a peripheral circuit PC via a bit line BL. The other end of each of these memory strings MS is connected to the peripheral circuit PC via a common source line SL.

[0023] The memory string MS comprises a drain-side selection transistor STD, multiple memory cells MC (memory cell transistors), and a source-side selection transistor STS, all connected in series between the bit line BL and the source line SL. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors STD, STS, etc.

[0024] A memory cell MC is a field-effect transistor comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage film. The memory cell MC stores one or more bits of user data. Word lines WL are connected to the gate electrodes of multiple memory cell MCs corresponding to one memory string MS. These word lines WL are each commonly connected to all memory string MS in one memory block BLK.

[0025] The selection transistors STD and STS are field-effect transistors comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrodes of the selection transistors STD and STS are connected to selection gate lines SGD and SGS, respectively. The drain-side selection gate line SGD is provided corresponding to a string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all memory strings MS in a memory block BLK.

[0026] The memory cell array MCA is provided above the semiconductor substrate 100, as shown in Figure 6, for example. Furthermore, multiple transistors Tr, which constitute the peripheral circuit PC, are provided on the upper surface of the semiconductor substrate 100. Each of these transistors Tr comprises a channel region that forms part of the upper surface of the semiconductor substrate 100, a gate insulating film formed on the upper surface of the semiconductor substrate 100, and a gate electrode facing the channel region via the gate insulating film.

[0027] The memory cell array MCA comprises multiple memory blocks BLK aligned in the Y direction. An interblock insulating layer ST, such as silicon oxide (SiO2), is provided between two adjacent memory blocks BLK in the Y direction. Furthermore, multiple bit lines BL, aligned in the X direction and extending in the Y direction, are provided above the memory cell array MCA.

[0028] The memory block BLK comprises a plurality of conductive layers 110 aligned in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gate insulating films 130 provided between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120, respectively.

[0029] The conductive layer 110 is a substantially plate-shaped conductive layer stretched in the X direction. The conductive layer 110 may contain a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also contain polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between a plurality of conductive layers 110 aligned in the Z direction.

[0030] Furthermore, one or more of the conductive layers 110 located at the bottom of the multiple conductive layers 110 function as gate electrodes for the source-side selection gate line SGS (Figure 5) and the multiple source-side selection transistors STS (Figure 5) connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0031] Furthermore, the multiple conductive layers 110 located above this function as gate electrodes for the word line WL (Figure 5) and the multiple memory cells MC (Figure 5) connected thereto. Each of these multiple conductive layers 110 is electrically independent for each memory block BLK.

[0032] Furthermore, one or more conductive layers 110 located above this function as gate electrodes for the drain-side selection gate wire SGD (Figure 5) and the multiple drain-side selection transistors STD (Figure 5) connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the other conductive layers 110.

[0033] A semiconductor layer 112 is provided below the multiple conductive layers 110. The semiconductor layer 112 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101, such as silicon oxide (SiO2), is provided between the semiconductor layer 112 and the conductive layers 110.

[0034] The semiconductor layer 112 functions as a source line SL (Figure 5). The source line SL is provided in common for all memory blocks BLK included in the memory cell array MCA, for example.

[0035] The semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions, as shown in Figure 6, for example. The semiconductor pillars 120 function as channel regions for multiple memory cells MC and selection transistors STD and STS included in one memory string MS (Figure 5). The semiconductor pillars 120 are semiconductor layers, such as polycrystalline silicon (Si). The semiconductor pillars 120 have a substantially cylindrical shape, as shown in Figure 6, for example, and an insulating layer 125, such as silicon oxide, is provided in the central portion. The outer surfaces of the semiconductor pillars 120 are each surrounded by conductive layers 110 and face the conductive layers 110.

[0036] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the end of the semiconductor column 120 on the bit line BL side. The impurity region 121 is connected to the bit line BL via contacts Ch and Cb.

[0037] The gate insulating film 130 has a substantially cylindrical shape that covers the outer surface of the semiconductor column 120. The gate insulating film 130 includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film laminated between the semiconductor column 120 and the conductive layer 110. The tunnel insulating film and the block insulating film are insulating films such as silicon oxide (SiO2). The charge storage film is a charge-storing film such as silicon nitride (SiN). The tunnel insulating film, the charge storage film, and the block insulating film have a substantially cylindrical shape and extend in the Z direction along the outer surface of the semiconductor column 120, excluding the contact portion between the semiconductor column 120 and the semiconductor layer 112.

[0038] Furthermore, the gate insulating film 130 may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

[0039] Multiple conductive layers 110 are connected to multiple contact CCs. The multiple conductive layers 110 are electrically connected to the peripheral circuit PC via these multiple contact CCs. As shown in Figure 6, these multiple contact CCs extend in the Z direction and are connected to the conductive layer 110 at their lower ends. The contact CCs may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0040] Furthermore, the memory cell array MCA may be formed upside down. That is, the bit lines BL may be located below multiple memory blocks BLK. Also, the semiconductor layer 112 may be located above multiple conductive layers 110.

[0041] [Peripheral Circuit PC Configuration] The peripheral circuit PC includes, for example, a row decoder RD and a sense amplifier SA connected to the memory cell array MCA, and a cache memory CM connected to the sense amplifier, as shown in Figure 4. The peripheral circuit PC also includes a voltage generation circuit VG and a sequencer SQC. Furthermore, the peripheral circuit PC includes an input / output control circuit I / O, a logic circuit CTR, an address register ADR, a command register CMR, and a status register STR.

[0042] The row decoder RD (Figure 4) includes, for example, a block decoder that decodes a portion of the row address RA included in the address data Add, and multiple word line selection transistors that, in accordance with the output signal of the block decoder, connect multiple word lines WL (Figure 5) included in one of the multiple memory blocks BLK to multiple voltage supply lines (not shown).

[0043] The sense amplifier SA comprises multiple sense circuits and multiple voltage transfer circuits connected to multiple bit lines BL, and a data latch circuit. The sense circuits latch "0" or "1" data based on the voltage or current of the bit line BL to the data latch circuit, for example, according to a control signal from the sequencer SQC. The voltage transfer circuits adjust the voltage of the bit line BL to "H" or "L" based on the "0" or "1" data latched to the data latch circuit, for example, according to a control signal from the sequencer SQC. User data Dat in the data latch circuit is output to the input / output control circuit I / O via the cache memory CM and data bus DB. User data Dat output from the input / output control circuit I / O is latched to the data latch circuit in the sense amplifier SA via the data bus DB and cache memory CM.

[0044] The voltage generation circuit VG (Figure 4) includes, for example, a boost circuit such as a charge pump circuit and a buck circuit such as a regulator. These boost and buck circuits each control the power supply voltage V CC and ground voltage V SS It is connected to a voltage supply line to which the voltage is supplied. These voltage supply lines are connected to the pad electrodes P, as explained with reference to Figures 2 and 3. The voltage generation circuit VG generates multiple operating voltages to be applied to the bit line BL, source line SL, word line WL, and selection gate lines SGD, SGS during read, write, and erase operations on the memory cell array MCA, according to a control signal from the sequencer SQC, and supplies these voltages to the bit line BL, source line SL, word line WL, and selection gate lines SGD, SGS via multiple voltage supply lines. The operating voltage output from the voltage supply line 31 is adjusted as appropriate according to the control signal from the sequencer SQC. The voltage generation circuit VG also generates the operating voltage V, which will be described later. DD It also generates and supplies it to each circuit via the voltage supply line.

[0045] The SQC sequencer outputs internal control signals to the row decoder RD, sense amplifier module SAM, and voltage generation circuit VG according to the command data Cmd input to the command register CMR. The SQC sequencer also outputs status data Stt, which indicates the state of the memory die MD, to the status register STR as needed.

[0046] Furthermore, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / / BY. The terminal RY / / BY is in the "L" state when operations that supply voltage to the memory cell array MCA are being performed, such as read operations, write operations, and erase operations, and is in the "H" state at all other times. During the period when the terminal RY / / BY is in the "L" state (busy period), access to the memory die MD is basically prohibited. Conversely, during the period when the terminal RY / / BY is in the "H" state (ready period), access to the memory die MD is permitted. The terminal RY / / BY is implemented by the pad electrode P, as explained with reference to Figures 2 and 3.

[0047] As shown in Figure 4, the address register ADR is connected to the input / output control circuit I / O and stores the address data Add input from the input / output control circuit I / O. The address register ADR comprises, for example, multiple 8-bit register sequences. When internal operations such as read, write, or erase operations are performed, the register sequences hold the address data Add corresponding to the internal operation being performed.

[0048] The address data Add includes, for example, the column address CA (Figure 4) and the row address RA (Figure 4). The row address RA includes, for example, the block address that identifies the memory block BLK (Figure 5), the page address that identifies the string unit SU and the word line WL, the plane address that identifies the memory cell array MCA, and the chip address that identifies the memory die MD.

[0049] The command register CMR is connected to the input / output control circuit I / O, and receives command data Cmd from the I / O. When command data Cmd is input to the command register CMR, a control signal is sent to the sequencer SQC.

[0050] The status register STR is connected to the input / output control circuit (I / O) and stores status data Stt that is output to the I / O control circuit. The status register STR comprises, for example, multiple 8-bit register sequences. When internal operations such as read, write, or erase operations are performed, the register sequences hold status data Stt related to the internal operation being performed. The register sequences also hold, for example, ready / busy information for the memory cell array (MCA).

[0051] The input / output control circuit (I / O) comprises data signal input / output terminals DQ0 to DQ7, data strobe signal input / output terminals DQS and DQS, a shift register, and multiple input and output circuits connected to the data signal input / output terminals DQ0 to DQ7, respectively. The input circuits are, for example, receivers such as comparators, and the output circuits are, for example, drivers such as OCD (Off Chip Driver) circuits.

[0052] Each of the data signal input / output terminals DQ0 to DQ7 and the data strobe signal input / output terminals DQS, / DQS are implemented by the pad electrodes P, as described with reference to Figures 2 and 3. Data input via the data signal input / output terminals DQ0 to DQ7 is input to the cache memory CM, address register ADR, or command register CMR in accordance with the internal control signal from the logic circuit CTR. Data output via the data signal input / output terminals DQ0 to DQ7 is output from the cache memory CM or status register STR in accordance with the internal control signal from the logic circuit CTR.

[0053] Signals input via the data strobe signal input / output terminals DQS, / DQS (e.g., data strobe signals and their complementary signals) are used when inputting data via the data signal input / output terminals DQ0 to DQ7.

[0054] The logic circuit CTR comprises multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE, and logic circuits connected to these multiple external control terminals / CE, CLE, ALE, / WE, / RE, RE. The logic circuit CTR receives external control signals from the controller die CD via the external control terminals / CE, CLE, ALE, / WE, / RE, RE, and outputs internal control signals to the input / output control circuit I / O accordingly. In the following description, the external control terminal / CE may be referred to as the "chip enable signal input terminal / CE".

[0055] Furthermore, each of the external control terminals / CE, CLE, ALE, / WE, / RE, and RE is implemented by the pad electrode P, as explained with reference to Figures 2 and 3.

[0056] Signals input via the external control terminal / CE (e.g., the chip enable signal) are used when selecting the memory die MD. When "L" is input to the external control terminal / CE, the memory die MD becomes capable of inputting and outputting user data Dat, command data Cmd, and address data Add (hereinafter sometimes simply referred to as "data"). When "H" is input to the external control terminal / CE, the memory die MD becomes incapable of inputting and outputting data.

[0057] Signals input via the external control terminal CLE (e.g., command latch enable signal) are used when using the command register CMR. When "H" is input to the external control terminal CLE, data input via the data signal input / output terminals DQ0 to DQ7 is stored as command data Cmd in the buffer memory within the input / output control circuit I / O and transferred to the command register CMR.

[0058] Signals input via the external control terminal ALE (e.g., the address latch enable signal) are used when using the address register ADR. When "H" is input to the external control terminal ALE, data input via the data signal input / output terminals DQ0 to DQ7 is stored as address data Add in the buffer memory within the input / output control circuit I / O and transferred to the address register ADR.

[0059] Furthermore, if "L" is input to both external control terminals CLE and ALE, the data input via data signal input / output terminals DQ0 to DQ7 will be stored as user data Dat in the buffer memory within the input / output control circuit I / O. The user data Dat stored in the buffer memory will be transferred to the cache memory CM via the bus DB.

[0060] Signals input via the external control terminal / WE (e.g., write enable signal) are used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is captured into the shift register within the input / output control circuit I / O at the timing of the rising edge of the voltage at the external control terminal / WE (switching of the input signal).

[0061] Furthermore, when inputting data, you may use the external control terminal / WE or the data strobe signal input / output terminals DQS, / DQS.

[0062] Signals input via the external control terminals / RE,RE (e.g., read enable signal and its complementary signal) are used when outputting data via the data signal input / output terminals DQ0 to DQ7.

[0063] [Configuration of the chip enable signal detection circuit] Figure 7 is a schematic circuit diagram showing the configuration of a chip enable signal detection circuit. Figure 7 illustrates the chip enable signal input terminal / CE and the signal detection circuit within the logic circuit CTR connected to the chip enable signal input terminal / CE. In this specification, such a signal detection circuit may be referred to as a "chip enable signal detection circuit".

[0064] As shown in Figure 7, the chip enable signal detection circuit comprises inverter circuits INV11, INV12, INV13, and INV14, and a transistor NF, which are provided in the transmission path of the chip enable signal. The inverter circuits INV11, INV12, INV13, and INV14 are CMOS inverter circuits.

[0065] The input terminal of the inverter circuit INV11 is connected to the chip enable signal input terminal / CE. The inverter circuit INV11 includes transistors P11, N111, and N112.

[0066] Transistor P11 is a P-channel field-effect transistor. The source electrode of transistor P11 is at the operating voltage V DD It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor P11 is connected to the output terminal of inverter circuit INV11. The gate electrode of transistor P11 is connected to the input terminal of inverter circuit INV11.

[0067] Transistor N111 is an N-channel field-effect transistor. The source electrode of transistor N111 is connected to the ground voltage V SS It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N111 is connected to node NN. The gate electrode of transistor N111 is connected to the input terminal of inverter circuit INV11.

[0068] Transistor N112 is an N-channel field-effect transistor. The source electrode of transistor N112 is connected to node NN. The drain electrode of transistor N112 is connected to the output terminal of inverter circuit INV11. The gate electrode of transistor N112 is connected to the input terminal of inverter circuit INV11.

[0069] The input terminal of inverter circuit INV12 is connected to the output terminal of inverter circuit INV11. Inverter circuit INV12 includes transistors P12 and N12.

[0070] Transistor P12 is a P-channel field-effect transistor. The source electrode of transistor P12 is at the operating voltage V DD It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor P12 is connected to the output terminal of inverter circuit INV12. The gate electrode of transistor P12 is connected to the input terminal of inverter circuit INV12.

[0071] Transistor N12 is an N-channel field-effect transistor. The source electrode of transistor N12 is connected to the ground voltage V SS It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N12 is connected to the output terminal of inverter circuit INV12. The gate electrode of transistor N12 is connected to the input terminal of inverter circuit INV12.

[0072] The input terminal of inverter circuit INV13 is connected to the output terminal of inverter circuit INV12. Inverter circuit INV13 includes transistors P13 and N13.

[0073] Transistor P13 is a P-channel field-effect transistor. The source electrode of transistor P13 is at the operating voltage V DDis connected to a voltage supply line to which voltage is supplied. The drain electrode of transistor P13 is connected to the output terminal of inverter circuit INV13. The gate electrode of transistor P13 is connected to the input terminal of inverter circuit INV13.

[0074] Transistor N13 is an N-channel field effect transistor. The source electrode of transistor N13 is connected to a voltage supply line to which ground voltage V SS is supplied. The drain electrode of transistor N13 is connected to the output terminal of inverter circuit INV13. The gate electrode of transistor N13 is connected to the input terminal of inverter circuit INV13.

[0075] The input terminal of inverter circuit INV14 is connected to the output terminal of inverter circuit INV13. Although not shown in the figure, similar to inverter circuits INV12 and INV13, inverter circuit INV14 includes a P-channel field effect transistor and an N-channel field effect transistor connected in series between a voltage supply line to which operating voltage V DD is supplied and a voltage supply line to which ground voltage V SS is supplied. The drain electrodes of these two transistors are connected to the output terminal of inverter circuit INV14. Also, the gate electrodes of these two transistors are connected to the input terminal of inverter circuit INV14.

[0076] Transistor NF is an N-channel field effect transistor. The source electrode of transistor NF is connected to node NN. The drain electrode of transistor NF is connected to a voltage supply line to which operating voltage V DD is supplied. The output signal (inverted signal of the chip enable signal) of inverter circuit INV11 is input to the gate electrode of transistor NF. In the illustrated example, the gate electrode of transistor NF is connected to the output terminal of inverter circuit INV13.

[0077] [Current Capacity of Transistor] Next, we will describe the current capabilities of the multiple transistors included in the chip enable signal detection circuit. The current capabilities of transistors N111 and N112 are higher than those of the other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and the transistors in the inverter circuit INV14).

[0078] For example, the threshold voltages of transistors N111 and N112 may be lower than the threshold voltages of other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and transistors in the inverter circuit INV14).

[0079] For example, the thickness of the gate insulating film of transistors N111 and N112 may be smaller than the thickness of the gate insulating film of other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and the transistor in inverter circuit INV14).

[0080] In this specification, the term "transistor threshold voltage" refers to the absolute value of the voltage difference between the source electrode and the gate electrode at which the transistor's ON / OFF state switches.

[0081] Furthermore, for example, the channel width of transistors N111 and N112 may be larger than the channel width of other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and transistors in the inverter circuit INV14).

[0082] In this specification, each transistor can be replaced by multiple transistors connected in parallel. In such cases, the channel width of the transistor is the sum of the channel widths of two or more transistors connected in parallel.

[0083] Furthermore, for example, the channel lengths of transistors N111 and N112 may be smaller than the channel lengths of other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and transistors in the inverter circuit INV14).

[0084] In this specification, each transistor can be replaced by multiple transistors connected in series. In such cases, the channel length of the transistor is the sum of the channel lengths of two or more transistors connected in series.

[0085] The following explanation shows an example where the threshold voltages of transistors N111 and N112 are lower than the threshold voltages of other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and the transistors in the inverter circuit INV14).

[0086] [Operation of the chip enable signal detection circuit] Figure 8 is a schematic graph illustrating the operation of the chip enable signal detection circuit. The horizontal axis of Figure 8 shows the voltage at the chip enable signal input terminal / CE, and the vertical axis of Figure 8 shows the output voltage of the chip enable signal detection circuit (voltage at the output terminal of the inverter circuit INV14). Figures 9 to 12 are schematic circuit diagrams showing the configuration of the chip enable signal detection circuit. In Figure 9, the voltage at the chip enable signal input terminal / CE is the operating voltage V DD This shows the situation when the voltage at the chip enable signal input terminal / CE is the operating voltage V. DD From the operating voltage V DD and ground voltage V SS The intermediate voltage V DD Figure 11 shows the situation when the voltage decreases to / 2. SS This shows the situation when the voltage at the chip enable signal input terminal / CE is equal to the ground voltage V. SSThis shows the behavior when the voltage increases to the threshold voltage V1 of transistor N111.

[0087] As shown in Figure 9, the voltage at the chip enable signal input terminal / CE is equal to the operating voltage V DD In this case, transistor P11 is in the OFF state, transistors N111 and N112 are in the ON state, and the ground voltage V is received from the inverter circuit INV11. SS The following is output. Also, transistor P12 is in the ON state and transistor N12 is in the OFF state, and the operating voltage V is output from the inverter circuit INV12. DD The following is output. Also, transistor P13 is in the OFF state and transistor N13 is in the ON state, and the ground voltage V is output from the inverter circuit INV13. SS The following is output. Also, the operating voltage V is output from the inverter circuit INV14. DD The output is [output value]. Also, transistor NF is in the OFF state.

[0088] As shown in Figure 10, the voltage at the chip enable signal input terminal / CE is equal to the operating voltage V DD From the operating voltage V DD and ground voltage V SS The intermediate voltage V DD Even when the voltage decreases to about half, the output voltage of the inverter circuit INV11 does not switch. This is because the threshold voltage of transistor P11 is greater than the threshold voltages of transistors N111 and N112.

[0089] The voltage at the chip enable signal input terminal / CE is the above intermediate voltage V DD A threshold voltage V lower than / 2 THF When it decreases further to this level, the output voltage of the inverter circuit INV11 switches. Note that the threshold voltage V THF This is the threshold voltage of the inverter circuit INV11, not the threshold voltage of the transistor.

[0090] As shown in Figure 11, the voltage at the chip enable signal input terminal / CE is equal to the ground voltage V SSIn this case, transistor P11 is ON, transistors N111 and N112 are OFF, and the operating voltage V is output from the inverter circuit INV11. DD The following is output. Also, transistor P12 is in the OFF state and transistor N12 is in the ON state, and the ground voltage V is output from the inverter circuit INV12. SS The following is output. Also, transistor P13 is in the ON state and transistor N13 is in the OFF state, and the operating voltage V is output from the inverter circuit INV13. DD The following is output. Also, the ground voltage V is output from the inverter circuit INV14. SS The following is output. Also, transistor NF turns ON, and node NN is at the operating voltage V DD From the threshold voltage V of transistor NF TH It will be charged to the voltage after subtracting [a certain value].

[0091] As shown in Figure 12, when the voltage at the chip enable signal input terminal / CE increases to the threshold voltage V1 of transistor N111, transistor N111 turns ON. This turns the operating voltage V DD The voltage supply line that provides the voltage, and the ground voltage V SS A current path is formed between the voltage supply line to which the voltage is supplied, via transistors NF and N111. In this state, the source-drain current of transistor N111 is sufficiently small, and transistor NF is in the ON state, so the voltage at node NN is the operating voltage V DD From the threshold voltage V of transistor NF TH The voltage is maintained at the level after subtracting the specified value. As a result, the output voltage of the inverter circuit INV11 does not switch.

[0092] As the voltage at the chip enable signal input terminal / CE increases further, the source-drain current of transistor N111 increases, and the voltage at node NN gradually decreases. When the voltage difference between the chip enable signal input terminal / CE and node NN reaches the threshold voltage of transistor N112 (i.e., when the voltage at the chip enable signal input terminal / CE reaches the intermediate voltage V DD A threshold voltage V higher than / 2 THRWhen this value is reached, transistor N112 turns ON, and the output voltage of inverter circuit INV11 switches. THR This is the threshold voltage of the inverter circuit INV11, not the threshold voltage of the transistor.

[0093] [effect] In the chip enable signal detection circuit according to this embodiment, the threshold voltage V when the voltage of the chip enable signal input terminal / CE decreases is THF However, when the voltage at the chip enable signal input terminal / CE increases, the threshold voltage V THR It is smaller than that. With such a configuration, it is possible to eliminate the effects of noise and realize a semiconductor device that operates stably.

[0094] Furthermore, memory dies (MDs) generally spend more time inactive than active. Therefore, it is desirable that the leakage current in the chip enable signal detection circuit be small when the memory die (MD) is inactive. Since the chip enable signal is a low-active signal, it is desirable that the chip enable signal detection circuit have a small leakage current when the chip enable signal is high (H). To achieve this, for example, one could select a transistor with a current capability below a predetermined value as the transistor in the inverter circuit INV11.

[0095] On the other hand, the chip enable signal is a signal that activates the memory die MD. Therefore, in order to improve the response speed of the memory die MD, it is desirable that the output voltage of the chip enable signal detection circuit also switches from the high state to the low state at high speed when the chip enable signal switches from the high state to the low state. To achieve this, for example, one could select a transistor with a current capability of a predetermined value or higher as the transistor in the inverter circuit INV11.

[0096] However, in a memory die MD as illustrated in this embodiment, the types of transistors Tr formed on the upper surface of the semiconductor substrate 100 (Figure 6) are limited due to manufacturing process constraints. Consequently, each circuit within the peripheral circuit PC must be implemented using a limited number of transistor types Tr, and it may not be possible to select a transistor Tr with ideal characteristics.

[0097] Therefore, as described with reference to Figure 7, the chip enable signal detection circuit according to this embodiment includes transistor NF in addition to inverter circuits INV11, INV12, INV13, and INV14 provided in the transmission path of the chip enable signal. Furthermore, the current capability of transistors N111 and N112 is higher than that of the other transistors included in the chip enable signal detection circuit (transistors P11, P12, N12, P13, N13, NF, and the transistor in inverter circuit INV14).

[0098] With this configuration, as explained with reference to Figures 8 to 12, the threshold voltage V when the voltage of the chip enable signal input terminal / CE decreases THF The threshold voltage V when the voltage at the chip enable signal input terminal / CE increases. THR It is possible to realize semiconductor devices that are smaller and operate optimally.

[0099] Furthermore, because the current capability of transistor P11 is lower than that of transistors N111 and N112, it is possible to reduce the leakage current in the chip enable signal detection circuit when the memory die MD is not in an active state, thereby providing a semiconductor device with low power consumption.

[0100] Furthermore, the voltage at the chip enable signal input terminal / CE is the operating voltage V DD In this case, since the transistor NF is in the OFF state, the response speed when the chip enable signal switches from the H state to the L state is high, making it possible to provide a semiconductor device that operates optimally.

[0101] [Second Embodiment] Next, a semiconductor device according to the second embodiment will be described with reference to Figure 13. Figure 13 is a schematic circuit diagram showing the configuration of a chip enable signal detection circuit according to the second embodiment. In the following description, parts the same as in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0102] The semiconductor device according to the second embodiment is basically configured in the same way as the semiconductor device according to the first embodiment. However, the chip enable signal detection circuit according to the second embodiment is different from the chip enable signal detection circuit according to the first embodiment. The chip enable signal detection circuit according to the second embodiment is basically configured in the same way as the chip enable signal detection circuit according to the first embodiment.

[0103] However, the chip enable signal detection circuit according to the second embodiment includes an inverter circuit INV21 instead of an inverter circuit INV11. Furthermore, the chip enable signal detection circuit according to the second embodiment includes switch transistors N212, N213, and P211.

[0104] The inverter circuit INV21 is basically configured the same way as the inverter circuit INV11. However, the inverter circuit INV21 also includes a transistor N211.

[0105] Transistor N211 is an N-channel field-effect transistor. The source electrode of transistor N211 is connected to the ground voltage V SS It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N211 is connected to the output terminal of inverter circuit INV21. The gate electrode of transistor N211 is connected to the input terminal of inverter circuit INV21.

[0106] Furthermore, the current capacity of transistors N111 and N112 is higher than that of transistor N211.

[0107] Switch transistor N212 is an N-channel field-effect transistor. Switch transistor N212 is connected to transistor N211 and the ground voltage V SS It is electrically connected between the voltage supply lines that are supplied with the ground voltage V. SS It is connected to the voltage supply line that provides the voltage. Also, the drain electrode of switch transistor N212 is connected to the source electrode of transistor N211. The gate electrode of switch transistor N212 is connected to the signal line SW1.

[0108] Switch transistor N213 is an N-channel field-effect transistor. Switch transistor N213 is connected to transistor N112 and the ground voltage V SS It is electrically connected between the voltage supply lines that are supplied with the ground voltage V. SS It is connected to the voltage supply line that provides the voltage. Also, the drain electrode of switch transistor N213 is connected to the source electrode of transistor N112. The gate electrode of switch transistor N213 is connected to the signal line SW2.

[0109] Switch transistor P211 is a P-channel field-effect transistor. Switch transistor P211 has transistor NF and operating voltage V DD It is electrically connected between the voltage supply lines to which the operating voltage V is supplied. That is, the source electrode of the switch transistor P211 is electrically connected to the operating voltage V DD It is connected to the voltage supply line that provides the voltage. Also, the drain electrode of switch transistor P211 is connected to the drain electrode of transistor NF. The gate electrode of switch transistor P211 is connected to the signal line SW3.

[0110] The chip enable signal detection circuit according to the second embodiment can be operated in two modes.

[0111] In the first operating mode, the signal on signal line SW1 is set to the L state, the signal on signal line SW2 is set to the H state, and the signal on signal line SW3 is set to the L state. As a result, the chip enable signal detection circuit according to the second embodiment operates in the same manner as the chip enable signal detection circuit according to the first embodiment.

[0112] In the second operating mode, the signal on signal line SW1 is set to H, the signal on signal line SW2 is set to L, and the signal on signal line SW3 is set to H. As a result, the chip enable signal detection circuit according to the second embodiment operates in a different manner than the chip enable signal detection circuit according to the first embodiment. Specifically, the threshold voltage of the inverter circuit INV21 when the voltage at the chip enable signal input terminal / CE decreases matches the threshold voltage of the inverter circuit INV21 when the voltage at the chip enable signal input terminal / CE increases. In this case, the threshold voltage of the inverter circuit INV21 is equal to the operating voltage V DD and ground voltage V SS The intermediate voltage V DD It will be approximately half.

[0113] [Third Embodiment] In the first and second embodiments, examples were described in which the chip enable signal is a low-active signal. However, even if the chip enable signal were a high-active signal, a semiconductor device that operates suitably with low power consumption can be provided by adopting a configuration similar to that of the first and second embodiments. To this end, for example, in the chip enable signal detection circuit according to the first or second embodiment, an N-channel field-effect transistor and a P-channel field-effect transistor can be swapped, and the operating voltage V DD The voltage supply line and ground voltage V are supplied. SS This can be done by swapping it with the voltage supply line that is supplied with the voltage. Below, an example of such a semiconductor device according to the third embodiment will be described.

[0114] Figure 14 is a schematic circuit diagram showing the configuration of the chip enable signal detection circuit according to the third embodiment. In the following description, parts the same as in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0115] The semiconductor device according to the third embodiment is basically configured the same as the semiconductor device according to the first embodiment. However, the chip enable signal according to the third embodiment is a high-active signal, not a low-active signal. Also, the chip enable signal detection circuit according to the third embodiment is different from the chip enable signal detection circuit according to the first embodiment. The chip enable signal detection circuit according to the third embodiment is basically configured the same as the chip enable signal detection circuit according to the first embodiment.

[0116] However, the chip enable signal detection circuit according to the third embodiment includes an inverter circuit INV31 and a transistor PF instead of the inverter circuit INV11 and transistor NF.

[0117] The inverter circuit INV31 is a CMOS inverter circuit. The input terminal of the inverter circuit INV31 is connected to the chip enable signal input terminal CE. The inverter circuit INV31 includes transistors P311, P312, and N31.

[0118] Transistor P311 is a P-channel field-effect transistor. The source electrode of transistor P311 is at the operating voltage V DD It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor P311 is connected to node NP. The gate electrode of transistor P311 is connected to the input terminal of inverter circuit INV31.

[0119] Transistor P312 is a P-channel field-effect transistor. The source electrode of transistor P312 is connected to node NP. The drain electrode of transistor P312 is connected to the output terminal of inverter circuit INV31. The gate electrode of transistor P312 is connected to the input terminal of inverter circuit INV31.

[0120] Transistor N31 is an N-channel field-effect transistor. The source electrode of transistor N31 is connected to the ground voltage V SS It is connected to the voltage supply line that provides the voltage. The drain electrode of transistor N31 is connected to the output terminal of inverter circuit INV31. The gate electrode of transistor N31 is connected to the input terminal of inverter circuit INV31.

[0121] Transistor PF is a P-channel field-effect transistor. The source electrode of transistor PF is connected to node NP. The drain electrode of transistor PF is connected to ground voltage V SS It is connected to the voltage supply line that provides the voltage. The gate electrode of transistor PF receives the output signal of inverter circuit INV31 (the inverted signal of the chip enable signal). In the illustrated example, the gate electrode of transistor PF is connected to the output terminal of inverter circuit INV13.

[0122] The current capability of transistors P311 and P312 is higher than that of the other transistors included in the chip enable signal detection circuit (transistors N31, P12, N12, P13, N13, PF, and the transistors in inverter circuit INV14).

[0123] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0124] / CE…Chip enable signal input terminal, INV11, INV12, INV13, INV14…Inverter circuit, N111, N112, N12, N13, NF, P11, P12, P13…Transistor, NN…Node, V DD ...operating voltage, V SS ...ground voltage.

Claims

1. A signal input terminal capable of receiving signals, A first transistor of a first conductivity type, in which the source electrode is electrically connected to a first voltage supply line, the drain electrode is electrically connected to a first node, and the gate electrode is electrically connected to the signal input terminal, A second transistor of second conductivity type, in which the source electrode is electrically connected to a second voltage supply line, the drain electrode is electrically connected to a second node, and the gate electrode is electrically connected to the signal input terminal, A third transistor of second conductivity type, in which the source electrode is electrically connected to the second node, the drain electrode is electrically connected to the first node, and the gate electrode is electrically connected to the signal input terminal, A fourth transistor of second conductivity type, in which the source electrode is electrically connected to the second node, the drain electrode is electrically connected to the first voltage supply line, and the signal from the first node is input to the gate electrode. Equipped with, The current capacity of the second transistor and the current capacity of the third transistor are higher than the current capacity of the first transistor. Semiconductor equipment.

2. The threshold voltage of the second transistor and the threshold voltage of the third transistor are smaller than the threshold voltage of the first transistor. The threshold voltage of the first transistor is the absolute value of the voltage difference between the source electrode and the gate electrode at which the ON / OFF state of the first transistor switches. The threshold voltage of the second transistor is the absolute value of the voltage difference between the source electrode and the gate electrode at which the ON / OFF state of the second transistor switches. The threshold voltage of the third transistor is the absolute value of the voltage difference between the source electrode and the gate electrode at which the ON / OFF state of the third transistor switches. The semiconductor device according to claim 1.

3. The thickness of the gate insulating film of the second transistor and the thickness of the gate insulating film of the third transistor are smaller than the thickness of the gate insulating film of the first transistor. The semiconductor device according to claim 1.

4. The channel width of the second transistor and the channel width of the third transistor are greater than the channel width of the first transistor. The semiconductor device according to claim 1.

5. The channel length of the second transistor and the channel length of the third transistor are smaller than the channel length of the first transistor. The semiconductor device according to claim 1.

6. A first inverter circuit having an input terminal electrically connected to the first node and an output terminal electrically connected to the third node, A second inverter circuit having an input terminal electrically connected to the third node and an output terminal electrically connected to the gate electrode of the fourth transistor, The semiconductor device according to claim 1, further comprising:

7. The first inverter circuit is, A fifth transistor of first conductivity type, in which the source electrode is electrically connected to the first voltage supply line, the drain electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first node, A sixth transistor of second conductivity type, wherein the source electrode is electrically connected to the second voltage supply line, the drain electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first node. Equipped with, The current capability of the second transistor and the current capability of the third transistor are higher than the current capability of the sixth transistor. The semiconductor device according to claim 6.

8. A seventh transistor of second conductivity type, in which the source electrode is electrically connected to the second voltage supply line, the drain electrode is electrically connected to the first node, and the gate electrode is electrically connected to the signal input terminal, A first switch transistor electrically connected between the seventh transistor and the second voltage supply line, A second switch transistor electrically connected between the second transistor and the second voltage supply line, A third switch transistor is electrically connected between the fourth transistor and the first voltage supply line. The semiconductor device according to claim 1, further comprising:

9. The voltage supplied to the first voltage supply line is higher than the voltage supplied to the second voltage supply line. The first type of transistor is a P-channel field-effect transistor. The second type of transistor is an N-channel field-effect transistor. The semiconductor device according to claim 1.

10. The voltage supplied to the first voltage supply line is lower than the voltage supplied to the second voltage supply line. The first type of transistor is an N-channel field-effect transistor. The second type of transistor is a P-channel field-effect transistor. The semiconductor device according to claim 1.

11. It also features NAND flash memory. The semiconductor device according to claim 1.

12. A signal input terminal capable of receiving signals, A first transistor of a first conductivity type, in which the source electrode is electrically connected to a first voltage supply line, the drain electrode is electrically connected to a first node, and the gate electrode is electrically connected to the signal input terminal, A second transistor of second conductivity type, in which the source electrode is electrically connected to a second voltage supply line, the drain electrode is electrically connected to a second node, and the gate electrode is electrically connected to the signal input terminal, A third transistor of second conductivity type, in which the source electrode is electrically connected to the second node, the drain electrode is electrically connected to the first node, and the gate electrode is electrically connected to the signal input terminal, A fourth transistor of second conductivity type, in which the source electrode is electrically connected to the second node, the drain electrode is electrically connected to the first voltage supply line, and the signal from the first node is input to the gate electrode, A fifth transistor of the first conductivity type, in which the source electrode is electrically connected to the first voltage supply line, the drain electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first node, A sixth transistor of second conductivity type, wherein the source electrode is electrically connected to the second voltage supply line, the drain electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first node. Equipped with, The current capability of the second transistor and the current capability of the third transistor are higher than the current capability of the sixth transistor. Semiconductor equipment.

13. The threshold voltage of the second transistor and the threshold voltage of the third transistor are smaller than the threshold voltage of the sixth transistor. The threshold voltage of the second transistor is the absolute value of the voltage difference between the source electrode and the gate electrode at which the ON / OFF state of the second transistor switches. The threshold voltage of the third transistor is the absolute value of the voltage difference between the source electrode and the gate electrode at which the ON / OFF state of the third transistor switches. The threshold voltage of the sixth transistor is the absolute value of the voltage difference between the source electrode and the gate electrode at which the ON / OFF state of the first transistor switches. The semiconductor device according to claim 12.

14. The thickness of the gate insulating film of the second transistor and the thickness of the gate insulating film of the third transistor are smaller than the thickness of the gate insulating film of the sixth transistor. The semiconductor device according to claim 12.

15. A seventh transistor of second conductivity type, in which the source electrode is electrically connected to the second voltage supply line, the drain electrode is electrically connected to the first node, and the gate electrode is electrically connected to the signal input terminal, A first switch transistor electrically connected between the seventh transistor and the second voltage supply line, A second switch transistor electrically connected between the second transistor and the second voltage supply line, A third switch transistor is electrically connected between the fourth transistor and the first voltage supply line. The semiconductor device according to claim 12, further comprising the above.

16. A signal input terminal capable of receiving signals, A first transistor of a first conductivity type, in which the source electrode is electrically connected to a first voltage supply line, the drain electrode is electrically connected to a first node, and the gate electrode is electrically connected to the signal input terminal, A second transistor of second conductivity type, in which the source electrode is electrically connected to a second voltage supply line, the drain electrode is electrically connected to a second node, and the gate electrode is electrically connected to the signal input terminal, A third transistor of second conductivity type, in which the source electrode is electrically connected to the second node, the drain electrode is electrically connected to the first node, and the gate electrode is electrically connected to the signal input terminal, A fourth transistor of second conductivity type, in which the source electrode is electrically connected to the second node, the drain electrode is electrically connected to the first voltage supply line, and the signal from the first node is input to the gate electrode. Equipped with, The thickness of the gate insulating film of the second transistor and the thickness of the gate insulating film of the third transistor are smaller than the thickness of the gate insulating film of the first transistor. Semiconductor equipment.

17. A first inverter circuit having an input terminal electrically connected to the first node and an output terminal electrically connected to the third node, A second inverter circuit having an input terminal electrically connected to the third node and an output terminal electrically connected to the gate electrode of the fourth transistor, The semiconductor device according to claim 16, further comprising the following:

18. The first inverter circuit is, A fifth transistor of first conductivity type, in which the source electrode is electrically connected to the first voltage supply line, the drain electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first node, A sixth transistor of second conductivity type, wherein the source electrode is electrically connected to the second voltage supply line, the drain electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first node. Equipped with, The thickness of the gate insulating film of the second transistor and the thickness of the gate insulating film of the third transistor are smaller than the thickness of the gate insulating film of the sixth transistor. The semiconductor device according to claim 17.

19. A seventh transistor of second conductivity type, in which the source electrode is electrically connected to the second voltage supply line, the drain electrode is electrically connected to the first node, and the gate electrode is electrically connected to the signal input terminal, A first switch transistor electrically connected between the seventh transistor and the second voltage supply line, A second switch transistor electrically connected between the second transistor and the second voltage supply line, A third switch transistor is electrically connected between the fourth transistor and the first voltage supply line. The semiconductor device according to claim 16, further comprising the following:

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