Semiconductor memory

Abstract

To provide a semiconductor memory device that operates optimally. [Solution] The semiconductor memory device comprises a plurality of first semiconductor layers stacked in a first direction, via wiring electrically connected to the plurality of first semiconductor layers, a plurality of memory sections electrically connected to the plurality of first semiconductor layers, and a plurality of first gate electrodes facing the plurality of first semiconductor layers. The semiconductor memory device also comprises a first wiring and a second wiring provided on one side and the other side in the first direction with respect to the plurality of first semiconductor layers, a second semiconductor layer provided between the plurality of first semiconductor layers and the first wiring and electrically connected to the via wiring, a first connecting electrode electrically connected to the first wiring and the second semiconductor layer, a second gate electrode facing the second semiconductor layer, a third semiconductor layer provided between the plurality of first semiconductor layers and the second wiring and electrically connected to the via wiring, a second connecting electrode electrically connected to the second wiring and the third semiconductor layer, and a third gate electrode facing the third semiconductor layer.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] With the increasing integration of semiconductor memory devices, research into the three-dimensionalization of semiconductor memory devices is progressing. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0068933 [Patent Document 2] U.S. Patent Application Publication No. 2020 / 0303400 [Patent Document 3] U.S. Patent Application Publication No. 2022 / 0005830 [Overview of the project] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that operates optimally. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a plurality of first semiconductor layers stacked in a first direction, via wirings extended in the first direction and electrically connected to the plurality of first semiconductor layers, a plurality of memory sections aligned in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first semiconductor layers, and a plurality of first gate electrodes aligned in the first direction corresponding to the plurality of first semiconductor layers and facing the plurality of first semiconductor layers. The semiconductor memory device also includes a first wiring provided on one side in the first direction with respect to the plurality of first semiconductor layers, a second semiconductor layer provided between the plurality of first semiconductor layers and the first wiring and electrically connected to the via wiring, a first connecting electrode provided between the plurality of memory sections and the first wiring and electrically connected to the first wiring and the second semiconductor layer, and a second gate electrode provided between the plurality of first gate electrodes and the first wiring and facing the second semiconductor layer. Furthermore, this semiconductor memory device includes a second wiring provided on the other side in the first direction with respect to a plurality of first semiconductor layers, a third semiconductor layer provided between the plurality of first semiconductor layers and the second wiring and electrically connected to via wiring, a second connecting electrode provided between the plurality of memory sections and the second wiring and electrically connected to the second wiring and the third semiconductor layer, and a third gate electrode provided between the plurality of first gate electrodes and the second wiring and facing the third semiconductor layer. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic circuit diagram illustrating the read operation of the semiconductor memory device. [Figure 3] This is a schematic XY cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 4] This is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device. [Figure 5] This is a schematic XY cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 6] This is a schematic XZ cross-sectional view showing a portion of the configuration of the semiconductor memory device. [Figure 7]It is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor memory device. [Figure 8] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 9] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 10] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 11] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 12] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 13] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 14] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 15] It is a schematic cross-sectional view for explaining the manufacturing method. [Figure 16] It is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 17] It is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 18] It is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 19] It is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 20] It is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 21] It is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. [Figure 22] It is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 23] It is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 24]This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 25] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. [Figure 26] This is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the seventh embodiment. [Figure 27] This is a schematic XY cross-sectional view showing some of the configurations of a semiconductor memory device according to other embodiments. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and the second configuration is electrically connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction intersecting a predetermined surface may be referred to as the first direction, and the direction intersecting the first direction along this surface may be referred to as the second direction. The direction intersecting the second direction along this surface may be referred to as the third direction. The first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0015] Furthermore, in this specification, when we refer to the "center position" of a certain configuration, it may mean, for example, the center of the circumscribed circle of the configuration, or it may mean the centroid of the configuration on the image.

[0016] [First Embodiment] [Circuit Configuration] Figure 1 is a schematic circuit diagram showing a part of the configuration of a semiconductor memory device according to the first embodiment. As shown in Figure 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory structures MS. In Figure 1, two of these plurality of memory structures MS are exemplified as memory structures MS0 and MS1. The memory cell array MCA also includes a plurality of global bit lines GBL and plate lines PL connected to these plurality of memory structures MS. Each of the plurality of memory structures MS includes a plurality of memory layers ML. In Figure 1, three of these plurality of memory layers ML are exemplified as memory layers MLa to MLc. Each of the plurality of memory structures MS also includes transistor layers TLs and TLu, and a plurality of bit lines BL connected to these plurality of memory layers ML and transistor layers TLs and TLu. Hereinafter, the bit line BL in memory structure MS0 may be referred to as "bit line BL0", and the bit line BL in memory structure MS1 may be referred to as "bit line BL1".

[0017] Each memory layer ML comprises a word line WL and a plurality of memory cells MC connected to the word line WL. Hereinafter, the word line WL in memory structure MS0 may be referred to as "word line WL0," and the word line WL in memory structure MS1 may be referred to as "word line WL1." Each memory cell MC comprises a transistor TrC and a capacitor CpC. One electrode of transistor TrC is connected to the bit line BL. The other electrode of transistor TrC is connected to the capacitor CpC. Note that one and the other electrode of transistor TrC function as source electrodes or drain electrodes depending on the voltage supplied to transistor TrC. The gate electrode of transistor TrC is connected to the word line WL. One electrode of capacitor CpC is connected to the other electrode of transistor TrC. The other electrode of capacitor CpC is connected to the plate line PL.

[0018] Each bit line BL is connected to multiple memory cells MC, which correspond to multiple memory layers ML.

[0019] The transistor layer TLs comprises bit line selection lines LBs and a plurality of transistors TrBs connected to the bit line selection lines LBs. Hereinafter, the bit line selection lines LBs in memory structure MS0 may be referred to as "bit line selection lines LB0s," and the bit line selection lines LBs in memory structure MS1 may be referred to as "bit line selection lines LB1s." One electrode of the transistors TrBs is connected to the global bit line GBL. The other electrode of the transistors TrBs is connected to the bit line BL. Note that one and the other electrode of the transistors TrBs function as source electrodes or drain electrodes depending on the voltage supplied to the transistors TrBs. The gate electrodes of the transistors TrBs are connected to the bit line selection lines LBs.

[0020] The transistor layer TLu comprises a bit line selection line LBu and a plurality of transistors TrBu connected to the bit line selection line LBu. Hereinafter, the bit line selection line LBu in memory structure MS0 may be referred to as "bit line selection line LB0u," and the bit line selection line LBu in memory structure MS1 may be referred to as "bit line selection line LB1u." One electrode of transistor TrBu is connected to the plate line PL. The other electrode of transistor TrBu is connected to the bit line BL. Note that one and the other electrode of transistor TrBu function as source electrodes or drain electrodes depending on the voltage supplied to transistor TrBu. The gate electrode of transistor TrBu is connected to the bit line selection line LBu.

[0021] [Read operation] Figure 2 is a schematic circuit diagram illustrating the read operation of a semiconductor memory device according to the first embodiment.

[0022] During a read operation, one of several memory structures MS is selected. Furthermore, one of several memory layers ML within the selected memory structure MS is selected. The following describes an example where memory layer MLa within memory structure MS0 is selected.

[0023] For example, in the illustrated example, in the selected memory structure MS0, a voltage V is applied to the word line WL0 in the memory layer MLa. ON The voltage V is supplied to the word line WL0 in the unselected memory layers MLb and MLC. OFF This supplies voltage V to the transistor TRC in memory layer MLa, which turns ON, while the transistor TRC in the unselected memory layers MLb and MLc turns OFF. In the illustrated example, voltage V is also supplied to the bit line selection line LB0s in transistor layer TLs. ON A voltage V is supplied to the bit line selection line LB0u in the transistor layer TLu. OFF This supplies power. As a result, bit line BL0 conducts to the global bit line GBL and is electrically isolated from the plate line PL.

[0024] As a result, the capacitor CpC in the memory cell MC (hereinafter sometimes referred to as the "selected memory cell MC") that is the target of the read operation becomes conductive with the global bit line GBL via the bit line BL. Consequently, the voltage of the global bit line GBL fluctuates, or current flows through the global bit line GBL. By detecting this voltage fluctuation or current, it is possible to read the data stored in the selected memory cell MC.

[0025] Furthermore, in the illustrated example, in the memory structure MS1 that was not selected, a voltage V is applied to the word line WL1 in all memory layers MLa, MLb, and MLc. OFF This supplies voltage V to all memory layers MLa, MLb, and MLc, causing transistors TRC to be in the OFF state. In the illustrated example, voltage V is also supplied to the bit line selection line LB1s in the transistor layer TLs. OFF A voltage V is supplied to the bit line selection line LB1u in the transistor layer TLu. ON This supplies power. As a result, bit line BL1 is electrically disconnected from global bit line GBL and becomes conductive with plate line PL.

[0026] As a result, the voltage V of the plate wire PL is transmitted to the bit wire BL1. PLis supplied. As a result, it is possible to fix the voltage of the bit line BL1 and suppress deterioration of the charge holding characteristics of the memory cell MC.

[0027] In addition, the voltage V ON has a magnitude sufficient to turn on the transistors TrC, TrBs, and TrBu. The voltage V OFF has a magnitude sufficient to turn off the transistors TrC, TrBs, and TrBu. For example, when the transistors TrC, TrBs, and TrBu are NMOS transistors, the voltage V ON is greater than the voltage V OFF . Also, for example, when the transistors TrC, TrBs, and TrBu are PMOS transistors, the voltage V ON is less than the voltage V OFF .

[0028] [Structure] FIG. 3 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device according to the present embodiment. FIG. 4 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device according to the present embodiment. In FIG. 3, the structure shown in FIG. 4 is cut along the C-C' line and shown as viewed along the direction of the arrow. Also, in FIG. 3, the global bit line GBL is shown by a two-dot chain line, and a contact electrode Cb described later is shown by a dotted line. In FIG. 4, the structure shown in FIG. 3 is cut along the A-A' line and shown as viewed along the direction of the arrow.

[0029] FIG. 5 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device according to the present embodiment. In FIG. 5, a part of FIG. 3 is enlarged and shown. FIG. 6 is a schematic XZ cross-sectional view showing a partial configuration of the semiconductor memory device according to the present embodiment. In FIG. 6, the structure shown in FIG. 5 is cut along the D-D' line and shown as viewed along the direction of the arrow.

[0030] As shown in Figure 4, the semiconductor memory device according to this embodiment includes a semiconductor substrate Sub located below the memory cell array MCA. The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub, the insulating layer (not shown), and the electrode layer constitute a control circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in the region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the bit line BL via the global bit line GBL. In a read operation, the sense amplifier circuit can read data stored in the selected memory cell MC by detecting fluctuations in the voltage or current of the bit line BL.

[0031] The memory cell array MCA comprises multiple memory structures MS arranged in the X direction. A conductive layer 102 is provided between the 2n+1 (where n is a non-negative integer) memory structure MS and the 2n+2 memory structure MS, counting from one side in the X direction. An insulating layer 101, such as silicon oxide (SiO), is provided between the 2n+2 memory structure MS and the 2n+3 memory structure MS, counting from one side in the X direction. A global bit line GBL is provided above the multiple memory structures MS, and a conductive layer 106 is provided below the multiple memory structures MS as part of a plate line PL.

[0032] Furthermore, an insulating layer 107 made of silicon oxide (SiO) or the like is provided between the global bit line GBL and the multiple memory structures MS, between the plate line PL and the multiple memory structures MS, and below the plate line PL.

[0033] [Memory structure of MS] As shown in Figure 3, the memory structure MS comprises a plurality of via wirings 104 and a plurality of insulating layers 115 arranged alternately in the Y direction. Furthermore, as shown in Figure 4, the memory structure MS comprises a plurality of memory layers ML stacked in the Z direction, a transistor layer TLs provided above the plurality of memory layers ML, and a transistor layer TLu provided below the plurality of memory layers ML.

[0034] Furthermore, insulating layers 103 made of silicon oxide (SiO) or the like are provided between multiple memory layers ML, and between the bottommost memory layer ML and the transistor layer TLu. Insulating layers 105 made of silicon oxide (SiO) or the like are provided between the topmost memory layer ML and the transistor layer TLs. The thickness of insulating layer 105 in the Z direction is greater than the thickness of insulating layer 103 in the Z direction.

[0035] The via wiring 104 extends in the Z direction, penetrating multiple memory layers ML and transistor layers TLs,TLu, as shown in Figure 4, for example. The via wiring 104 includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive member 104c such as tungsten (W), as shown in Figure 6. The via wiring 104 may also contain ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. Furthermore, the via wiring 104 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals.

[0036] In this specification, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0037] The conductive member 104c has a substantially cylindrical shape that extends in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape that extends in the Z direction along the outer circumferential surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape that extends in the Z direction along the outer circumferential surface of the barrier conductive film 104b.

[0038] The via wiring 104 functions, for example, as a bit line BL (Figure 1). Multiple bit lines BL are provided, corresponding to multiple transistors TrC included in the memory layer ML, as shown in Figure 1.

[0039] The insulating layer 115 contains silicon oxide (SiO) or the like. The insulating layer 115 extends in the Z direction, penetrating multiple memory layers ML and transistor layers TLs and TLu.

[0040] [Structure of Memory Layer ML] The memory layer ML comprises, for example, as shown in Figure 3, a plurality of transistor structures 110 arranged in the Y direction corresponding to a plurality of via wirings 104, a conductive layer 120 provided between the plurality of transistor structures 110 and the insulating layer 101, and a plurality of capacitor structures 130 provided between the plurality of transistor structures 110 and the conductive layer 102.

[0041] The transistor structure 110 includes, for example, a semiconductor layer 111 connected to the outer surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the insulating layer 112.

[0042] In the XY cross-section illustrated in Figure 5, the side surface of the semiconductor layer 111 on one side in the X direction (the conductive layer 102 side) may be formed along a circle centered on the center position of the via wiring 104. The other side surface of the semiconductor layer 111, insulating layer 112, and conductive layer 113 on the other side in the X direction (the conductive layer 120 side) may be formed linearly along the side surface of the conductive layer 120. Furthermore, both sides of the semiconductor layer 111, insulating layer 112, and conductive layer 113 in the Y direction may be formed linearly along the side surface of the insulating layer 115.

[0043] The semiconductor layer 111 functions as the channel region of the transistor TrC (Figure 1). The semiconductor layer 111 may be a semiconductor containing, for example, at least one element from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or it may be another oxide semiconductor. Multiple semiconductor layers 111 aligned in the Z direction are commonly connected to via wiring 104 extending in the Z direction.

[0044] The insulating layer 112 functions as a gate insulating film of the transistor TrC (Figure 1). The insulating layer 112 contains, for example, silicon oxide (SiO).

[0045] The conductive layer 113 functions as the gate electrode of the transistor TrC (Figure 1). The conductive layer 113 contains, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). Multiple conductive layers 113 aligned in the Y direction are commonly connected to a conductive layer 120 that extends in the Y direction (see Figure 5). The conductive layer 113 faces the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112.

[0046] The conductive layer 120 functions as a word line WL (Figure 1). The conductive layer 120 is stretched in the Y direction and connected to a plurality of conductive layers 113 aligned in the Y direction. The conductive layer 120 comprises, for example, a barrier conductive film 121 made of titanium nitride (TiN) and a conductive film 122 made of tungsten (W).

[0047] The capacitor structure 130 includes, for example, a conductive layer 131, an insulating layer 132 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 110) of the conductive layer 131, and a conductive layer 133 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 110) of the insulating layer 132.

[0048] The conductive layer 131 functions as one electrode of the capacitor CpC (Figure 1). The conductive layer 131 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 131 may also contain, for example, a conductive oxide. In addition, the conductive layer 131 may contain ruthenium (Ru), iridium (Ir), or other metals instead of conductive oxides. Furthermore, the conductive layer 131 may contain only conductive oxides, or only ruthenium (Ru), iridium (Ir), or other metals. The conductive layer 131 is continuous with the conductive layer 102.

[0049] The insulating layer 132 functions as an insulating layer for the capacitor CpC (Figure 1). The insulating layer 132 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxides. Alternatively, the insulating layer 132 may be, for example, a multilayer film of multiple insulating metal oxides (e.g., a multilayer film of zirconia and alumina).

[0050] The conductive layer 133 functions as the other electrode of the capacitor CpC (Figure 1). The conductive layer 133 contains a conductive oxide such as indium tin oxide (ITO). The conductive layer 133 faces the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (conductive layer 120 side) of the conductive layer 131 via the insulating layer 132. The conductive layer 133 is connected to the X-direction side of the semiconductor layer 111.

[0051] [Structure of transistor layer TLs] As shown in Figure 4, the transistor layer TLs is basically configured similarly to the memory layer ML. However, the conductive layer 133 in the transistor layer TLs is connected to the global bit line GBL via a contact electrode Cb. Also, the upper end of the conductive layer 102 is located in the Z direction between the uppermost memory layer ML and the transistor layer TLs, and the conductive layer 131 in the transistor layer TLs is spaced apart from the conductive layer 102.

[0052] The semiconductor layer 111 in the transistor layer TLs functions as the channel region of the transistor TrBs (Figure 1). The insulating layer 112 in the transistor layer TLs functions as the gate insulating film of the transistor TrBs (Figure 1). The conductive layer 113 in the transistor layer TLs functions as the gate electrode of the transistor TrBs (Figure 1). The conductive layer 120 in the transistor layer TLs functions as the bit line selection line LBs (Figure 1). The conductive layer 133 in the transistor layer TLs functions as a connecting electrode that electrically connects one of the electrodes of the transistor TrBs to the global bit line GBL. These configurations in the transistor layer TLs are positioned to overlap with their corresponding configurations in the memory layer ML when viewed from the Z direction.

[0053] [Structure of the transistor layer TLU] The transistor layer TLu is basically constructed similarly to the memory layer ML. However, as shown in Figure 4, the conductive layer 133 in the transistor layer TLu is connected to the plate wire PL via the contact electrode Cp.

[0054] The semiconductor layer 111 in the transistor layer TLu functions as the channel region of the transistor TrBu (Figure 1). The insulating layer 112 in the transistor layer TLu functions as the gate insulating film of the transistor TrBu (Figure 1). The conductive layer 113 in the transistor layer TLu functions as the gate electrode of the transistor TrBu (Figure 1). The conductive layer 120 in the transistor layer TLu functions as the bit line selection line LBu (Figure 1). The conductive layer 133 in the transistor layer TLu functions as a connecting electrode that electrically connects one of the electrodes of the transistor TrBu to the plate line PL. These components in the transistor layer TLu are positioned to overlap with their corresponding components in the memory layer ML when viewed from the Z direction.

[0055] [Structure of conductive layer 102] The conductive layer 102 may include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). Alternatively, the conductive layer 102 may contain, for example, a conductive oxide. Furthermore, instead of a conductive oxide, the conductive layer 102 may contain ruthenium (Ru), iridium (Ir), or other metals. The conductive layer 102 may also contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals. The conductive layer 102 functions as part of the plate wire PL (Figure 1).

[0056] [Structure of Global Bit Lines (GBLs)] As shown in Figure 3, the global bit lines GBL are aligned in the Y direction and extend in the X direction, electrically connected to the conductive layer 133 in the capacitor structure 130 contained in the transistor layer TLs. In the illustrated example, the global bit lines GBL are positioned to overlap with the corresponding multiple capacitor structures 130 when viewed from the Z direction. A contact electrode Cb is also provided at the position where the global bit lines GBL and the capacitor structures 130 overlap when viewed from the Z direction. The contact electrode Cb illustrated in Figure 4 has its upper end connected to the global bit lines GBL and its lower end connected to the capacitor structure 130 in the transistor layer TLs, more specifically, to the conductive layer 133.

[0057] [Structure of conductive layer 106] The conductive layer 106 (Figure 4) is provided over a region that overlaps with all memory structures MS and all conductive layers 102 in the memory cell array MCA when viewed from the Z direction. Contact electrodes Cp are provided at the location where the conductive layer 106 and the capacitor structure 130 overlap when viewed from the Z direction. The lower end of such contact electrodes Cp is connected to the conductive layer 106, and the upper end is connected to the capacitor structure 130 in the transistor layer TLu, more specifically to the conductive layer 133. In addition, contact electrodes Cp are also provided at the location where the conductive layer 106 and the conductive layer 102 overlap when viewed from the Z direction. The lower end of such contact electrodes Cp is connected to the conductive layer 106, and the upper end is connected to the conductive layer 102.

[0058] [Manufacturing method] Figures 7 to 15 are schematic cross-sectional views illustrating the manufacturing method of a semiconductor memory device according to the first embodiment, and show the cross-section corresponding to Figure 4.

[0059] In this manufacturing method, for example, as shown in Figure 7, a plurality of memory structures MS are formed on a substrate Sub'. These plurality of memory structures MS can be formed, for example, using the manufacturing method described in Japanese Patent Application Publication No. 2024-106917.

[0060] Next, as shown in Figure 8, for example, an opening CbA is formed at the position corresponding to the contact electrode Cb. The opening CbA extends in the Z direction, penetrating the insulating layer 107 and exposing the conductive layer 133 in the transistor layer TLs. This process is performed, for example, by RIE (Reactive Ion Etching).

[0061] Next, as shown in Figure 9, for example, a contact electrode Cb is formed inside the opening CbA. This process is carried out, for example, by CVD (Chemical Vapor Deposition).

[0062] Next, as shown in Figure 10, for example, a global bit line (GBL) is formed on the exposed surfaces of the insulating layer 107 and the contact electrode Cb. This process is carried out, for example, by CVD.

[0063] Next, as shown in Figure 11, for example, the substrate Sub' is removed to expose the insulating layer 103, via wiring 104, and conductive layer 102. This step is performed by means such as CMP (Chemical Mechanical Polishing).

[0064] Next, as shown in Figure 12, for example, an insulating layer 107 is formed on the exposed surfaces of the insulating layer 103, via wiring 104, and conductive layer 102. This step is carried out by means such as CVD.

[0065] Next, as shown in Figure 13, for example, an opening CpA is formed at a position corresponding to the contact electrode Cp. The opening CpA extends in the Z direction, penetrating the insulating layer 107 and exposing the conductive layer 133 and conductive layer 102 in the transistor layer TLu. This process is performed, for example, by RIE.

[0066] Next, as shown in Figure 14, for example, a contact electrode Cp is formed inside the opening CpA. This process is carried out, for example, by CVD.

[0067] Next, as shown in Figure 15, for example, a conductive layer 106 and an insulating layer 107 are formed on the exposed surfaces of the insulating layer 107 and the contact electrode Cp. This process is carried out, for example, by CVD.

[0068] Subsequently, the formed wafer is bonded to a wafer containing the semiconductor substrate Sub (a wafer on which peripheral circuits are formed), and then diced to form individual pieces, thereby creating a semiconductor memory device according to the first embodiment. In this embodiment, the wafer containing the semiconductor substrate Sub is bonded to the insulating layer 107, but an insulating film may be provided on the global bit line GBL, and the wafer may be bonded via this insulating film.

[0069] [effect] In this embodiment, the bit line BL is electrically connected to the global bit line GBL via transistor TrBs and electrically connected to the plate line PL via transistor TrBu. With this configuration, as explained with reference to Figure 2, etc., it is possible to fix the voltage of the bit line BL in the memory structure MS that was not selected during the read operation, thereby suppressing deterioration of the charge retention characteristics of the memory cell MC.

[0070] In realizing the transistors TrBs and TrBu according to this embodiment, it is conceivable to adopt a structure similar to that of the memory layer ML. This would allow the transistors TrBs and TrBu to be formed without significantly increasing the number of manufacturing steps.

[0071] Therefore, in this embodiment, an opening CbA is formed in the process described with reference to Figure 8 to expose the conductive layer 133 in the transistor layer TLs, and a contact electrode Cb connected to this exposed surface is formed in the process described with reference to Figure 9.

[0072] Furthermore, in this embodiment, the substrate Sub' is removed in the process described with reference to Figure 11 to expose the conductive layer 102, the opening CpA is formed in the process described with reference to Figure 13 to expose the conductive layer 133 and the conductive layer 102 in the transistor layer TLu, and the contact electrode Cp is formed in the process described with reference to Figure 14 to connect to these exposed surfaces.

[0073] This method makes it possible to form transistors TrBs and TrBu with virtually no increase in the number of manufacturing steps. In other words, it is possible to provide a semiconductor memory device that can be easily manufactured.

[0074] [Second Embodiment] Figures 16 and 17 are schematic cross-sectional views showing a portion of the configuration of a semiconductor memory device according to the second embodiment. Figure 17 shows an enlarged view of a portion of the configuration shown in Figure 16. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0075] The semiconductor memory device according to the second embodiment includes a memory cell array MCA2. The memory cell array MCA2 is basically configured in the same way as the memory cell array MCA. However, as shown in Figure 16, the memory cell array MCA2 includes a memory structure MS2 instead of a memory structure MS. Furthermore, the semiconductor memory device according to the second embodiment does not include a contact electrode Cp connected to the conductive layer 133 in the conductive layer 106 and transistor layer TLu.

[0076] The memory structure MS2, like the memory structure MS, comprises multiple via connections 104 and multiple insulating layers 115 arranged alternately in the Y direction. Furthermore, the memory structure MS2 comprises two regions R arranged in the Z direction. L ,RU It includes the following: Region R U is region R L It is located above that. Also, region R L ,R U An insulating layer 205 made of silicon oxide (SiO) or the like is provided between them. The thickness of the insulating layer 205 in the Z direction is greater than the thickness of the insulating layer 105 in the Z direction.

[0077] area R L It comprises multiple memory layers ML stacked in the Z direction, and a transistor layer TLu2 provided above the multiple memory layers ML. Region R U It comprises multiple memory layers ML stacked in the Z direction, and transistor layers TLs provided above the multiple memory layers ML.

[0078] The transistor layer TLu2 is basically configured similarly to the memory layer ML. However, the transistor layer TLu2 has a structure 230 instead of a capacitor structure 130.

[0079] Structure 230 functions as a connecting electrode that electrically connects one of the electrodes of transistor TrBu to the plate wire PL. One end of structure 230 in the X direction is connected to the semiconductor layer 111 in the transistor layer TLu2, and the other end in the X direction is connected to the conductive layer 102.

[0080] Structure 230 comprises, for example, a conductive layer 231 and conductive layers 233 provided on the upper surface, lower surface, both sides in the Y direction, and one side in the X direction (towards the transistor structure 110), as shown in Figure 17.

[0081] The conductive layer 231 is configured in the same way as the conductive layer 131. When viewed from the Z direction, the conductive layer 231 is located in a position that overlaps with the conductive layer 131 and the insulating layer 132 in the memory layer ML.

[0082] The conductive layer 233 is basically constructed in the same way as the conductive layer 133. However, the conductive layer 233 is in contact with the top surface, bottom surface, both sides in the Y direction, and one side in the X direction (the side facing the transistor structure 110) of the conductive layer 231. When viewed from the Z direction, the conductive layer 233 is positioned to overlap with the conductive layer 133 in the memory layer ML.

[0083] Such a structure can be formed, for example, in the manufacturing process by removing the insulating layer 132 in the transistor layer TLu2 after forming the insulating layer 132 but before forming the conductive layer 131.

[0084] This method also makes it possible to form transistors TrBs and TrBu with virtually no increase in the number of manufacturing steps. In other words, it is possible to provide a semiconductor memory device that can be easily manufactured.

[0085] [Third Embodiment] Figure 18 is a schematic circuit diagram showing a partial configuration of a semiconductor memory device according to the third embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0086] As shown in Figure 18, the semiconductor memory device according to this embodiment includes a memory cell array MCA3. The memory cell array MCA3 includes a plurality of memory structures MS3b, a plurality of memory structures MS3p provided corresponding to these plurality of memory structures MS3b, and a plurality of global bit lines GBL and plate lines PL connected to these plurality of memory structures MS3b and MS3p.

[0087] Each of the multiple memory structures MS3b comprises multiple memory layers ML, transistor layers TLs, and multiple bit lines BL connected to these multiple memory layers ML and transistor layers TLs. These multiple bit lines BL are electrically connected to the corresponding global bit line GBL via transistors TrBs in the transistor layers TLs.

[0088] Each of the multiple memory structures MS3p comprises multiple memory layers ML, a transistor layer TLu3, and multiple bit lines BL connected to these multiple memory layers ML and transistor layer TLu3. The transistor layer TLu3 is configured in the same way as the transistor layer TLu in the first embodiment in the circuit diagram. The multiple bit lines BL are electrically connected to the plate line PL via the transistor TrBu in the transistor layer TLu3. Furthermore, these multiple bit lines BL are connected to the corresponding bit lines BL in the corresponding memory structure MS3b.

[0089] Figure 19 is a schematic XY cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment. In Figure 19, the global bit line GBL, contact electrode Cb, and contact electrode Cp3 (described later) are shown as dotted lines. Also in Figure 19, the wirings m0b and m0p in the wiring layer M0 (described later) are shown as dashed lines. Figure 20 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment. Figure 20 shows the structure shown in Figure 19 cut along line AA' and viewed in the direction of the arrow.

[0090] As shown in Figure 20, in the memory cell array MCA3, multiple memory structures MS3b and MS3p are arranged alternately in the X direction. An insulating layer 101 is provided between the p-th memory structure MS3b (where p is an integer greater than or equal to 1) and the p-th memory structure MS3p, counting from one side in the X direction. A conductive layer 102 is provided between the p-th memory structure MS3p and the (p+1)th memory structure MS3b, counting from one side in the X direction. A wiring layer M0 is provided above the multiple memory structures MS3b and MS3p, and a wiring layer M1 is provided above the wiring layer M0. The wiring layer M1 includes multiple global bit lines GBL. Below the multiple memory structures MS3b and MS3p, a conductive layer 106, contact electrodes Cp connecting the conductive layer 106 and the conductive layer 102, and a semiconductor substrate Sub (not shown in Figure 20) are provided.

[0091] Furthermore, an insulating layer 107 is provided between multiple memory structures MS and wiring layers M0, and between wiring layers M0 and wiring layers M1.

[0092] The memory structure MS3b is basically configured the same way as the memory structure MS. However, the memory structure MS3b does not have a transistor layer TLu.

[0093] The memory structure MS3p is basically configured the same way as the memory structure MS. However, the memory structure MS3p does not have a transistor layer TLu. Also, the memory structure MS3p has a transistor layer TLu3 instead of a transistor layer TLs.

[0094] The transistor layer TLu3 is basically constructed similarly to the transistor layer TLu. However, the transistor layer TLu3 is located above the multiple memory layers ML. In addition, the conductive layer 133 in the transistor layer TLu3 is connected to the conductive layer 102 (plate wire PL) via a pair of contact electrodes Cp3 and wiring m0p.

[0095] The wiring layer M0 includes, for example, as shown in Figure 19, a plurality of wirings m0b corresponding to a plurality of via wirings 104 in the memory structures MS3b and MS3p, and a plurality of wirings m0p corresponding to a plurality of conductive layers 102.

[0096] The wiring m0b is positioned to overlap, as viewed from the Z direction, with one via wiring 104 in the p-th memory structure MS3b (counting from one side in the X direction) and one via wiring 104 in the p-th memory structure MS3p (counting from one side in the X direction). Wiring m0b is electrically connected to these two corresponding via wirings 104. In the example in Figure 20, wiring m0b is connected to the upper ends of the two corresponding via wirings 104.

[0097] The wiring m0p is positioned so as to overlap with the conductive layer 102 and all the capacitor structures 130 in the memory structure MS3p when viewed from the Z direction, as shown in Figure 19, for example. The wiring m0p is electrically connected to the conductive layer 102 and the capacitor structures 130 in the memory structure MS3p and functions as part of the plate wire PL. In the example of Figure 19, contact electrodes Cp3 are provided at the positions where the wiring m0p and the conductive layer 102 overlap when viewed from the Z direction, and at the positions where the wiring m0p and the capacitor structures 130 overlap when viewed from the Z direction. As shown in Figure 20, the upper end of one contact electrode Cp3 is connected to the wiring m0p and the lower end is connected to the capacitor structure 130 in the transistor layer TLu3, more specifically to the conductive layer 133. The other contact electrode Cp3 has its upper end connected to the wiring m0p and its lower end connected to the plate wire PL, more specifically to the conductive layer 102.

[0098] In the third embodiment, via wiring 104 is electrically connected between two adjacent memory structures MS3b and MS3p in the X direction. Therefore, in memory structure MS3b, it is possible to connect the conductive layer 133 in the transistor layer TLs provided above the multiple memory layers ML to the global bit line GBL. In memory structure MS3p, it is possible to connect the conductive layer 133 in the transistor layer TLu provided above the multiple memory layers ML to the plate line PL.

[0099] Such a structure can be realized with virtually no increase in the number of manufacturing steps. Therefore, this embodiment also makes it possible to provide a semiconductor memory device that can be easily manufactured.

[0100] [Fourth Embodiment] Figure 21 is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. In the following description, parts the same as those in the third embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0101] The semiconductor memory device according to the fourth embodiment includes a memory cell array MCA4. The memory cell array MCA4 is basically configured the same as the memory cell array MCA3. However, the memory cell array MCA4 does not have wiring m0b, and instead has connection structures 404. Similar to wiring m0b, multiple connection structures 404 are provided corresponding to multiple via wirings 104 in the memory structures MS3b and MS3p.

[0102] The connection structure 404 is positioned to overlap, as viewed from the Z direction, with one via 104 in the p-th memory structure MS3b (counting from one side in the X direction) and one via 104 in the p-th memory structure MS3p (counting from one side in the X direction). The connection structure 404 is electrically connected to these two corresponding via 104s. In the example in Figure 21, the connection structure 404 is connected to the lower ends of the two corresponding via 104s.

[0103] The connection structure 404 includes, for example, a conductive oxide film 404a containing a conductive oxide, a barrier conductive film 404b such as titanium nitride (TiN), and a conductive member 404c such as tungsten (W). The conductive oxide film 404a is continuous with the conductive oxide film 104a in the via wiring 104 and contains the same material as the conductive oxide film 104a. The barrier conductive film 404b is continuous with the barrier conductive film 104b in the via wiring 104 and contains the same material as the barrier conductive film 104b. The conductive member 404c is continuous with the conductive member 104c in the via wiring 104 and contains the same material as the conductive member 104c.

[0104] Furthermore, the top, bottom, and outer surfaces of the connection structure 404 are covered by a semiconductor layer 411 and an insulating layer 412. The semiconductor layer 411 is continuous with the semiconductor layer 111 in the transistor structure 110 and contains the same material as the semiconductor layer 111. The insulating layer 412 is continuous with the insulating layer 112 in the transistor structure 110 and contains the same material as the insulating layer 112.

[0105] Such a structure can be realized with virtually no increase in the number of manufacturing steps. Therefore, this embodiment also makes it possible to provide a semiconductor memory device that can be easily manufactured.

[0106] [Fifth Embodiment] Figure 22 is a schematic circuit diagram showing a partial configuration of the semiconductor memory device according to the fifth embodiment. In the following description, parts similar to those in the third embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0107] The semiconductor memory device according to the fifth embodiment is basically configured the same as the semiconductor memory device according to the third embodiment. However, the memory cell array MCA5 according to the fifth embodiment includes multiple shielding wires SL connected to multiple memory structures MS. In addition, in the fifth embodiment, one electrode of the transistor TrBu is connected to the shielding wire SL instead of the plate wire PL.

[0108] As will be explained in more detail later, the shielded wire SL is arranged alternately with the global bit wire GBL. Furthermore, a predetermined fixed voltage is supplied to the shielded wire SL during the read operation. Therefore, during the read operation, the influence of the electric field between adjacent global bit wires GBL is suppressed, making it possible to read the charge of the capacitor CpC effectively.

[0109] Furthermore, during the read operation, a voltage V is applied to the bit line selection line LBu in the transistor layer TLu3 in the memory structure MS3p that was not selected. ON This supplies the bit line BL in the unselected memory structures MS3b and MS3p to conduct with the shield line SL, fixing the voltage of the bit line BL and suppressing the deterioration of the charge retention characteristics of the memory cell MC.

[0110] Figure 23 is a schematic XY cross-sectional view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. In Figure 23, the global bit line GBL, shield line SL, contact electrode Cb, and contact electrode Cs (described later) are shown by dotted lines. Figure 24 is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to this embodiment. Figure 24 shows a view of the structure shown in Figure 23 cut along line AA' and along the direction of the arrow. However, in Figure 24, at the height position corresponding to the global bit line GBL, a view of the structure shown in Figure 23 cut along line BB' and along the direction of the arrow is shown. Also, in Figure 24, contact electrode Cs provided at a position not corresponding to line AA' in Figure 23 is shown by a dotted line.

[0111] The semiconductor memory device according to the fifth embodiment is basically configured the same as the semiconductor memory device according to the third embodiment. However, as shown in Figure 23, in the fifth embodiment, the wiring layer M1 is provided with multiple shielding lines SL in addition to multiple global bit lines GBL. Furthermore, the semiconductor memory device according to the fifth embodiment does not have wiring m0p and contact electrodes Cp3, but instead has contact electrodes Cs.

[0112] As shown in Figure 23, multiple global bit lines GBL and multiple shield lines SL are arranged alternately in the Y direction. Each of the multiple shield lines SL is provided between two adjacent global bit lines GBL in the Y direction and extends in the X direction. In the illustrated example, the shield lines SL are provided at a position that overlaps with the capacitor structure 130 electrically connected to the corresponding bit line BL when viewed from the Z direction. A contact electrode Cs is provided at the position where the shield line SL and the capacitor structure 130 overlap when viewed from the Z direction. The upper end of the contact electrode Cs is connected to the shield line SL, and the lower end is connected to the capacitor structure 130 in the transistor layer TLu3, more specifically to the conductive layer 133.

[0113] Such a structure can be realized with virtually no increase in the number of manufacturing steps. Therefore, this embodiment also makes it possible to provide a semiconductor memory device that can be easily manufactured.

[0114] [Sixth Embodiment] Figure 25 is a schematic cross-sectional view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. In the following description, parts the same as those in the fourth and fifth embodiments are denoted by the same reference numerals and their descriptions are omitted.

[0115] The semiconductor memory device according to the sixth embodiment includes a memory cell array MCA6. The memory cell array MCA6 is basically configured the same as the memory cell array MCA5. However, the memory cell array MCA6 does not have a wiring layer M0, and instead has a connection structure 404, similar to the fourth embodiment.

[0116] Such a structure can be realized with virtually no increase in the number of manufacturing steps. Therefore, this embodiment also makes it possible to provide a semiconductor memory device that can be easily manufactured.

[0117] In particular, the semiconductor memory device according to this embodiment does not have a wiring layer M0. Therefore, it is possible to reduce the number of manufacturing steps compared to the semiconductor memory device according to the fourth embodiment.

[0118] [Seventh Embodiment] Figure 26 is a schematic cross-sectional view showing a partial configuration of a semiconductor memory device according to the seventh embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0119] The semiconductor memory device according to the seventh embodiment includes a memory cell array MCA7. The memory cell array MCA7 is basically configured the same as the memory cell array MCA. However, the memory cell array MCA7 includes a memory structure MS7 instead of a memory structure MS. Furthermore, a plurality of wirings 702 corresponding to the plurality of memory structures MS7 are provided between the plurality of memory structures MS7 and the plurality of global bit lines GBL. In addition, the memory cell array MCA7 does not include contact electrodes Cp connected to the conductive layer 106 and the conductive layer 133 in the transistor layer TLu.

[0120] The memory structure MS7 is basically configured the same way as the memory structure MS. However, the memory structure MS7 does not have a transistor layer TLu. In addition, the memory structure MS7 is provided in accordance with the multiple via wirings 104 and includes multiple transistor structures 710 located above the via wirings 104.

[0121] The transistor structure 710 comprises a cylindrical semiconductor layer 711 extending in the Z direction, an insulating layer 712 extending in the Z direction along the outer surface of the semiconductor layer 711, and a conductive layer 713 provided on the outer surface of the insulating layer 712. Furthermore, a cylindrical insulating layer 714 extending in the Z direction is provided in the central portion of the semiconductor layer 711. The insulating layer 714 contains, for example, silicon oxide (SiO).

[0122] The semiconductor layer 711 functions as the channel region of the transistor TrBu. The semiconductor layer 711 is continuous with the semiconductor layer 111 in the transistor structure 110 and contains the same material as the semiconductor layer 111.

[0123] The insulating layer 712 functions as the gate insulating film of the transistor TrBu. The insulating layer 712 is continuous with the insulating layer 112 in the transistor structure 110 and contains the same material as the insulating layer 112.

[0124] The conductive layer 713 functions as the gate electrode of the transistor TrBu and as the bit line selection line LBu (Figure 1). The conductive layer 713 includes, for example, a barrier conductive film such as titanium nitride (TiN) and a conductive material such as tungsten (W).

[0125] The wiring 702 extends in the Y direction and is commonly connected to multiple semiconductor layers 711 of multiple transistor structures 710 that are aligned in the Y direction. The wiring 702 includes, for example, a conductive oxide. The wiring 702 may also include, for example, a laminated structure of titanium nitride (TiN) and tungsten (W). During the read operation, a predetermined fixed voltage is supplied to the wiring 702.

[0126] [Other embodiments] The semiconductor memory devices according to the first to seventh embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations can be adjusted as appropriate.

[0127] For example, the configurations in the memory cell arrays MCA, MCA2, MCA3, MCA4, MCA5, MCA6, and MCA7 according to the first to seventh embodiments may be arranged upside down. For example, when the memory cell array MCA and the control circuit are formed on separate substrates and bonded together, as in the first embodiment, the global bit line GBL can be placed on the lower side to suitably connect the global bit line GBL and the sense amplifier circuit. This configuration can also be adopted for the memory cell arrays MCA2, MCA3, MCA4, MCA5, MCA6, and MCA7 according to the second to seventh embodiments.

[0128] Furthermore, in the first to seventh embodiments, for example, as illustrated in Figures 3 and 23, the positions of the via wirings 104 are approximately the same in two adjacent memory structures MS in the X direction. However, such configurations are merely illustrative, and the specific arrangement can be adjusted as appropriate.

[0129] For example, in the example shown in Figure 27, between a pair of adjacent memory structures MS3b and MS3p in the X direction, the position of the via wiring 104 included in one memory structure MS3b coincides with the position of the insulating layer 115 included in the other memory structure MS3p, and the position of the insulating layer 115 included in one memory structure MS3b coincides with the position of the via wiring 104 included in the other memory structure MS3p. With such a configuration, the central positions of the global bit line GBL, via wiring 104, and contact electrode Cb in the Y direction can be aligned, making it possible to arrange the global bit line GBL at equal intervals in the Y direction. Furthermore, in configurations including a shield wire SL, as in the fifth and sixth embodiments, the central positions of the shield wire SL, via wiring 104, and contact electrode Cs in the Y direction can be aligned, making it possible to arrange the shield wire SL at equal intervals in the Y direction.

[0130] Furthermore, in the semiconductor memory devices according to the first to seventh embodiments, the via wiring 104, which functions as a bit line BL, contains a conductive oxide such as indium tin oxide (ITO). However, such a conductive oxide may be included in the transistor structure 110 rather than in the via wiring 104 extending in the Z direction. Also, the via wiring 104 and the transistor structure 110 may contain other materials.

[0131] Furthermore, in the semiconductor memory devices according to the first to seventh embodiments, the conductive layer 113, which functions as the gate electrode of the transistor TrC, may face only one of the upper or lower surfaces of the semiconductor layer 111, which functions as the channel region of the transistor TrC.

[0132] Furthermore, the above description described an example in which a capacitor CpC is used as the memory section connected to the transistor structure 110. It also described an example in which the memory section includes one electrode, another electrode facing this electrode, and a memory film provided between them, and the memory film is an insulating metal oxide. However, the memory section does not have to be a capacitor CpC, and the memory film does not have to be an insulating metal oxide. For example, the memory film may contain a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other materials. The memory section may also record data by utilizing the properties of these materials.

[0133] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0134] Sub...semiconductor substrate, ML...memory layer, TLs, TRu...transistor layer, BL...bit line, WL...word line, GBL...global bit line, PL...plate line, TraC...transistor, CpC...capacitor, 102...conductive layer, 104...via wiring, 110...transistor structure, 111...semiconductor layer, 112...insulating layer, 113...conductive layer, 120...conductive layer, 130...capacitor structure.

Claims

1. A plurality of first semiconductor layers stacked in a first direction, via wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers, A plurality of memory units are arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first semiconductor layers, A plurality of first gate electrodes are arranged in the first direction corresponding to the plurality of first semiconductor layers and facing the plurality of first semiconductor layers, A first wiring provided on one side in the first direction for the plurality of first semiconductor layers, A second semiconductor layer is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring. A first connecting electrode is provided between the plurality of memory units and the first wiring, and is electrically connected to the first wiring and the second semiconductor layer. A second gate electrode is provided between the plurality of first gate electrodes and the first wiring, and facing the second semiconductor layer, A second wiring provided on the other side in the first direction with respect to the plurality of first semiconductor layers, A third semiconductor layer is provided between the plurality of first semiconductor layers and the second wiring, and is electrically connected to the via wiring. A second connecting electrode is provided between the plurality of memory units and the second wiring, and is electrically connected to the second wiring and the third semiconductor layer. A third gate electrode is provided between the plurality of first gate electrodes and the second wiring, and facing the third semiconductor layer. A semiconductor memory device equipped with the following features.

2. A first contact electrode is provided between the first wiring and the first connecting electrode, extending in a first direction and electrically connected to the first wiring and the first connecting electrode, A second contact electrode is provided between the second wiring and the second connecting electrode, extends in the first direction, and is electrically connected to the second wiring and the second connecting electrode. A semiconductor memory device according to claim 1, comprising:

3. Each of the aforementioned multiple memory units is, A first electrode electrically connected to a corresponding one of the plurality of first semiconductor layers, A second electrode facing the first electrode, A memory film provided between the first electrode and the second electrode and Equipped with, The second electrode is electrically connected to the second wiring. The semiconductor memory device according to claim 1.

4. The first semiconductor layer and the second semiconductor layer each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 1.

5. The device comprises a plurality of third wirings arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first gate electrodes, The first gate electrode faces one or both of the first semiconductor layer's surface in the first direction and the other surface. The memory portion is provided on one side of the first semiconductor layer in a second direction intersecting the first direction, The third wiring is provided on the other side in the second direction relative to the first semiconductor layer. The semiconductor memory device according to claim 1.

6. A plurality of first semiconductor layers stacked in a first direction, via wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers, A plurality of memory units are arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first semiconductor layers, A plurality of first gate electrodes are arranged in the first direction corresponding to the plurality of first semiconductor layers and facing the plurality of first semiconductor layers, A first wiring is provided on one side of the plurality of first semiconductor layers in the first direction and extends in a second direction intersecting the first direction, A second semiconductor layer is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring. A first connecting electrode is provided between the plurality of memory units and the first wiring, and is electrically connected to the first wiring and the second semiconductor layer. A second gate electrode is provided between the plurality of first gate electrodes and the first wiring, and facing the second semiconductor layer, A second wiring extending in the first direction and aligned with the plurality of first semiconductor layers in the second direction, A third semiconductor layer is provided in a position that overlaps with the plurality of first semiconductor layers when viewed from the first direction, and is electrically connected to the via wiring, A second connecting electrode is provided in a position that overlaps with the plurality of memory sections when viewed from the first direction, and is electrically connected to the third semiconductor layer and the second wiring, A third gate electrode is provided at a position that overlaps with the plurality of first gate electrodes when viewed from the first direction, and is facing the third semiconductor layer. A semiconductor memory device equipped with the following features.

7. Each of the aforementioned multiple memory units is, A first electrode, the end of which in the second direction is electrically connected to a corresponding one of the plurality of first semiconductor layers, The other end in the second direction is connected to the second wiring, and the second electrode faces the first electrode in the first direction, A memory film provided between the first electrode and the second electrode and Equipped with, The second connecting electrode has one end in the second direction connected to the third semiconductor layer, and the other end in the second direction connected to the second wiring. The semiconductor memory device according to claim 6.

8. A portion of the plurality of first semiconductor layers is provided on one side in the first direction relative to the third semiconductor layer. A portion of the plurality of first semiconductor layers is provided on the other side in the first direction relative to the third semiconductor layer. The semiconductor memory device according to claim 6.

9. The first semiconductor layer and the second semiconductor layer each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 6.

10. The device comprises a plurality of third wirings arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first gate electrodes, The first gate electrode faces one or both of the first semiconductor layer's surface in the first direction and the other surface. The memory portion is provided on one side of the second direction with respect to the first semiconductor layer, The third wiring is provided on the other side in the second direction relative to the first semiconductor layer. The semiconductor memory device according to claim 6.

11. It comprises a pair of memory structures and a first wiring that are spaced apart in a first direction, The pair of memory structures are arranged in a second direction intersecting the first direction, The pair of memory structures described above are, A plurality of first semiconductor layers stacked in the first direction, via wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers, A plurality of memory units are arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first semiconductor layers, A plurality of first gate electrodes are arranged in the first direction corresponding to the plurality of first semiconductor layers and facing the plurality of first semiconductor layers, A second semiconductor layer is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring. A connecting electrode is provided between the plurality of memory units and the first wiring, and is electrically connected to the second semiconductor layer. A second gate electrode is provided between the plurality of first gate electrodes and the first wiring, and facing the second semiconductor layer. Equipped with, The connecting electrode included in one of the pair of memory structures is electrically connected to the first wiring, The via wiring included in one of the pair of memory structures is electrically connected to the via wiring included in the other of the pair of memory structures. Semiconductor memory device.

12. A second wiring is provided between the pair of memory structures, The connecting electrode included in the other of the pair of memory structures is electrically connected to the second wiring. The semiconductor memory device according to claim 11.

13. A fourth wiring is provided between the pair of memory structures and the first wiring, A contact electrode is provided between the connecting electrode included in the other of the pair of memory structures and the fourth wiring, extending in the first direction and electrically connected to the connecting electrode included in the other of the pair of memory structures and the fourth wiring, A second contact electrode is provided between the second wiring and the fourth wiring, extending in the first direction and electrically connected to the second wiring and the fourth wiring. The semiconductor memory device according to claim 12, comprising:

14. The system includes a fifth wiring that runs parallel to the first wiring in a third direction intersecting the first and second directions, and extends in the second direction, The connecting electrode included in the other of the pair of memory structures is electrically connected to the fifth wiring. The semiconductor memory device according to claim 11.

15. The pair of memory structures and the first wiring are provided with a sixth wiring, The vias included in the pair of memory structures are electrically connected to each other via the sixth wiring. The semiconductor memory device according to claim 11.

16. The pair of memory structures are provided with a connection structure located in the first direction, on the side opposite to the first wiring, The vias included in the pair of memory structures are electrically connected to each other via the connection structure. The semiconductor memory device according to claim 11.

17. The first semiconductor layer and the second semiconductor layer each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 11.

18. Each of the pair of memory structures comprises a plurality of third wirings arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first gate electrodes. The first gate electrode faces one or both of the first semiconductor layer's surface in the first direction and the other surface. The memory portion is provided on one side of the second direction with respect to the first semiconductor layer, The third wiring is provided on the other side in the second direction relative to the first semiconductor layer. The semiconductor memory device according to claim 11.

19. A plurality of first semiconductor layers stacked in a first direction, via wiring extending in the first direction and electrically connected to the plurality of first semiconductor layers, A plurality of memory units are arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first semiconductor layers, A plurality of first gate electrodes are arranged in the first direction corresponding to the plurality of first semiconductor layers and facing the plurality of first semiconductor layers, A first wiring provided on one side in the first direction for the plurality of first semiconductor layers, A second semiconductor layer is provided between the plurality of first semiconductor layers and the first wiring, and is electrically connected to the via wiring. A first connecting electrode is provided between the plurality of memory units and the first wiring, and is electrically connected to the first wiring and the second semiconductor layer. A second gate electrode is provided between the plurality of first gate electrodes and the first wiring, and facing the second semiconductor layer, A second wiring is provided between the first wiring and the second semiconductor layer, A third semiconductor layer is provided between the via wiring and the second wiring, and is electrically connected to the via wiring and the second wiring. A third gate electrode is provided between the via wiring and the second wiring, and faces the outer surface of the third semiconductor layer. A semiconductor memory device equipped with the following features.

20. The first semiconductor layer and the second semiconductor layer each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O). The semiconductor memory device according to claim 19.

21. The device comprises a plurality of third wirings arranged in the first direction corresponding to the plurality of first semiconductor layers and electrically connected to the plurality of first gate electrodes, The first gate electrode faces one or both of the first semiconductor layer's surface in the first direction and the other surface. The memory portion is provided on one side of the first semiconductor layer in a second direction intersecting the first direction, The third wiring is provided on the other side in the second direction relative to the first semiconductor layer. The semiconductor memory device according to claim 19.

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