Semiconductor devices and semiconductor memory devices

Abstract

To provide a semiconductor device with excellent transistor characteristics. [Solution] The semiconductor device of the embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer, and a gate electrode. The first electrode includes a first region, a second region, and a third region. The first region is provided between the second region and the oxide semiconductor layer and contains a first metal element and oxygen, the first metal element being at least one element selected from the group consisting of In, Sn, Zn, Ta, and W. The second region includes a second metal element and may or may not contain nitrogen, the second metal element being one element selected from the group consisting of Ti, W, Mo, and Ta. The third region includes a first part and a second part, the second region is provided between the first part and the second part, and the third region contains the first element and oxygen, the first element being at least one element selected from the group consisting of Ti, Al, Zr, Hf, and Si.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device.

Background Art

[0002] An oxide semiconductor transistor that forms a channel in an oxide semiconductor layer has excellent characteristics such that the channel leakage current during the off operation is extremely small. Therefore, for example, it is possible to apply an oxide semiconductor transistor to a switching transistor of a memory cell of a Dynamic Random Access Memory (DRAM).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device having excellent transistor characteristics.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment comprises a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, wherein the first electrode includes a first region, a second region, and a third region, the first region is provided between the second region and the oxide semiconductor layer and is in contact with the oxide semiconductor layer and the second region, and includes a first metal element and oxygen (O), the first metal element is at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W), and the second region is the The material comprises two metallic elements, and may or may not contain nitrogen (N), wherein the second metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta), the third region is in contact with the first and second regions and comprises a first part and a second part, the second region is provided between the first part and the second part in a second direction perpendicular to a first direction connecting the first electrode and the second electrode, the third region comprises the first element and oxygen (O), wherein the first element is at least one element selected from the group consisting of titanium (Ti), aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si). [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] A schematic cross-sectional view of the semiconductor device of the first comparative example. [Figure 16] A schematic cross-sectional view of the semiconductor device of the second comparative example. [Figure 17] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 18] Equivalent circuit diagram of the semiconductor memory device of the third embodiment. [Figure 19] A schematic cross-sectional view of a semiconductor memory device according to the third embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described may be omitted from the description as appropriate.

[0008] Furthermore, for convenience, the terms "up," "down," "upper part," "lower part," "upper," or "downward" may be used in this specification. "Up," "down," "upper part," "lower part," "upper," or "downward" are terms that indicate relative positions within the drawings and do not define positional relationships with respect to gravity.

[0009] Qualitative and quantitative analyses of the chemical composition of components constituting semiconductor devices and semiconductor memory devices described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, a transmission electron microscope (TEM) can be used, for example, to measure the thickness, distance between components, and grain size of components constituting semiconductor devices and semiconductor memory devices.

[0010] (First embodiment) The semiconductor device of the first embodiment includes a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer. The first electrode includes a first region, a second region, and a third region. The first region is provided between the second region and the oxide semiconductor layer, contacts the oxide semiconductor layer and the second region, contains a first metal element and oxygen (O), and the first metal element is at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W). The second region contains a second metal element, and may or may not contain nitrogen (N). The second metal element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta). The third region contacts the first region and the second region, and includes a first portion and a second portion. The second region is provided between the first portion and the second portion in a second direction perpendicular to a first direction connecting the first electrode and the second electrode. The third region contains a first element and oxygen (O), and the first element is at least one element selected from the group consisting of titanium (Ti), aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si).

[0011] FIG. 1, FIG. 2, FIG. 3, and FIG. 4 are schematic cross-sectional views of the semiconductor device of the first embodiment. FIG. 2 is a cross-sectional view taken along line AA' of FIG. 1. FIG. 3 is a cross-sectional view taken along line BB' of FIG. 1. FIG. 4 is a cross-sectional view taken along line CC' of FIG. 1. In FIG. 1, the vertical direction is referred to as the first direction. In FIG. 1, the horizontal direction is referred to as the second direction. The second direction is perpendicular to the first direction.

[0012] The semiconductor device of the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. In the transistor 100, a gate electrode is provided so as to surround an oxide semiconductor layer in which a channel is formed. The transistor 100 is a so-called Surrounding Gate Transistor (SGT). The transistor 100 is a so-called vertical transistor.

[0013] The transistor 100 includes an upper electrode 12, a lower electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, and an interlayer insulating layer 22. The upper electrode 12 includes a first metal oxide region 12a, a first metal region 12b, a sidewall region 12c, and an upper region 12d. The first metal region 12b includes an inner region 12bx and an outer region 12by. The sidewall region 12c includes a first portion 12c1 and a second portion 12c2. The lower electrode 14 includes a second metal oxide region 14a and a second metal region 14b. The second metal region 14b includes a third portion 14b1, a fourth portion 14b2, and a fifth portion 14b3.

[0014] The upper electrode 12 is an example of a first electrode. The first metal oxide region 12a is an example of a first region. The first metal region 12b is an example of a second region. The sidewall region 12c is an example of a third region. The upper region 12d is an example of a fourth region.

[0015] The lower electrode 14 is an example of a second electrode. The second metal oxide region 14a is an example of a fifth region. The second metal region 14b is an example of a sixth region.

[0016] The upper electrode 12 is provided on the oxide semiconductor layer 16. The upper electrode 12 is electrically connected to the oxide semiconductor layer 16. The upper electrode 12, for example, contacts the oxide semiconductor layer 16. The upper electrode 12 functions as a source electrode or a drain electrode of the transistor 100.

[0017] The lower electrode 14 is provided beneath the oxide semiconductor layer 16. The lower electrode 14 is electrically connected to the oxide semiconductor layer 16. The lower electrode 14 is in contact with the oxide semiconductor layer 16, for example. The lower electrode 14 functions as either the source electrode or the drain electrode of the transistor 100.

[0018] The oxide semiconductor layer 16 is provided between the upper electrode 12 and the lower electrode 14. The oxide semiconductor layer 16 is in contact with, for example, the upper electrode 12. The oxide semiconductor layer 16 is in contact with the lower electrode 14.

[0019] A channel is formed in the oxide semiconductor layer 16 that serves as a current path when the transistor 100 is turned on.

[0020] The oxide semiconductor layer 16 is an oxide semiconductor. For example, the oxide semiconductor layer 16 is amorphous.

[0021] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), as well as zinc (Zn) and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium gallium zinc oxide. The oxide semiconductor layer 16 is, for example, an indium gallium zinc oxide layer.

[0022] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The oxide semiconductor layer 16 includes, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 is, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0023] The oxide semiconductor layer 16 contains, for example, oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.

[0024] The length of the oxide semiconductor layer 16 in the first direction is, for example, 80 nm to 200 nm. The length of the oxide semiconductor layer 16 in the second direction is, for example, 10 nm to 50 nm.

[0025] The first direction is the direction connecting the upper electrode 12 and the lower electrode 14. The second direction is the direction perpendicular to the first direction.

[0026] The gate electrode 18 faces the oxide semiconductor layer 16. The gate electrode 18 is positioned such that its position coordinate in the first direction is between the position coordinates of the upper electrode 12 and the lower electrode 14 in the first direction.

[0027] As shown in Figure 2, the gate electrode 18 surrounds the oxide semiconductor layer 16 in a cross-section perpendicular to the first direction. The gate electrode 18 is provided around the oxide semiconductor layer 16.

[0028] The gate electrode 18 is a conductor. The gate electrode 18 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 18 contains, for example, tungsten (W). The gate electrode 18 is, for example, a tungsten layer.

[0029] The length of the gate electrode 18 in the first direction is, for example, between 20 nm and 100 nm.

[0030] The gate insulating layer 20 is provided between the oxide semiconductor layer 16 and the gate electrode 18. As shown in Figure 2, the gate insulating layer 20 surrounds the oxide semiconductor layer 16 in a cross section perpendicular to the first direction. The gate insulating layer 20 is provided between the upper electrode 12 and the lower electrode 14. The gate insulating layer 20 is in contact with, for example, the upper electrode 12 and the lower electrode 14.

[0031] The gate insulating layer 20 includes, for example, silicon (Si) and nitrogen (N). The gate insulating layer 20 includes, for example, silicon nitride.

[0032] The gate insulating layer 20 includes, for example, silicon (Si) and oxygen (O). The gate insulating layer 20 includes, for example, silicon oxide.

[0033] The gate insulating layer 20 is, for example, a laminated film of a silicon oxide film and a silicon nitride film.

[0034] The thickness of the gate insulating layer 20 is, for example, 2 nm to 10 nm.

[0035] The interlayer insulating layer 22 surrounds, for example, the upper electrode 12, the lower electrode 14, the oxide semiconductor layer 16, and the gate insulating layer 20. The interlayer insulating layer 22 is provided, for example, between the upper electrode 12 and the gate electrode 18. The interlayer insulating layer 22 is provided, for example, between the lower electrode 14 and the gate electrode 18.

[0036] The interlayer insulating layer 22 surrounds the upper electrode 12, for example, in a cross-section perpendicular to the first direction. The interlayer insulating layer 22 surrounds the side wall region 12c of the upper electrode 12, for example. The interlayer insulating layer 22 is in contact with the side wall region 12c, for example.

[0037] The interlayer insulating layer 22 is an insulator. The interlayer insulating layer 22 is, for example, an oxide, nitride, or oxynitride. The interlayer insulating layer 22 contains, for example, silicon (Si) and oxygen (O). The interlayer insulating layer 22 contains, for example, silicon oxide. The interlayer insulating layer 22 is, for example, silicon oxide.

[0038] The chemical composition of the interlayer insulating layer 22 is different from, for example, the chemical composition of the sidewall region 12c of the upper electrode 12.

[0039] The upper electrode 12 includes a first metal oxide region 12a, a first metal region 12b, a side wall region 12c, and an upper region 12d.

[0040] The first metal oxide region 12a is provided between the oxide semiconductor layer 16 and the first metal region 12b. The first metal oxide region 12a is in contact with the oxide semiconductor layer 16 and the first metal region 12b.

[0041] The first metal oxide region 12a is a conductor. The first metal oxide region 12a contains a conductive metal oxide.

[0042] The first metal oxide region 12a contains a first metal element and oxygen (O). The first metal element is at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W).

[0043] The first metal oxide region 12a includes, for example, indium tin oxide, tin oxide, zinc oxide, tantalum-containing tin oxide, or tungsten-containing tin oxide.

[0044] The first metallic element is, for example, indium (In) and tin (Sn). The first metal oxide region 12a includes, for example, indium tin oxide. The first metal oxide region 12a is, for example, indium tin oxide.

[0045] The thickness of the first metal oxide region 12a in the first direction is, for example, 5 nm to 20 nm.

[0046] The first metal region 12b is provided on top of the first metal oxide region 12a.

[0047] The first metallic region 12b is a conductor. The first metallic region 12b contains a metal or a metallic compound.

[0048] The first metallic region 12b contains the second metallic element. Furthermore, the first metallic region 12b may or may not contain nitrogen (N). The first metallic region 12b may or may not contain oxygen (O). The second metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta).

[0049] The first metallic region 12b includes, for example, titanium nitride, tungsten nitride, molybdenum nitride, tantalum nitride, tungsten, or molybdenum.

[0050] The second metallic element is, for example, titanium (Ti). The first metallic region 12b includes, for example, nitrogen (N). The first metallic region 12b includes, for example, titanium nitride. The first metallic region 12b is, for example, titanium nitride.

[0051] The first metal region 12b includes an internal region 12bx and an external region 12by. As shown in Figure 1, in a cross-section parallel to the first direction, the internal region 12bx is located between a part of the external region 12by and another part of the external region 12by. As shown in Figure 3, in a cross-section perpendicular to the first direction, the external region 12by surrounds the internal region 12bx.

[0052] The outer region 12by contains, for example, oxygen (O). The inner region 12bx may or may not contain, for example, oxygen (O). The oxygen concentration in the outer region 12by is higher than the oxygen concentration in the inner region 12bx. For example, the oxygen concentration in the first metal region 12b decreases monotonically in the direction from the outer region 12by to the inner region 12bx.

[0053] The thickness of the first metal region 12b in the first direction is, for example, 5 nm to 50 nm. The length of the first metal region 12b in the second direction (d1 in Figure 1) is, for example, 10 nm to 50 nm.

[0054] The sidewall region 12c is provided on the first metal oxide region 12a. The sidewall region 12c is in contact with the first metal oxide region 12a and the first metal region 12b.

[0055] As shown in Figure 1, the side wall region 12c includes a first portion 12c1 and a second portion 12c2. The first metal region 12b is provided between the first portion 12c1 and the second portion 12c2 in a second direction. As shown in Figure 3, the side wall region 12c surrounds the first metal region 12b.

[0056] The sidewall region 12c is an insulator or a conductor. The sidewall region 12c includes, for example, an oxide.

[0057] The sidewall region 12c contains a first element and oxygen (O). The first element is at least one element selected from the group consisting of titanium (Ti), aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si).

[0058] The sidewall region 12c includes, for example, titanium oxide, aluminum oxide, zirconium oxide, hafnium oxide, or silicon oxide.

[0059] The first element is, for example, titanium (Ti). The sidewall region 12c contains, for example, titanium oxide. The sidewall region 12c is, for example, titanium oxide.

[0060] The first element is, for example, silicon (Si). The sidewall region 12c contains, for example, silicon oxide. The sidewall region 12c is, for example, silicon oxide.

[0061] For example, if the first element is silicon (Si) and the interlayer insulating layer 22 contains silicon (Si) and oxygen (O), the density of the sidewall region 12c is higher than the density of the interlayer insulating layer 22. For example, if the sidewall region 12c contains silicon oxide and the interlayer insulating layer 22 contains silicon oxide, the density of silicon oxide in the sidewall region 12c is higher than the density of silicon oxide in the interlayer insulating layer 22.

[0062] The thickness of the sidewall region 12c in the first direction is, for example, 5 nm to 50 nm. The length of the first portion 12c1 of the sidewall region 12c in the second direction (d2 in Figure 1) is, for example, one-quarter to three-quarters of the length of the first metal region 12b in the second direction (d1 in Figure 1). The length of the second portion 12c2 of the sidewall region 12c in the second direction (d3 in Figure 1) is, for example, one-quarter to three-quarters of the length of the first metal region 12b in the second direction (d1 in Figure 1).

[0063] The upper region 12d is provided on the first metal region 12b. The first metal region 12b is provided between the first metal oxide region 12a and the upper region 12d. The upper region 12d is in contact with the first metal region 12b.

[0064] A side wall region 12c is provided between the first metal oxide region 12a and the upper region 12d. The upper region 12d is in contact with the side wall region 12c.

[0065] The upper region 12d is a conductor. The upper region 12d contains a metal or a metallic compound.

[0066] The upper region 12d contains tungsten (W) or titanium (Ti). The upper region 12d contains, for example, tungsten or titanium nitride. The upper region 12d is, for example, tungsten or titanium nitride.

[0067] The lower electrode 14 includes a second metal oxide region 14a and a second metal region 14b.

[0068] The second metal oxide region 14a is provided between the oxide semiconductor layer 16 and the second metal region 14b. The second metal oxide region 14a is in contact with the oxide semiconductor layer 16 and the second metal region 14b.

[0069] The second metal oxide region 14a is a conductor. The second metal oxide region 14a contains a conductive metal oxide.

[0070] The second metal oxide region 14a contains a third metal element and oxygen (O). The third metal element is at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W).

[0071] The second metal oxide region 14a includes, for example, indium tin oxide, tin oxide, zinc oxide, tantalum-containing tin oxide, or tungsten-containing tin oxide.

[0072] The third metallic element is, for example, indium (In) and tin (Sn). The second metallic oxide region 14a includes, for example, indium tin oxide. The second metallic oxide region 14a is, for example, indium tin oxide.

[0073] The third metallic element is, for example, the same element as the first metallic element included in the first metallic oxide region 12a.

[0074] The thickness of the second metal oxide region 14a in the first direction is, for example, 5 nm to 20 nm.

[0075] The second metallic region 14b is located below the second metallic oxide region 14a. The second metallic region 14b includes a third portion 14b1, a fourth portion 14b2, and a fifth portion 14b3.

[0076] The second metal oxide region 14a is provided between the third portion 14b1 and the oxide semiconductor layer 16. The second metal oxide region 14a is provided between the fourth portion 14b2 and the fifth portion 14b3 in the second direction. The second metal oxide region 14a is in contact with the third portion 14b1, the fourth portion 14b2, and the fifth portion 14b3.

[0077] As shown in Figure 4, in a cross-section perpendicular to the first direction, the second metal oxide region 14a is surrounded by the second metal region 14b.

[0078] The second metallic region 14b is a conductor. The second metallic region 14b contains a metal or a metallic compound.

[0079] The second metallic region 14b contains a fourth metallic element. Furthermore, the second metallic region 14b may or may not contain nitrogen (N). The second metallic region 14b may or may not contain oxygen (O). The fourth metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta).

[0080] The second metallic region 14b includes, for example, titanium nitride, tungsten nitride, molybdenum nitride, tantalum nitride, tungsten, or molybdenum.

[0081] The fourth metallic element is, for example, titanium (Ti). The second metallic region 14b includes, for example, nitrogen (N). The second metallic region 14b includes, for example, titanium nitride. The second metallic region 14b is, for example, titanium nitride.

[0082] The fourth metallic element is, for example, the same element as the second metallic element included in the first metallic region 12b.

[0083] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0084] Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are schematic cross-sectional views showing an example of a manufacturing method for a semiconductor device according to the first embodiment. Figures 5 to 14 each show a cross-section corresponding to Figure 1. Figures 5 to 14 are diagrams showing an example of a manufacturing method for transistor 100.

[0085] The following explanation will be given using the example where the first metal oxide region 12a of the upper electrode 12 is indium tin oxide, the first metal region 12b is titanium nitride, the sidewall region 12c is titanium oxide, the upper region 12d is tungsten, and the interlayer insulating layer 22 is silicon oxide.

[0086] First, a lower electrode 14, an oxide semiconductor layer 16, a gate insulating layer 20, a gate electrode 18, and an interlayer insulating layer 22 are formed on a substrate (not shown) by a known manufacturing method.

[0087] Next, an indium tin oxide film 51, a titanium oxide film 52, and a silicon nitride film 53 are formed in this order (Figure 5). The indium tin oxide film 51 and the titanium oxide film 52 are formed, for example, by sputtering. The silicon nitride film 53 is formed, for example, by chemical vapor deposition (CVD).

[0088] Next, openings 54 are formed in the silicon nitride film 53 and the titanium oxide film 52 (Figure 6). The openings 54 are formed, for example, using lithography and reactive ion etching (RIE).

[0089] Next, the opening 54 is filled with an amorphous silicon film 55 (Figure 7). For example, the opening 54 is filled with an amorphous silicon film 55 by depositing the amorphous silicon film 55 by the CVD method and removing the amorphous silicon film 55 on the silicon nitride film 53 using the Chemical Mechanical Polishing (CMP) method.

[0090] Next, after removing the silicon nitride film 53, a first silicon oxide film 56 is formed on the amorphous silicon film 55 (Figure 8). The silicon nitride film 53 is removed, for example, by a wet etching method. The first silicon oxide film 56 is formed, for example, by the ALD method (ALD-CVD method).

[0091] Next, the sidewall of the first silicon oxide film 56 is formed on the side surface of the amorphous silicon film 55 (Figure 9). The sidewall of the first silicon oxide film 56 is formed, for example, using the RIE method.

[0092] Next, a sidewall of the titanium oxide film 52 is formed on the side surface of the amorphous silicon film 55 (Figure 10). The sidewall of the titanium oxide film 52 is formed, for example, by etching the titanium oxide film 52 using the sidewall of the first silicon oxide film 56 as a mask material. At this time, the indium tin oxide film 51 is also etched simultaneously.

[0093] Next, a second silicon oxide film 57 is formed around the indium tin oxide film 51, the titanium oxide film 52, and the first silicon oxide film 56 (Figure 11). The second silicon oxide film 57 is formed by deposition using the CVD method and removal using the CMP method.

[0094] Next, the amorphous silicon film 55 embedded in the opening 54 is removed (Figure 12). The amorphous silicon film 55 is removed, for example, by a wet etching method.

[0095] Next, the opening 54 is filled with a titanium nitride film 58 (Figure 13). The titanium nitride film 58 is formed, for example, by a CVD method.

[0096] Next, a portion of the titanium nitride film 58, a portion of the second silicon oxide film 57, and the first silicon oxide film 56 are removed to expose the titanium oxide film 52 on the surface (Figure 14). The removal of the portion of the titanium nitride film 58, a portion of the second silicon oxide film 57, and the first silicon oxide film 56 is performed, for example, by the CMP method.

[0097] Subsequently, a tungsten film is formed on the titanium nitride film 58 and patterned to form the upper region 12d.

[0098] By the above manufacturing method, the transistor 100 shown in Figures 1, 2, 3, and 4 is manufactured.

[0099] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0100] Figure 15 is a schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 15 corresponds to Figure 1 of the first embodiment.

[0101] The semiconductor device of the first comparative example is transistor 901. Transistor 901 of the first comparative example differs from transistor 100 of the first embodiment in that the upper electrode 12 does not include the side wall region 12c.

[0102] The following describes the problems of the first comparative example transistor 901, using the case where the first metal oxide region 12a of the upper electrode 12 is indium tin oxide, the first metal region 12b is titanium nitride, and the upper region 12d is tungsten as an example.

[0103] The indium tin oxide material of the first metal oxide region 12a and the titanium nitride material of the first metal region 12b do not necessarily have high adhesion to each other. Therefore, for example, during the operation of transistor 901, film delamination may occur at the interface between indium tin oxide and titanium nitride. If film delamination occurs at the interface between indium tin oxide and titanium nitride, for example, the interfacial resistance will increase, the on-resistance of transistor 901 will increase, and the characteristics of transistor 901 will deteriorate.

[0104] Figure 16 is a schematic cross-sectional view of a semiconductor device of a second comparative example. Figure 16 corresponds to Figure 1 of the first embodiment.

[0105] The semiconductor device of the second comparative example is transistor 902. Transistor 902 of the second comparative example differs from transistor 100 of the first embodiment in that the upper electrode 12 does not include the side wall region 12c. Transistor 902 of the second comparative example differs from transistor 901 of the first comparative example in that an interface region 12x is provided between the first metal oxide region 12a and the first metal region 12b.

[0106] The material in interface region 12x is a material that has high adhesion to the material in the first metal oxide region 12a. For example, if the first metal oxide region 12a is indium tin oxide, the material in interface region 12x is titanium oxide, which has high adhesion to indium tin oxide. Titanium oxide also has high adhesion to titanium nitride, which is the material in the first metal region 12b.

[0107] By providing an interface region 12x with high adhesion to the material of the first metal oxide region 12a, film delamination during operation of the transistor 902 is suppressed. However, the interfacial resistance between indium tin oxide and titanium oxide is higher than that between indium tin oxide and titanium nitride. Therefore, the on-resistance, which is an initial characteristic of the transistor 902, becomes high.

[0108] As described above, there is a trade-off between suppressing film peeling at the upper electrode 12 and reducing interfacial resistance.

[0109] In the first embodiment, the transistor 100 has an upper electrode 12 which includes a first metal region 12b that is in contact with the first metal oxide region 12a, and a side wall region 12c that is in contact with the first metal oxide region 12a and surrounds the first metal region 12b.

[0110] The material of the first metal region 12b is a material with low interfacial resistance with the material of the first metal oxide region 12a. Furthermore, the material of the sidewall region 12c is, for example, a material with high bonding energy and high adhesion with the material of the first metal oxide region 12a.

[0111] For example, if the first metal oxide region 12a is indium tin oxide, the first metal region 12b is titanium nitride, which has low interfacial resistance with indium tin oxide. Also, the sidewall region 12c is titanium oxide, which has high bonding energy with indium tin oxide and high adhesion.

[0112] Therefore, according to the transistor 100 of the first embodiment, it is possible to suppress film peeling at the upper electrode 12 and reduce interfacial resistance simultaneously, thereby realizing a transistor with excellent characteristics.

[0113] From the viewpoint of suppressing film peeling at the upper electrode 12, the length of the first portion 12c1 of the sidewall region 12c in the second direction (d2 in Figure 1) is preferably one-quarter or more of the length of the first metal region 12b in the second direction (d1 in Figure 1), more preferably one-third or more, and even more preferably one-half or more. From a similar viewpoint, the length of the second portion 12c2 of the sidewall region 12c in the second direction (d3 in Figure 1) is preferably one-quarter or more of the length of the first metal region 12b in the second direction (d1 in Figure 1), more preferably one-third or more, and even more preferably one-half or more.

[0114] From the viewpoint of reducing interfacial resistance at the upper electrode 12, the length of the first portion 12c1 of the sidewall region 12c in the second direction (d2 in Figure 1) is preferably 3 / 4 or less of the length of the first metal region 12b in the second direction (d1 in Figure 1), and more preferably 2 / 3 or less. From a similar viewpoint, the length of the second portion 12c2 of the sidewall region 12c in the second direction (d3 in Figure 1) is preferably 3 / 4 or less of the length of the first metal region 12b in the second direction (d1 in Figure 1), and more preferably 2 / 3 or less.

[0115] Furthermore, in the transistor 100 of the first embodiment, consider the case where, in order to reduce the interfacial resistance at the lower electrode 14, a material is selected for the second metal region 14b that has lower interfacial resistance than the material for the second metal oxide region 14a. In this case, similar to the case of the upper electrode 12, the adhesion between the material for the second metal oxide region 14a and the material for the second metal region 14b becomes low, raising concerns about film delamination.

[0116] However, unlike the upper electrode 12, in the lower electrode 14, in a cross-section perpendicular to the first direction shown in Figure 4, the second metal oxide region 14a is surrounded by the second metal region 14b. Therefore, the adhesion between the second metal oxide region 14a and the second metal region 14b is improved, and film peeling can be suppressed. Accordingly, for example, even if the material of the second metal oxide region 14a and the material of the first metal oxide region 12a are the same, and the material of the second metal region 14b and the material of the first metal region 12b are the same, film peeling can be suppressed by having a different structure for the lower electrode 14 from the upper electrode 12, without providing a region corresponding to the side wall region 12c.

[0117] For example, when manufacturing the transistor 100 of the first embodiment, if oxygen (O) is excessively diffused into the first metal region 12b during heat treatment in an oxidizing atmosphere after the formation of the upper electrode, oxidation of the material of the first metal region 12b may progress, potentially increasing the resistance of the upper electrode 12.

[0118] The first metal region 12b of the transistor 100 in the first embodiment includes an internal region 12bx and an external region 12by. The oxygen concentration in the external region 12by is higher than that in the internal region 12bx. In other words, the oxygen concentration in the internal region 12bx is lower than that in the external region 12by.

[0119] In the internal region 12bx with a low oxygen concentration, the increase in resistance due to oxidation of the first metal region 12b is suppressed. Therefore, in the transistor 100 of the first embodiment, the increase in resistance of the upper electrode 12 is suppressed, and a transistor with low on-resistance and excellent characteristics can be realized.

[0120] From the viewpoint of suppressing the increase in resistance due to oxidation of the first metal region 12b of the transistor 100 in the first embodiment, it is preferable that the side wall region 12c surrounding the first metal region 12b contains a material with low oxygen permeability, such as silicon oxide or aluminum oxide. Therefore, it is preferable that the first element contained in the side wall region 12c is silicon (Si) or aluminum (Al).

[0121] For example, if the sidewall region 12c contains silicon oxide and the interlayer insulating layer 22 also contains silicon oxide, it is preferable that the density of silicon oxide in the sidewall region 12c is higher than the density of silicon oxide in the interlayer insulating layer 22. In other words, it is preferable that the density of the sidewall region 12c is higher than the density of the interlayer insulating layer 22. In other words, if the first element is silicon (Si) and the interlayer insulating layer 22 contains silicon (Si) and oxygen (O), it is preferable that the density of the sidewall region 12c is higher than the density of the interlayer insulating layer 22.

[0122] The high density of silicon oxide contained in the sidewall region 12c further suppresses the permeation of oxygen into the first metal region 12b.

[0123] From the viewpoint of suppressing oxidation of the first metal region 12b, it is preferable that the side wall region 12c is in contact with the upper region 12d.

[0124] As described above, according to the first embodiment, a semiconductor device with excellent transistor characteristics can be realized.

[0125] (Second embodiment) The semiconductor device of the second embodiment includes a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode facing the oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer. The first electrode includes a first region, a second region, and a third region. The first region is provided between the second region and the oxide semiconductor layer and is in contact with the oxide semiconductor layer and the second region, and contains a first metal element and oxygen (O), the first metal element being at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W). The second region contains a second metal element and may or may not contain nitrogen (N), the second metal element being one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta). The third region is in contact with the first and second regions and includes the first and second portions, the second region being provided between the first and second portions in a second direction perpendicular to the first direction connecting the first and second electrodes, and the third region includes silicon (Si) and nitrogen (N), silicon (Si) and oxygen (O) and nitrogen (N), aluminum (Al) and nitrogen (N), or tantalum (Ta) and nitrogen (N). The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the third region includes silicon (Si) and nitrogen (N), silicon (Si) and oxygen (O) and nitrogen (N), aluminum (Al) and nitrogen (N), or tantalum (Ta) and nitrogen (N). Some descriptions that overlap with the semiconductor device of the first embodiment may be omitted below.

[0126] Figure 17 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. Figure 17 corresponds to Figure 1 of the first embodiment.

[0127] The semiconductor device of the second embodiment is a transistor 200. The transistor 200 differs from the transistor 100 of the first embodiment in that the side wall region 12c of the upper electrode 12 contains silicon (Si) and nitrogen (N).

[0128] The sidewall region 12c includes silicon (Si) and nitrogen (N), silicon (Si) and oxygen (O) and nitrogen (N), aluminum (Al) and nitrogen (N), or tantalum (Ta) and nitrogen (N). The sidewall region 12c includes a combination of at least one element selected from the group consisting of a first combination of silicon (Si) and nitrogen (N), a second combination of silicon (Si) and oxygen (O) and nitrogen (N), a third combination of aluminum (Al) and nitrogen (N), and a fourth combination of tantalum (Ta) and nitrogen (N). The sidewall region 12c includes, for example, silicon nitride, silicon oxynitride, aluminum nitride, or tantalum nitride. The sidewall region 12c is, for example, silicon nitride, silicon oxynitride, aluminum nitride, or tantalum nitride.

[0129] The interlayer insulating layer 22 surrounds the upper electrode 12, for example, in a cross-section perpendicular to the first direction. The interlayer insulating layer 22 surrounds the side wall region 12c of the upper electrode 12, for example. The interlayer insulating layer 22 is in contact with the side wall region 12c, for example.

[0130] The interlayer insulating layer 22 is an insulator. The interlayer insulating layer 22 is, for example, an oxide, nitride, or oxynitride. The interlayer insulating layer 22 contains, for example, silicon (Si) and oxygen (O). The interlayer insulating layer 22 contains, for example, silicon oxide. The interlayer insulating layer 22 is, for example, silicon oxide.

[0131] The chemical composition of the interlayer insulating layer 22 is different from, for example, the chemical composition of the sidewall region 12c of the upper electrode 12.

[0132] Next, the operation and effects of the semiconductor device according to the second embodiment will be described.

[0133] When manufacturing the transistor 200 of the second embodiment, if oxygen (O) is excessively diffused into the first metal region 12b during heat treatment in an oxidizing atmosphere after the formation of the upper electrode, oxidation of the material in the first metal region 12b may progress, potentially increasing the resistance of the upper electrode 12.

[0134] The transistor 200 of the second embodiment uses a material with low oxygen permeability in the sidewall region 12c, namely a material containing silicon (Si) and nitrogen (N), silicon (Si) and oxygen (O) and nitrogen (N), aluminum (Al) and nitrogen (N), or tantalum (Ta) and nitrogen (N). The sidewall region 12c includes, for example, silicon nitride, silicon oxynitride, aluminum nitride, or tantalum nitride. In the transistor 200 of the second embodiment, oxidation of the material in the first metal region 12b is suppressed by using a material with low oxygen permeability in the sidewall region 12c.

[0135] The first metal region 12b of the transistor 200 in the second embodiment includes an internal region 12bx and an external region 12by. The oxygen concentration in the external region 12by is higher than that in the internal region 12bx. In other words, the oxygen concentration in the internal region 12bx is lower than that in the external region 12by. The internal region 12bx, with its lower oxygen concentration, suppresses the increase in resistance due to oxidation of the first metal region 12b.

[0136] From the viewpoint of suppressing oxidation of the first metal region 12b, it is preferable that the side wall region 12c is in contact with the upper region 12d.

[0137] From the viewpoint of suppressing oxidation of the first metal region 12b, the length of the first portion 12c1 of the sidewall region 12c in the second direction (d2 in Figure 17) is preferably one-quarter or more, more preferably one-third or more, and even more preferably one-half or more, of the length of the first metal region 12b in the second direction (d1 in Figure 17). From a similar viewpoint, the length of the second portion 12c2 of the sidewall region 12c in the second direction (d3 in Figure 17) is preferably one-quarter or more, more preferably one-third or more, and even more preferably one-half or more, of the length of the first metal region 12b in the second direction (d1 in Figure 17).

[0138] From the viewpoint of reducing interfacial resistance at the upper electrode 12, the length of the first portion 12c1 of the sidewall region 12c in the second direction (d2 in Figure 17) is preferably 3 / 4 or less of the length of the first metal region 12b in the second direction (d1 in Figure 17), and more preferably 2 / 3 or less. From a similar viewpoint, the length of the second portion 12c2 of the sidewall region 12c in the second direction (d3 in Figure 17) is preferably 3 / 4 or less of the length of the first metal region 12b in the second direction (d1 in Figure 17), and more preferably 2 / 3 or less.

[0139] As described above, according to the second embodiment, a semiconductor device with excellent transistor characteristics can be realized.

[0140] (Third embodiment) The semiconductor memory device of the third embodiment comprises the semiconductor device of the first embodiment and a capacitor electrically connected to the second electrode.

[0141] The semiconductor memory device of the third embodiment is a semiconductor memory 300. The semiconductor memory device of the third embodiment is a DRAM. The semiconductor memory 300 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.

[0142] In the following, some descriptions that overlap with the first embodiment will be omitted.

[0143] Figure 18 is an equivalent circuit diagram of a semiconductor memory device according to the third embodiment. Although Figure 18 illustrates the case where there is one memory cell MC, multiple memory cell MCs may be provided, for example, in an array.

[0144] The semiconductor memory 300 comprises a memory cell MC, a word line WL, a bit line BL, and a plate line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. In Figure 18, the region enclosed by the dashed line is the memory cell MC.

[0145] The word wire WL is electrically connected to the gate electrode of the switching transistor TR. The bit wire BL is electrically connected to one of the source and drain electrodes of the switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of the switching transistor TR. The other electrode of capacitor CA is connected to the plate wire PL.

[0146] Memory cells (MC) store data by accumulating electric charge in capacitors (CA). Data is written to and read by turning on a switching transistor (TR).

[0147] For example, a switching transistor TR is turned on while a desired voltage is applied to the bit line BL, and data is written to the memory cell MC.

[0148] Furthermore, for example, by turning on a switching transistor TR, the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor is detected, and data from the memory cell MC is read out.

[0149] Figure 19 is a schematic cross-sectional view of a semiconductor memory device according to the third embodiment. Figure 19 shows a cross-section of the memory cell MC of the semiconductor memory 300.

[0150] The semiconductor memory 300 includes a silicon substrate 10, a switching transistor TR, and a capacitor CA.

[0151] The switching transistor TR has the same structure as the transistor 100 in the first embodiment.

[0152] Capacitor CA is provided between the silicon substrate 10 and the switching transistor TR. Capacitor CA is provided between the silicon substrate 10 and the lower electrode 14. Capacitor CA is electrically connected to the lower electrode 14.

[0153] The capacitor CA comprises a cell electrode 71, a plate electrode 72, and a capacitor insulating film 73. The cell electrode 71 is electrically connected to the lower electrode 14.

[0154] The cell electrode 71 and plate electrode 72 are made of, for example, titanium nitride. The capacitor insulating film 73 has a layered structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide.

[0155] The gate electrode 18 is electrically connected, for example, to a word line WL (not shown). The upper electrode 12 is electrically connected, for example, to a bit line BL (not shown). The plate electrode 72 is connected, for example, to a plate line PL (not shown).

[0156] The semiconductor memory 300 applies an oxide semiconductor transistor with extremely low channel leakage current during off-operation to the switching transistor TR. Therefore, a DRAM with excellent charge retention characteristics is realized.

[0157] Furthermore, the switching transistor TR of the semiconductor memory 300 is the transistor 100 with excellent characteristics of the first embodiment. Therefore, a semiconductor memory 300 with excellent operating characteristics can be realized.

[0158] In the third embodiment, a semiconductor memory to which the transistor of the first embodiment is applied was described as an example, but the semiconductor memory of the embodiment of the present invention may also be a semiconductor memory to which the transistor of the second embodiment is applied.

[0159] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0160] 12 Upper electrode (first electrode) 12a First metal oxide region (first region) 12b First metallic region (second region) 12bx internal area 12by external area 12c Sidewall region (third region) 12c1 Part 1 12c2 Second part 12d Upper region (fourth region) 14. Lower electrode (second electrode) 14a Second metal oxide region (fifth region) 14b Second metallic region (sixth region) 14b1 Third part 14b2 Part 4 14b3 Part 5 16 Oxide semiconductor layer 18 Guard gate 20 Gate insulating layer 22 Interlayer insulating layer (insulating layer) 100 Transistors (Semiconductor Devices) 200 Transistors (Semiconductor Equipment) 300 Semiconductor memory (semiconductor storage device) CA Capacitor

Claims

1. The first electrode and The second electrode and An oxide semiconductor layer provided between the first electrode and the second electrode, A gate electrode facing the oxide semiconductor layer, The gate insulating layer is provided between the gate electrode and the oxide semiconductor layer, The first electrode includes a first region, a second region, and a third region. The first region is provided between the second region and the oxide semiconductor layer, is in contact with the oxide semiconductor layer and the second region, and contains a first metal element and oxygen (O), the first metal element being at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W). The second region contains a second metallic element, and may or may not contain nitrogen (N), and the second metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta). A semiconductor device wherein the third region is in contact with the first region and the second region and includes a first portion and a second portion, the second region is provided between the first portion and the second portion in a second direction perpendicular to a first direction connecting the first electrode and the second electrode, and the third region includes a first element and oxygen (O), the first element being at least one element selected from the group consisting of titanium (Ti), aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si).

2. The first electrode further includes a fourth region, A second region is provided between the first region and the fourth region, and the fourth region is in contact with the second region. A third region is provided between the first region and the fourth region, and the fourth region is in contact with the third region. The semiconductor device according to claim 1, wherein the fourth region comprises tungsten (W) or titanium (Ti).

3. The semiconductor device according to claim 1, wherein the third region surrounds the second region.

4. The semiconductor device according to claim 1, wherein the first element is silicon (Si) or aluminum (Al).

5. The semiconductor device according to claim 1, further comprising an insulating layer surrounding the third region.

6. The semiconductor device according to claim 5, wherein, when the first element is silicon (Si) and the insulating layer contains silicon (Si) and oxygen (O), the density of the third region is higher than the density of the insulating layer.

7. The semiconductor device according to claim 1, wherein the second region includes an internal region and an external region, the internal region is provided between a part and another part of the external region in the second direction, the external region contains oxygen (O), the internal region contains or does not contain oxygen (O), and the oxygen concentration of the external region is higher than the oxygen concentration of the internal region.

8. The semiconductor device according to claim 1, wherein the first metallic element is indium (In) and tin (Sn), the second metallic element is titanium (Ti), the second region contains nitrogen (N), and the first element is titanium (Ti).

9. The semiconductor device according to claim 1, wherein the length of the first portion in the second direction is one-quarter or more of the length of the second region in the second direction, and the length of the second portion in the second direction is one-quarter or more of the length of the second region in the second direction.

10. The semiconductor device according to claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.

11. The second electrode includes a fifth region and a sixth region. The fifth region is provided between the oxide semiconductor layer and the sixth region, is in contact with the oxide semiconductor layer and the sixth region, and contains a third metal element and oxygen (O), the third metal element being at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W). The semiconductor device according to claim 1, wherein the sixth region includes a third portion, a fourth portion, and a fifth portion, the fifth region is provided between the third portion and the oxide semiconductor layer, the fifth region is provided between the fourth portion and the fifth portion in the second direction, the fifth region is in contact with the third portion, the fourth portion, and the fifth portion, and the sixth region includes a fourth metallic element, which may or may not include nitrogen (N), and the fourth metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta).

12. The semiconductor device according to claim 11, wherein the first metal element and the third metal element are the same element, and the second metal element and the fourth metal element are the same element.

13. The semiconductor device according to claim 1, A capacitor electrically connected to the second electrode, A semiconductor memory device equipped with the following features.

14. The first electrode and The second electrode and An oxide semiconductor layer provided between the first electrode and the second electrode, A gate electrode facing the oxide semiconductor layer, The gate insulating layer is provided between the gate electrode and the oxide semiconductor layer, The first electrode includes a first region, a second region, and a third region. The first region is provided between the second region and the oxide semiconductor layer, is in contact with the oxide semiconductor layer and the second region, and contains a first metal element and oxygen (O), the first metal element being at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W). The second region contains a second metallic element, and may or may not contain nitrogen (N), and the second metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta). A semiconductor device comprising: a third region in contact with the first region and the second region, comprising a first portion and a second portion, wherein the second region is provided between the first portion and the second portion in a second direction perpendicular to a first direction connecting the first electrode and the second electrode, and the third region comprises silicon (Si) and nitrogen (N), silicon (Si) and oxygen (O) and nitrogen (N), aluminum (Al) and nitrogen (N), or tantalum (Ta) and nitrogen (N).

15. The first electrode further includes a fourth region, A second region is provided between the first region and the fourth region, and the fourth region is in contact with the second region. A third region is provided between the first region and the fourth region, and the fourth region is in contact with the third region. The semiconductor device according to claim 14, wherein the fourth region comprises tungsten (W) or titanium (Ti).

16. The semiconductor device according to claim 14, wherein the third region surrounds the second region.

17. The semiconductor device according to claim 14, further comprising an insulating layer surrounding the third region and having a different chemical composition from the third region.

18. The semiconductor device according to claim 14, wherein the second region includes an internal region and an external region, the internal region is provided between a part and another part of the external region in the second direction, the external region contains oxygen (O), the internal region contains or does not contain oxygen (O), and the oxygen concentration of the external region is higher than the oxygen concentration of the internal region.

19. The semiconductor device according to claim 14, wherein the first metallic element is indium (In) and tin (Sn), the second metallic element is titanium (Ti), and the second region includes nitrogen (N).

20. The semiconductor device according to claim 14, wherein the length of the first portion in the second direction is one-quarter or more of the length of the second region in the second direction, and the length of the second portion in the second direction is one-quarter or more of the length of the second region in the second direction.

21. The semiconductor device according to claim 14, wherein the gate electrode surrounds the oxide semiconductor layer.

22. The second electrode includes a fifth region and a sixth region. The fifth region is provided between the oxide semiconductor layer and the sixth region, is in contact with the oxide semiconductor layer and the sixth region, and contains a third metal element and oxygen (O), the third metal element being at least one element selected from the group consisting of indium (In), tin (Sn), zinc (Zn), tantalum (Ta), and tungsten (W). The semiconductor device according to claim 14, wherein the sixth region includes a third portion, a fourth portion, and a fifth portion, the fifth region is provided between the third portion and the oxide semiconductor layer, the fifth region is provided between the fourth portion and the fifth portion in the second direction, the fifth region is in contact with the third portion, the fourth portion, and the fifth portion, and the sixth region includes a fourth metallic element, which may or may not include nitrogen (N), and the fourth metallic element is one element selected from the group consisting of titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta).

23. The semiconductor device according to claim 22, wherein the first metal element and the third metal element are the same element, and the second metal element and the fourth metal element are the same element.

24. The semiconductor device according to claim 14, A capacitor electrically connected to the second electrode, A semiconductor memory device equipped with the following features.

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