Semiconductor element driving circuit

Abstract

The objective is to provide a technology that can suppress malfunctions in power semiconductor devices. [Solution] The semiconductor element driving circuit includes a first output terminal to which a first power semiconductor element is connected, a second output terminal to which a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected, a first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, a second cutoff semiconductor element that reduces the voltage at the second output terminal when turned on, and a cutoff control circuit that turns on the first cutoff semiconductor element and the second cutoff semiconductor element via a cutoff pre-stage circuit.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor element drive circuit.

Background Art

[0002] A semiconductor element drive circuit for driving two power semiconductor elements connected in parallel has been proposed (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a semiconductor device including two power semiconductor elements connected in parallel, it is required to improve the characteristics of one power semiconductor element to reduce conduction loss and to miniaturize the chip of one power semiconductor element to reduce cost. As one configuration that satisfies this requirement, a configuration for lowering the threshold voltage of one power semiconductor element has been proposed. However, in an inverter device including two power semiconductor elements as its own arm, when the opposing arm connected in series with the own arm performs switching, the voltage between the collector and emitter (between the drain and source) of the two power semiconductor elements of the own arm increases steeply.

[0005] As a result, the displacement current generated by the time change of the voltage (dV / dt) charges the gate capacitance of the power semiconductor element of the own arm, resulting in a floating of the gate voltage that makes it difficult for the gate voltage to drop. As a result, there is a problem that a malfunction may occur in which the power semiconductor element (especially a power semiconductor element with a low threshold voltage) turns on even when trying to turn it off.

[0006] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that can suppress malfunctions of power semiconductor devices. [Means for solving the problem]

[0007] The semiconductor element driving circuit according to this disclosure includes an input terminal, a first output terminal to which a first power semiconductor element is connected, a second output terminal connected in parallel with the first power semiconductor element and to which a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected, a first output pre-stage circuit that generates a first input corresponding signal based on the input signal of the input terminal, a first output circuit that drives the first power semiconductor element via the first output terminal based on the first input corresponding signal, a first cutoff semiconductor element that reduces the voltage of the first output terminal when turned on, and based on the input signal The device comprises: a second output pre-stage circuit that generates a second input corresponding signal; a second output circuit that drives the second power semiconductor element via the second output terminal based on the second input corresponding signal; a second cutoff semiconductor element that reduces the voltage at the second output terminal when turned on; a cutoff pre-stage circuit connected to the first cutoff semiconductor element and the second cutoff semiconductor element; and a cutoff control circuit that turns on the first cutoff semiconductor element and the second cutoff semiconductor element via the cutoff pre-stage circuit when the input signal is at a low level and the voltage at the first output terminal is lower than a predetermined value. [Effects of the Invention]

[0008] According to this disclosure, the cutoff control circuit turns on the first cutoff semiconductor element and the second cutoff semiconductor element when the input signal at the input terminal is at a low level and the voltage at the first output terminal is lower than a predetermined value. With this configuration, malfunctions of the first power semiconductor element and the second power semiconductor element can be suppressed. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing the configuration of a semiconductor element driving circuit according to Embodiment 1. [Figure 2]This is a timing chart showing the operation of the semiconductor element driving circuit according to Embodiment 1. [Figure 3] This is a circuit diagram showing an example of the configuration of the cutoff control circuit according to Embodiment 1. [Figure 4] This is a circuit diagram showing an example of the configuration of the cutoff control circuit according to Embodiment 1. [Figure 5] This is a circuit diagram showing an example of the configuration of the cutoff control circuit according to Embodiment 1. [Figure 6] This is a circuit diagram showing an example of the configuration of the cutoff control circuit according to Embodiment 1. [Figure 7] This is a circuit diagram showing the configuration of a semiconductor element driving circuit according to Embodiment 2. [Figure 8] This is a timing chart showing the operation of the semiconductor element driving circuit according to Embodiment 2. [Figure 9] This is a circuit diagram showing an example of the configuration of a delay buffer according to Embodiment 2. [Figure 10] This is a circuit diagram showing the configuration of a semiconductor element driving circuit according to Embodiment 3. [Figure 11] This is a timing chart showing the operation of the semiconductor element driving circuit according to Embodiment 3. [Figure 12] This is a circuit diagram showing the configuration of a semiconductor element driving circuit according to Embodiment 4. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components will be described primarily.

[0011] <Embodiment 1> Figure 1 is a circuit diagram showing the configuration of a semiconductor element driving circuit IC according to this first embodiment, and Figure 2 is a timing chart showing an overview of the operation of the semiconductor element driving circuit IC.

[0012] The semiconductor element drive circuit IC in FIG. 1 includes an input terminal IN, a first output terminal OUT1, a second output terminal OUT2, a first pre-output circuit 1, a first output circuit including semiconductor elements 2 and 3, a first cut-off semiconductor element 4, a second pre-output circuit 5, a second output circuit including semiconductor elements 6 and 7, a second cut-off semiconductor element 8, a pre-cut-off circuit 9, and a cut-off control circuit 10. The semiconductor element drive circuit IC and a first power semiconductor element 31 and a second power semiconductor element 32 connected to the semiconductor element drive circuit IC are provided in a semiconductor device.

[0013] The first output terminal OUT1 is connected to the gate of the first power semiconductor element 31, and the second output terminal OUT2 is connected to the gate of the second power semiconductor element 32. Since the threshold voltage Vth2 of the second power semiconductor element 32 is lower than the threshold voltage Vth1 of the first power semiconductor element 31, the second power semiconductor element 32 is more likely to malfunction due to floating of the gate voltage than the first power semiconductor element 31.

[0014] In the first embodiment, the first power semiconductor element 31 is an IGBT (Insulated Gate Bipolar Transistor) made of silicon (Si), and the second power semiconductor element 32 is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of silicon carbide (SiC).

[0015] However, the first power semiconductor element 31 and the second power semiconductor element 32 are not limited to this. For example, at least one of the first power semiconductor element 31 and the second power semiconductor element 32 may be an IGBT or a MOSFET. In this specification, for example, at least one of A, B, C,..., and Z means any one of all combinations extracted from one or more types from the group of A, B, C,..., and Z.

[0016] Further, at least one of the first power semiconductor device 31 and the second power semiconductor device 32 may be composed of Si or SiC. Instead of this SiC, another wide bandgap semiconductor such as gallium nitride (GaN), gallium oxide (Ga2O3), diamond, etc. may be used. When at least one of the first power semiconductor device 31 and the second power semiconductor device 32 is composed of a wide bandgap semiconductor, stable operation of the semiconductor device at high temperature and high voltage, high-speed switching, and miniaturization are possible.

[0017] The second power semiconductor device 32 is connected in parallel with the first power semiconductor device 31. The first power semiconductor device 31 and the second power semiconductor device 32 may constitute an arm of an inverter device that drives an inductive load such as a motor. The inverter device mentioned here includes, for example, a half-bridge inverter device, a full-bridge inverter device, and a three-phase inverter device.

[0018] For example, the first power semiconductor device 31 and the second power semiconductor device 32 may constitute the upper arm. Then, the collector of the first power semiconductor device 31 and the drain of the second power semiconductor device 32 may be connected to a power supply not shown, and the emitter of the first power semiconductor device 31 and the source of the second power semiconductor device 32 may be connected to a lower arm not shown and an inductive load. The lower arm may be composed of two power semiconductor devices connected in parallel in the same manner as the first power semiconductor device 31 and the second power semiconductor device 32.

[0019] The first output pre-stage circuit 1 generates a first input corresponding signal based on the input signal at the input terminal IN. In this embodiment 1, the first output pre-stage circuit 1 is a NOT circuit (inverter) and generates the first input corresponding signal by inverting the level of the input signal. In other words, the first output pre-stage circuit 1 outputs a low-level first input corresponding signal when the input signal is at a high level, and outputs a high-level first input corresponding signal when the input signal is at a low level. In this embodiment 1, the low level corresponds to the reference voltage (GND) connected to the semiconductor element drive circuit IC, and the high level corresponds to the power supply voltage (VCC) connected to the semiconductor element drive circuit IC.

[0020] The first output circuit, which includes semiconductor elements 2 and 3, drives the first power semiconductor element 31 via the first output terminal OUT1 based on the first input corresponding signal from the first output pre-stage circuit 1.

[0021] After the input signal at input terminal IN reaches a high level, semiconductor element 2 of the first output circuit charges the gate capacitance of the first power semiconductor element 31. In other words, as shown in Figure 2, after the input signal at input terminal IN reaches a high level, the voltage at the first output terminal OUT1 becomes higher than the threshold voltage Vth1, and the first power semiconductor element 31 is turned on.

[0022] On the other hand, after the input signal at input terminal IN goes to a low level, semiconductor element 3 of the first output circuit discharges the gate capacitance of the first power semiconductor element 31. In other words, as shown in Figure 2, after the input signal at input terminal IN goes to a low level, the voltage at the second output terminal OUT2 becomes lower than the threshold voltage Vth1, and the first power semiconductor element 31 is turned off.

[0023] In this embodiment 1, semiconductor elements 2 and 3 are PMOS (P-type MOSFET) and NMOS (N-type MOSFET), respectively, but are not limited to these.

[0024] When the first cutoff semiconductor element 4 is turned on, it reduces the impedance between the first output terminal OUT1 and ground (GND), thereby reducing the voltage at the first output terminal OUT1 and suppressing the gate voltage floating of the first power semiconductor element 31. In this embodiment 1, the first cutoff semiconductor element 4 is an NMOS, but it is not limited to this.

[0025] The second output pre-stage circuit 5, the second output circuit including semiconductor elements 6 and 7, and the second cutoff semiconductor element 8 are configured similarly to the first output pre-stage circuit 1, the first output circuit including semiconductor elements 2 and 3, and the first cutoff semiconductor element 4. In other words, the second output pre-stage circuit 5 generates a second input corresponding signal based on the input signal, and the second output circuit drives the second power semiconductor element 32 via the second output terminal OUT2 based on the second input corresponding signal from the second output pre-stage circuit 5. When the second cutoff semiconductor element 8 is turned on, it reduces the impedance between the second output terminal OUT2 and ground (GND), thereby reducing the voltage at the second output terminal OUT2 and suppressing gate floating of the second power semiconductor element 32.

[0026] If the first power semiconductor element 31 and the second power semiconductor element 32 are not connected to the first output terminal OUT1 and the second output terminal OUT2, respectively, the signal waveforms of the first output terminal OUT1 and the second output terminal OUT2 will be square waves, similar to the signal waveform of the input terminal IN. When the first power semiconductor element 31 and the second power semiconductor element 32 are connected to the first output terminal OUT1 and the second output terminal OUT2, respectively, as shown in Figure 2, the rise and fall rates of the signal waveforms of the first output terminal OUT1 and the second output terminal OUT2 will be slower than the rise and fall rates of the square wave signal waveform of the input terminal IN. For convenience of explanation, the rise rate change per unit time and the fall rate change per unit time may be referred to as rise rate change and fall rate change, respectively, below.

[0027] The degree to which the rising and falling edges of the signal waveform at the first output terminal OUT1 are gradual is determined by the on-resistance of the first output circuit and the gate capacitance of the first power semiconductor element 31. Similarly, the degree to which the rising and falling edges of the signal waveform at the second output terminal OUT2 are gradual is determined by the on-resistance of the second output circuit and the gate capacitance of the second power semiconductor element 32.

[0028] In this embodiment 1, by adjusting the on-resistance and gate capacitance, the rising edge change of the signal waveform at the second output terminal OUT2 is made gentler than the rising edge change of the signal waveform at the first output terminal OUT1. Furthermore, by adjusting the on-resistance and gate capacitance, the falling edge change of the signal waveform at the second output terminal OUT2 is made steeper than the falling edge change of the signal waveform at the first output terminal OUT1. As a result, the second power semiconductor element 32, which has a low threshold voltage, can operate without substantially contributing to switching, thereby reducing conduction losses.

[0029] In this embodiment 1, the chip area of ​​the second power semiconductor element 32 is smaller than that of the first power semiconductor element 31. With this configuration, the falling edge change of the signal waveform at the second output terminal OUT2 can be made steeper than the falling edge change of the signal waveform at the first output terminal OUT1. As a result, the second power semiconductor element 32, which has a low threshold voltage, can be easily made to operate without substantially contributing to switching, and thus conduction losses can be easily reduced.

[0030] For the sake of clarity, Figure 2 does not reflect the floating gate voltages of the first output terminal OUT1 and the second output terminal OUT2, nor the reduction in the gate voltage of the first output terminal OUT1 due to the turning on of the first cutoff semiconductor element 4.

[0031] The pre-cutting circuit 9 in Figure 1 is connected to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8. In this embodiment 1, the pre-cutting circuit 9 is a NOT gate (inverter) that inverts the level of the signal from the cutoff control circuit 10 and outputs it to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8.

[0032] The cutoff control circuit 10 controls the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9 based on the input signal from the input terminal IN and the voltage at the first output terminal OUT1. The control of the cutoff control circuit 10 will be described below with reference to the voltage at the connection point VG between the cutoff pre-stage circuit 9 and the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8.

[0033] When the input signal at input terminal IN changes from a low level to a high level, the cutoff control circuit 10 outputs a low-level signal from the cutoff pre-stage circuit 9 to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8, as shown in the voltage at connection point VG at time t1 in Figure 2. As a result, the cutoff control circuit 10 turns off the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9.

[0034] On the other hand, if the input signal at input terminal IN is at a low level and the voltage at the first output terminal OUT1 is lower than a predetermined value Vgt, the cutoff control circuit 10 outputs a high-level signal from the cutoff pre-stage circuit 9 to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8, as shown in the voltage at connection point VG at time t2 in Figure 2. As a result, the cutoff control circuit 10 turns on the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9.

[0035] In this embodiment 1, the time t2 at which the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 turn on is sufficiently delayed from the time at which the voltages at the first output terminal OUT1 and the second output terminal OUT2 become less than or equal to the threshold voltages Vth1 and Vth2, respectively. In this way, if the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 turn on with sufficient delay from the switching of the first power semiconductor element 31 and the second power semiconductor element 32, noise radiated to the outside from the semiconductor device can be suppressed.

[0036] Figures 3 to 6 are circuit diagrams showing example configurations of the cutoff control circuit 10.

[0037] As shown in Figure 3, the cutoff control circuit 10 may consist of NOT circuits 41 and 42 and a NAND circuit 43 to which the NOT circuits 41 and 42 are connected as inputs. The threshold voltage value of the NOT circuit 41 to which the signal from the first output terminal OUT1 is input is the value Vgt in Figure 2. With the cutoff control circuit 10 configured in this way, when the input signal from the input terminal IN is at a low level and the voltage at the first output terminal OUT1 is lower than the value Vgt, it outputs a low-level signal, so the voltage at the connection point VG at time t2 in Figure 2 can be raised to a high level.

[0038] As shown in Figure 4, the cutoff control circuit 10 may consist of a NOT circuit 44 and an SR-FF circuit 45 to which the NOT circuit 44 is connected to the S terminal and the input signal from the input terminal IN is input to the R terminal. According to the configuration in Figure 3, the cutoff control circuit 10 can be realized with a simple circuit configuration, but if the gate voltage floats and the voltage at the first output terminal OUT1 becomes greater than or equal to the value Vgt, the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 cannot be turned on. In contrast, according to the configuration in Figure 4, even if the gate voltage floats and the voltage at the first output terminal OUT1 becomes greater than or equal to the value Vgt, the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 can be turned on.

[0039] As shown in Figures 5 and 6, the cutoff control circuit 10 may also be configured in which the NOT circuits 41 and 44 in Figures 3 and 4 are replaced with comparators 41a and 44a. With such a configuration, the circuit size may increase slightly depending on the response speed of the comparator, but since Vgt becomes the reference voltage of the comparator, the effects of changes in power supply voltage and temperature can be reduced.

[0040] Note that the configuration of the circuit breaker control circuit 10 is not limited to those shown in Figures 3 to 6, and other configurations may be used. An appropriate configuration for the circuit breaker control circuit 10 will be applied depending on the application.

[0041] <Summary of Embodiment 1> According to the semiconductor element driving circuit IC of this embodiment 1 described above, the cutoff control circuit 10 turns on the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 when the input signal at the input terminal IN is at a low level and the voltage at the first output terminal OUT1 is lower than the value Vgt. With this configuration, the floating of the gate voltage in the first power semiconductor element 31 and the second power semiconductor element 32 can be suppressed, and thus malfunctions of the first power semiconductor element 31 and the second power semiconductor element 32 can be suppressed.

[0042] Furthermore, in this embodiment 1, one pre-cutting circuit 9 and one cut-off control circuit 10 control both the first cut-off semiconductor element 4 and the second cut-off semiconductor element 8. Therefore, the circuit size can be reduced compared to a configuration in which a pre-cutting circuit and a cut-off control circuit are provided for each of the first cut-off semiconductor element 4 and the second cut-off semiconductor element 8.

[0043] Furthermore, generally, as the value Vgt decreases, the circuit size of the cutoff control circuit 10 that determines whether the voltage at the first output terminal OUT1 is lower than the value Vgt increases. In contrast, in this embodiment 1, the cutoff control circuit 10 controls the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 based on the input and output of the first output circuit that controls the first power semiconductor element 31 which has a high threshold voltage Vth1.

[0044] Therefore, based on the input and output of the second output circuit that controls the second power semiconductor element 32, which has a low threshold voltage Vth2, the value Vgt of the cutoff control circuit 10 can be made higher than the value Vgt of the related circuit that controls the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8. As a result, according to this embodiment 1, the circuit size of the cutoff control circuit 10, and consequently the circuit size of the semiconductor element driving circuit IC, can be reduced.

[0045] In this embodiment 1, the configuration is provided with a blocking control circuit 10 that controls both the first blocking semiconductor element 4 and the second blocking semiconductor element 8. However, the timing of turning on the second blocking semiconductor element 8 may be delayed compared to a configuration with two blocking control circuits that control the first blocking semiconductor element 4 and the second blocking semiconductor element 8, respectively. Nevertheless, since it is not expected that the opposing arm will switch before the voltage at the first output terminal OUT1 becomes sufficiently low, the above-mentioned timing delay will not cause problems.

[0046] Furthermore, if the size of the semiconductor element 7 in the second output circuit is sufficiently large, it is possible to suppress the floating of the gate voltage of the second power semiconductor element 32. However, in such cases, the current when discharging the voltage at the second output terminal OUT2 becomes large, and the off operation of the second power semiconductor element 32 becomes faster, which leads to a problem in that the noise radiated to the outside from the semiconductor device becomes large. In contrast, according to this embodiment 1, the floating of the gate voltage of the second power semiconductor element 32 can be suppressed without increasing the size of the semiconductor element 7 in the second output circuit, so the increase in the above-mentioned noise can be suppressed.

[0047] <Embodiment 2> Figure 7 is a circuit diagram showing the configuration of the semiconductor element driving circuit IC according to this second embodiment, and Figure 8 is a timing chart showing an overview of the operation of the semiconductor element driving circuit IC.

[0048] The configuration in Figure 7 is the same as the configuration in Figure 1, except that the cutoff control circuit 10 is replaced by a delay buffer 16. The input terminal IN, the first output terminal OUT1, the second output terminal OUT2, the first output pre-stage circuit 1, the first output circuit including semiconductor elements 2 and 3, the first cutoff semiconductor element 4, the second output pre-stage circuit 5, the second output circuit including semiconductor elements 6 and 7, the second cutoff semiconductor element 8, and the cutoff pre-stage circuit 9 are the same as those in Embodiment 1.

[0049] The delay buffer 16 is configured to enable the first and second blocking semiconductor elements 4 and 8 to be turned on by outputting a delayed signal, which is a signal whose falling edge is delayed from the input signal, to the first blocking semiconductor element 4 and 8 via the blocking pre-stage circuit 9.

[0050] In this second embodiment, the delay buffer 16 outputs a low-level signal to the pre-cutoff circuit 9 at time t8, which is delayed by time td from the falling edge time t7 of the input signal at the input terminal IN in Figure 8, causing the voltage at the connection point VG to become high. As a result, at time t8, the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are turned on.

[0051] Furthermore, it is preferable that the delay by the delay buffer 16 is adjusted so that the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 turn on with a sufficient delay after the switching of the first power semiconductor element 31 and the second power semiconductor element 32. With such a configuration, noise radiated to the outside from the semiconductor device can be suppressed.

[0052] In this second embodiment, the delayed signal is a signal whose falling edge is delayed from the input signal, but whose rising edge is not delayed from the input signal. Therefore, the delay buffer 16 outputs a high-level signal to the pre-cutoff circuit 9 at the rising edge time t6 of the input signal at the input terminal IN in Figure 8, causing the voltage at the connection point VG to become low.

[0053] Figure 9 is a circuit diagram showing an example configuration of the delay buffer 16. As shown in Figure 9, the delay buffer 16 may be composed of PMOS 51, 54, resistor 52, and NMOS 53, 55. The PMOS 51, resistor 52, and NMOS 53 are connected in series in this order from the power supply voltage (VCC) to the reference voltage (GND) to form a first NOT gate. The PMOS 54 and NMOS 55 are connected in series in this order from the power supply voltage (VCC) to the reference voltage (GND) to form a second NOT gate. The connection point between resistor 52 and NMOS 53 is connected to the gates of PMOS 54 and NMOS 55, effectively connecting the first NOT gate and the second NOT gate in series.

[0054] The resistor 52 connected to the PMOS 51 delays the rising edge of the output signal of the first NOT circuit relative to the falling edge of the input signal. The second NOT circuit inverts the output signal of the first NOT circuit. As a result, the delay buffer 16 configured in this way is able to output a low-level signal to the pre-cutoff circuit 9 at a time t8, which is delayed by time td from the falling edge t7 of the input signal at the input terminal IN in Figure 8.

[0055] Note that the configuration of the delay buffer 16 is not limited to the configuration shown in Figure 9; other configurations may be used. The appropriate configuration for the delay buffer 16 should be applied depending on the application.

[0056] <Summary of Embodiment 2> As described above, the semiconductor element driving circuit IC according to this second embodiment is configured to enable the first and second interruption semiconductor elements 4 and 8 to be turned on by outputting a delayed signal, which is a signal whose falling edge is delayed from the input signal, to the first interruption semiconductor element 4 and the second interruption semiconductor element 8 via the interruption pre-stage circuit 9. With this configuration, malfunctions of the first power semiconductor element 31 and the second power semiconductor element 32 can be suppressed, similar to the first embodiment.

[0057] Furthermore, in this embodiment 2, one pre-cutting circuit 9 and one delay buffer 16 control both the first cut-off semiconductor element 4 and the second cut-off semiconductor element 8. Therefore, the circuit size can be reduced compared to a configuration in which a pre-cutting circuit and a delay buffer are provided for each of the first cut-off semiconductor element 4 and the second cut-off semiconductor element 8.

[0058] <Embodiment 3> Figure 10 is a circuit diagram showing the configuration of the semiconductor element driving circuit IC according to this third embodiment, and Figure 11 is a timing chart showing an overview of the operation of the semiconductor element driving circuit IC.

[0059] The configuration in Figure 10 is the same as that in Figure 1, with the addition of a delay buffer 18. The input terminal IN, the first output terminal OUT1, and the second output terminal OUT2 are the same as those in Embodiment 1.

[0060] The delay buffer 18 is generally the same as the delay buffer 16 according to Embodiment 2, and generates a delay signal from the input signal of the input terminal IN, which is a signal whose falling edge is delayed.

[0061] The first output pre-stage circuit 1 generates a delay-response signal based on the delay signal from the delay buffer 18. In this embodiment 3, the first output pre-stage circuit 1 is a NOT gate (inverter) and generates a delay-response signal by inverting the level of the delay signal.

[0062] The first output circuit, which includes semiconductor elements 2 and 3, is generally the same as the first output circuit according to Embodiment 1, and drives the first power semiconductor element 31 via the first output terminal OUT1 based on a delay-responding signal from the first output pre-stage circuit 1.

[0063] The first cutoff semiconductor element 4 is the same as the first cutoff semiconductor element 4 according to Embodiment 1. The second output pre-stage circuit 5 is generally the same as the second output pre-stage circuit 5 according to Embodiment 1, and generates an input corresponding signal based on the input signal of the input terminal IN. The second output circuit, including semiconductor elements 6 and 7, is generally the same as the second output circuit according to Embodiment 1, and drives the second power semiconductor element 32 via the second output terminal OUT2 based on the input corresponding signal from the second output pre-stage circuit 5.

[0064] The second cutoff semiconductor element 8 is generally the same as the second cutoff semiconductor element 8 in Embodiment 1, and when turned on, it reduces the voltage at the second output terminal OUT2. However, in Embodiment 3, the second cutoff semiconductor element 8 is turned on based on a delayed response signal from the first output pre-stage circuit 1.

[0065] In this embodiment 3, the delay buffer 18 outputs a low-level signal to the first output pre-stage circuit 1 at time t13, which is delayed by time td from the falling edge time t12 of the input signal at the input terminal IN in Figure 11. As a result, the voltage at the first output terminal OUT1 begins to fall. Also, at time t13, the voltage at the connection point VG2 between the first output pre-stage circuit 1 and the second cutoff semiconductor element 8 becomes high, so the second cutoff semiconductor element 8 turns on.

[0066] Furthermore, it is preferable that the delay by the delay buffer 18 is adjusted so that the second cutoff semiconductor element 8 turns on with a sufficient delay after the switching of the second power semiconductor element 32. With such a configuration, noise radiated to the outside from the semiconductor device can be suppressed.

[0067] In this embodiment 3, the delayed signal is a signal whose falling edge is delayed from the input signal, but whose rising edge is not delayed from the input signal. Therefore, the delay buffer 18 outputs a high-level signal to the first output pre-stage circuit 1 at the rising edge time t11 of the input signal at the input terminal IN in Figure 11, causing the voltage at the connection point VG2 to become low.

[0068] The pre-cutting circuit 9 in Figure 10 is generally the same as the pre-cutting circuit 9 according to Embodiment 1, and is connected to the gate of the first cutoff semiconductor element 4. However, in Embodiment 3, the pre-cutting circuit 9 is not connected to the gate of the second cutoff semiconductor element 8.

[0069] The cutoff control circuit 10 is generally the same as the cutoff control circuit 10 according to Embodiment 1, and turns on the first cutoff semiconductor element 4 via the cutoff pre-stage circuit 9 when the input signal is at a low level and the voltage of the first output terminal OUT1 is lower than a predetermined value Vgt. In other words, at time t14 in Figure 11, the cutoff control circuit 10 turns on the first cutoff semiconductor element 4 via the cutoff pre-stage circuit 9. However, in Embodiment 3, the cutoff control circuit 10 does not turn on the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9.

[0070] <Summary of Embodiment 3> According to the semiconductor element driving circuit IC of this embodiment 3 described above, the cutoff control circuit 10 turns on the first cutoff semiconductor element 4 when the input signal at the input terminal IN is at a low level and the voltage at the first output terminal OUT1 is lower than the value Vgt. The second cutoff semiconductor element 8 is turned on based on a delayed response signal from the first output pre-stage circuit 1. With this configuration, malfunctions of the first power semiconductor element 31 and the second power semiconductor element 32 can be suppressed, similar to embodiment 1.

[0071] Furthermore, in this embodiment 3, the delay buffer 18 and the first output pre-stage circuit 1 control the second cutoff semiconductor element 8. Therefore, the circuit size can be reduced compared to a configuration in which the second cutoff semiconductor element 8 is equipped with a cutoff pre-stage circuit and a cutoff control circuit.

[0072] <Embodiment 4> Figure 12 is a circuit diagram showing the configuration of the semiconductor element driving circuit IC according to this fourth embodiment. The timing chart showing the general operation of the semiconductor element driving circuit IC is generally the same as the timing chart in Figure 2.

[0073] The configuration in Figure 12 is the same as the configuration in Figure 1, but with the addition of diode 21. Diode 21 has a cathode connected to the first output terminal OUT1 and an anode connected to the second output terminal OUT2. The diode may be an SBD (Schottky barrier diode) or a PND (PN junction diode).

[0074] With the semiconductor element driving circuit IC according to this embodiment 4, the voltage at the second output terminal OUT2 can be made lower than the voltage at the first output terminal OUT1. As a result, the gate voltage floating of the second power semiconductor element 32 can be suppressed more than the gate voltage floating of the first power semiconductor element 31, thereby preventing the second power semiconductor element 32, which has a low threshold voltage Vth2, from malfunctioning.

[0075] In the above description, an example was given in which the diode 21 according to Embodiment 4 is applied to the configuration shown in Figure 1 of Embodiment 1. However, the diode 21 may also be applied to the configurations of Embodiments 2 and 3.

[0076] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0077] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0078] The various aspects of this disclosure are summarized below as an appendix.

[0079] (Note 1) Input terminals, The first output terminal to which the first power semiconductor element is connected, A second output terminal is connected in parallel with the first power semiconductor element, and a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected to the second output terminal, A first output pre-stage circuit that generates a first input corresponding signal based on the input signal of the input terminal, A first output circuit that drives the first power semiconductor element via the first output terminal based on the first input corresponding signal, A first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, A second output pre-stage circuit that generates a second input corresponding signal based on the aforementioned input signal, A second output circuit that drives the second power semiconductor element via the second output terminal based on the second input corresponding signal, A second cutoff semiconductor element that reduces the voltage at the second output terminal when turned on, A pre-interruption circuit connected to the first interruption semiconductor element and the second interruption semiconductor element, When the input signal is at a low level and the voltage at the first output terminal is lower than a predetermined value, the cutoff control circuit turns on the first cutoff semiconductor element and the second cutoff semiconductor element via the cutoff pre-stage circuit. A semiconductor device driving circuit equipped with the following features.

[0080] (Note 2) Input terminals, The first output terminal to which the first power semiconductor element is connected, A second output terminal is connected in parallel with the first power semiconductor element, and a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected to the second output terminal, A first output pre-stage circuit that generates a first input corresponding signal based on the input signal of the input terminal, A first output circuit that drives the first power semiconductor element via the first output terminal based on the first input corresponding signal, A first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, A second output pre-stage circuit that generates a second input corresponding signal based on the aforementioned input signal, A second output circuit that drives the second power semiconductor element via the second output terminal based on the second input corresponding signal, A second cutoff semiconductor element that reduces the voltage at the second output terminal when turned on, A pre-interruption circuit connected to the first interruption semiconductor element and the second interruption semiconductor element, A delay signal, which is a signal whose falling edge is delayed from the input signal, is output to the first and second blocking semiconductor elements via the pre-blocking circuit, thereby creating a delay buffer that can turn on the first and second blocking semiconductor elements. A semiconductor device driving circuit equipped with the following features.

[0081] (Note 3) Input terminals, The first output terminal to which the first power semiconductor element is connected, A second output terminal is connected in parallel with the first power semiconductor element, and a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected to the second output terminal, A delay buffer generates a delayed signal from the input signal of the aforementioned input terminal, which is a signal whose falling edge is delayed. A first output pre-stage circuit that generates a delay-compatible signal based on the aforementioned delay signal, A first output circuit that drives the first power semiconductor element via the first output terminal based on the delay-responding signal, A first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, A second output pre-stage circuit that generates an input-corresponding signal based on the aforementioned input signal, A second output circuit drives the second power semiconductor element via the second output terminal based on the input corresponding signal, A second cutoff semiconductor element that is turned on based on the aforementioned delay-responding signal and, when turned on, reduces the voltage at the second output terminal, The interruption pre-stage circuit connected to the first interruption semiconductor element, When the input signal is at a low level and the voltage at the first output terminal is lower than a predetermined value, a cutoff control circuit turns on the first cutoff semiconductor element via the cutoff pre-stage circuit. A semiconductor device driving circuit equipped with the following features.

[0082] (Note 4) A semiconductor element driving circuit described in any one of the items from Appendix 1 to Appendix 3, A semiconductor device driving circuit further comprising a diode having a cathode connected to the first output terminal and an anode connected to the second output terminal.

[0083] (Note 5) A semiconductor element driving circuit described in any one of the items from Appendix 1 to Appendix 4, The second power semiconductor element is a semiconductor element driving circuit with a smaller chip area than the first power semiconductor element.

[0084] (Note 6) A semiconductor element driving circuit described in any one of the items from Appendix 1 to Appendix 5, The first power semiconductor device is an IGBT made of silicon, The second power semiconductor element is a MOSFET made of silicon carbide, and the semiconductor element driving circuit is a semiconductor element. [Explanation of Symbols]

[0085] 1 First output pre-stage circuit, 2,3,6,7 Semiconductor elements, 4 First cutoff semiconductor element, 5 Second output pre-stage circuit, 8 Second cutoff semiconductor element, 9 Cutoff pre-stage circuit, 10 Cutoff control circuit, 16,18 Delay buffer, 21 Diode, 31 First power semiconductor element, 32 Second power semiconductor element, IC Semiconductor element driving circuit, IN Input terminal, OUT1 First output terminal, OUT2 Second output terminal.

Claims

1. Input terminals, The first output terminal to which the first power semiconductor element is connected, A second output terminal is connected in parallel with the first power semiconductor element, and a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected to the second output terminal, A first output pre-stage circuit that generates a first input corresponding signal based on the input signal of the input terminal, A first output circuit that drives the first power semiconductor element via the first output terminal based on the first input corresponding signal, A first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, A second output pre-stage circuit that generates a second input corresponding signal based on the aforementioned input signal, A second output circuit that drives the second power semiconductor element via the second output terminal based on the second input corresponding signal, A second cutoff semiconductor element that reduces the voltage at the second output terminal when turned on, A pre-interruption circuit connected to the first interruption semiconductor element and the second interruption semiconductor element, When the input signal is at a low level and the voltage at the first output terminal is lower than a predetermined value, the cutoff control circuit turns on the first cutoff semiconductor element and the second cutoff semiconductor element via the cutoff pre-stage circuit. A semiconductor device driving circuit equipped with the following features.

2. Input terminals, The first output terminal to which the first power semiconductor element is connected, A second output terminal is connected in parallel with the first power semiconductor element, and a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected to the second output terminal, A first output pre-stage circuit that generates a first input corresponding signal based on the input signal of the input terminal, A first output circuit that drives the first power semiconductor element via the first output terminal based on the first input corresponding signal, A first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, A second output pre-stage circuit that generates a second input corresponding signal based on the aforementioned input signal, A second output circuit that drives the second power semiconductor element via the second output terminal based on the second input corresponding signal, A second cutoff semiconductor element that reduces the voltage at the second output terminal when turned on, A pre-interruption circuit connected to the first interruption semiconductor element and the second interruption semiconductor element, A delay signal, which is a signal whose falling edge is delayed from the input signal, is output to the first and second blocking semiconductor elements via the pre-blocking circuit to create a delay buffer that can turn on the first and second blocking semiconductor elements. A semiconductor device driving circuit equipped with the following features.

3. Input terminals, The first output terminal to which the first power semiconductor element is connected, A second output terminal is connected in parallel with the first power semiconductor element, and a second power semiconductor element having a lower threshold voltage than the first power semiconductor element is connected to the second output terminal, A delay buffer generates a delayed signal from the input signal of the aforementioned input terminal, which is a signal whose falling edge is delayed. A first output pre-stage circuit that generates a delay-compatible signal based on the aforementioned delay signal, A first output circuit that drives the first power semiconductor element via the first output terminal based on the delay-responding signal, A first cutoff semiconductor element that reduces the voltage at the first output terminal when turned on, A second output pre-stage circuit generates an input-corresponding signal based on the aforementioned input signal, A second output circuit drives the second power semiconductor element via the second output terminal based on the input corresponding signal, A second cutoff semiconductor element that is turned on based on the aforementioned delay-responding signal and, when turned on, reduces the voltage at the second output terminal, The interruption pre-stage circuit connected to the first interruption semiconductor element, When the input signal is at a low level and the voltage at the first output terminal is lower than a predetermined value, the cutoff control circuit turns on the first cutoff semiconductor element via the cutoff pre-stage circuit. A semiconductor device driving circuit equipped with the following features.

4. A semiconductor device driving circuit according to any one of claims 1 to 3, A semiconductor device driving circuit further comprising a diode having a cathode connected to the first output terminal and an anode connected to the second output terminal.

5. A semiconductor device driving circuit according to any one of claims 1 to 3, The second power semiconductor element is a semiconductor element driving circuit with a smaller chip area than the first power semiconductor element.

6. A semiconductor device driving circuit according to any one of claims 1 to 3, The first power semiconductor device is an IGBT made of silicon, The second power semiconductor element is a MOSFET made of silicon carbide, and the semiconductor element driving circuit is also a semiconductor element.

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