Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing leakage current. [Solution] The semiconductor device includes a first power line to which a first voltage is supplied, a second power line to which a second voltage lower than the first voltage is supplied, a first logic circuit including a first electrode and electrically connected to the first power line, a second logic circuit including a second electrode provided spaced apart from the first electrode and electrically connected to the first power line and the first logic circuit, a voltage supply circuit that controls whether or not to supply a third voltage lower than the first voltage and higher than the second voltage to the first electrode by a first control signal, and a first transistor having a gate electrode to which a second control signal is input and electrically connected between the second electrode and the second power line.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices.

Background Art

[0002] A memory system including a NAND-type flash memory as a semiconductor device is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0005] To provide a semiconductor device capable of suppressing leakage current. [Means for solving the problem]

[0006] A semiconductor memory device according to one embodiment includes: a first power line to which a first voltage is supplied; a second power line to which a second voltage lower than the first voltage is supplied; a first logic circuit including a first electrode and electrically connected to the first power line; a second logic circuit including a second electrode provided at a distance from the first electrode and electrically connected to the first power line and the first logic circuit; a voltage supply circuit that controls whether or not to supply a third voltage lower than the first voltage and higher than the second voltage to the first electrode by a first control signal; and a first transistor having a gate electrode to which a second control signal is input and electrically connected between the second electrode and the second power line.

[0007] A semiconductor memory device according to one embodiment includes: a first power line to which a first voltage is supplied; a second power line to which a second voltage lower than the first voltage is supplied; a first logic circuit including a first electrode and electrically connected to the first power line; a second logic circuit including a second electrode provided spaced apart from the first electrode and electrically connected to the first power line and the first logic circuit; a voltage supply circuit that controls whether or not to supply a third voltage lower than the first voltage and higher than the second voltage by a first control signal; a first transistor having a gate electrode to which a second control signal is input and electrically connected between the second electrode and the second power line; a second transistor having a gate electrode to which a third control signal is input and electrically connected between the first electrode and the second power line; a first switch whose switching is controlled by a fourth control signal and electrically connected between the voltage supply circuit and the first electrode; and a second switch whose switching is controlled by the fourth control signal and electrically connected between the voltage supply circuit and the second electrode. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing the configuration of a memory system and host including a semiconductor storage device according to the first embodiment. [Figure 2] This is a block diagram showing the configuration of a memory system including a semiconductor storage device according to the first embodiment. [Figure 3] This is a circuit diagram showing the configuration of a memory cell according to the first embodiment. [Figure 4] This figure shows an example of a sense amplifier module according to the first embodiment. [Figure 5] This figure shows the configuration of a circuit for outputting data from the input / output circuit to the memory cell array according to the first embodiment. [Figure 6] This is a circuit diagram showing the configuration of the leakage current reduction circuit according to the first embodiment. [Figure 7] Figure 6 is a diagram illustrating an example of the operation of the leakage current reduction circuit shown. [Figure 8]This is a circuit diagram showing the configuration of the leakage current reduction circuit according to the first embodiment. [Figure 9] This is a circuit diagram showing an example of the configuration of the leakage current reduction circuit according to the comparative example. [Figure 10] This is a diagram for explaining an example of the electrical characteristics of an n-channel MOS transistor and an n-channel MOS transistor. [Figure 11] This is a diagram for explaining an example of the electrical characteristics of a p-channel MOS transistor and a p-channel MOS transistor. [Figure 12] This is a schematic diagram showing an example of the structure of an n-channel MOS transistor and a p-channel MOS transistor. [Figure 13] This is a circuit diagram showing the configuration of the leakage current reduction circuit according to the second embodiment. [Figure 14] This is a diagram for explaining an example of the operation of the leakage current reduction circuit shown in FIG. 13. [Figure 15] This is a diagram for explaining an example of the operation of the leakage current reduction circuit shown in FIG. 13.

Modes for Carrying Out the Invention

[0009] Hereinafter, each embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions and configurations are denoted by common reference numerals. When distinguishing a plurality of components having the same reference numeral, a suffix (for example, a capital letter of the alphabet, a capital letter of the alphabet, a number, a hyphen and a capital letter and a number, etc.) is attached to the common reference numeral for distinction.

[0010] In the following description, signal X <p:0>A signal X (where p is a natural number) is a (p+1) bit signal, where each bit is 1 bit. <0> , X <1> , , , and X It means a set of elements. Component Y <p:0>This refers to signal X <p:0> Component Y has a one-to-one correspondence with either the input or output. <0> , Y <1> , , , and Y< / p:0> means a set of.

[0011] [1. First Embodiment] Referring to FIGS. 1 to 8, a semiconductor device according to the first embodiment will be described. As an example, the semiconductor device is a memory system 3.

[0012] [1-1. Overview of Memory System 3 and Host 4] Referring to FIG. 1, an overview of the memory system 3 and the host 4 will be described. FIG. 1 is a block diagram showing a configuration example of the memory system 3 and the host 4. The memory system 3 includes a memory controller 1 and a semiconductor memory device 2. The memory system 3 is connectable to the host 4. The memory system 3 is, for example, a memory card such as an SSD (solid state drive), an SD card, etc. The host 4 is, for example, an electronic device such as a personal computer, a mobile terminal, etc. The memory system 3 may include the host 4.

[0013] The semiconductor memory device 2 is, for example, connected to the memory controller 1 and controlled using the memory controller 1. The semiconductor memory device 2 is a memory that stores data non-volatilely and includes, for example, a NAND memory (NAND type flash memory). The semiconductor memory device 2 includes i memory cells electrically connected to i bit lines BL. Each of the memory cells includes a memory cell transistor MT (see FIG. 3). One memory cell (memory cell transistor MT) can be set to two n or more threshold voltages (n is a positive integer). In this case, a plurality of memory cells that are units of read and write operations can hold n pages of data. For example, when the unit of data for read and write operations is 16 kB, read and write operations are performed collectively on 217 memory cells.

[0014] The semiconductor memory device 2 may include a 5-bit / Cell (PLC (Penta Level Cell)) NAND memory, each memory cell capable of being set to a threshold voltage of 5 bits (25 combinations, 32 values). Alternatively, the semiconductor memory device 2 may include a 4-bit / Cell (QLC (Quad Level Cell)) NAND memory, each memory cell capable of being set to a threshold voltage of 4 bits (24 combinations, 16 values), a 3-bit / Cell (TLC (Triple Level Cell)) NAND memory, each memory cell capable of being set to a threshold voltage of 3 bits (23 combinations, 8 values), or a 2-bit / Cell (MLC (Multi Level Cell)) NAND memory, each memory cell capable of being set to a threshold voltage of 2 bits (22 combinations, 4 values). For example, if the semiconductor memory device 2 includes a 5-bit / Cell NAND memory, the 217 memory cells, as units for read and write operations, can hold 5 pages (16kB x 5) of data.

[0015] For example, the memory controller 1 receives a request from the host 4 necessary for the operation of the semiconductor storage device 2 and sends the request to the semiconductor storage device 2. The memory controller 1 sends the request to the semiconductor storage device 2 and controls the read operation of data from the semiconductor storage device 2, the write operation of data to the semiconductor storage device 2, and the erase operation of data in the semiconductor storage device 2.

[0016] [1-2. Configuration of Memory Controller 1] The configuration of the memory controller 1 will be explained with reference to Figures 1 and 2. Figure 2 is a block diagram showing the configuration of the memory system 3, which includes the semiconductor memory device 2.

[0017] The following signals are transmitted and received between the memory controller 1 and the semiconductor memory device 2: chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, write protect signal WPn, signal DQ<7:0>, data strobe signal DQSn, and the complementary signal BDQSn of the data strobe signal DQSn.

[0018] For example, the semiconductor memory device 2 and the memory controller 1 are each formed as semiconductor chips (hereinafter also simply referred to as chips).

[0019] The chip enable signal CEn is a signal used to enable (activate) the semiconductor memory device 2. The command latch enable signal CLE is a signal used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 2 is the command CMD. The address latch enable signal ALE is a signal used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 2 is the address information ADD.

[0020] The write enable signal WEn is a signal for inputting the received signal into the semiconductor memory device 2, and is asserted by the memory controller 1 each time a command, address, and data are received. For example, the semiconductor memory device 2 is instructed to input the signal DQ<7:0> while the signal WEn is low. Alternatively, the semiconductor memory device 2 may be instructed to input the signal DQ<7:0> while the signal WEn is high. A low level may be denoted as Low level, "L" level, or "0", and a high level may be denoted as High level, "H" level, or "1". For example, a high level indicates a high voltage value, a low level indicates a low voltage value, and a high level is a higher voltage than a low level.

[0021] The read enable signal REn is a signal used by the memory controller 1 to read data from the semiconductor memory device 2. For example, the read enable signal REn is used to control the operating timing of the semiconductor memory device 2 when it outputs the signal DQ<7:0>.

[0022] The write-protect signal WPn is a signal used to instruct the semiconductor memory device 2 to prohibit data writing and erasure. The signal DQ<7:0> is the actual data transmitted and received between the semiconductor memory device 2 and the memory controller 1. The signal DQ<7:0> is an 8-bit signal. The data strobe signal DQSn and its complementary signal BDQSn are signals used to control the input and output timing of the signal DQ<7:0>.

[0023] The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correct) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are connected to each other by an internal bus 16.

[0024] The host interface 13 outputs requests, user data (write data), etc., received from the host 4 to the internal bus 16. The host interface 13 also sends user data read from the semiconductor memory device 2, responses from the processor 12, etc., to the host 4.

[0025] The memory interface 15 controls write operations, which write user data etc. to the semiconductor storage device 2, and read operations, which read user data etc. from the semiconductor storage device 2, based on instructions from the processor 12.

[0026] The processor 12 provides overall control over the memory controller 1. The processor 12 is, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), etc. When the processor 12 receives a request from the host 4 via the host interface 13, it performs control according to that request.

[0027] RAM 11 temporarily stores user data received from host 4 before storing it in semiconductor memory 2, and temporarily stores data read from semiconductor memory 2 before sending it to host 4. RAM 11 is a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0028] The ECC circuit 14 encodes user data stored in the RAM 11 to generate a codeword. The ECC circuit 14 also decodes the codeword read from the semiconductor memory device 2.

[0029] As an example, the memory system 3 shown in Figure 1 includes a memory controller 1 equipped with an ECC circuit 14 and a memory interface 15. However, the memory system 3 is not limited to the example shown in Figure 1. For example, the memory system 3 may include an ECC circuit 14 built into the memory interface 15, or it may include an ECC circuit 14 built into the semiconductor memory device 2.

[0030] Here, we will briefly explain the operation of memory system 3.

[0031] For example, the processor 12 may instruct the memory interface 15 to write user data and parity to the semiconductor storage device 2 in response to a request received from the host 4, and may also instruct the memory interface 15 to read user data and parity from the semiconductor storage device 2 in response to a request received from the host 4.

[0032] Furthermore, the processor 12 determines the storage area (memory area) on the semiconductor memory device 2 for user data stored in RAM 11. User data is stored in RAM 11 via the internal bus 16. The processor 12 determines the memory area for data in page units (page data, e.g., 16kB), which are the writing units. For example, user data stored in one page of the semiconductor memory device 2 is defined as unit data. Generally, unit data is encoded by the ECC circuit 14 and stored in the semiconductor memory device 2 as a codeword. Encoding is not mandatory in the memory system 3. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding it. Note that the configuration of the memory system 3 shown in Figure 1 is an example configuration in which encoding is performed. If the memory controller 1 does not perform encoding, the page data will match the unit data. Also, one codeword may be generated based on one unit data, or one codeword may be generated based on divided data obtained by dividing the unit data. Furthermore, one codeword may be generated using multiple unit data.

[0033] Furthermore, the processor 12 determines the memory area of ​​the semiconductor storage device 2 to which each unit data should be written. A physical address is assigned to the memory area of ​​the semiconductor storage device 2. The processor 12 manages the memory area to which the unit data should be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor storage device 2 by specifying the determined memory area (physical address). The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host 4) and its physical address. When the processor 12 receives a read request from the host 4 that includes a logical address, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0034] For example, when the memory system 3 receives a write request from the host 4, the memory system 3 operates as follows: The processor 12 temporarily stores the data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory device 2.

[0035] Furthermore, for example, if the memory system 3 receives a read request from the host 4, the memory system 3 operates as follows: The memory interface 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host 4 via the host interface 13.

[0036] [1-3. Configuration of Semiconductor Memory Device 2] The configuration of the semiconductor memory device 2 will be described with reference to Figures 1 and 2. As shown in Figure 2, the semiconductor memory device 2 includes a memory cell array 21, input / output circuits 22, logic control circuits 23, a sequencer 24, registers 25, a ready / busy circuit 26, a voltage generation circuit 27, a driver set 28, a row decoder 29, a sense amplifier module 100, a group of input / output pads 71, and a group of logic control pads 72. Various operations are performed in the semiconductor memory device 2, such as a write operation to store write data DAT in the memory cell array 21, and a read operation to read read data DAT from the memory cell array 21.

[0037] The memory cell array 21 is connected to, for example, a sense amplifier module 100, a row decoder 29, and a driver set 28. The memory cell array 21 includes blocks BLK0, BLK1, ..., BLKn (where n is an integer greater than or equal to 1). As will be described in detail later, each block BLK includes multiple string units SU (SU0, SU1, SU2, SU3). Each string unit SU includes multiple non-volatile memory cells associated with bit lines and word lines. A block BLK serves, for example, as a data erasure unit. Data held by memory cell transistors MTe0~MTe7 and MTo0~MTo7 (see Figure 2) contained within the same block BLK is erased collectively. In semiconductor memory devices 2, memory cell transistors MT are sometimes simply referred to as memory cells.

[0038] The input / output circuit 22 is connected, for example, to the register 25, the logic control circuit 23, and the sense amplifier module 100. The input / output circuit 22 controls the transmission and reception of data signals DQ<7:0> between the memory interface 15 included in the memory controller 1 and the semiconductor memory device 2.

[0039] As explained in "1-1-2. Configuration of Memory Controller 1," signal DQ<7:0> is the actual data transmitted and received between the semiconductor memory device 2 and the memory interface 15 included in the memory controller 1. Signal DQ<7:0> includes command CMD, data DAT, address information ADD, and status information STS, etc.

[0040] Command CMD includes, for example, commands for executing requests sent from host 4 to semiconductor storage device 2 via memory interface 15 included in memory controller 1. Command CMD includes, for example, commands for instructing the execution of write requests and read requests. Data DAT includes write data DAT to semiconductor storage device 2 or read data DAT from semiconductor storage device 2. Data DAT includes, for example, Edata. Address information ADD includes, for example, column addresses and row addresses for selecting a plurality of non-volatile memory cells associated with bit lines and word lines. Status information STS includes, for example, information regarding the status of semiconductor storage device 2 with respect to write and read operations.

[0041] Specifically, the input / output circuit 22 comprises an input circuit and an output circuit, which perform the following processing. The input circuit receives write data DAT, address information ADD, and command CMD from the memory controller 1. The input circuit transmits the received write data DAT to the sense amplifier module 100 and transmits the received address information ADD and command CMD to register 25. Meanwhile, the output circuit receives status information STS from register 25 and read data DAT from the sense amplifier module 100. The output circuit transmits the received status information STS and read data DAT to the memory interface 15 included in the memory controller 1.

[0042] The logic control circuit 23 is connected, for example, to the memory controller 1 and the sequencer 24. The logic control circuit 23 receives, for example, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, and the write protect signal WPn via the memory interface 15 of the memory controller 1. Based on the received signals, the logic control circuit 23 controls the input / output circuit 22 and the sequencer 24. The logic control circuit 23 and the sequencer 24 may be referred to as the "control circuit," and either the logic control circuit 23 or the sequencer 24 may be referred to as the "control circuit."

[0043] The sequencer 24 is connected, for example, to the ready / busy control circuit 26, the sense amplifier module 100, and the driver set 28. The sequencer 24 controls the operation of the entire semiconductor memory device 2 based on the command CMD held in the command register. For example, the sequencer 24 controls the sense amplifier module 100, the row decoder 29, the voltage generation circuit 27, and the driver set 28, etc., to perform various operations such as write operations, read operations, and erase operations.

[0044] Register 25 includes, for example, a status register (not shown in the diagram), an address register (not shown in the diagram), and a command register (not shown in the diagram). The status register receives and holds status information STS from the sequencer 24 and transmits the status information STS to the input / output circuit 22 based on instructions from the sequencer 24. The address register receives and holds address information ADD from the input / output circuit 22. The address register transmits the column address in the address information ADD to the sense amplifier module 100 and the row address in the address information ADD to the row decoder 29. The command register receives and holds the command CMD from the input / output circuit 22 and transmits the command CMD to the sequencer 24.

[0045] The ready / busy control circuit 26 generates a ready / busy signal R / Bn according to the control by the sequencer 24 and transmits the generated ready / busy signal R / Bn to the memory controller 1. The ready / busy signal R / Bn is a signal that indicates whether the semiconductor memory device 2 is in a ready state to accept instructions from the memory controller 1 or in a busy state that does not accept instructions.

[0046] The voltage generation circuit 27 is connected to, for example, a driver set 28. Based on control by the sequencer 24, the voltage generation circuit 27 generates voltages used for writing and reading operations, and supplies the generated voltages to the driver set 28.

[0047] The driver set 28 is connected to the memory cell array 21, the sense amplifier module 100, and the row decoder 29. Based on the voltage supplied from the voltage generation circuit 27 or the control signals supplied from the sequencer 24, the driver set 28 generates various voltages or control signals to be supplied to the selection gate line SGD (see Figure 3), word line WL (see Figure 3), source line SL (see Figure 3), and bit line BL (see Figure 3) during various operations such as read and write operations. The driver set 28 supplies the generated voltages or control signals to the sense amplifier module 100, the row decoder 29, the source line SL, etc.

[0048] The row decoder 29 receives a row address from the address register and decodes the received row address. Based on the result of the decoding, the row decoder 29 selects a block BLK (see Figure 3) to which it will perform various operations such as read and write operations. The row decoder 29 can supply voltage from the driver set 28 to the selected block BLK.

[0049] The sense amplifier module 100, for example, receives a column address from the address register and, based on the column address, performs data transmission and reception operations between the memory controller 1 and the memory cell array 21. The sense amplifier module 100 can also sense data (threshold voltage) read from the memory cell array 21 based on a read operation command and temporarily hold the read data. The sense amplifier module 100 can also perform logical operations based on the temporarily stored data. The sense amplifier module 100 transmits the read data (read data) DAT to the memory controller 1 via the input / output circuit 22. Furthermore, the sense amplifier module 100 receives write data DAT from the memory controller 1 via the input / output circuit 22 based on a write operation command and transmits the write data DAT to the memory cell array 21.

[0050] The sense amplifier module 100 includes, for example, a sense amplifier unit SAU (see Figure 4) provided for each bit line BL (BL0 to BL(N-1), where (N-1) is a natural number greater than or equal to 2, Figure 3). The sense amplifier unit SAU is electrically connected to the bit line BL so as to be able to supply data.

[0051] The input / output pad group 71 transmits the signal DQ<7:0> received from the memory controller 1 to the input / output circuit 22. The input / output pad group 71 transmits the signal DQ<7:0> received from the input / output circuit 22 to the memory controller 1.

[0052] The logic control pad group 72 forwards the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn received from the memory controller 1 to the logic control circuit 23. The logic control pad group 72 also forwards the ready / busy signal R / Bn received from the ready / busy control circuit 26 to the memory controller 1.

[0053] [1-4. Configuration of Memory Cell Array 21] The configuration of the memory cell array 21 will be described with reference to Figure 3. Figure 3 is a circuit diagram of a block BLK included in the memory cell array 21 of the semiconductor memory device 2. Block BLK0 will be used as an example for explanation, but the other blocks BLK1, 2, ... have similar circuits. Note that the circuit diagram shown in Figure 3 is an example and does not limit the circuit diagram of the memory cell array 21 of the first embodiment. Configurations identical or similar to those in Figures 1 and 2 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 and 2 may be omitted.

[0054] Block BLK0 is connected to N bit lines BL(BL0, BL1, ..., BL(N-1)). Block BLK0 is also connected to source line SL. A NAND string 116 is connected between the bit lines BL and source line SL. The NAND string 116 includes, for example, eight memory cell transistors MT(MT0~MT7), as well as selection transistors ST1 and ST2. Each memory cell transistor MT has a control gate and a charge storage layer to hold data non-volatile. The memory cell transistors MT are connected in series between the source of selection transistor ST1 and the drain of selection transistor ST2. The NAND string 116 is provided on the N bit lines BL to form a string unit SU(SU0, SU1). In Figure 3, the NAND string 116 includes, for example, eight memory cell transistors MT, but the number of memory cell transistors MT included in the NAND string 116 is not limited to eight. For example, the number of memory cell transistors MT may be i. For example, the integer i is a positive natural number, and it can be greater than or less than 8.

[0055] The selection transistor ST1 (corresponding to the lower-layer selection gate transistor described later) is connected to the selection gate line SGD0. The gate of the selection transistor ST1 in each string unit SU is connected to the selection gate line SGD (SGD0, SGD1, ...). The gates of the eight memory cell transistors MT (MT0 to MT7) are connected to the corresponding word lines WL (WL7 to WL0). In addition, the gate of the selection transistor ST2 in each string unit SU is connected to the selection gate line SGS. The gates of the selection transistor ST1 connected to each of the multiple bit lines BL within the same string unit SU are connected to the common selection gate line SGD. The gates of the selection transistor ST1 connected to each of the multiple bit lines BL within the same string unit SU are connected to the common selection gate line SGD. The gates of the memory cell transistors MT (MT0 to MT7) within the same string unit SU are connected to the common word lines WL (WL0 to WL7). Within the same string unit SU, memory cell transistors MT (MT0 to MT7) connected to the same word line WL (WL0 to WL7) constitute a unit for read and write operations. For example, the memory cell transistors MT7 in each NAND string 116 included in the string unit SU corresponding to the selected gate line SGD0 constitute a memory cell group MG as a unit for read and write operations, and read and write operations are performed collectively on the memory cell group MG. For example, if the unit of data to be read and written is 16kB, each memory cell group MG contains 217 memory cell transistors MT. In this case, 217 bit lines BL are provided.

[0056] [1-5. Configuration of the Sense Amplifier Unit SAU] Referring to Figure 4, an example of the circuit configuration of the sense amplifier unit SAU will be explained. Figure 4 is a diagram showing an example of the circuit configuration of the sense amplifier unit SAU. Note that the circuit configuration of the sense amplifier unit SAU shown in Figure 4 is just one example, and the circuit configuration of the sense amplifier unit SAU of the semiconductor memory device 2 is not limited to the example shown in Figure 4. Configurations identical or similar to those in Figures 1 to 3 will be explained as necessary, and explanations of configurations identical or similar to those in Figures 1 to 3 may be omitted.

[0057] For example, the sense amplifier unit SAU can temporarily hold data (threshold voltage) read out on the corresponding bit line BL. Furthermore, the sense amplifier unit SAU can perform logical operations using the temporarily stored data, and can temporarily hold the data after the logical operations. For example, the semiconductor memory device 2 can perform read and write operations using the sense amplifier module 100 (sense amplifier unit SAU).

[0058] As shown in Figure 4, the sense amplifier unit SAU includes a sense amplifier section SA, and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS so that they can send and receive data from each other.

[0059] For example, the sense amplifier section SA senses the data read to the corresponding bit line BL during a read operation and determines whether the read data is "0" or "1". For example, the sense amplifier section SA includes a p-channel MOS transistor 120, n-channel MOS transistors 121 to 128, and a capacitor 129.

[0060] One end of transistor 120 is connected to the first power line 202, and the gate of transistor 120 is connected to node INV in the latch circuit SDL. One end of transistor 121 is connected to the other end of transistor 120, and the other end of transistor 121 is connected to node COM, and the control signal BLX is input to the gate of transistor 121. One end of transistor 122 is connected to node COM, and the control signal BLC is input to the gate of transistor 122. Transistor 123 is a high-voltage MOS transistor, one end of transistor 123 is connected to the other end of transistor 122, and the other end of transistor 123 is connected to the corresponding bit line BL, and the control signal BLS is input to the gate of transistor 123.

[0061] One end of transistor 124 is connected to node COM, the other end of transistor 124 is connected to node SRC, and the gate of transistor 124 is connected to node INV. One end of transistor 125 is connected to the other end of transistor 120, the other end of transistor 125 is connected to node SEN, and the control signal HLL is input to the gate of transistor 125. One end of transistor 126 is connected to node SEN, the other end of transistor 126 is connected to node COM, and the control signal XXL is input to the gate of transistor 126.

[0062] One end of transistor 127 is grounded, and the gate of transistor 127 is connected to node SEN. One end of transistor 128 is connected to the other end of transistor 127, and the other end of transistor 128 is connected to bus LBUS, and the control signal STB is input to the gate of transistor 128. One end of capacitor 129 is connected to node SEN, and the clock CLK is input to the other end of capacitor 129.

[0063] For example, control signals BLX, BLC, BLS, HLL, XXL, and STB are generated by the sequencer 24. Also, for example, the first power line 202 connected to one end of the transistor 120 is supplied with voltage VDD (first voltage), which is the internal power supply voltage of the semiconductor memory device 2. Also, for example, node SRC is electrically connected to the second power line 204, and the second power line is supplied with voltage VSS (second voltage) as the reference voltage of the semiconductor memory device 2. For example, voltage VSS is a reference voltage that can define other voltages with respect to voltage VSS, and voltage VSS may be a reference voltage, may be 0V, or may be ground potential (earth potential).

[0064] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold the read data. For example, the latch circuit XDL is connected to register 25 and is used for data input and output between the sense amplifier unit SAU and the input / output circuit 22.

[0065] For example, the latch circuit SDL includes inverters 130 and 131, and n-channel MOS transistors 132 and 133. The input node of inverter 130 is connected to node LAT, and the output node of inverter 130 is connected to node INV. The input node of inverter 131 is connected to node INV, and the output node of inverter 131 is connected to node LAT. One end of transistor 132 is connected to node INV, and the other end of transistor 132 is connected to bus LBUS, and the control signal STI is input to the gate of transistor 132. One end of transistor 133 is connected to node LAT, and the other end of transistor 133 is connected to bus LBUS, and the control signal STL is input to the gate of transistor 133. For example, the data held at node LAT corresponds to the data held in the latch circuit SDL, and the data held at node INV corresponds to the inverted data of the data held at node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are similar to, for example, the circuit configuration of latch circuit SDL, so their explanation is omitted.

[0066] The timing at which each sense amplifier unit SAU in the sense amplifier module 100 determines the data read to the bit line BL is based on the timing at which the control signal STB is asserted. For example, "the sequencer 24 asserting the control signal STB" corresponds to the sequencer 24 changing the control signal STB from the "L" level to the "H" level.

[0067] In addition, in the sense amplifier unit SAU of the semiconductor memory device 2, the transistor 128 to which the control signal STB is input to the gate may be a p-channel MOS transistor. In this case, "the sequencer 24 asserting the control signal STB" corresponds to the sequencer 24 changing the control signal STB from a "H" level to a "L" level.

[0068] Furthermore, the number of latch circuits in the sense amplifier unit SAU can be set to any number. For example, the number of latch circuits is designed based on the number of bits of data held by one memory cell transistor MT. Also, multiple bit lines BL may be connected to a single sense amplifier unit SAU via a selector.

[0069] [1-6. Circuit configuration for sending and receiving data from input / output circuit 22 to memory cell array 21] Referring to Figure 5, the circuit configuration for sending and receiving data from the input / output circuit 22 to the memory cell array 21 will be explained. Configurations identical or similar to those in Figures 1 to 4 will be explained as necessary, and explanations of identical or similar configurations to those in Figures 1 to 4 may be omitted.

[0070] Figure 5 schematically shows the paths between the input / output pad group 71 and the memory cell array 21. For example, the path through which read data is transferred is the path from the memory cell array 21 to the input / output pad group 71, and the path through which write data is transferred is the path from the input / output pad group 71 to the memory cell array 21.

[0071] As described in "1-3. Configuration of Semiconductor Memory Device 2" or "1-5. Circuit Configuration of Sense Amplifier Unit SAU", the sense amplifier module 100 includes a plurality of sense amplifier units SAU. Each sense amplifier unit SAU includes a sense amplifier section SA and a latch circuit XDL. Furthermore, as shown in Figure 5, the sense amplifier module 100 includes a plurality of latch circuits XDL and a multiplexer MUX electrically connected to the holding section 50.

[0072] The multiplexer MUX is connected to the holding unit 50 by the sequencer 24 and a first data bus 51 consisting of 128 wires. The number of wires included in the first data bus 51 is not limited to 128. The number of wires included in the first data bus 51 is less than the number of wires connecting the multiple latch circuits XDL and the multiplexer MUX.

[0073] The storage unit 50 is connected to the input / output circuit 22 by a second data bus 52 consisting of 16 signal lines. Note that the number of wires included in the second data bus 502 is not limited to 16. The storage unit 50 has the function of storing multiple data read from the memory cell array 21 and is a memory device (Global FIFO) configured to perform so-called "first-in, first-out" (FIFO) operation.

[0074] The input / output circuit 22 is electrically connected to the input / output pad group 71. For example, the input / output pad group 71 includes 10 pads. Signal DQ <0> ~DQ <7> The data strobe signal DQSn and the complementary signal BDQSn are each supplied to 10 pads corresponding to their respective signals.

[0075] Furthermore, the semiconductor memory device 2 includes a leakage current reduction circuit 300. For example, at least one of the input / output circuit 22, the holding unit 50, and the multiplexer MUX includes an internal circuit 200 and a leakage current reduction circuit 300. As an example, in the semiconductor memory device 2 shown in Figure 5, each of the input / output circuit 22, the holding unit 50, and the multiplexer MUX includes an internal circuit 200 and a leakage current reduction circuit 300. As will be described in detail later, the leakage current reduction circuit 300 includes a plurality of logic circuits electrically connected to the internal circuit 200. For example, when the output signal of the internal circuit 200 maintains an "L" level or an "H" level, that is, when the input signal to one of the plurality of logic circuits electrically connected to the internal circuit 200 maintains an "L" level or an "H" level, the leakage current reduction circuit 300 has the function of suppressing the leakage current of the plurality of logic circuits.

[0076] When distinguishing between leakage current reduction circuits 300, they are denoted as leakage current reduction circuit 300A or leakage current reduction circuit 300B. Similarly, when distinguishing between internal circuits 200, they are denoted as internal circuit 200A or internal circuit 200B.

[0077] Here, we will explain, as an example, how the data to be read is transferred.

[0078] For example, data read from the memory cell array 21 is transmitted from the sense amplifier unit SA to the latch circuit XDL, held there, and then transferred to the holding unit 50 via the multiplexer MUX. The multiplexer MUX sequentially transfers the data transmitted from each of the multiple latch circuits XDL to the holding unit 50 via the first data bus 51.

[0079] The holding unit 50 temporarily holds multiple data transferred from the multiplexer MUX and transfers (outputs) these data to the input / output circuit 22 in the order in which the data was input. The data transferred from the holding unit 50 to the input / output circuit 22 is temporarily held inside the input / output circuit 22 and then output to the outside as signal DQ<7:0> from the input / output pad group 71.

[0080] For example, when a sequencer 24 receives a read request from the logic control circuit 23, it controls the transfer of data from the holding unit 50 to the input / output circuit 22. When the semiconductor memory device 2 receives a read request from the host 4 to read data containing consecutive "L" level data, and data containing consecutive "L" level data is input to the leakage current reduction circuit 300, the sequencer 24 controls the leakage current reduction circuit 300 to suppress the leakage current of the leakage current reduction circuit 300 based on the request.

[0081] [1-7. Leakage Current Reduction Circuit 300A] The leakage current reduction circuit 300A will be described with reference to Figures 6 to 8. Figure 6 is a circuit diagram showing the configuration of the leakage current reduction circuit 300A. Figure 7 is a diagram illustrating an example of the operation of the leakage current reduction circuit 300A shown in Figure 6. Figure 8 is a circuit diagram showing the specific configuration of the voltage supply circuit 350A included in the leakage current reduction circuit 300A.

[0082] [1-7-1. Configuration of the 300A Leakage Current Reduction Circuit] Referring to Figure 6, the configuration of the leakage current reduction circuit 300A will be explained. The leakage current reduction circuit 300A includes multiple logic circuits (logic circuits 310, 320, 330, and 340), a voltage supply circuit 350A, and a transistor 450 (first transistor). The number of multiple logic circuits shown in Figure 6 is an example, and the number of multiple logic circuits is not limited to the configuration shown in Figure 6. For example, a logic circuit is expressed in terms of the number of stages, depending on the number of electrically connected logic circuits. For example, one logic circuit is expressed as a one-stage logic circuit, and a circuit in which two logic circuits are electrically connected is expressed as a two-stage logic circuit. Therefore, the multiple logic circuits shown in Figure 6 are a four-stage logic circuit. Configurations identical or similar to those in Figures 1 to 5 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0083] For example, each of logic circuits 310, 320, 330, and 340 is an inverter (NOT gate). Each of logic circuits 310, 320, 330, and 340 may be a NAND gate or a NOR gate. Also, each of logic circuits 310, 320, 330, and 340 may be an inverter, a NAND gate, or a NOR gate.

[0084] The logic circuit 310 (first logic circuit) includes transistors 410 and 510. Transistor 410 includes a gate electrode 412, a first electrode 414, and a second electrode 416. Transistor 510 includes a gate electrode 512, a first electrode 514, and a second electrode 516. The gate electrode 412, the gate electrode 512, and the input terminal IN1 are electrically connected, the second electrode 416, the first electrode 514, and the output terminal OUT1 are electrically connected, the first electrode 414 is electrically connected to the second electrode 208, and the second electrode 516 is electrically connected to the first power line 202. The input terminal IN1 is also electrically connected to the internal circuit 200A via wiring 220. The logic circuit 310 is controlled by a control signal S5 supplied to the input terminal IN1. When a "L" level is supplied to the control signal S5, transistor 510 turns ON, transistor 410 turns OFF, and the logic circuit 310 outputs a voltage VDD to the output terminal OUT1. When a "H" level signal is supplied to the control signal S5, transistor 410 turns on, transistor 510 turns off, and the logic circuit 310 outputs the voltage VA (see Figure 7, etc.) supplied to the second electrode 208 to the output terminal OUT1.

[0085] Logic circuits 320, 330, and 340 have the same configuration as logic circuit 310.

[0086] The logic circuit 320 (second logic circuit) includes transistors 420 and 520. Transistor 420 includes a gate electrode 422, a first electrode 424, and a second electrode 426. Transistor 520 includes a gate electrode 522, a first electrode 524, and a second electrode 526. The gate electrode 422, the gate electrode 522, and the input terminal IN2 are electrically connected, the second electrode 426, the first electrode 524, and the output terminal OUT2 are electrically connected, the first electrode 424 is electrically connected to the first electrode 206, and the second electrode 526 is electrically connected to the first power line 202. The first electrode 206 is provided at a distance from the second electrode 208. In addition, the input terminal IN2 is electrically connected to the output terminal OUT1. The logic circuit 320 is controlled by a signal (voltage, potential) supplied to the input terminal IN2 (output terminal OUT1). When a "L" level is supplied to the signal, transistor 520 turns on and transistor 420 turns off, and logic circuit 320 outputs voltage VDD to output terminal OUT2. When a "H" level is supplied to the signal, transistor 420 turns on and transistor 520 turns off, and logic circuit 320 outputs voltage VA (see Figure 7, etc.) supplied to the second electrode 208 to output terminal OUT2.

[0087] The logic circuit 330 includes transistors 430 and 530. Transistor 430 includes a gate electrode 432, a first electrode 434, and a second electrode 436. Transistor 530 includes a gate electrode 532, a first electrode 534, and a second electrode 536. The gate electrode 432 and the input terminal IN3 are electrically connected, the second electrode 436 and the first electrode 534 are electrically connected, the first electrode 434 is electrically connected to the second electrode 208, and the second electrode 536 is electrically connected to the first power line 202. In addition, the input terminal IN3 is electrically connected to the output terminal OUT2. The logic circuit 330 is controlled by a signal (voltage, potential) supplied to the input terminal IN3 (output OUT2). When a "L" level signal is supplied, transistor 530 turns ON, transistor 430 turns OFF, and the logic circuit 330 outputs a voltage VDD to the output terminal OUT3. When a "H" level signal is supplied to the signal, transistor 430 turns on, transistor 530 turns off, and logic circuit 330 outputs the voltage VA (see Figure 7, etc.) supplied to the second electrode 208 to output terminal OUT3.

[0088] The logic circuit 340 includes transistors 440 and 540. Transistor 440 includes a gate electrode 442, a first electrode 444, and a second electrode 446. Transistor 540 includes a gate electrode 542, a first electrode 544, and a second electrode 546. The gate electrode 442, the gate electrode 542, and the input terminal IN4 are electrically connected, the second electrode 446, the first electrode 544, and the output terminal OUT4 are electrically connected, the first electrode 444 is electrically connected to the first electrode 206, and the second electrode 546 is electrically connected to the first power line 202. In addition, the input terminal IN4 is electrically connected to the output terminal OUT3, and the output terminal OUT4 is electrically connected to any circuit within each circuit. The logic circuit 340 is controlled by a signal (voltage, potential) supplied to the input terminal IN4 (output OUT2). When a "L" level signal is supplied to the signal, transistor 540 turns on and transistor 440 turns off, and logic circuit 340 outputs voltage VDD to output terminal OUT4. When a "H" level signal is supplied to the signal, transistor 440 turns on and transistor 540 turns off, and logic circuit 340 outputs voltage VA (see Figure 7, etc.) supplied to the second electrode 208 to output terminal OUT4.

[0089] The voltage supply circuit 350A is electrically connected to the second electrode 208 via wiring 218 and to the sequencer 24 via wiring 210. The voltage supply circuit 350A is controlled by a control signal S1 (first control signal) supplied to wiring 210. For example, when a "L" level is supplied to control signal S1, the voltage supply circuit 350A turns on and outputs voltage VA to wiring 218 and the second electrode 208. When a "H" level is supplied to control signal S1, the voltage supply circuit 350A turns off and does not output voltage VA to wiring 218 and the second electrode 208. The voltage supply circuit 350A generates voltage VA. Voltage VA is the voltage at which the potential difference Vgs (gate-source voltage) between the gate electrode and the first electrode of each transistor 410, 420, 430, and 440 becomes less than 0V when each transistor is in the off state. For example, voltage VA is less than voltage VDD (first voltage) and greater than voltage VSS (second voltage). For example, voltage VA is 50mV, but voltage VA is not limited to 50mV. Voltage VA can be set to any value depending on the specifications and application of the semiconductor memory device 2.

[0090] Transistor 450 includes a gate electrode 452, a first electrode 454, and a second electrode 456. The gate electrode 452 is electrically connected to the sequencer 24 via wiring 212, the first electrode 454 is electrically connected to the second power line 204, and the second electrode 456 is electrically connected to the first electrode 206. Transistor 450 is controlled by a control signal S2 (second control signal) supplied to wiring 212. For example, when a "H" level is supplied to control signal S2, transistor 450 turns on and outputs a voltage VSS to the first electrode 206. When a "L" level is supplied to control signal S2, transistor 450 turns off and does not output a voltage VSS to the first electrode 206.

[0091] The internal circuit 200A includes multiple logic circuits. The multiple logic circuits include combinational circuits or sequential circuits. For example, the internal circuit 200A outputs a control signal S5 to wiring 220. The control signal S5 is an output signal of the internal circuit 200A. Depending on the signal input to the internal circuit 200A, the internal circuit 200A may output a control signal S5 of the "L" level, may output a control signal S5 of the "H" level, may output a control signal S5 that includes both "L" and "H" levels, with probabilistically more "L" levels than "H" levels, or may output a control signal S5 that includes both "L" and "H" levels, with probabilistically more "H" levels than "L" levels.

[0092] In the leakage current reduction circuit 300A, odd-numbered logic circuits (310 and 330) are electrically connected to the second electrode 208, and even-numbered logic circuits (320 and 230) are electrically connected to the first electrode 206 and transistor 450. Also, as explained in "1-5. Configuration of Sense Amplifier Unit SAU", the first power line 202 is supplied with voltage VDD, and the second power line 204 is supplied with voltage VSS.

[0093] Transistors 410, 420, 430, 440, and 450 are n-channel MOS transistors, while transistors 510, 520, 530, and 540 are p-channel MOS transistors.

[0094] In the semiconductor memory device 2, the conduction state of a transistor is defined as the state in which the transistor is ON, where the first electrode (e.g., source electrode) and the second electrode (e.g., drain electrode) are conducting, and the state in which the transistor is OFF, where the first electrode (e.g., source electrode) and the second electrode (e.g., drain electrode) are not conducting. In each transistor, the source electrode and drain electrode may be swapped depending on the voltage or potential supplied to each electrode.

[0095] [1-7-2. An example of how the 300A leakage current reduction circuit operates] Referring to Figure 7, an example of how the leakage current reduction circuit 300A operates will be explained. For clarity, the symbols for the electrodes of each transistor have been omitted in Figure 7. The example of operation shown in Figure 7 includes the internal circuit 200A supplying a "L" level control signal S5 to the wiring 220. Configurations identical or similar to those in Figures 1 to 6 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0096] For example, the semiconductor memory device 2 receives a read request from the host 4 to read data containing consecutive "L" level data, and the sequencer 24 receives a read request from the logic control circuit 23. Based on this request, the sequencer 24 supplies an "H" level control signal S1 to the voltage supply circuit 350A via the wiring 210. The sequencer 24 also supplies a High level ("H" level) control signal S2 to the gate electrode 452 of the transistor 450 via the wiring 212.

[0097] When the voltage supply circuit 350A receives a "H" level control signal S1, it generates a voltage VA and supplies voltage VA to the second electrode 208 via wiring 218. When transistor 450 receives a "H" level control signal S2, it turns on and supplies voltage VSS to the first electrode 206. The voltage VDD supplied to the first power line 202 is supplied to transistors 510, 520, 530, and 540.

[0098] When a control signal S5 at the "L" level (for example, voltage VSS or 0V) is supplied to the first-stage logic circuit 310, the transistor 510 turns on, and the logic circuit 310 outputs voltage VDD to the output terminal OUT1 (input terminal IN2). At this time, the gate electrode 412 of transistor 410 is supplied with the "L" level control signal S5, and the first electrode 414 of transistor 410 is supplied with voltage VA. As a result, the potential difference Vgs is the difference between the "L" level and voltage VA, which is less than 0V. Therefore, as shown in Figure 7, the leakage current Ileak flowing through transistor 410 is suppressed. Here, the symbol "×" shown in Figure 7 means that the leakage current flowing between the second electrode 416 and the first electrode 414 of transistor 410 is suppressed.

[0099] When the voltage VDD is supplied to the second-stage logic circuit 320, transistor 420 turns on, and logic circuit 320 outputs the voltage VSS to output terminal OUT2 (input terminal IN3). At this time, the gate electrode 522 of transistor 520 is supplied with the voltage VDD, and transistor 520 is in the off state.

[0100] When the voltage VSS is supplied to the third-stage logic circuit 330, the transistor 530 turns on, and the logic circuit 330 outputs the voltage VDD to the output terminal OUT3 (input terminal IN4). At this time, the gate electrode 432 of transistor 430 is supplied with the voltage VSS, and the first electrode 434 of transistor 430 is supplied with the voltage VA. As a result, similar to the potential difference Vgs of transistor 410 in the first-stage logic circuit 330, the potential difference Vgs of transistor 430 in the third-stage logic circuit 330 is the difference between the voltage VSS and the voltage VA, and is less than 0V. Therefore, as shown in Figure 7, the leakage current Ileak flowing through transistor 430 is suppressed. Here, the symbol "×" shown in Figure 7 means that the leakage current flowing between the second electrode 436 and the first electrode 434 of transistor 430 is suppressed.

[0101] When the voltage VDD is supplied to the fourth-stage logic circuit 340, transistor 440 turns ON, and logic circuit 340 outputs the voltage VSS to output terminal OUT4. At this time, the gate electrode 542 of transistor 540 is supplied with the voltage VDD, and transistor 540 is OFF. The control signal OD is a signal that includes the voltage VSS.

[0102] Here, with reference to Figures 9 to 12, a leakage current reduction circuit related to a comparative example (hereinafter referred to as circuit 600A) will be described. Figure 9 is a circuit diagram showing an example of the configuration of circuit 600A. Figure 10 is a diagram illustrating an example of the electrical characteristics of an n-channel MOS transistor and an n-channel MOS transistor. Figure 11 is a diagram illustrating an example of the electrical characteristics of a p-channel MOS transistor and a p-channel MOS transistor. Figure 12 is a schematic diagram showing an example of the structure of an n-channel MOS transistor and a p-channel MOS transistor. When describing circuit 600A, if circuit 600A includes a configuration similar to that of leakage current reduction circuit 300A, circuit 600A will be described using components with the same reference numerals as those of leakage current reduction circuit 300A.

[0103] As shown in Figure 9, all of the first electrodes 414, 424, 434, and 444 of the logic circuits 310, 320, 330, and 340 in circuit 600A are connected to the first electrode 206, and the first electrode 206 is electrically connected to the second power line 204 via the n-channel MOS transistor 470.

[0104] Circuit 600A can be in at least a standby state and an active state. For example, the standby state is when the internal power supply voltage (voltage VDD) is supplied to the semiconductor memory device 2, but circuit 600A is not in use. In this state, the signal from circuit 600A does not affect the next stage circuit. The active state is when the semiconductor memory device 2 is operational. In this state, circuit 600A outputs a signal in response to the signal supplied from the internal circuit 200A.

[0105] First, we will explain how to suppress the leakage current flowing through circuit 600A when it is in standby mode. For example, when circuit 600A is in standby mode, the n-channel MOS transistor 470 is turned off, thereby blocking the current paths of logic circuits 310, 320, 330, and 340. For example, the n-channel MOS transistor 470 in circuit 600A is sometimes called a foot switch. By providing a foot switch in circuit 600A, it is possible to suppress the leakage current in the standby state of circuit 600A.

[0106] Furthermore, in the active state of circuit 600A, if the on-resistance of the n-channel MOS transistor 470 (foot switch) is high, the voltage drop across the n-channel MOS transistor 470 will increase, causing the potential of the first electrode 206 to rise above the voltage VSS. In this case, the operating speed of logic circuits 310, 320, 330, and 340 will decrease. To ensure the operating performance of circuit 600A in the active state, the on-resistance of the n-channel MOS transistor 470 (foot switch) must be sufficiently low. Therefore, in circuit 600A, the size of the n-channel MOS transistor 470 is made sufficiently large. Specifically, for example, the gate electrode 472 of the n-channel MOS transistor 470 should have a sufficient gate width. Consequently, generally, when an n-channel MOS transistor 470 is provided as a foot switch in circuit 600A, the overall area of ​​circuit 600A increases.

[0107] On the other hand, the footswitch suppresses leakage current in the standby state, but does not contribute to suppressing leakage current when the entire 600A circuit is in the active state.

[0108] Next, we will explain the suppression of leakage current flowing through circuit 600A when circuit 600A is in the active state. Generally, the threshold voltage Vth of an n-channel MOS transistor and a p-channel MOS transistor changes by applying a bias to the substrate electrodes. That is, the threshold voltage of a MOS transistor can be controlled by applying a bias to the substrate electrodes of the MOS transistor.

[0109] As an example, the suppression of leakage current in the active state of a p-channel MOS transistor using the substrate bias effect will be explained using transistor 510 as an example. For example, the configuration and electrical characteristics of MOS transistor 510 are shown in Figure 10. For example, the first electrode 514 is the drain electrode, the second electrode 516 is the source electrode, and the third electrode 518 is the body electrode (substrate electrode). MOS transistors 520, 530, and 540 have similar electrical characteristics. Note that the substrate electrodes of each p-channel MOS transistor in the first embodiment and the second embodiment described later are omitted.

[0110] The plot shown in Figure 10 illustrates the relationship between the voltage |Vgs| (absolute value of Vgs) supplied between the gate electrode 512 and the first electrode 514 of the MOS transistor 510 and the drain current |Ids| (absolute value of Ids). It includes the electrical characteristics PB1 when no bias is applied to the third electrode 518, and the electrical characteristics PB2 when a bias is applied to the third electrode 518.

[0111] As shown in Figure 10, the threshold voltage |Vthp2| (absolute value of Vthp2) when a bias is applied to the third electrode 518 is greater than the threshold voltage |Vthp1| (absolute value of Vthp1) when no bias is applied to the third electrode 518. That is, when the same voltage |Vgs| is applied, the drain current |Ids| in the electrical characteristic PB2 when a bias is applied to the third electrode 518 is smaller than the drain current |Ids| in the electrical characteristic PB1 when no bias is applied to the third electrode 518. The substrate bias effect caused by applying a bias to the third electrode 518 suppresses the leakage current of the MOS transistor 510 (and MOS transistors 520, 530, 540). By applying a substrate bias effect to the p-channel MOS transistors included in circuit 600A, the leakage current when circuit 600A is in the active state can be suppressed.

[0112] Similarly, using MOS transistor 410 as an example, the suppression of leakage current in the active state of an n-channel MOS transistor using the substrate bias effect will be explained. For example, the configuration and electrical characteristics of MOS transistor 410 are shown in Figure 11. For example, the first electrode 414 is the drain electrode, the second electrode 416 is the source electrode, and the third electrode 418 is the body electrode (substrate electrode). MOS transistors 420, 430, and 440 have similar electrical characteristics. Note that, as with the p-channel MOS transistor, the description of the substrate electrodes of each n-channel MOS transistor in the first embodiment and the second embodiment described later is omitted.

[0113] The plot shown in Figure 11 illustrates the relationship between the voltage Vgs supplied between the gate electrode 412 and the first electrode 414 of the MOS transistor 410 and the drain current Ids. The plot shown in Figure 11 includes the electrical characteristics NB1 when no bias is applied to the third electrode 418, and the electrical characteristics NB2 when a bias is applied to the third electrode 418.

[0114] As shown in Figure 11, the threshold voltage Vthn2 when a bias is applied to the third electrode 418 is greater than the threshold voltage Vthn1 when no bias is applied to the third electrode 418. That is, when the same voltage Vgs is applied, the drain current Ids in the electrical characteristic NB2 when a bias is applied to the third electrode 418 is smaller than the drain current Ids in the electrical characteristic NB1 when no bias is applied to the third electrode 418. The substrate bias effect caused by applying a bias to the third electrode 418 suppresses the leakage current of the MOS transistor 410 (and MOS transistors 420, 430, and 440). By applying a substrate bias effect to the n-channel MOS transistors included in circuit 600A, the leakage current when circuit 600A is in the active state can be further suppressed.

[0115] On the other hand, in practice, it is difficult to impart a substrate bias effect to an n-channel MOS transistor. Figure 12 schematically shows the cross-sectional configuration of logic circuit 310 (MOS transistor 410 and MOS transistor 510). Note that in Figure 12, the specific connection relationship between MOS transistor 410 and MOS transistor 510 in logic circuit 310 is omitted.

[0116] For example, as shown in Figure 12, the gate electrode 412, first electrode 414, second electrode 416, third electrode 418, gate electrode 512, first electrode 514, second electrode 516, and third electrode 518 are connected to the gate 602, n-type diffusion layer 604, n-type diffusion layer 606, p-type substrate 608, gate 612, p-type diffusion layer 614, p-type diffusion layer 616, and n-well 618, respectively.

[0117] As shown in Figure 12, the MOS transistor 510 is formed in an n-well 618 provided on the p-type substrate 608, and the MOS transistor 410 is formed on the p-type substrate 608. Furthermore, the n-well 618 is provided for each p-channel MOS transistor corresponding to circuit 600A, and the p-type substrate 608 is shared with circuits other than circuit 600A.

[0118] The leakage current of the MOS transistor 510 in the active state is suppressed by applying a bias to the n-well 618 via the third electrode 518. On the other hand, the leakage current of the MOS transistor 410 in the active state is suppressed by applying a bias to the p-type substrate 608 via the third electrode 418. However, as described above, the p-type substrate 608 is shared with circuits other than circuit 600A. Since the p-type substrate 608 is normally supplied with voltage VSS, it is difficult to apply a bias to the p-type substrate 608 in circuit 600A for the purpose of reducing the leakage current of the MOS transistor 410 in the active state.

[0119] For example, circuits other than circuit 600A may prioritize high-speed operation by lowering the transistor threshold voltage rather than suppressing leakage current in the active state by raising the transistor threshold voltage. Therefore, circuit 600A may not be able to utilize the board bias effect depending on the state of the circuits other than circuit 600A.

[0120] In other words, in circuit 600A, while the leakage current in the active state of the p-channel MOS transistor can be suppressed by adjusting the threshold voltage of the transistor using the substrate bias effect, it is difficult to suppress the leakage current in the active state of the n-channel MOS transistor by adjusting the threshold voltage of the transistor using the substrate bias effect. Therefore, in circuit 600A, even if the threshold voltage of the transistor is adjusted using the substrate bias effect, it is difficult to suppress the overall leakage current of circuit 600A in the active state.

[0121] On the other hand, as described above, in the leakage current reduction circuit 300A, the first electrodes 414 and 434 of transistors 410 and 430 of the odd-numbered logic circuits 310 and 330 are connected to the second electrode 208 to which voltage VA is supplied by the voltage supply circuit 350A, and the first electrodes 424 and 444 of transistors 420 and 440 of the even-numbered logic circuits 320 and 340 are connected to the first electrode 206 to which transistor 460 is connected and to which voltage VSS is supplied. As a result, voltage VA is supplied by the voltage supply circuit 350 to the odd-numbered logic circuits 310 and 330 to which "L" level, voltage VSS, or 0V is input, so that the potential difference Vgs of transistors 410 and 430 of the odd-numbered logic circuits 310 and 330 can be made smaller than 0V. As a result, the semiconductor memory device 2 can suppress the leakage current Ileak flowing through the leakage current reduction circuit 300 more effectively than the leakage current reduction circuit (circuit 600A) in the comparative example.

[0122] [1-7-3. Configuration of the 350A Voltage Supply Circuit] Referring to Figure 8, the specific configuration of the voltage supply circuit 350A included in the leakage current reduction circuit 300A will be explained. Configurations identical or similar to those in Figures 1 to 7 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0123] The voltage supply circuit 350A includes an operational amplifier circuit 380 and a transistor 460.

[0124] The operational amplifier circuit 380 includes a first input terminal 382, ​​a second input terminal 384, a third input terminal 388, and an output terminal 386. The first input terminal 382 is electrically connected to the second electrode 208, the second input terminal 384 is electrically connected to the wiring 218 to which voltage VA is supplied, the third input terminal 388 is electrically connected to the sequencer 24 via the wiring 210, and the output terminal 386 is electrically connected to the gate electrode 462 of transistor 460. For example, voltage VA is generated by the voltage generation circuit 27 and supplied to the voltage supply circuit 350. For example, the operational amplifier circuit 380 operates so that the voltage supplied to the second electrode 208 maintains voltage VA.

[0125] Transistor 460 includes a gate electrode 462, a first electrode 464, and a second electrode 466. The first electrode 464 is electrically connected to the second power line 204, and the second electrode 466 is electrically connected to the first electrode 206. Transistor 460 is controlled by a signal (voltage, potential) supplied to the output terminal 386. For example, when a "H" level is supplied to the output terminal 386, transistor 450 turns on, and transistor 460 outputs a voltage VSS to the first electrode 206. When a "L" level is supplied to the output terminal 386, transistor 450 turns off, and transistor 450 does not output a voltage VSS to the first electrode 206. Transistor 460 is an n-channel MOS transistor. Transistors 450 and 460 also function as footswitches.

[0126] For example, the leakage current reduction circuit (circuit 600A) in the comparative example shown in Figure 9 includes a configuration in which an n-channel MOS transistor 470 controls logic circuits 310, 320, 330, and 340. The size of the n-channel MOS transistor 470 (e.g., the gate width of the gate electrode 472) needs to be large in order to ensure current driving capability for logic circuits 310, 320, 330, and 340.

[0127] On the other hand, the leakage current reduction circuit 300A includes a configuration that allows for the separate control of odd-numbered logic circuits 310 and 330 connected to transistor 460, which functions as a foot switch, and even-numbered logic circuits 320 and 340 connected to transistor 450, which also functions as a foot switch. The size of transistor 460 only needs to be large enough to ensure current driving power for logic circuits 310 and 330, and the size of transistor 450 only needs to be large enough to ensure current driving power for logic circuits 320 and 340. Therefore, the combined size of transistor 470 provided in the comparative example circuit 600A and the combined size of transistors 460 and 450 provided in the leakage current reduction circuit 300A of this embodiment can be the same. Thus, the difference in circuit area of ​​the leakage current reduction circuit 300 compared to the circuit area of ​​circuit 600A is substantially limited to the increase due to the addition of the operational amplifier circuit 380 included in the voltage supply circuit 350A.

[0128] In other words, the leakage current reduction circuit 300A includes a configuration in which the odd-numbered logic circuits 310 and 330 and the even-numbered logic circuits 320 and 340 are separated, and the even-numbered logic circuits and the odd-numbered logic circuits can be controlled using different footswitches (transistors 460 and 450), and a configuration that minimizes the increase in circuit area. In this way, the semiconductor memory device 2 including the leakage current reduction circuit 300A can suppress leakage current in the active state in addition to suppressing leakage current in the standby state, while minimizing the increase in circuit area compared to the leakage current reduction circuit (circuit 600A) of the comparative example.

[0129] In addition, as an example of the leakage current reduction circuit 300A, the voltage VA supplied by the voltage supply circuit 350A is shown to be supplied to the second electrode 208 connected to the logic circuits 310 and 330. In this case, as shown in Figure 7, the effect of suppressing leakage current in the active state is enhanced when the control signal S5 supplied to the first-stage logic circuit 310 is at the "L" level. Therefore, it is preferable to apply the configuration of the leakage current reduction circuit 300A to circuits in which the first-stage logic circuit is often supplied with a control signal at the "L" level. On the other hand, even when the signal can be at either the "L" or "H" level, if a configuration similar to the leakage current reduction circuit 300A is applied to multiple locations in the semiconductor memory device 2, the leakage current in the active state can be statistically suppressed throughout the entire semiconductor memory device 2. Furthermore, in circuits where a "H" level control signal is often supplied to the first-stage logic circuit, the leakage current suppression effect in the active state can be enhanced by configuring the voltage VA supplied by the voltage supply circuit 350A to be supplied to the first electrode 206 connected to the logic circuits 320 and 340, based on the configuration of the leakage current reduction circuit 300A.

[0130] [2. Second Embodiment] The leakage current reduction circuit 300B according to the second embodiment will be described with reference to Figures 13 to 15. Figure 13 is a circuit diagram showing the configuration of the leakage current reduction circuit 300B. Figures 14 and 15 are circuit diagrams illustrating an example of the operation of the leakage current reduction circuit 300B shown in Figure 13. Configurations identical or similar to those in Figures 1 to 12 will be described as necessary, and descriptions of identical or similar configurations may be omitted.

[0131] [2-1. Configuration of the 300B Leakage Current Reduction Circuit] Referring to Figure 13, the configuration of the leakage current reduction circuit 300B will be explained. The leakage current reduction circuit 300B includes configurations 1 to 3 shown below. Configurations 1 to 3 in the leakage current reduction circuit 300B differ from the configuration of the leakage current reduction circuit 300A according to the first embodiment. Configuration 1: Includes voltage supply circuit 350B, switches 360 and 370. Configuration 2: The sequencer 24 is electrically connected to the transistor 460 via wiring 214, electrically connected to the transistor 460 via wiring 214, electrically connected to switches 360 and 370 via wiring 216, and electrically connected to the voltage supply circuit 350B via wiring 210. Configuration 3: Voltage supply circuit 350B, switches 360 and 370, transistor 460, and configurations related to the voltage supply circuit 350B, switches 360 and 370, and transistor 460.

[0132] The voltage supply circuit 350B is controlled by the control signal S1 supplied to the wiring 210. For example, when a "H" level is supplied to the control signal S1, the voltage supply circuit 350B turns on and outputs voltage VA to the wiring 218. When a "L" level is supplied to the control signal S1, the voltage supply circuit 350B turns off and does not output voltage VA to the wiring 218. The voltage supply circuit 350B generates voltage VA.

[0133] The gate electrode 462 of transistor 460 is electrically connected to the sequencer 24 via wiring 214. Transistor 460 is controlled by a control signal S3 (third control signal) supplied to wiring 214. For example, when a "H" level is supplied to control signal S3, transistor 460 turns on and outputs a voltage VSS to the second electrode 208. When a "L" level is supplied to control signal S3, transistor 460 turns off and does not output a voltage VSS to the second electrode 208.

[0134] Switch 360 is electrically connected between the voltage supply circuit 350B and the second electrode 208. Switch 360 is also electrically connected to the sequencer 24 via wiring 216. Control signal S4 (fourth control signal) is supplied to wiring 216 by the sequencer 24, and switch 360 is controlled by control signal S4. For example, when a "H" level is supplied to control signal S4, switch 360 turns ON and outputs the voltage VA supplied from the voltage supply circuit 350B to wiring 218 to the second electrode 208. When a "L" level is supplied to control signal S4, switch 360 turns OFF and does not output voltage VA to the second electrode 208.

[0135] Switch 370 is electrically connected between the voltage supply circuit 350B and the first electrode 206. Switch 370 is also electrically connected to the sequencer 24 via wiring 216. A control signal S4 is supplied to wiring 216 by the sequencer 24, and switch 370 is controlled by the control signal S4. For example, when a "L" level is supplied to control signal S4, switch 370 turns ON and outputs the voltage VA supplied from the voltage supply circuit 350B to wiring 218 to the first electrode 206. When a "H" level is supplied to control signal S4, switch 370 turns OFF and does not output the voltage VA to the first electrode 206.

[0136] Internal circuit 200C includes internal circuit 200A and internal circuit 200B. Internal circuit 200A includes supplying an "L" level control signal S5 to wiring 220, similar to the leakage current reduction circuit 300A according to the first embodiment. Internal circuit 200B also includes supplying an "H" level control signal S5 to wiring 220. For example, internal circuit 200C may receive a control signal from the sequencer 24 and select internal circuit 200A and internal circuit 200B. For example, based on the request, the sequencer 24 supplies an "H" level control signal S1 to the voltage supply circuit 350 via wiring 210. Furthermore, since the sequencer 24 receives requests from the logic control circuit 23, it is aware in advance that the request may include a signal followed by an "H" level signal, a signal followed by an "L" level signal, and a request may probabilistically include both "L" and "H" levels. Therefore, the sequencer 24 can control whether to select internal circuit 200A or internal circuit 200B.

[0137] Configurations other than those described above, including configurations 1 to 3, are the same as those of the leakage current reduction circuit 300A according to the first embodiment. Configurations and functions similar to those of the leakage current reduction circuit 300A will be described as necessary, and descriptions of configurations and functions similar to those of the leakage current reduction circuit 300A may be omitted.

[0138] [2-2. An example of how the 300B leakage current reduction circuit operates] Referring to Figure 14, an example of how the leakage current reduction circuit 300B operates will be explained. For clarity, the symbols for the electrodes of each transistor have been omitted in Figure 14. The example of operation shown in Figure 14 includes the internal circuit 200A supplying a "L" level control signal S5 to the wiring 220. Configurations identical or similar to those in Figures 1 to 13 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0139] For example, the semiconductor memory device 2 receives a read request from the host 4 to read data containing consecutive "L" level data, and the sequencer 24 receives a read request from the logic control circuit 23. Based on this request, the sequencer 24 supplies an "H" level control signal S1 to the voltage supply circuit 350 via wiring 210, an "H" level control signal S2 to the gate electrode 452 of transistor 450 via wiring 212, an "L" level control signal S3 to the gate electrode 462 of transistor 460 via wiring 214, and an "H" level control signal S4 to switches 360 and 370 via wiring 216. In addition, for example, an "H" level control signal is supplied to the internal circuit 200A.

[0140] When switches 360 and 370 receive a "H" level control signal S4, switch 360 turns ON, connecting and conducting wiring 218 to the second electrode 208, while switch 370 turns OFF, disconnecting wiring 218 from the first electrode 206. When the voltage supply circuit 350B receives a "H" level control signal S1, it generates voltage VA. Also, when transistor 460 receives a "L" level control signal S3, it turns OFF, disconnecting the second power line 204 from the second electrode 208. Therefore, voltage VA is supplied to the second electrode 208 via wiring 218 and switch 360. When transistor 450 receives a "H" level control signal S2, it turns ON and supplies voltage VSS to the first electrode 206. For example, when the internal circuit 200A receives a "H" level control signal, it supplies a "L" level control signal S5 to the first stage logic circuit 310. The voltage VDD supplied to the first power line 202 is supplied to transistors 510, 520, 530, and 540.

[0141] An "L" level control signal S5 is supplied to the first-stage logic circuit 310, and the logic circuit 340 outputs a voltage VSS to the output terminal OUT4. The operation method of the first-stage logic circuit 310 to the fourth-stage logic circuit 340 is the same as the operation method of the leakage current reduction circuit 300A described with reference to Figure 7. Therefore, the explanation of the operation method of the leakage current reduction circuit 300B with reference to Figure 14 is omitted here.

[0142] [2-3. An example of how the 300B leakage current reduction circuit operates] Referring to Figure 15, an example of how the leakage current reduction circuit 300B operates will be explained. For clarity, the symbols for the electrodes of each transistor have been omitted in Figure 15. The example of operation shown in Figure 15 includes the internal circuit 200B supplying a "H" level control signal S5 to the wiring 220. Configurations identical or similar to those in Figures 1 to 14 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0143] For example, the semiconductor memory device 2 receives a read request from the host 4 to read data containing consecutive "H" level data, and the sequencer 24 receives a read request from the logic control circuit 23. Based on this request, the sequencer 24 supplies an "H" level control signal S1 to the voltage supply circuit 350 via wiring 210, an "L" level control signal S2 to the gate electrode 452 of transistor 450 via wiring 212, an "H" level control signal S3 to the gate electrode 462 of transistor 460 via wiring 214, and an "L" level control signal S4 to switches 360 and 370 via wiring 216. In addition, for example, an "L" level control signal is supplied to the internal circuit 200B.

[0144] When switches 360 and 370 receive a "L" level control signal S4, switch 370 turns ON, connecting and conducting wiring 218 to the first electrode 206, while switch 360 turns OFF, disconnecting wiring 218 from the second electrode 208. When the voltage supply circuit 350B receives a "H" level control signal S1, it generates voltage VA. Also, when transistor 450 receives a "L" level control signal S2, it turns OFF, disconnecting the second power line 204 from the first electrode 206. Therefore, voltage VA is supplied to the second electrode 208 via wiring 218 and switch 360. When transistor 460 receives a "H" level control signal S2, it turns ON and supplies voltage VSS to the second electrode 208. For example, when the internal circuit 200B receives a "L" level control signal, it supplies a "H" level control signal S5 to the first stage logic circuit 310. The voltage VDD supplied to the first power line 202 is supplied to transistors 510, 520, 530, and 540.

[0145] When a control signal S5 of the "H" level (for example, voltage VDD) is supplied to the first-stage logic circuit 310, transistor 410 turns on, and logic circuit 310 outputs voltage VSS to output terminal OUT1 (input terminal IN2). At this time, the gate electrode 522 of transistor 510 is supplied with the "H" level control signal S5, and transistor 520 is in the off state.

[0146] When the voltage VSS is supplied to the second stage logic circuit 320, transistor 520 turns on, and logic circuit 320 outputs the voltage VDD to the output terminal OUT2 (input terminal IN3). The gate electrode 422 of transistor 420 is supplied with the voltage VSS, and the first electrode 424 of transistor 420 is supplied with the voltage VA. As a result, the potential difference Vgs is the difference between the voltage VSS and the voltage VA, and is less than 0V. Therefore, as shown in Figure 15, the leakage current Ileak flowing through transistor 420 is suppressed. Here, the symbol "×" shown in Figure 15 means that the leakage current flowing between the second electrode 426 and the first electrode 424 of transistor 420 is suppressed.

[0147] When the voltage VDD is supplied to the third-stage logic circuit 330, transistor 430 turns on, and logic circuit 330 outputs the voltage VSS to output terminal OUT3 (input terminal IN4). At this time, the gate electrode 532 of transistor 530 is supplied with the voltage VDD, and transistor 530 is in the off state.

[0148] When the voltage VSS is supplied to the fourth-stage logic circuit 340, transistor 540 turns on, and logic circuit 340 outputs the voltage VDD to the output terminal OUT4. At this time, the gate electrode 442 of transistor 440 is supplied with the voltage VSS, and the first electrode 444 of transistor 440 is supplied with the voltage VA. As a result, similar to the potential difference Vgs of transistor 420 in the second-stage logic circuit 320, the potential difference Vgs of transistor 440 in the fourth-stage logic circuit 340 is the difference between the voltage VSS and the voltage VA, and is less than 0V. Therefore, as shown in Figure 15, the leakage current Ileak flowing through transistor 440 is suppressed. Here, the symbol "×" shown in Figure 15 means that the leakage current flowing between the second electrode 446 and the first electrode 444 of transistor 440 is suppressed. Also, the control signal OD is a signal that includes the voltage VDD.

[0149] In other words, the leakage current reduction circuit 300B, like the leakage current reduction circuit 300A, includes a configuration in which the odd-numbered logic circuits 310 and 330 and the even-numbered logic circuits 320 and 340 are separated, and the even-numbered logic circuits and the odd-numbered logic circuits can be controlled using different footswitches (transistors 460 and 450). Furthermore, the leakage current reduction circuit 300B can control the supply of voltage VA to the first electrode 206 and the supply of voltage VSS to the second electrode 208, and the supply of voltage VSS to the first electrode 206 and the supply of voltage VA to the second electrode 208, using control signals S1 to S4, voltage supply circuits 350B, switches 360 and 370, and transistors 450 and 460. As a result, the semiconductor memory device 2 can control the footswitch (transistors 460 and 450) in accordance with the control signal S5 supplied to the leakage current reduction circuit 300B. Therefore, compared to the leakage current reduction circuit (circuit 600A) in the comparative example, it is possible to suppress leakage current in the active state in addition to suppressing leakage current in the standby state. Furthermore, since the voltage supply circuit 350B can selectively supply voltage VA to either the second electrode 208 connected to logic circuits 310 and 330 or the first electrode 206 connected to logic circuits 320 and 340, the leakage current suppression effect in the active state can be enhanced whether an "L" level control signal is supplied to the first-stage logic circuit or an "H" level control signal is supplied to the first-stage logic circuit.

[0150] In each of the above embodiments, when the terms "identical" and "identical" are used, these terms may include cases where errors within the design range are included.

[0151] Although several embodiments of the semiconductor device of this disclosure have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and may be combined as appropriate without departing from the spirit of the invention, and various omissions, substitutions, and modifications are permitted. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0152] 1: Memory controller, 2: Semiconductor memory device, 3: Memory system, 4: Host, 12: Processor, 13: Host interface, 14: ECC (Error Check and Correct) circuit, 15: Memory interface, 16: Internal bus, 21: Memory cell array, 22: Input / output circuit, 23: Logic control circuit, 24: Sequencer, 25: Register, 26: Busy control circuit 116: NAND string, 120: transistor, 121: transistor, 122: transistor, 123: transistor, 124: transistor Transistor, 125: Transistor, 126: Transistor, 127: Transistor, 128: Transistor, 129: Capacitor, 130: Inverter, 131: Inverter, 132: Transistor, 133: Transistor, 200: Internal circuit, 200A: Internal circuit, 200B: Internal circuit, 200C: Internal circuit, 202: First power line, 204: Second power line, 206: First electrode, 208: Second electrode, 210: Wiring, 212: Wiring, 214: Wiring, 216: Wiring, 218: Wiring, 220: Wiring, 230: Logic circuit, 300: Leakage current reduction circuit, 300A: Recycle 300B: Leakage current reduction circuit, 310: Logic circuit, 311: Logic circuit, 312: Logic circuit, 313: Logic circuit, 314: Logic circuit, 320: Logic circuit, 330: Logic circuit, 340: Logic circuit, 350A: Voltage supply circuit, 350B: Voltage supply circuit, 360: Switch, 370: Switch, 380: Operational amplifier circuit, 382: First input terminal, 384: Second input terminal, 386: Output terminal, 388: Third input terminal, 410: Transistor, 412: Gate electrode, 414: First electrode, 416: Second electrode, 418: Third electrode, 420: Transistor,422: Gate electrode, 424: First electrode, 426: Second electrode, 430: Transistor, 432: Gate electrode, 434: First electrode, 436: Second electrode, 440: Transistor, 442: Gate electrode, 444: First electrode, 446: Second electrode, 450: Transistor, 452: Gate electrode, 454: First electrode, 456: Second electrode, 460: Transistor, 462: Gate electrode, 464: First electrode, 466: Second electrode, 502: Second data bus, 510: Transistor, 512: Gate electrode, 514: First electrode, 5 16: Second electrode, 518: Third electrode, 520: Transistor, 522: Gate electrode, 524: First electrode, 526: Second electrode, 530: Transistor, 532: Gate electrode, 534: First electrode, 536: Second electrode, 540: Transistor, 542: Gate electrode, 544: First electrode, 546: Second electrode, 550: Transistor, 600A: Circuit, 602: Gate, 604: n-type diffusion layer, 606: n-type diffusion layer, 608: p-type substrate, 612: Gate, 614: p-type diffusion layer, 616: p-type diffusion layer, 618: n-well,

Claims

1. A first power line to which the first voltage is supplied, A second power line to which a second voltage lower than the first voltage is supplied, A first logic circuit including a first electrode and electrically connected to the first power line, A second logic circuit, which includes a second electrode provided at a distance from the first electrode, and is electrically connected to the first power line and the first logic circuit, A voltage supply circuit that controls whether or not to supply a third voltage lower than the first voltage and higher than the second voltage to the first electrode based on a first control signal, A semiconductor device comprising: a first transistor having a gate electrode to which a second control signal is input, and which is electrically connected between the second electrode and the second power line.

2. The semiconductor device according to claim 1, further comprising a control circuit that outputs the first control signal and the second control signal.

3. The semiconductor device according to claim 2, wherein when the second voltage is input to the first logic circuit, the control circuit controls the following to be possible: supply a high-level voltage to the first control signal, causing the voltage supply circuit to supply the third voltage to the first electrode; and supply a high-level voltage to the second control signal, causing the first transistor to supply the second voltage to the second electrode.

4. The semiconductor device according to claim 1, wherein the first transistor is an n-channel MOS transistor.

5. The aforementioned voltage supply circuit is A second transistor having a gate electrode and electrically connected between the second electrode and the second power line, The operational amplifier circuit includes a first input terminal electrically connected to the second electrode, a second input terminal to which the third voltage is supplied, a third input terminal to which the first control signal is input, and an output terminal electrically connected to the gate electrode of the second transistor. The semiconductor device according to claim 4, wherein the second transistor is an n-channel MOS transistor.

6. A first power line to which the first voltage is supplied, A second power line to which a second voltage lower than the first voltage is supplied, A first logic circuit including a first electrode and electrically connected to the first power line, A second logic circuit, which includes a second electrode provided at a distance from the first electrode, and is electrically connected to the first power line and the first logic circuit, A voltage supply circuit that controls whether or not to supply a third voltage lower than the first voltage and higher than the second voltage based on a first control signal, A first transistor having a gate electrode to which a second control signal is input, and electrically connected between the second electrode and the second power line, A second transistor having a gate electrode to which a third control signal is input, and electrically connected between the first electrode and the second power line, A fourth control signal controls the switching of a first switch, which is electrically connected between the voltage supply circuit and the first electrode. The switching is controlled by the fourth control signal, and a second switch is electrically connected between the voltage supply circuit and the second electrode, Semiconductor equipment, including

7. The semiconductor device according to claim 6, wherein the first transistor and the second transistor are n-channel MOS transistors.

8. The semiconductor device according to claim 7, further comprising a control circuit that outputs the first control signal, the second control signal, the third control signal, and the fourth control signal.

9. When the second voltage is input to the first logic circuit, the control circuit controls the following to be possible: supply a high-level voltage to the fourth control signal, turn on the second switch to connect the voltage supply circuit and the second electrode, and turn off the first switch to disconnect the voltage supply circuit from the first electrode; supply a high-level voltage to the first control signal, causing the voltage supply circuit to supply the third voltage to the second electrode; supply a low-level voltage to the third control signal, turning off the second transistor to disconnect the second power line from the second electrode; and supply a high-level voltage to the second control signal, turning on the first transistor to connect the second power line and the first electrode.

10. When the first voltage is input to the first logic circuit, the control circuit controls the following to be possible: supply a low-level voltage to the fourth control signal, turning on the first switch to connect the voltage supply circuit and the first electrode, and turning off the second switch to disconnect the voltage supply circuit from the second electrode; supply a high-level voltage to the first control signal, causing the voltage supply circuit to supply the third voltage to the first electrode; supply a high-level voltage to the third control signal, turning on the second transistor to connect the second power line to the second electrode; and supply a low-level voltage to the second control signal, turning off the first transistor to disconnect the second power line from the first electrode, as described in claim 8.

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