Drive detection circuit and drive device

Abstract

To provide a drive detection circuit and drive device with high detection accuracy. [Solution] The drive detection circuit of the embodiment comprises a first transistor having a first terminal, a second terminal, a first end connected to the first terminal, a second end connected to a first node, and a control end connected to the second terminal; a second transistor having a first end connected to the second terminal, a second end connected to a second node, and a control end connected to the first terminal; a first current mirror circuit having an input terminal connected to a first node and an output terminal connected to a second node; a current source having an input terminal connected to a second node; and a third transistor having a control end connected to a second node.

Description

Technical Field

[0001] Embodiments of the present invention relate to a drive detection circuit and a drive device.

Background Art

[0002] There is known a drive device that drives a transistor to control a motor or the like, and a drive detection circuit that detects the drive of the transistor in the drive device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a drive detection circuit and a drive device with high detection accuracy.

Means for Solving the Problems

[0005] The drive detection circuit of the embodiment includes a first terminal, a second terminal, a first transistor, a second transistor, a first current mirror circuit, a current source, and a third transistor. The first transistor has a first end connected to the first terminal, a second end connected to a first node, and a control end connected to the second terminal. The second transistor has a first end connected to the second terminal, a second end connected to a second node, and a control end connected to the first terminal. The first current mirror circuit has an input end connected to the first node and an output end connected to the second node. The current source has an input end connected to the second node. The third transistor has a control end connected to the second node.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing a first example of the configuration of a motor drive system including a drive device according to an embodiment. [Figure 2] A block diagram showing a second example of the configuration of a motor drive system including a drive device according to the embodiment. [Figure 3] A circuit diagram showing an example of the configuration of the drive detection circuit of the drive device according to the embodiment. [Modes for carrying out the invention]

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration will be denoted by the same reference numeral. When elements having similar configurations need to be specifically distinguished, different letters or numbers may be added to the end of the same reference numeral.

[0008] 1. Structure 1.1 Drive System Figure 1 is a block diagram showing a first example of the configuration of a motor drive system including a drive device according to an embodiment. Figure 2 is a block diagram showing a second example of the configuration of a motor drive system including a drive device according to an embodiment. The motor drive system 1 includes a drive device 2, a group of transistors (FETs), and a motor 3. The motor drive system 1 is an application that performs a predetermined operation using the torque obtained from the motor 3.

[0009] As shown in Figure 1, the transistor group FETs may be configured to be externally attached to the drive unit 2. As shown in Figure 2, the transistor group FETs may be configured to be built into the drive unit 2.

[0010] The drive unit 2 is, for example, an integrated circuit (IC) chip that functions as a motor control driver (MCD). The drive unit 2 drives a group of transistors (FETs) according to a control signal from, for example, an MCU (microcontroller unit) (not shown). By driving the group of transistors (FETs), the drive unit 2 can control the motor 3. Specifically, the drive unit 2 includes a gate driver GD, and terminals GHX, SHX, GLX, and SLX. The gate driver GD includes power supplies E1 and E2, and drivers D1 and D2.

[0011] Driver D1 has an output terminal connected to terminal GHX. The output voltage from driver D1 is, for example, a high voltage of 40V or more. Power supply E1 drives driver D1 by generating a potential difference of, for example, about 12V. The low-potential side of power supply E1 is connected to terminal SHX.

[0012] Driver D2 has an output terminal connected to terminal GLX. Power supply E2 drives driver D2 by generating a potential difference of, for example, about 12V. The lower potential side of power supply E2 is connected to terminal SLX.

[0013] The transistor group FETs includes transistors HST and LST, as well as a load L. The transistors HST and LST are, for example, field-effect transistors with an N-type conductivity.

[0014] The HST transistor has a first terminal to which voltage VM is supplied, a second terminal connected to terminal SHX, and a control terminal connected to terminal GHX. The HST transistor is configured to have a high voltage withstand capability that allows it to operate stably even with the high voltage supplied from terminal GHX. Hereafter, a transistor with a high voltage withstand capability that allows it to operate stably even with the high voltage supplied from terminal GHX will also be called a "high-voltage transistor" in contrast to a normal transistor that operates with a voltage of several volts.

[0015] Transistor LST has a first terminal connected to terminal SHX, a second terminal connected to terminal SLX, and a control terminal connected to terminal GLX. Load L has a first terminal connected to terminal SLX and a second terminal that is grounded. Thus, transistors HST and LST, and load L, are connected in this order in series between the voltage VM source and ground. Hereafter, transistors HST and LST will also be called “high-side transistors” and “low-side transistors,” respectively.

[0016] In the configuration described above, the gate driver GD controls the drive state (i.e., on and off states) of transistors HST and LST by applying appropriate voltages to the gates of each transistor. Motor 3 is connected to the node (i.e., terminal SHX) connecting transistors HST and LST. This allows the gate driver GD to drive motor 3 via the transistor group FETs.

[0017] The drive unit 2 further includes a drive detection circuit 10 and a terminal GHX_VGS. The drive detection circuit 10 is a circuit for detecting whether the transistor HST is in an ON state or an OFF state. The drive detection circuit 10 is connected to terminals GHX, SHX, and GHX_VGS. The drive detection circuit 10 detects whether the transistor HST is in an ON state or an OFF state based on the voltages of terminals GHX and SHX. The drive detection circuit 10 then outputs a signal indicating the detection result to terminal GHX_VGS.

[0018] In the examples of FIGS. 1 and 2, the motor drive system 1 is shown as having one set of gate driver GD, transistor group FETs, and drive detection circuit 10 for one motor 3, but it is not limited thereto. For example, the motor drive system 1 may have multiple sets (e.g., three sets) of gate driver GD, transistor group FETs, and drive detection circuit 10 for one motor 3. When the motor drive system 1 has three sets of gate driver GD, transistor group FETs, and drive detection circuit 10 for one motor 3, the motor 3 can function as a three-phase AC motor.

[0019] Note that when the motor drive system 1 has multiple sets of gate driver GD, transistor group FETs, and drive detection circuit 10 for one motor 3, the configuration of each of the multiple drive detection circuits 10 provided in the drive device 2 is equivalent. Hereinafter, the configuration of any one drive detection circuit 10 provided in the drive device 2 will be described.

[0020] 1.2 Drive Detection Circuit FIG. 3 is a circuit diagram showing an example of the configuration of the drive detection circuit of the drive device according to the embodiment.

[0021] The drive detection circuit 10 includes a plurality of resistors R, a plurality of transistors T, a current source I1, and a buffer HB. The plurality of resistors R includes resistors R1, R2, R3, R4, R5, R6, and R7. The plurality of transistors T includes transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11. Transistors T1, T2, T3, and T4 are high-voltage withstand transistors. In contrast, transistors T5, T6, T7, T8, T9, T10, and T11 are normal transistors.

[0022] Resistor R1 has a first end connected to terminal SHX and a second end connected to node N1. Resistor R2 has a first end connected to node N1. Resistor R3 has a first end connected to node N1 and a second end connected to node N3.

[0023] Transistor T1 is a DMOS (double-diffused metal oxide semiconductor) with N-type conductivity. Transistor T1 has a first terminal to which voltage VCP is supplied, a second terminal connected to node N3, and a control terminal connected to the second terminal of resistor R2. Transistor T1 functions as a source follower circuit for transistor T3.

[0024] Voltage VCP is a voltage higher than or equal to the voltage supplied from driver D1 to transistor HST (i.e., the voltage applied to terminal GHX). Voltage VCP is supplied, for example, from a charge pump circuit (not shown) in the drive unit 2.

[0025] Resistor R4 has a first end connected to terminal GHX and a second end connected to node N2. Resistor R5 has a first end connected to node N2. Resistor R6 has a first end connected to node N2 and a second end connected to node N4.

[0026] Transistor T2 is a DMOS having an N-type conductivity. Transistor T2 has a first terminal to which the voltage VCP is supplied, a second terminal connected to node N4, and a control terminal connected to the second terminal of resistor R5. Transistor T2 functions as a source follower circuit for transistor T4.

[0027] Transistors T3 and T4 are DMOS transistors with a P-type conductivity. Transistor T3 has a first terminal connected to node N3, a second terminal connected to node N5, and a control terminal connected to node N4. Transistor T4 has a first terminal connected to node N4, a second terminal connected to node N6, and a control terminal connected to node N3. Transistors T3 and T4 function as a fully differential circuit FD with node N3 as the first input terminal, node N4 as the second input terminal, node N5 as the first output terminal, and node N6 as the second output terminal.

[0028] Capacitor C1 is the parasitic capacitance that occurs between the substrate SUB and the source of transistor T3. Capacitor C2 is the parasitic capacitance that occurs between the source and drain of transistor T3.

[0029] Capacitor C3 is the parasitic capacitance that occurs between the substrate SUB and the source of transistor T4. Capacitor C4 is the parasitic capacitance that occurs between the source and drain of transistor T4.

[0030] Furthermore, parasitic capacitance between the substrate and source, as well as between the source and drain, can occur in transistors T5, T6, T7, T8, T9, T10, and T11, which will be discussed later. However, as mentioned above, transistors T3 and T4 are high-voltage transistors and are therefore larger in size than the ordinary transistors T5, T6, T7, T8, T9, T10, and T11. For this reason, from the perspective of high-precision detection of the driving state of the transistor HST, the parasitic capacitance of ordinary transistors is negligibly small, while the parasitic capacitance of capacitors C1, C2, C3, and C4 of the high-voltage transistors is not negligibly large. Therefore, capacitors C1, C2, C3, and C4 are intentionally shown in Figure 3.

[0031] Transistors T5 and T6 are CMOS (complementary metal oxide semiconductor) with N-type conductivity. Transistor T5 has a first terminal and a control terminal connected to node N5, and a second terminal grounded to voltage GND. Transistor T6 has a first terminal connected to node N6, a second terminal grounded to voltage GND, and a control terminal connected to node N5. Voltage GND is the ground voltage (e.g., 0V). Transistors T5 and T6 function as a current mirror circuit CM1 with node N5 as the input terminal and node N6 as the output terminal.

[0032] Transistors T7 and T8 are CMOS transistors with N-type conductivity. Transistor T7 has a first terminal and a control terminal connected to node N6, and a second terminal grounded to voltage GND. Transistor T8 has a first terminal connected to node N7, a second terminal grounded to voltage GND, and a control terminal connected to node N6. Transistors T7 and T8 function as a current mirror circuit CM2 with node N6 as the input terminal and node N6 as the output terminal. Thus, the output terminal of current mirror circuit CM1 and the input terminal of current mirror circuit CM2 are connected in parallel to node N6.

[0033] Transistors T9 and T10 are CMOS transistors with a P-type conductivity. Transistor T9 has a first terminal and a control terminal connected to node N7, and a second terminal to which the voltage VDD is supplied. Transistor T10 has a first terminal connected to node N8, a second terminal to which the voltage VDD is supplied, and a control terminal connected to node N7. The voltage VDD is the power supply voltage (e.g., several volts). Transistors T9 and T10 function as a current mirror circuit CM3 with node N7 as the input terminal and node N8 as the output terminal.

[0034] The current source I1 has an input terminal connected to node N8 and an output terminal grounded to voltage GND. The current flowing through the current source I1 is associated with the current flowing through transistor T7 via current mirror circuits CM2 and CM3. Thus, although the current source I1 is not electrically connected to node N6, it can be considered to be connected via a current buffer circuit formed by the current mirror circuits CM2 and CM3.

[0035] Resistor R7 has a first end to which the voltage VDD is supplied and a second end connected to node N9.

[0036] Transistor T11 is a CMOS having an N-type conductivity. Transistor T11 has a first terminal connected to node N9, a second terminal grounded to voltage GND, and a control terminal connected to node N8. When transistor T11 is ON, the voltage at node N9 decreases towards voltage GND. When transistor T11 is OFF, the voltage at node N9 increases towards voltage VDD.

[0037] Buffer HB is a hysteresis buffer driven by the voltage VDD. Buffer HB has an input terminal connected to node N9 and an output terminal connected to terminal GHX_VGS. Buffer HB determines the drive state of transistor T11 based on the voltage at node N9. Buffer HB outputs the result of the determination of the drive state of transistor T11 to terminal GHX_VGS. Specifically, for example, if the voltage at node N9 is above a threshold, buffer HB outputs a "High" level indicating that transistor T11 is in the off state. If the voltage at node N9 is below the threshold, buffer HB outputs a "Low" level indicating that transistor T11 is in the on state. The threshold is set between the voltages GND and VDD.

[0038] With the above configuration, in the drive detection circuit 10, the potential difference between terminals GHX and SHX (i.e., the potential difference between the gate and source of transistor HST) is converted into current by transistor T4. Then, the drive state of transistor T11 is switched by comparing the current flowing through transistor T4 with the current flowing through current source I1. Therefore, by adjusting the conditions for switching the drive state of transistor T11 to match the conditions for switching the drive state of transistor HST, the drive detection circuit 10 can output a signal indicating the drive state of transistor T11 as a signal indicating the drive state of transistor HST to terminal GHX_VGS.

[0039] Specifically, when the potential difference between terminals GHX and SHX is large, the current flowing through transistor T4 increases. This causes the voltage at node N8 to rise, and transistor T11 turns on. When transistor T11 turns on, the voltage input to buffer HB decreases. Therefore, buffer HB can output a "Low" level signal to terminal GHX_VGS indicating that transistor T11 (and HST) are on.

[0040] On the other hand, when the potential difference between terminals GHX and SHX is small, the current flowing through transistor T4 decreases. As a result, the voltage at node N8 drops, and transistor T11 turns off. When transistor T11 is off, the voltage input to buffer HB increases. Therefore, buffer HB can output a "High" level signal to terminal GHX_VGS indicating that transistor T11 (and HST) is off.

[0041] 2. Effects according to the embodiment According to the embodiment, transistor T3 has a first terminal connected to terminal SHX, a second terminal connected to node N5, and a control terminal connected to terminal GHX. Transistor T4 has a first terminal connected to terminal GHX, a second terminal connected to node N6, and a control terminal connected to terminal SHX. Current mirror circuit CM1 has an input terminal connected to node N5 and an output terminal connected to node N6. As a result, current mirror circuit CM1 can suppress the influence of parasitic current caused by capacitor C4, which is the parasitic capacitance of transistor T4, on the driving state of transistor T11, for example, when motor 3 is regenerating.

[0042] To elaborate, during regeneration of motor 3, the voltage applied to the gate and source of transistor HST increases simultaneously, even though there is no potential difference between the gate and source of transistor HST (i.e., transistor HST remains in the off state). In this case, a parasitic current caused by capacitor C4 may be generated within the drive detection circuit 10. If this parasitic current is included in the comparison with the current flowing through current source I1, the voltage applied to the gate of transistor T11 may increase, potentially causing transistor T11 to turn on even though transistor HST is in the off state. Thus, including a parasitic current caused by capacitor C4 in the comparison with the current flowing through current source I1 is undesirable because it may lead to false detection of the transistor HST being in the on state.

[0043] According to this embodiment, transistors T3 and T4 constitute a full differential circuit FD. The two output terminals of the full differential circuit are connected to the input and output terminals of the current mirror circuit CM1, respectively. As a result, during motor 3 regeneration, the parasitic current caused by capacitor C2 and the parasitic current caused by capacitor C4 can be passed to the input and output terminals of the current mirror circuit CM1, respectively. Therefore, the parasitic current caused by capacitor C4 can be canceled out from the current compared with the current source I1. Consequently, false detection of the ON state of transistor HST during motor 3 regeneration can be suppressed.

[0044] Furthermore, transistor T1 has a first terminal to which voltage VCP is supplied, a second terminal connected to terminal SHX, and a control terminal. Transistor T2 has a first terminal to which voltage VCP is supplied, a second terminal connected to terminal GHX, and a control terminal. In other words, transistors T1 and T2 function as source follower circuits for transistors T3 and T4, respectively. As a result, when capacitors C1 and C2 are charged in response to voltage fluctuations at terminal SHX during the transition from the off state to the on state of transistor HST, the current required for such charging can be supplied from the voltage VCP source. Similarly, when capacitors C3 and C4 are charged in response to voltage fluctuations at terminal GHX during the transition from the off state to the on state of transistor HST, the current required for such charging can be supplied from the voltage VCP source. Therefore, the amount of current flowing to the drive detection circuit 10 via terminals SHX and GHX can be reduced. Consequently, the load that the drive detection circuit 10 places on the driver D1 during the drive control of transistor HST can be reduced.

[0045] Furthermore, the current mirror circuits CM2 and CM3 function as current buffer circuits provided between nodes N6 and N8. This electrically isolates the current source I1 from the capacitor C4, which is the parasitic capacitance of transistor T4. As a result, the effect of the voltage change applied to the gate of transistor T11 being delayed by capacitor C4 can be reduced. Consequently, the time it takes for the drive detection circuit 10 to detect a transition in the drive state of transistor T11 (for example, a transition from the ON state to the OFF state) can be shortened.

[0046] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0047] 1…Motor drive system 2…Drive unit 3…motor 10…Drive detection circuit GD...Gate Driver E1,E2…Power supply D1, D2... Driver FETs…a group of transistors GHX,SHX,GLX,SLX,GHX_VGS…terminal HST, LST, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11… Transistors R1,R2,R3,R4,R5,R6,R7...Resistance C1, C2, C3, C4... Capacitors I1…Current source HB...buffer

Claims

1. First terminal and The second terminal and, A first transistor having a first terminal connected to the first terminal, a second terminal connected to the first node, and a control terminal connected to the second terminal, A second transistor having a first terminal connected to the second terminal, a second terminal connected to the second node, and a control terminal connected to the first terminal, A first current mirror circuit having an input terminal connected to the first node and an output terminal connected to the second node, A current source having an input terminal connected to the second node, A third transistor having a control terminal connected to the second node, A drive detection circuit equipped with the following features.

2. A fourth transistor having a first terminal connected to a power supply, a second terminal connected to the first terminal, and a control terminal, A fifth transistor having a first terminal connected to the power supply, a second terminal connected to the second terminal, and a control terminal, Furthermore, The power supply is configured to supply a voltage greater than or equal to the voltage applied to the second terminal. The drive detection circuit according to claim 1.

3. The first transistor and the second transistor have a first conductivity type, The third transistor, the fourth transistor, the fifth transistor, and the first current mirror circuit have a second conductivity type. The drive detection circuit according to claim 2.

4. The system further includes a current buffer circuit provided between the second node, the current source, and the third transistor. The drive detection circuit according to claim 1.

5. The current buffer circuit is A second current mirror circuit having an input terminal connected to the second node and an output terminal connected to the third node, A third current mirror circuit having an input terminal connected to the third node and an output terminal connected to the input terminal of the current source and the control terminal of the third transistor, including, The drive detection circuit according to claim 4.

6. The first transistor, the second transistor, and the third current mirror circuit each have a first conductivity type. The third transistor, the first current mirror circuit, and the second current mirror circuit each have a second conductivity type. The drive detection circuit according to claim 5.

7. The first current mirror circuit is, A sixth transistor having a first terminal and a control terminal connected to the first node, A seventh transistor having a first terminal connected to the second node and a control terminal connected to the first node, Includes, The second current mirror circuit is, An eighth transistor having a first terminal and a control terminal connected to the second node, A ninth transistor having a first end connected to the third node and a control end connected to the second node, Includes, The third current mirror circuit is, A tenth transistor having a first terminal and a control terminal connected to the third node, An eleventh transistor having a first terminal connected to the input terminal of the current source and the control terminal of the third transistor, and a control terminal connected to the third node, including, The drive detection circuit according to claim 6.

8. The first and second transistors are DMOS (double-diffused metal oxide semiconductors). The drive detection circuit according to claim 1.

9. A drive detection circuit according to any one of claims 1 to 8, A driver that outputs a first voltage to the second terminal, A drive system equipped with this.

10. The first voltage is 40V or higher. The drive device according to claim 9.

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