Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor substrate 1 has a p-type substrate region SB, an n-type embedded layer BL on the p-type substrate region SB, and a p-type semiconductor layer EP on the n-type embedded layer BL. A DTI region 5 is formed in a groove 4 that penetrates the p-type semiconductor layer EP and the n-type embedded layer BL and reaches the p-type substrate region SB. Multiple scallops 6 are formed on the side surface of the groove 4. The size L1d of each of the multiple scallops 6d formed on the side surface of the groove 4 in the p-type semiconductor layer EP is larger than the size L1e of each of the multiple scallops 6e formed on the side surface of the groove 4 in the n-type embedded layer BL.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device including a DTI region and a method for manufacturing the same.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2011-66067 (Patent Document 1) describes a semiconductor device having a DTI structure.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Even in a semiconductor device including a DTI region, it is desirable to improve the performance of the semiconductor device.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate and an element isolation region. The semiconductor substrate includes a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer. The element isolation region is formed in a groove that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region. The size of each of a plurality of first scallops formed on a side surface of the groove in the second semiconductor layer is larger than the size of each of a plurality of second scallops formed on a side surface of the groove in the first semiconductor layer.

Effects of the Invention

[0007] According to one embodiment, the performance of a semiconductor device can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view of the main part of the semiconductor device according to the embodiment. [Figure 2] This is a cross-sectional view of a key part during the manufacturing process of a semiconductor device according to the embodiment. [Figure 3] Figure 2 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 4] Figure 3 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 5] Figure 4 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 6] Figure 5 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 7] Figure 6 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 8] Figure 7 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 9] Figure 8 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 10] Figure 9 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 11] Figure 10 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 12] Figure 11 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 13] This is a process flow diagram showing a part of the manufacturing process of the semiconductor device according to the embodiment. [Figure 14] This is an explanatory diagram of the groove formation process. [Figure 15] This is an explanatory diagram of the groove formation process. [Figure 16] This is an explanatory diagram of the groove formation process. [Figure 17] This is an explanatory diagram of the groove formation process. [Figure 18] It is an explanatory diagram of the groove formation process. [Figure 19] It is an explanatory diagram of the groove formation process. [Figure 20] It is an explanatory diagram of the groove formation process. [Figure 21] It is an explanatory diagram of the groove formation process. [Figure 22] It is an explanatory diagram of the groove formation process. [Figure 23] It is an explanatory diagram of the groove formation process. [Figure 24] It is a partial enlarged cross-sectional view obtained by enlarging a part of FIG. 7. [Figure 25] It is a partial enlarged cross-sectional view obtained by enlarging a part of FIG. 1. [Figure 26] It is a cross-sectional view of a main part during the manufacturing process of the semiconductor device of the study example. [Figure 27] It is a cross-sectional view of a main part during the manufacturing process of the semiconductor device of the study example. [Figure 28] It is a cross-sectional view of a main part during the manufacturing process of the semiconductor device of the study example following FIG. 27. [Figure 29] It is a partial enlarged cross-sectional view obtained by enlarging a part of FIG. 8. [Figure 30] It is a partial enlarged cross-sectional view obtained by enlarging a part of FIG. 1. [Figure 31] It is a graph showing the correlation between the scallop size and the leakage current. [Figure 32] It is a graph showing the correlation between the scallop size and the sidewall resistance of the DTI region. [Figure 33] It is a plan view showing a test pattern for measuring the sidewall resistance of the DTI region.

Embodiments for Carrying Out the Invention

[0009] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0010] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, components having the same function will be denoted by the same reference numeral, and repeated descriptions will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless particularly necessary.

[0011] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0012] Furthermore, a planar view corresponds to viewing the semiconductor substrate 1 from a plane that is approximately parallel to the main surface or back surface. Also, the bottom surface and the lower surface have the same meaning.

[0013] (Embodiment) <About the structure of semiconductor devices> A semiconductor device of an embodiment will be described with reference to Figure 1.

[0014] As shown in Figure 1, the semiconductor device of the embodiment includes a semiconductor substrate 1, a Zener diode 2, an STI region 3, a DTI region 5, an insulating film IL, a plurality of plugs (contact plugs) PG, and a plurality of wirings M1.

[0015] As shown in Figure 1, the semiconductor substrate 1 has a p-type substrate region SB, an n-type embedded layer BL formed on the p-type substrate region SB, and a p-type semiconductor layer EP formed on the n-type embedded layer BL.

[0016] The p-type substrate region SB is made of p-type single-crystal silicon, for example, into which p-type impurities such as boron (B) have been introduced. The thickness of the p-type substrate region SB is almost uniform. The n-type embedded layer BL is an n-type semiconductor layer. The n-type embedded layer BL is made of n-type single-crystal silicon, for example, formed on the p-type substrate region SB. The thickness of the n-type embedded layer BL is almost uniform. The p-type semiconductor layer EP is made of p-type single-crystal silicon, for example, formed on the n-type embedded layer BL. The n-type embedded layer BL and the p-type substrate region SB are in contact with each other. The p-type semiconductor layer EP and the n-type embedded layer BL are in contact with each other.

[0017] The p-type substrate region SB may have a stacked structure consisting of a p-type substrate body made of a p-type single-crystal silicon substrate or the like, and a p-type semiconductor layer formed on the p-type substrate body. In that case, the p-type impurity concentration of the p-type semiconductor layer on the p-type substrate body is lower than the p-type impurity concentration of the p-type substrate body, and the p-type impurity concentration of the p-type semiconductor layer EP on the n-type embedded layer BL is lower than the p-type impurity concentration of the p-type substrate body.

[0018] The main surface of semiconductor substrate 1 is synonymous with the main surface of the p-type semiconductor layer EP. Similarly, the back surface of semiconductor substrate 1 is synonymous with the back surface of the p-type substrate region SB. The main surface and the back surface of semiconductor substrate 1 are located on opposite sides of each other.

[0019] The STI (Shallow Trench Isolation) region 3 consists of an insulating film embedded in a groove formed within the semiconductor substrate 1. The DTI (Deep Trench Isolation) region 5 consists of an insulating film embedded in the insulating film IL on the semiconductor substrate 1 and in a groove 4 formed within the semiconductor substrate 1. The bottom surface of the DTI region 5 is in contact with the bottom surface of the groove 4, and the side surface of the DTI region 5 is in contact with the side surface of the groove 4. Therefore, the depth of the bottom surface of the DTI region 5 is the same as the depth of the bottom surface of the groove 4. Both the STI region 3 and the DTI region 5 can be considered insulating regions.

[0020] The bottom surface of STI region 3 is shallower than the bottom surface of the p-type semiconductor layer EP. The bottom surface of DTI region 5 is deeper than the bottom surface of STI region 3. Groove 4 and DTI region 5 within groove 4 penetrate the insulating film IL, STI region 3, p-type semiconductor layer EP, and n-type embedding layer BL to reach the p-type substrate region SB. The bottom surface of groove 4 is deeper than the bottom surface of the n-type embedding layer BL, and therefore the bottom surface of DTI region 5 is deeper than the bottom surface of the n-type embedding layer BL. Groove 4 and DTI region 5 within groove 4 do not penetrate the p-type substrate region SB. A portion of the p-type substrate region SB exists below the bottom surface of groove 4. DTI region 5 functions as an element isolation region.

[0021] In Figure 1, the groove 4 and the DTI region 5 penetrate the insulating film IL, with a portion of the DTI region 5 located within the insulating film IL and the other portion located within the semiconductor substrate 1. The groove 4 may be formed within the semiconductor substrate 1 without penetrating the insulating film IL. In that case, the DTI region 5 is embedded within the groove 4 in the semiconductor substrate 1, and the height of the upper surface of the DTI region 5 is approximately the same as the height of the main surface of the semiconductor substrate 1.

[0022] The Zener diode 2 has a p-type well region PW, a p-type semiconductor region AD, an n-type semiconductor region CD, and a p-type semiconductor region PR. In a plan view, the Zener diode 2 is surrounded by a DTI region 5.

[0023] The p-type well region PW, the p-type semiconductor region AD, the n-type semiconductor region CD, and the p-type semiconductor region PR are formed within the p-type semiconductor layer EP. Specifically, the p-type well region PW is formed in the upper part of the p-type semiconductor layer EP, and the p-type semiconductor region AD, the n-type semiconductor region CD, and the p-type semiconductor region PR are formed within the p-type well region PW.

[0024] The n-type semiconductor region CD is in contact with the main surface of the semiconductor substrate 1 and is formed to a predetermined depth from the main surface of the semiconductor substrate 1. The n-type semiconductor region CD functions as the n-type cathode region of the Zener diode 2.

[0025] The p-type semiconductor region AD is formed beneath the n-type semiconductor region CD. The bottom surface of the p-type semiconductor region AD is shallower than the bottom surface of the p-type well region PW. A portion of the p-type well region PW exists beneath the bottom surface of the p-type semiconductor region AD. The p-type impurity concentration in the p-type semiconductor region AD is higher than that of the p-type well region PW. A portion of the p-type semiconductor layer EP (p-type semiconductor region) exists beneath the bottom surface of the p-type well region PW. The p-type impurity concentration in the p-type well region PW is higher than that of the p-type semiconductor layer EP beneath the p-type well region PW.

[0026] In the direction from the main surface to the back surface of the semiconductor substrate 1, the n-type semiconductor region CD and the p-type semiconductor region AD are in contact with each other, and a PN junction is formed between the n-type semiconductor region CD and the p-type semiconductor region AD.

[0027] The planar dimensions (area) of the p-type semiconductor region AD are smaller than the planar dimensions (area) of the n-type semiconductor region CD. The center of the bottom surface of the n-type semiconductor region CD is in contact with the p-type semiconductor region AD, and the outer periphery of the bottom surface of the n-type semiconductor region CD is in contact with the p-type well region PW. Therefore, a PN junction is also formed between the n-type semiconductor region CD and the p-type well region PW. The sides and bottom surface of the p-type semiconductor region AD are covered by the p-type well region PW.

[0028] A p-type semiconductor region having a p-type semiconductor region AD and a p-type well region PW functions as the p-type anode region of the Zener diode 2. The PN junction surface formed at the interface between the n-type cathode region and the p-type anode region is composed of a PN junction surface between the n-type semiconductor region CD and the p-type semiconductor region AD, and a PN junction surface between the n-type semiconductor region CD and the p-type well region PW. In a plan view, the PN junction surface between the n-type semiconductor region CD and the p-type semiconductor region AD is surrounded by the PN junction surface between the n-type semiconductor region CD and the p-type well region PW.

[0029] Since the p-type impurity concentration in the p-type semiconductor region AD is higher than that in the p-type well region PW, the breakdown of Zener diode 2 occurs at the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD. Therefore, the breakdown voltage of Zener diode 2 is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD.

[0030] The p-type semiconductor region PR is in contact with the main surface of the semiconductor substrate 1 and is formed to a predetermined depth from the main surface of the semiconductor substrate 1. The depth of the bottom surface of the p-type semiconductor region PR is shallower than the depth of the bottom surface of the p-type well region PW. A portion of the p-type well region PW is located below the bottom surface of the p-type semiconductor region PR. The p-type impurity concentration in the p-type semiconductor region PR is higher than the p-type impurity concentration in the p-type well region PW.

[0031] In a plan view, the p-type semiconductor region PR does not overlap with the n-type semiconductor region CD. For example, in a plan view, the p-type semiconductor region PR surrounds the n-type semiconductor region CD. In a plan view, the STI region 3 is located between the n-type semiconductor region CD and the p-type semiconductor region PR.

[0032] A back electrode (not shown) may be formed on the back surface of the semiconductor substrate 1. For example, a ground potential can be supplied from the back electrode to the substrate body SB.

[0033] Next, we will describe the structure on the semiconductor substrate 1.

[0034] An insulating film IL is formed on the main surface of the semiconductor substrate 1. The insulating film IL 1 consists of, for example, a laminated film of a silicon nitride film and a silicon oxide film. Multiple contact holes are formed within the insulating film IL, and multiple conductive plugs PG are formed within the multiple contact holes. The multiple plugs PG include plugs PGA and plugs PGC. Plugs PGA are placed on a p-type semiconductor region PR and are electrically connected to the p-type semiconductor region PR. Plugs PGC are placed on an n-type semiconductor region CD and are electrically connected to the n-type semiconductor region CD.

[0035] A metal silicide layer (not shown) can also be formed on the n-type semiconductor region CD and the p-type semiconductor region PR. In this case, plug PGC is electrically connected to the n-type semiconductor region CD via the metal silicide layer on the n-type semiconductor region CD. Plug PGA is electrically connected to the p-type semiconductor region PR via the metal silicide layer on the p-type semiconductor region PR.

[0036] Multiple wirings M1 are formed on the insulating film IL. The multiple wirings M1 include an anode wiring M1A and a cathode wiring M1C. The cathode wiring M1C is electrically connected to the n-type semiconductor region CD via a plug PGC. The cathode potential is supplied from the cathode wiring M1C to the n-type cathode region of the Zener diode 2 via the plug PGC. The anode wiring M1A is electrically connected to the p-type semiconductor region PR via a plug PGA, and further electrically connected to the p-type well region PW via the p-type semiconductor region PR. The anode potential is supplied from the anode wiring M1A to the p-type anode region of the Zener diode 2 via the plug PGA. The cathode wiring M1C and the anode wiring M1A are not connected to each other and are isolated from each other.

[0037] Illustrations and descriptions of structures formed above the insulating film IL and the multiple wirings M1 are omitted.

[0038] The n-type cathode region and p-type cathode region of the Zener diode 2 are formed within the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the n-type embedded layer BL. Therefore, the Zener diode 2 formed in the semiconductor substrate 1 can be electrically isolated from other semiconductor elements formed on the semiconductor substrate 1.

[0039] As a Zener diode 2 is formed within the p-type semiconductor layer substrate EP, which is surrounded by the DTI region 5 and the n-type embedded layer BL, an NPN parasitic transistor and a PNP parasitic transistor can be formed within the semiconductor substrate SB. The NPN parasitic transistor has an n-type emitter region consisting of an n-type semiconductor region CD, a p-type base region consisting of a p-type semiconductor region AD, a p-type semiconductor region PR, and a p-type well region PW, and an n-type collector region consisting of the n-type embedded layer BL. The PNP parasitic transistor has a p-type emitter region consisting of a p-type substrate region SB, an n-type base region consisting of the n-type embedded layer BL, and a p-type collector region consisting of a p-type semiconductor region AD, a p-type semiconductor region PR, and a p-type well region PW. A parasitic thyristor can be formed by the NPN parasitic transistor and the PNP parasitic transistor.

[0040] The case described above involves the formation of a Zener diode 2 as a semiconductor element within the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the n-type embedded layer BL. It is also possible to form semiconductor elements other than the Zener diode 2 within the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the n-type embedded layer BL.

[0041] <Regarding the manufacturing process of semiconductor devices> As shown in Figure 2, a semiconductor substrate 1 is prepared having a p-type substrate region SB, an n-type embedded layer BL on the p-type substrate region SB, and a p-type semiconductor layer EP on the n-type embedded layer BL. The thickness of the p-type semiconductor layer EP is, for example, 3 micrometers or more and 6 micrometers or less. The thickness of the n-type embedded layer BL is, for example, 4 micrometers or more and 7 micrometers or less.

[0042] For example, an n-type embedded layer BL can be formed in the surface layer of a p-type silicon substrate by ion implantation, and then a p-type semiconductor layer EP can be formed on the n-type embedded layer BL using epitaxial growth. In this case, the p-type silicon substrate below the n-type embedded layer BL corresponds to the p-type substrate region SB. An epitaxial wafer can also be used instead of the above-mentioned p-type silicon substrate. The epitaxial wafer has a p-type silicon substrate body and a p-type semiconductor layer formed on the p-type silicon substrate body.

[0043] Next, as shown in Figure 3, the STI region 3 is formed using the STI method.

[0044] After forming grooves on the main surface of the semiconductor substrate 1, an insulating film, such as a silicon oxide film, is formed on the main surface of the semiconductor substrate 1 to fill the grooves. Subsequently, the insulating film located outside the grooves is removed using a method such as CMP (Chemical Mechanical Polishing). This makes it possible to form an STI region 3 consisting of the insulating film embedded in the grooves.

[0045] Next, as shown in Figure 4, a p-type well region PW, a p-type semiconductor region AD, an n-type semiconductor region CD, and a p-type semiconductor region PR are formed within the p-type semiconductor layer EP using methods such as ion implantation. The formation order of the p-type well region PW, p-type semiconductor region AD, n-type semiconductor region CD, and p-type semiconductor region PR can be selected as needed.

[0046] Next, as shown in Figure 5, an insulating film IL is formed on the main surface of the semiconductor substrate 1 using a method such as CVD (Chemical Vapor Deposition). After the formation of the insulating film IL, the upper surface of the insulating film IL can also be planarized by polishing using a method such as CMP.

[0047] Next, as shown in Figure 5, a photoresist pattern RP1 is formed on the insulating film IL using photolithography technology.

[0048] Next, as shown in Figure 6, grooves 4 are formed by etching the insulating film IL and the STI region 3 using the photoresist pattern RP1 as an etching mask. This etching process is referred to as the etching process in Figure 6.

[0049] In the etching process shown in Figure 6, the groove 4 is formed to penetrate the insulating film IL and the STI region 3, and the semiconductor substrate 1 (p-type semiconductor layer EP) functions as an etching stopper. Therefore, the etching process in Figure 6 includes a step of etching the insulating film IL and a step of etching the STI region 3. The step of etching the STI region 3 is performed under conditions where the etching rate of the semiconductor substrate 1 (p-type semiconductor layer EP) is lower than the etching rate of the STI region 3. Therefore, in the etching process in Figure 6, the semiconductor substrate 1 (p-type semiconductor layer EP) is hardly etched. At the end of the etching process in Figure 6, the side surface of the groove 4 is composed of the insulating film IL and the STI region 3, the bottom surface of the groove 4 is composed of the semiconductor substrate 1 (p-type semiconductor layer EP), and the depth of the bottom surface of the groove 4 is approximately the same as the depth of the surface of the semiconductor substrate 1 (p-type semiconductor layer EP) below the STI region 3. The side surface of the groove 4 is aligned with the side surface of the opening OP1 of the photoresist pattern RP1.

[0050] Next, as shown in Figure 7, the depth of the groove 4 is increased by etching the semiconductor substrate 1 (p-type semiconductor layer EP, n-type embedded layer BL, and p-type substrate region SB) exposed from the groove 4 using the photoresist pattern RP1 as an etching mask. This etching process is referred to as the etching process shown in Figure 7.

[0051] By performing the etching process shown in Figure 7, groove 4 penetrates the p-type semiconductor layer EP and the n-type embedding layer BL to reach the p-type substrate region SB. At the end of the etching process shown in Figure 7, groove 4 penetrates the insulating film IL, the STI region 3, the p-type semiconductor layer EP, and the n-type embedding layer BL to reach the p-type substrate region SB, and the bottom surface of groove 4 is deeper than the bottom surface of the n-type embedding layer BL. However, groove 4 does not penetrate the p-type substrate region SB. The bottom surface of groove 4 is located in the middle of the thickness of the p-type substrate region SB. The depth from the bottom surface of the n-type embedding layer BL to the bottom surface of groove 4 is, for example, approximately 6 micrometers or more and 9 micrometers or less.

[0052] The etching process shown in Figure 7 will be explained in more detail later.

[0053] Next, as shown in Figure 8, ion implantation of p-type impurities is performed on the semiconductor substrate 1 exposed from the groove 4. This ion implantation is schematically shown as ion implantation IM in Figure 8.

[0054] As an ion implantation method (IM), oblique ion implantation of p-type impurities is performed. In the case of oblique ion implantation, the incident direction of the impurity ions is inclined with respect to the normal direction of the main surface of the semiconductor substrate. Figure 9 shows the region PL in the semiconductor substrate 1 where p-type impurities have been implanted by ion implantation IM. By ion implantation IM, p-type impurities are implanted into the semiconductor substrate 1 from the bottom and sides of the groove 4. Therefore, the region PL is formed in the semiconductor substrate 1 along the bottom and sides of the groove 4.

[0055] Next, the photoresist pattern RP1 is removed as shown in Figure 9. Note that the region PL is not shown in Figures 9 through 12.

[0056] Next, as shown in Figure 10, a DTI region 5 is formed within the groove 4.

[0057] After forming the groove 4, an insulating film made of silicon oxide or the like is formed on the insulating film IL to fill the groove 4. Then, the insulating film located outside the groove 4 is removed using a method such as CMP. This makes it possible to form a DTI region 5 consisting of the insulating film embedded in the groove 4. A void may be formed within the DTI region 5. The step of removing the insulating film located outside the groove 4 using a method such as CMP has been described, but this step is not required. In that case, the insulating film formed integrally with the DTI region 5 remains on the insulating film IL.

[0058] Next, as shown in Figure 11, the insulating film IL is etched using a photoresist pattern (not shown) formed on the insulating film IL as an etching mask to form multiple contact holes penetrating the insulating film IL. Subsequently, multiple conductive plugs PG are formed within each of the multiple contact holes.

[0059] For example, a barrier conductor film is formed on the bottom surface of the contact hole, the side surface of the contact hole, and the top surface of the insulating film IL. Next, a lead body film made of tungsten or the like is formed on the barrier conductor film to fill the inside of the contact hole. After that, the lead body film and barrier conductor film located outside the contact hole are removed by methods such as CMP. This allows for the formation of multiple plugs PG.

[0060] Next, as shown in Figure 12, multiple wirings M1 are formed on the insulating film IL. For example, a conductive film is formed on the insulating film IL. Then, by patterning the conductive film using photolithography and etching techniques, multiple wirings M1 made of the conductive film can be formed. Aluminum wiring is preferred for the multiple wirings M1, but wiring made of other metal materials, such as tungsten wiring, can also be used. In addition, copper wiring formed using damascene techniques can also be used as the multiple wirings M1.

[0061] Multiple wires M1 have an anode wire M1A and a cathode wire M1C.

[0062] The illustration and explanation of the process of forming insulating film and wiring on multiple wirings M1 are omitted.

[0063] <Regarding the groove formation process> Let's further explain the groove formation process. Figure 13 shows the specific flow of the etching process in Figure 7.

[0064] Figure 14 is a cross-sectional view showing the state after the etching process in Figure 6 has been completed and before the etching process in Figure 7 is performed. In Figure 14, a laminated structure consisting of an STI region 3, an insulating film IL on the STI region 3, and a photoresist pattern RP1 on the insulating film IL is schematically shown as a mask layer MK. The opening OP2 of the mask layer MK shown in Figure 14 consists of the opening OP1 of the photoresist pattern RP1 shown in Figure 6 and a groove 4. The side surface of the opening OP2 of the mask layer MK shown in Figure 14 is composed of the side surface of the groove 4 shown in Figure 6 and the side surface of the opening OP1 of the photoresist pattern RP1. The opening OP2 of the mask layer MK penetrates the mask layer MK. The semiconductor substrate 1 exposed from the opening OP2 of the mask layer MK corresponds to the semiconductor substrate 1 exposed from the groove 4.

[0065] After the etching process shown in Figure 6, as shown in Figure 15, the semiconductor substrate 1 exposed through the opening OP2 of the mask layer MK (and therefore the semiconductor substrate 1 exposed through the groove 4) is isotropically etched using the mask layer MK as an etching mask (step S1 in Figure 13).

[0066] In the isotropic etching step of step S1, it is preferable to use isotropic dry etching. Isotropic dry etching can be performed, for example, using fluorine radicals. In step S1, for example, SF6 gas can be suitably used as the etching gas. The isotropic etching step of step S1 is performed under conditions in which the etching rate of the semiconductor substrate 1 is greater than the etching rate of the mask layer MK.

[0067] In the isotropic etching process of step S1, etching occurs not only along the depth direction but also side etching. The depth direction is perpendicular to the main surface of the semiconductor substrate 1 and is in the direction from the main surface to the back surface of the semiconductor substrate 1. The isotropic etching process of step S1 generates a removal region 4a of the semiconductor substrate 1. The removal region 4a is, for example, a shell-shaped or bowl-shaped depression. The removal region 4a constitutes part of the groove 4. The bottom surface of the removal region 4a corresponds to the bottom surface of the groove 4. In a plan view, the planar dimensions (planar area) of the removal region 4a are larger than the planar dimensions of the opening OP2 of the mask layer MK.

[0068] Next, a protective film DP is formed as shown in Figure 16 (step S2 in Figure 13).

[0069] In the protective film formation step S2, the protective film DP is formed on the upper surface of the mask layer MK, on ​​the side surface of the opening OP2 of the mask layer MK, and on the surface of the semiconductor substrate 1 exposed from the groove 4. Therefore, the protective film DP is formed on the side surface and bottom surface of the groove 4. In the protective film formation step S2, the protective film DP can be formed using, for example, fluorocarbon-based radicals. For example, the protective film DP can be formed (deposited) using C4F8 gas.

[0070] Next, as shown in Figure 17, the protective film DP is anisotropically etched using the mask layer MK as an etching mask (step S3 in Figure 13).

[0071] In the anisotropic etching step S3, anisotropic dry etching is used. Anisotropic dry etching can be performed using, for example, fluorine-based ions. In the anisotropic etching step S3, SF6 gas can be suitably used as the etching gas.

[0072] In the anisotropic etching process of step S3, the portion of the protective film DP on the bottom surface of the groove 4 that overlaps with the opening OP2 of the mask layer MK in a plan view is removed, thereby forming an opening OP3 in the protective film DP. The semiconductor substrate 1 is exposed through the opening OP3 in the protective film DP. The opening OP3 of the protective film DP is formed on the bottom surface of the groove 4. In a plan view, the planar dimensions (planar area) of the removal region of the protective film DP are approximately the same as, or slightly smaller than, the planar dimensions of the opening OP2 of the mask layer MK. Therefore, in a plan view, the planar dimensions of the opening OP3 of the protective film DP are smaller than the planar dimensions of the removal region 4a.

[0073] Next, as shown in Figure 18, the semiconductor substrate 1 exposed through the opening OP3 of the protective film DP is isotropically etched using the mask layer MK and the protective film DP as etching masks (step S4 in Figure 13).

[0074] In the isotropic etching step S4, it is preferable to use isotropic dry etching. Isotropic dry etching can be performed, for example, using fluorine radicals. In the isotropic etching step S4, for example, SF6 gas can be suitably used as the etching gas. The isotropic etching step S4 is performed under conditions where the etching rate of the semiconductor substrate 1 is greater than the etching rate of the protective film DP.

[0075] In the isotropic etching process of step S4, the semiconductor substrate 1 exposed through the opening OP3 of the protective film DP is isotropically etched, so the semiconductor substrate 1 undergoes not only etching along the depth direction but also side etching. The isotropic etching process of step S4 generates a removal region 4b of the semiconductor substrate 1. The removal region 4b is located below the removal region 4a. The removal region 4b is, for example, a shell-shaped or bowl-shaped depression. The removal region 4b constitutes part of the groove 4. The bottom surface of the removal region 4b corresponds to the bottom surface of the groove 4. In a plan view, the planar dimensions of the removal region 4b are larger than the planar dimensions of the opening OP3 of the protective film DP and larger than the planar dimensions of the opening OP2 of the mask layer MK.

[0076] Next, the protective film DP is removed as shown in Figure 19 (step S5 in Figure 13).

[0077] Subsequently, the protective film formation process in step S2, the anisotropic etching process in step S3, the isotropic etching process in step S4, and the protective film removal process in step S5 are repeated multiple times, each time forming one cycle.

[0078] Specifically, a protective film DP is formed as shown in Figure 20 (step S2 in Figure 13). The protective film DP is formed on the side and bottom surfaces of the groove 4.

[0079] Next, as shown in Figure 21, the protective film DP is anisotropically etched using the mask layer MK as an etching mask (step S3 in Figure 13). The anisotropic etching process in step S3 forms an opening OP3 in the protective film DP, and the semiconductor substrate 1 is exposed through the opening OP3 in the protective film DP. The opening OP3 in the protective film DP is formed on the bottom surface of the groove 4.

[0080] Next, as shown in Figure 22, the semiconductor substrate 1 exposed through the opening OP3 of the protective film DP is isotropically etched using the mask layer MK and the protective film DP as an etching mask (step S4 in Figure 13). The isotropic etching process in step S4 generates a removal region 4c of the semiconductor substrate 1. The removal region 4c is located below the removal region 4b. The removal region 4c is, for example, a shell-shaped or bowl-shaped depression. The removal region 4c constitutes part of the groove 4, and the bottom surface of the removal region 4c corresponds to the bottom surface of the groove 4.

[0081] Next, the protective film DP is removed as shown in Figure 23 (step S5 in Figure 13).

[0082] Each time steps S2, S3, S4, and S5 are repeated, the depth of the groove 4 gradually increases. Steps S2, S3, S4, and S5 are repeated until the groove 4 penetrates the p-type semiconductor layer EP and the n-type embedded layer BL and reaches the p-type substrate region SB.

[0083] <Regarding groove 4 and DTI area 5> Figures 24 and 25 show the X, Y, and Z directions. The X, Y, and Z directions are orthogonal to each other. The X and Y directions are approximately parallel to the main surface of the semiconductor substrate, and the Z direction is approximately perpendicular to the main surface of the semiconductor substrate. Therefore, the Z direction is parallel to the depth direction. Figures 24 and 25 show cross-sections that are parallel to the X and Z directions and perpendicular to the Y direction. The groove 4 shown in Figure 24 extends in the Y direction. The X direction is the width direction of the groove 4 shown in Figure 24.

[0084] Within the semiconductor substrate 1, the groove 4 is formed by the continuation of multiple removal regions of the semiconductor substrate 1, such as the aforementioned removal region 4a, removal region 4b, and removal region 4c, in the Z direction. As a result, as shown in Figures 24 and 25, multiple scallops 6 are formed on the side surface of the groove 4 within the semiconductor substrate 1. The multiple scallops 6 are connected in the Z direction.

[0085] The scallops 6 have, for example, a shell-like or bowl-shaped curved surface, or an inverse tapered shape, and protrusions (convex portions) 7 exist at the boundaries between the scallops 6. The protrusions 7 are portions that locally protrude from the side surface of the groove 4 toward the inside of the groove 4. Each protrusion 7 extends along the side surface of the groove 4 in a direction substantially perpendicular to the Z direction (horizontal direction). The protrusions 7 shown in Figures 24 and 25 protrude in the X direction and extend in the Y direction along the side surface of the groove 4. Because multiple scallops 6 are connected in the Z direction, multiple protrusions 7 that extend in the Y direction along the side surface of the groove 4 are arranged periodically in the Z direction.

[0086] The reason scallops 6 are formed is that the etching of the semiconductor substrate 1 when forming the grooves 4 is mainly carried out by the isotropic etching process in step S4. One scallop 6 is formed by the removal area of ​​the semiconductor substrate 1 generated in one isotropic etching process in step S4. For example, as shown in Figure 23, scallop 6a is formed by the side surface of the removal area 4a, scallop 6b is formed below scallop 6a by the side surface of the removal area 4b, and scallop 6c is formed below scallop 6b by the side surface of the removal area 4c. A protrusion 7a is formed at the boundary between scallop 6a and scallop 6b, and a protrusion 7b is formed at the boundary between scallop 6b and scallop 6c. A number of scallops 6 corresponding to the number of cycles of repeating steps S2, S3, S4, and S5 are stacked in the Z direction.

[0087] Figures 23, 24, and 25 show the size L1 of the scallops 6. The size L1 of the scallops 6 corresponds to the distance between the tip of the projection 7 and the bottom of the scallop 6 in the width direction (X direction) of the groove 4. The bottom of each scallop 6 corresponds to the part furthest from the center of the groove 4 in the width direction (X direction) of the groove 4. Therefore, the size L1 of the scallops 6 represents the size of the unevenness (step) on the side surface of the groove 4 caused by the scallops 6. A larger size L1 of the scallops 6 indicates a larger unevenness (step) caused by the scallops 6. The size L1 of the scallops 6 can be controlled by the etching amount in the isotropic etching process of step S4. The larger the etching amount of the semiconductor substrate 1 in the isotropic etching process of step S4 (etching amount in the Z direction), the larger the size L1 of the scallops 6 becomes.

[0088] The groove 4 penetrates the p-type semiconductor layer EP and the n-type embedded layer BL, reaching the p-type substrate region SB. Therefore, the side surface of the groove 4 includes the side surface of the groove 4 formed within the p-type semiconductor layer EP, the side surface of the groove 4 formed within the n-type embedded layer BL, and the side surface of the groove 4 formed within the p-type substrate region SB. The side surface of the groove 4 formed within the p-type semiconductor layer EP is continuous with the side surface of the groove 4 formed within the n-type embedded layer BL, and the side surface of the groove 4 formed within the n-type embedded layer BL is continuous with the side surface of the groove 4 formed within the p-type substrate region SB.

[0089] Here, the scallop 6 formed on the side surface of the groove 4 in the p-type semiconductor layer EP is referred to as scallop 6d, the scallop 6 formed on the side surface of the groove 4 in the n-type embedded layer BL is referred to as scallop 6e, and the scallop 6 formed on the side surface of the groove 4 in the p-type substrate region SB is referred to as scallop 6f. The size L1 of scallop 6d is referred to as size L1d, the size L1 of scallop 6e is referred to as size L1e, and the size L1 of scallop 6f is referred to as size L1f. The protrusion 7 formed on the side surface of the groove 4 in the p-type semiconductor layer EP is referred to as protrusion 7d, the protrusion 7 formed on the side surface of the groove 4 in the n-type embedded layer BL is referred to as protrusion 7e, and the protrusion 7 formed on the side surface of the groove 4 in the p-type substrate region SB is referred to as protrusion 7f.

[0090] The size L1d of scallop 6d is preferably larger than the size L1e of scallop 6e. Similarly, the size L1f of scallop 6f is preferably larger than the size L1e of scallop 6e. The reasons for this will be explained in detail later.

[0091] Scallop 6d is formed by isotropically etching the p-type semiconductor layer EP in the isotropic etching process of step S4. Scallop 6e is formed by isotropically etching the n-type embedded layer BL in the isotropic etching process of step S4. Scallop 6f is formed by isotropically etching the p-type substrate region SB in the isotropic etching process of step S4.

[0092] <Background of the consideration> Examples of studies conducted by the inventors will be explained with reference to Figures 26 to 28.

[0093] Figure 26 shows a state in which grooves 104 for the DTI region are formed in the semiconductor substrate 1. The grooves 104 are formed by anisotropic etching of the p-type semiconductor layer EP, the n-type embedded layer BL, and the p-type substrate region SB. For this reason, the scallops 6 are not formed on the sides of the grooves 104.

[0094] In the process of forming the groove 104, when the n-type embedded layer BL is etched, etching residue containing n-type impurities may adhere to the side surface of the groove 104 in the p-type semiconductor layer EP. As a result, due to the etching residue containing n-type impurities, an n-type semiconductor region NR may be formed in the p-type semiconductor layer EP along the side surface of the groove 104, as shown in Figure 27.

[0095] If an n-type semiconductor region NR is formed within the p-type semiconductor layer EP along the side surface of groove 104, it may adversely affect the operation of the semiconductor element (e.g., the Zener diode 2) formed within the p-type semiconductor layer EP. This is because the n-type semiconductor region NR may constitute part of a parasitic transistor and act to promote the operation of the parasitic transistor. Therefore, in order to improve the performance of the semiconductor device, it is desirable to prevent the formation of unnecessary n-type semiconductor regions NR within the p-type semiconductor layer EP.

[0096] Therefore, after forming the groove 104, ion implantation of p-type impurities is performed on the semiconductor substrate 1 exposed from the groove 104, as shown in Figure 28. This ion implantation is schematically shown as ion implantation IM101 in Figure 28.

[0097] Oblique ion implantation of p-type impurities is performed as ion implantation IM101. Figure 28 shows the region PL100 in the semiconductor substrate 1 where p-type impurities have been implanted by ion implantation IM101. Region PL100 is formed in the semiconductor substrate 1 so as to follow the bottom and side surfaces of groove 104. Region PL100 includes region PL101 located within the p-type semiconductor layer EP, region PL102 located within the n-type embedded layer BL, and region PL103 located within the p-type substrate region SB.

[0098] It is desirable that the amount of p-type impurities implanted into region PL101 by ion implantation IM101 be large. This is because if the amount of p-type impurities implanted into region PL101 by ion implantation IM101 is small, the n-type semiconductor region NR will remain in the p-type semiconductor layer EP even after ion implantation IM101. It is necessary to make the conductivity type of region PL101 p-type, and for this purpose, it is necessary to implant p-type impurities into region PL101 by ion implantation IM101 at a higher concentration than the n-type impurity concentration in the n-type semiconductor region NR.

[0099] On the other hand, it is desirable that the amount of p-type impurities implanted into region PL102 by ion implantation IM101 be small. This is because if the amount of p-type impurities implanted into region PL102 by ion implantation IM101 is large, there is a risk that the conductivity type of region PL102 will become p-type. If the conductivity type of region PL102 becomes p-type, the p-type substrate region SB and the p-type semiconductor layer EP will conduct through the p-type region PL102. It is necessary to prevent the p-type substrate region SB and the p-type semiconductor layer EP from conducting through the p-type region PL102. Therefore, it is necessary to prevent the conductivity type of region PL102 from becoming p-type, and for this reason, it is desirable that the amount of p-type impurities implanted into region PL102 by ion implantation IM101 be small.

[0100] Therefore, it is desirable that the amount of p-type impurities implanted into region PL101 by ion implantation IM101 be large, and that the amount of p-type impurities implanted into region PL102 by ion implantation IM101 be small. However, even if the conditions of ion implantation IM101 are adjusted, it is difficult to achieve both a large amount of p-type impurities implanted into region PL101 and a small amount of p-type impurities implanted into region PL102.

[0101] <Main Features and Effects> The semiconductor device of this embodiment has a groove 4 that penetrates the p-type semiconductor layer EP and the n-type embedded layer BL and reaches the p-type substrate region SB, and a DTI region 5 formed within the groove 4.

[0102] One of the distinctive features is that multiple scallops 6 are formed on the side surface of the groove 4, and these multiple scallops 6 include multiple scallops 6d formed on the side surface of the groove 4 within the p-type semiconductor layer EP and multiple scallops 6e formed on the side surface of the groove 4 within the n-type embedded layer BL. The size L1d of each of the multiple scallops 6d is larger than the size L1e of each of the multiple scallops 6e.

[0103] Figure 29 is a partially enlarged cross-sectional view, which is an enlarged portion of Figure 8. Figure 30 is a partially enlarged cross-sectional view, which is an enlarged portion of Figure 1, and the region PL, in which p-type impurities were implanted by ion implantation IM, is also shown in Figure 30.

[0104] The reason for performing ion implantation IM as shown in Figure 29 is the same as the reason for performing ion implantation IM101 described above. That is, when the n-type embedded layer BL is etched during the process of forming the groove 4, etching residues containing n-type impurities are generated and adhere to the side surface of the groove 4 in the p-type semiconductor layer EP, which may cause an n-type semiconductor region to be formed in the p-type semiconductor layer EP along the side surface of the groove 4.

[0105] After forming the groove 4, as shown in Figures 8 and 29, ion implantation (IM) of p-type impurities is performed to implant p-type impurities into the semiconductor substrate 1 exposed from the groove 4. In ion implantation IM, it is necessary to incident the p-type impurities on the side surface of the groove 4. For this reason, it is desirable to apply oblique ion implantation of p-type impurities as the ion implantation IM.

[0106] Region PL, into which p-type impurities are implanted by ion implantation IM, is formed within the semiconductor substrate 1 along the bottom and side surfaces of groove 4. As shown in Figures 29 and 30, region PL includes region PL1 located within the p-type semiconductor layer EP, region PL2 located within the n-type embedded layer BL, and region PL3 located within the p-type substrate region SB.

[0107] By increasing the size L1d of each of the multiple scallops 6d formed on the side surface of the groove 4 in the p-type semiconductor layer EP, the amount of p-type impurities implanted into region PL1 by ion implantation IM can be increased. The reason for this is as follows.

[0108] By increasing the size L1d of the scallop 6d, the protrusion amount of the protrusion 7d can be increased, and the effective surface area of ​​the side surface of the groove 4 in the p-type semiconductor layer EP can be increased. If the protrusion amount of the protrusion 7d is large, the amount of p-type impurities implanted into the p-type semiconductor layer EP from the surface of the protrusion 7d will be large. If the effective surface area of ​​the side surface of the groove 4 in the p-type semiconductor layer EP is large, the amount of p-type impurities implanted into the p-type semiconductor layer EP from the side surface of the groove 4 will be large. As a result, the amount of p-type impurities implanted into region PL1 by ion implantation IM can be increased.

[0109] When the size L1d of the scallop 6d is large, the probability of p-type impurities reflected by the scallop 6d being implanted into the p-type semiconductor layer EP increases. As a result, the amount of p-type impurities implanted into region PL1 by ion implantation IM can be increased.

[0110] By reducing the size L1e of each of the multiple scallops 6e formed on the side surface of the groove 4 in the n-type embedding layer BL, the amount of p-type impurities implanted into region PL2 by ion implantation IM can be reduced. The reason for this is as follows.

[0111] By reducing the size L1e of the scallop 6e, the irregularities (steps) on the sides of the groove 4 in the n-type embedded layer BL are reduced, and the flatness of the sides of the groove 4 in the n-type embedded layer BL is improved. Therefore, by reducing the size L1e of the scallop 6e, the influence of the protrusion 7e is reduced, and the increase in the effective area (surface area) of the groove 4 caused by the scallop 6e can be suppressed. As a result, the amount of p-type impurities implanted into region PL2 by ion implantation IM can be reduced.

[0112] Increasing the size L1 of scallop 6 increases the amount of p-type impurities implanted into the region PL by ion implantation IM, while decreasing the size L1 of scallop 6 decreases the amount of p-type impurities implanted into the region PL by ion implantation IM. Therefore, the size L1d of scallop 6d is made larger than the size L1e of scallop 6e. This makes it possible to increase the amount of p-type impurities implanted into region PL1 by ion implantation IM compared to the amount of p-type impurities implanted into region PL2 by ion implantation IM. As a result, it is possible to achieve both an increase in the amount of p-type impurities implanted into region PL1 by ion implantation IM and a decrease in the amount of p-type impurities implanted into region PL2 by ion implantation IM. This improves the performance of the semiconductor device.

[0113] In other words, by increasing the amount of p-type impurities implanted into region PL1 by ion implantation IM, the conductivity type of region PL1 can be reliably made p-type, thus preventing the existence of unwanted n-type semiconductor regions such as the n-type semiconductor region NR within the p-type semiconductor layer EP. As a result, it is possible to prevent the operation of parasitic transistors from being accelerated due to unwanted n-type semiconductor regions such as the n-type semiconductor region NR. Furthermore, by decreasing the amount of p-type impurities implanted into region PL2 by ion implantation IM, it becomes easier to maintain the conductivity type of region PL2 as n-type, thereby effectively preventing the p-type substrate region SB and the p-type semiconductor layer EP from conducting through region PL2.

[0114] Therefore, in the manufactured semiconductor device, region PL1 is a p-type semiconductor region, and region PL2 is an n-type semiconductor region. Region PL1 is formed within the p-type semiconductor layer EP along the side surface of groove 4 and is in contact with the DTI region 5. Region PL2 is formed within the n-type embedded layer BL along the side surface of groove 4 and is in contact with the DTI region 5. It is preferable that the p-type impurity concentration in region PL1 is higher than the p-type impurity concentration in the p-type semiconductor layer EP.

[0115] The size L1 of the scallop 6 can be controlled by the etching amount in the isotropic etching process in step S4. When isotropically etching the p-type semiconductor layer EP in step S4, the etching amount of the p-type semiconductor layer EP (etching amount in the Z direction) is made larger than the etching amount of the n-type embedded layer BL (etching amount in the Z direction) when isotropically etching the n-type embedded layer BL in step S4. This makes the size L1d of the scallop 6d larger than the size L1e of the scallop 6e. The etching amount in step S4 can be controlled by the etching time in step S4. By increasing the etching time in step S4, the etching amount in step S4 can be increased.

[0116] The multiple scallops 6 formed on the side surface of groove 4 further include multiple scallops 6f formed on the side surface of groove 4 within the p-type substrate region SB. It is preferable that the size L1f of each of the multiple scallops 6f is larger than the size L1e of each of the multiple scallops 6e. The reason for this is as follows:

[0117] It is undesirable for the n-type semiconductor region NR to be formed within the p-type semiconductor layer EP along the side surface of groove 4. This is because the n-type semiconductor region formed within the p-type semiconductor layer EP may constitute part of a parasitic transistor. In comparison, the adverse effects of the n-type semiconductor region being formed within the p-type substrate region SB along the side surface of groove 4 are small.

[0118] On the other hand, reducing the size L1 of the scallop 6 increases the time required for the etching process shown in Figure 7, while increasing the size L1 of the scallop 6 shortens the time required for the etching process shown in Figure 7. This is because reducing the size L1 of the scallop 6 requires increasing the number of cycles in steps S2, S3, S4, and S5.

[0119] Therefore, the size L1f of the scallop 6f is made larger than the size L1e of the scallop 6e. This makes it possible to suppress the time required for the groove 4 to form in the p-type substrate region SB after the groove 4 penetrates the n-type embedded layer BL. As a result, the time required for the etching process shown in Figure 7 can be shortened. Consequently, the manufacturing time of the semiconductor device can be reduced. In addition, the throughput of the semiconductor device can be improved.

[0120] Therefore, it is preferable to increase the size L1d of scallop 6d, decrease the size L1e of scallop 6e, and increase the size L1f of scallop 6f. For this reason, the size L1d of scallop 6d is made larger than the size L1e of scallop 6e, and the size L1f of scallop 6f is made larger than the size L1d of scallop 6d and larger than the size L1e of scallop 6e. This makes it possible to increase the amount of p-type impurities implanted into region PL1 by ion implantation IM, decrease the amount of p-type impurities implanted into region PL2 by ion implantation IM, and suppress the time required for the etching process shown in Figure 7.

[0121] In step S4, when isotropically etching the p-type substrate region SB, the etching amount of the p-type substrate region SB (etching amount in the Z direction) is made larger than the etching amount of the n-type embedded layer BL (etching amount in the Z direction) when isotropically etching the n-type embedded layer BL in step S4. This makes it possible to make the size L1f of the scallop 6f larger than the size L1e of the scallop 6e.

[0122] When the width of the groove 4 is large, it is easy to implant p-type impurities into the p-type semiconductor layer EP from the side of the groove 4 by performing oblique ion implantation after the groove 4 is formed. However, when the width of the groove 4 is 1 micrometer or less, it is difficult to implant p-type impurities into the p-type semiconductor layer EP from the side of the groove 4 when oblique ion implantation is performed after the groove 4 is formed. As described above, by forming multiple scallops 6 on the side of the groove 4, the amount of p-type impurities implanted into the p-type semiconductor layer EP from the side of the groove 4 can be increased even when the width of the groove 4 is 1 micrometer or less. For this reason, this embodiment is particularly effective when applied when the width of the groove 4 is 1 micrometer or less.

[0123] Figure 31 is a graph showing the correlation between the size L1e of the scallop 6e and the leakage current between the p-type substrate region SB and the p-type semiconductor layer EP. The horizontal axis of the graph in Figure 31 corresponds to the size L1e of the scallop 6e. The vertical axis of the graph in Figure 31 corresponds to the leakage current between the p-type substrate region SB and the p-type semiconductor layer EP.

[0124] The graph in Figure 31 shows that when the size L1e of the scallop 6e is 20 nm or less, the leakage current between the p-type substrate region SB and the p-type semiconductor layer EP can be sufficiently suppressed. For this reason, it is preferable that the size L1e of the scallop 6e be 20 nm or less.

[0125] The size L1e of the scallop 6e can be controlled by the amount of etching of the n-type embedded layer BL when the n-type embedded layer BL is isotropically etched in step S4. For example, by setting the amount of etching of the n-type embedded layer BL (etching amount in the Z direction) when the n-type embedded layer BL is isotropically etched in step S4 to 60 nm or less, the size L1e of the scallop 6e can be set to 20 nm or less.

[0126] Figure 32 is a graph showing the correlation between the scallop size and the sidewall resistance of the DTI region. The horizontal axis of the graph in Figure 32 corresponds to the scallop size. The vertical axis of the graph in Figure 32 corresponds to the sidewall resistance of the DTI region. Figure 33 is a plan view showing a test pattern for measuring the sidewall resistance of the DTI region.

[0127] The test pattern shown in Figure 33 includes n-type regions NW1 and NW2 formed within the p-type semiconductor layer EP1 of a test semiconductor substrate, a plug PG1 placed on n-type region NW1, a plug PG2 placed on n-type region NW2, and a test DTI region 5a in contact with both n-type regions NW1 and NW2. Multiple scallops are formed on the side surface of the groove in which the DTI region 5a is embedded. The sidewall resistance of the DTI region 5a is measured by the electrical resistance between plugs PG1 and PG2.

[0128] If an n-type semiconductor region NR is formed within the p-type semiconductor layer EP1 along the sidewall of the DTI region 5a, then the n-type region NW1 and the n-type region NW2 conduct through the n-type semiconductor region NR, resulting in a smaller sidewall resistance of the DTI region 5a. Conversely, if an n-type semiconductor region NR is not formed within the p-type semiconductor layer EP1 along the sidewall of the DTI region 5a, then no conduction path is formed along the sidewall of the DTI region 5a, resulting in a larger sidewall resistance of the DTI region 5a.

[0129] Therefore, the magnitude of the sidewall resistance of the DTI region 5a allows us to evaluate whether or not an n-type semiconductor region NR is formed along the sidewall of the DTI region 5a. In other words, if the magnitude of the sidewall resistance of the DTI region 5a is large, it can be determined that an n-type semiconductor region NR is not formed along the sidewall of the DTI region 5a. The absence of an n-type semiconductor region NR along the sidewall of the DTI region 5a means that the n-type impurities in the n-type semiconductor region NR were canceled out by the p-type impurities implanted by ion implantation after groove formation (corresponding to the ion implantation IM mentioned above).

[0130] The graph in Figure 32 shows that when the scallop size is less than 20 nm, the sidewall resistance of the DTI region decreases. The graph in Figure 32 also shows that when the scallop size is greater than 150 nm, the sidewall resistance of the DTI region decreases. When the scallop size is 20 nm or more and 150 nm, the sidewall resistance of the DTI region is large. When the scallop size is greater than 150 nm, the protrusions 7 above become more effective at shielding the p-type impurities from being injected into the p-type semiconductor layer EP1 from the scallops, which is thought to reduce the sidewall resistance of the DTI region.

[0131] Therefore, the size L1d of the scallop 6d is preferably 20 nm or more and 150 nm or less. By setting the size L1d of the scallop 6d within the range of 20 nm or more and 150 nm or less, the amount of p-type impurities implanted into region PL1 by ion implantation IM can be increased, thereby preventing the existence of unwanted n-type semiconductor regions, such as the n-type semiconductor region NR, within the p-type semiconductor layer EP along the DTI region.

[0132] The size L1d of the scallop 6d can be controlled by the amount of etching of the p-type semiconductor layer EP when isotropically etching the p-type semiconductor layer EP in step S4. For example, by setting the amount of etching of the p-type semiconductor layer EP (etching amount in the Z direction) when isotropically etching the p-type semiconductor layer EP in step S4 to 60 nm or more and 450 nm or less, the size L1d of the scallop 6d can be set to 20 nm or more and 150 nm or less.

[0133] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0134] In the above embodiment, the case in which a Zener diode 2 is formed as a semiconductor element in a p-type semiconductor layer EP surrounded by a DTI region 5 and an n-type embedded layer BL has been described. When a Zener diode 2 is formed in a p-type semiconductor layer EP, if the n-type semiconductor region NR is formed in the p-type semiconductor layer EP along the side surface of the groove 4, the n-type semiconductor region NR constitutes part of a parasitic transistor and acts to promote the operation of the parasitic transistor.

[0135] In the above embodiment, an n-channel LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) may be formed as a semiconductor element within the p-type semiconductor layer EP surrounded by the DTI region 5 and the n-type embedded layer BL. Even when an n-channel LDMOSFET is formed within the p-type semiconductor layer substrate EP surrounded by the DTI region 5 and the n-type embedded layer BL, an n-channel NPN parasitic transistor and a PNP parasitic transistor may be formed within the semiconductor substrate SB, thereby forming a parasitic thyristor. When an n-channel LDMOSFET is formed within the p-type semiconductor layer EP, if the n-type semiconductor region NR is formed within the p-type semiconductor layer EP along the side surface of the groove 4, the n-type semiconductor region NR constitutes part of the parasitic transistor and acts to promote the operation of the parasitic transistor. Note that LDMOSFETs include not only MOSFETs using an oxide film as the gate insulating film, but also MOSFETs using insulating films other than oxide films as the gate insulating film. Furthermore, an n-channel LDMOSFET is referred to as an n-type LDMOSFET, and a p-channel LDMOSFET is referred to as a p-type LDMOSFET.

[0136] Therefore, the above embodiment is particularly effective when applied to a case where a Zener diode or an n-channel type LDMOSFET (n-type LDMOSFET) is formed as a semiconductor element within a p-type semiconductor layer EP surrounded by a DTI region 5 and an n-type embedded layer BL. [Explanation of Symbols]

[0137] 1. Semiconductor substrate 2 Zener diodes 3 STI area 4,104 grooves 4a,4b,4c removal area 5,5a,5b DTI area 6,6a,6b,6c,6d,6e,6f Scallop 7,7a,7b,7d,7e,7f Protrusion AD p-type semiconductor region BL n-type embedded layer CD n-type semiconductor region DP protective film EP p-type semiconductor layer IL insulating film IM, IM101 Ion implantation M1 Wiring M1A Anode Wiring M1C Cathode Wiring MK Mask Layer NR n-type semiconductor region OP1, OP2, OP3 opening PG, PG1, PG2, PGA, PGC plugs PL,PL1,PL2,PL3 area PL100,PL101,PL102,PL103 area PR p-type semiconductor region PW p-type well area RP1 Photoresist Pattern SB p-type substrate area

Claims

1. A semiconductor substrate having a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, A groove that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region, The element isolation region formed within the groove, It has, Multiple scallops are formed on the side surface of the groove, The plurality of scallops include a plurality of first scallops formed on the side surface of the groove in the second semiconductor layer and a plurality of second scallops formed on the side surface of the groove in the first semiconductor layer. A semiconductor device in which the size of each of the plurality of first scallops is larger than the size of each of the plurality of second scallops.

2. In the semiconductor device described in claim 1, The bottom surface of the groove is deeper than the bottom surface of the first semiconductor layer. The plurality of scallops further include a plurality of third scallops formed on the side surface of the groove in the substrate region, A semiconductor device in which the size of each of the plurality of third scallops is larger than the size of each of the plurality of second scallops.

3. In the semiconductor device described in claim 1, The second semiconductor layer further comprises a semiconductor element formed within the second semiconductor layer, A semiconductor device in which, in a plan view, the semiconductor element is surrounded by the element isolation region.

4. In the semiconductor device according to claim 3, The semiconductor device is a Zener diode or the second-type LDMOSFET.

5. In the semiconductor device according to claim 4, The Zener diode is The well region of the first conductivity type formed within the second semiconductor layer, The second conductive cathode region formed within the well region, A semiconductor device having

6. In the semiconductor device described in claim 1, The second semiconductor layer further comprises a first semiconductor region of the first conductivity type formed along the side surface of the groove, A semiconductor device wherein the impurity concentration of the first conductivity type in the first semiconductor region is greater than the impurity concentration of the first conductivity type in the first semiconductor layer.

7. In the semiconductor device described in claim 1, A semiconductor device in which the size of each of the plurality of first scallops is 20 nm or more and 150 nm or less.

8. In the semiconductor device according to claim 7, A semiconductor device in which the size of each of the plurality of second scallops is 20 nm or less.

9. (a) A step of preparing a semiconductor substrate having a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer. (b) A step of forming a groove that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region. (c) After step (b), a step of ion implanting the first conductivity type impurity into the semiconductor substrate exposed from the groove, (d) After step (c), a step of forming an element isolation region in the groove, It has, In step (b) above, the groove is formed such that a plurality of scallops are formed on the side surface of the groove, The plurality of scallops include a plurality of first scallops formed on the side surface of the groove in the second semiconductor layer and a plurality of second scallops formed on the side surface of the groove in the first semiconductor layer. A method for manufacturing a semiconductor device, wherein the size of each of the plurality of first scallops is larger than the size of each of the plurality of second scallops.

10. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein the ion implantation in step (c) is oblique ion implantation.

11. In the method for manufacturing a semiconductor device according to claim 9, The bottom surface of the groove is deeper than the bottom surface of the first semiconductor layer. The plurality of scallops further include a plurality of third scallops formed on the side surface of the groove in the substrate region, A method for manufacturing a semiconductor device, wherein the size of each of the plurality of third scallops is larger than the size of each of the plurality of second scallops.

12. In the method for manufacturing a semiconductor device according to claim 9, The above step (b) is, (b1) A step of forming a protective film on the semiconductor substrate, (b2) After step (b1), a step of forming an opening in the protective film by anisotropic etching the protective film, (b3) After step (b2), an isotropic etching of the semiconductor substrate exposed from the opening of the protective film, (b4) After step (b3), a step of removing the protective film, A method for manufacturing a semiconductor device, comprising multiple cycles.

13. In the method for manufacturing a semiconductor device according to claim 12, A method for manufacturing a semiconductor device, wherein the amount of etching of the second semiconductor layer when the second semiconductor layer is isotropically etched in step (b3) is greater than the amount of etching of the first semiconductor layer when the first semiconductor layer is isotropically etched in step (b3).

14. In the method for manufacturing a semiconductor device according to claim 13, The bottom surface of the groove is deeper than the bottom surface of the first semiconductor layer. The plurality of scallops further include a plurality of third scallops formed on the side surface of the groove in the substrate region, A method for manufacturing a semiconductor device, wherein the size of each of the plurality of third scallops is larger than the size of each of the plurality of second scallops.

15. In the method for manufacturing a semiconductor device according to claim 14, The above step (b) is, (b1) A step of forming a protective film on the semiconductor substrate, (b2) A step of forming an opening in the protective film by anisotropic etching of the protective film, (b3) A step of isotropically etching the semiconductor substrate exposed from the opening of the protective film, (b4) Step of removing the protective film, This includes multiple cycles, When the second semiconductor layer is isotropically etched in step (b3), the amount of etching of the second semiconductor layer is greater than the amount of etching of the first semiconductor layer when the first semiconductor layer is isotropically etched in step (b3). A method for manufacturing a semiconductor device, wherein the amount of etching of the substrate region when the substrate region is isotropically etched in step (b3) is greater than the amount of etching of the first semiconductor layer when the first semiconductor layer is isotropically etched in step (b3).

16. In the method for manufacturing a semiconductor device according to claim 9, (e) A step of forming a semiconductor element in the second semiconductor layer, It further possesses, A method for manufacturing a semiconductor device, wherein, in a plan view, the semiconductor element is surrounded by the element isolation region.

17. In the method for manufacturing a semiconductor device according to claim 16, A method for manufacturing a semiconductor device, wherein the semiconductor element is a Zener diode or the second-conductivity type LDMOSFET.

18. In the method for manufacturing a semiconductor device according to claim 17, The Zener diode is The well region of the first conductivity type formed within the second semiconductor layer, The second conductive cathode region formed within the well region, A method for manufacturing a semiconductor device having the following characteristics.

19. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein the size of each of the plurality of first scallops is 20 nm or more and 150 nm or less.

20. In the method for manufacturing a semiconductor device according to claim 19, A method for manufacturing a semiconductor device, wherein the size of each of the plurality of second scallops is 20 nm or less.

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