Semiconductor memory

Abstract

The present invention provides a semiconductor memory device that enables an improvement in the charge storage density of the charge storage layer. [Solution] The semiconductor memory device of the embodiment comprises a semiconductor layer, a gate electrode layer, a first insulating layer provided between the semiconductor layer and the gate electrode layer, a second insulating layer provided between the first insulating layer and the gate electrode layer, and a charge storage layer provided between the first insulating layer and the second insulating layer, which includes at least one first crystal having a first space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31), and which includes at least one first element selected from the group consisting of Hf and Zr, at least one second element selected from the group consisting of Ti, Ce, Ta, W, Nb, Mo, Mn, Ru, and Sn, and oxygen.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] In a flash memory, thinning of the charge storage layer is desired in order to miniaturize memory cells. In order to realize thinning of the charge storage layer, it is necessary to improve the charge storage ability per unit thickness of the charge storage layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device capable of improving charge storage ability.

Means for Solving the Problems

[0005] The semiconductor memory device of the embodiment comprises a semiconductor layer, a gate electrode layer, a first insulating layer provided between the semiconductor layer and the gate electrode layer, a second insulating layer provided between the first insulating layer and the gate electrode layer, and one space selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31), provided between the first insulating layer and the second insulating layer. The device comprises a charge storage layer containing at least one first crystal including a first region having an intergroup, at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O). [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of a semiconductor memory device according to the first embodiment. [Figure 2] A schematic cross-sectional view of a portion of the charge storage layer in the first embodiment. [Figure 3] A diagram illustrating the operation and effects of the semiconductor memory device according to the first embodiment. [Figure 4] A schematic cross-sectional view of a portion of the charge storage layer in the second embodiment. [Figure 5] A diagram illustrating the operation and effects of the semiconductor memory device according to the second embodiment. [Figure 6] A schematic cross-sectional view of a portion of the charge storage layer in the third embodiment. [Figure 7] A diagram illustrating the operation and effects of the semiconductor memory device according to the third embodiment. [Figure 8] A schematic cross-sectional view of a portion of the charge storage layer in the fourth embodiment. [Figure 9] A diagram illustrating the operation and effects of the semiconductor memory device according to the fourth embodiment. [Figure 10] Circuit diagram of the memory cell array of the semiconductor memory device according to the fifth embodiment. [Figure 11] A schematic cross-sectional view of a memory cell array of a semiconductor memory device according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described will be omitted from the description as appropriate.

[0008] Furthermore, for convenience, the terms "upper" or "lower" may be used in this specification. "Upper" or "lower" are terms that indicate relative positional relationships within the drawings and do not define positional relationships relative to gravity.

[0009] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor memory device described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or electron energy loss spectroscopy (EELS). Furthermore, a transmission electron microscope (TEM) can be used, for example, to measure the thickness of the components constituting the semiconductor memory device, the distance between components, etc. Furthermore, for identifying the crystal systems of the components constituting semiconductor memory devices and comparing the relative abundances of these crystal systems, methods such as scanning transmission electron microscopy (STEM), X-ray diffraction analysis (XRD), electron beam diffraction analysis (EBD), X-ray photoelectron spectroscopy (XPS), or synchrotron radiation X-ray absorption fine structure analysis (XAFS) can be used. Additionally, the presence or absence of oriented structures in the components constituting semiconductor memory devices can be confirmed using, for example, TEM. Furthermore, the presence of polarization domains in the crystals constituting semiconductor memory devices and the determination of the polarization direction of these domains can be performed using, for example, spherical aberration-corrected scanning transmission electron microscopy (Cs-corrected STEM).

[0010] (First embodiment) The semiconductor memory device of the first embodiment comprises a semiconductor layer, a gate electrode layer, a first insulating layer provided between the semiconductor layer and the gate electrode layer, a second insulating layer provided between the first insulating layer and the gate electrode layer, and a space group provided between the first insulating layer and the second insulating layer, selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). The device comprises a charge storage layer containing at least one first crystal including a first region, at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O).

[0011] The first crystal of the semiconductor memory device of the first embodiment further includes a second region having one space group selected from the group consisting of P42 / nmc (space group number 137), space group Pbca (space group number 61), and Pbcm (space group number 57).

[0012] Figure 1 is a schematic cross-sectional view of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to the first embodiment is a charge trap type memory cell 100 that traps charge in a charge storage layer.

[0013] The memory cell 100 of the first embodiment comprises a semiconductor layer 10, a tunnel insulating layer 12, a charge storage layer 14, a block insulating layer 16, and a gate electrode layer 18. The tunnel insulating layer 12 is an example of a first insulating layer. The block insulating layer 16 is an example of a second insulating layer. The semiconductor layer 10 has a source region 10a, a drain region 10b, and a channel region 10c.

[0014] The semiconductor layer 10 is, for example, single-crystal silicon.

[0015] The source region 10a is provided in the semiconductor layer 10. The source region 10a is, for example, an n-type impurity region. The drain region 10b is provided in the semiconductor layer 10. The drain region 10b is, for example, an n-type impurity region. The channel region 10c is provided in the semiconductor layer 10. The channel region 10c is, for example, a p-type impurity region.

[0016] The tunnel insulating layer 12 is provided on the semiconductor layer 10. The tunnel insulating layer 12 is provided between the semiconductor layer 10 and the gate electrode layer 18.

[0017] The tunnel insulating layer 12 has a function of allowing charges to pass therethrough according to the voltage applied between the gate electrode layer 18 and the semiconductor layer 10.

[0018] The tunnel insulating layer 12 is, for example, an oxide, an oxynitride, or a nitride. The tunnel insulating layer 12 contains, for example, silicon oxide, silicon oxynitride, or silicon nitride. The thickness of the tunnel insulating layer 12 in the direction from the semiconductor layer 10 toward the gate electrode layer 18 is, for example, 3 nm or more and 8 nm or less.

[0019] The charge storage layer 14 is provided on the tunnel insulating layer 12. The charge storage layer 14 is located between the tunnel insulating layer 12 and the block insulating layer 16. The thickness of the charge storage layer 14 in the direction from the semiconductor layer 10 toward the gate electrode layer 18 is, for example, 2 nm or more and 10 nm or less.

[0020] The charge storage layer 14 has a function of trapping and storing charges. The charges are, for example, electrons. According to the amount of charges stored in the charge storage layer 14, the threshold voltage of the transistor of the memory cell 100 changes. By utilizing this change in the threshold voltage, the memory cell 100 can store data.

[0021] For example, a change in the threshold voltage of the transistor in memory cell 100 changes the voltage at which the transistor in memory cell 100 turns on. If we define a high threshold voltage state as data "0" and a low threshold voltage state as data "1", then the memory cell can store 1-bit data of "0" and "1".

[0022] The charge storage layer 14 contains at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O).

[0023] The charge storage layer 14 is, for example, hafnium oxide or zirconium oxide. The charge storage layer 14 is, for example, hafnium oxide containing zirconium (Zr). Alternatively, the charge storage layer 14 is, for example, zirconium oxide containing hafnium (Hf).

[0024] The charge storage layer 14 mainly consists of, for example, hafnium oxide or zirconium oxide. The charge storage layer 14 is, for example, a hafnium oxide layer or a zirconium oxide layer.

[0025] The charge storage layer 14 is mainly composed of, for example, hafnium oxide. This means that hafnium oxide accounts for the largest proportion of the components contained in the charge storage layer 14.

[0026] Among the elements contained in the charge storage layer 14, the atomic proportions of hafnium (Hf) and oxygen (O) are, for example, 85% or more.

[0027] Among the elements contained in the charge storage layer 14, the atomic proportions of hafnium (Hf), zirconium (Zr), and oxygen (O) are, for example, 85% or more.

[0028] The charge storage layer 14 is mainly composed of, for example, zirconium oxide. This means that zirconium oxide accounts for the largest proportion of the components contained in the charge storage layer 14.

[0029] Among the elements contained in the charge storage layer 14, the atomic proportions of zirconium (Zr) and oxygen (O) are, for example, 85% or more.

[0030] Among the elements contained in the charge storage layer 14, the atomic proportions of zirconium (Zr), hafnium (Hf), and oxygen (O) are, for example, 85% or more.

[0031] The charge storage layer 14 contains at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn). The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the charge storage layer 14 is, for example, 1% to 15%.

[0032] The charge storage layer 14 contains at least one third element selected from the group consisting of, for example, barium (Ba), strontium (Sr), and calcium (Ca). The atomic concentration of the third element contained in the charge storage layer 14 is, for example, smaller than the atomic concentration of the second element contained in the charge storage layer 14.

[0033] The charge storage layer 14 contains, for example, at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si). The atomic concentration of the fourth element contained in the charge storage layer 14 is, for example, smaller than the atomic concentration of the second element contained in the charge storage layer 14.

[0034] The charge storage layer 14 includes, for example, a third element and a fourth element.

[0035] Figure 2 is a schematic cross-sectional view of a portion of the charge storage layer of the first embodiment. Figure 2 is a cross-section parallel to the direction from the semiconductor layer 10 toward the gate electrode layer 18. In other words, Figure 2 is a cross-section perpendicular to the surface of the semiconductor layer 10.

[0036] The charge storage layer 14 is polycrystalline. The charge storage layer 14 contains multiple crystal grains 20. Grain boundaries 22 exist between adjacent crystal grains 20. Each of the multiple crystal grains 20 is an example of the first crystal.

[0037] Each crystal grain 20 contains at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O).

[0038] The crystal grains 20 are, for example, hafnium oxide or zirconium oxide. The charge storage layer 14 is, for example, hafnium oxide containing zirconium (Zr). Alternatively, the charge storage layer 14 is, for example, zirconium oxide containing hafnium (Hf).

[0039] The crystal grains 20 are mainly composed of, for example, hafnium oxide or zirconium oxide.

[0040] The crystal grain 20 is mainly composed of, for example, hafnium oxide. Among the elements contained in the crystal grain 20, the atomic proportions of hafnium (Hf) and oxygen (O) are, for example, 90% or more. Among the elements contained in the crystal grain 20, the atomic proportions of hafnium (Hf), zirconium (Zr), and oxygen (O) are, for example, 90% or more.

[0041] The crystal grain 20 is mainly composed of zirconium oxide, for example. The atomic proportions of zirconium (Zr) and oxygen (O) in the elements contained in the crystal grain 20 are, for example, 90% or more. The atomic proportions of zirconium (Zr), hafnium (Hf), and oxygen (O) in the elements contained in the crystal grain 20 are, for example, 90% or more.

[0042] Each crystal grain 20 contains at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn). The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the crystal grain 20 is, for example, 1% to 9%.

[0043] The crystal grain 20 contains at least one third element selected from the group consisting of, for example, barium (Ba), strontium (Sr), and calcium (Ca). The atomic concentration of the third element contained in the crystal grain 20 is, for example, less than the atomic concentration of the second element contained in the crystal grain 20.

[0044] For example, the crystal grain 20 contains at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si), and the atomic concentration of the fourth element contained in the crystal grain 20 is smaller than the atomic concentration of the second element contained in the crystal grain 20.

[0045] The crystal grains 20 contain, for example, a third element and a fourth element.

[0046] The median major axis of the crystal grains 20 is, for example, between 1 nm and 5 nm. The median major axis of the crystal grains 20 is, for example, between 1 / 20 and 1 / 2 of the thickness of the charge storage layer 14 in the direction from the semiconductor layer 10 to the gate electrode layer 18. For example, the median major axis of the crystal grains 20 can be determined by randomly measuring the major axes of 10 crystal grains 20 in a cross-sectional image acquired by TEM.

[0047] A crystal grain 20 contains a first polarization domain 20a and a second polarization domain 20b. A crystal grain 20 contains, for example, multiple first polarization domains 20a and multiple second polarization domains 20b. A domain wall 24 exists between adjacent first polarization domains 20a and second polarization domains 20b.

[0048] The first polarization domain 20a is an example of the first region. The second polarization domain 20b is an example of the second region. The first polarization domain 20a and the second polarization domain 20b are examples of polarization domains.

[0049] A crystal grain 20 contains, for example, multiple first polarization domains 20a. The median number of first polarization domains 20a contained in each of the multiple crystal grains 20 is between 3 and 100. For example, the median number of first polarization domains 20a can be determined by measuring the number of first polarization domains 20a contained in each of 10 randomly selected crystal grains 20 in cross-sectional images acquired by STEM.

[0050] The first polarization domain 20a has one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Hafnium oxide or zirconium oxide having space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), or Pmn21 (space group number 31) is a ferroelectric. The first polarization domain 20a has ferroelectric properties.

[0051] The second polarization domain 20b has one space group selected from the group consisting of P42 / nmc (space group number 137), space group Pbca (space group number 61), and Pbcm (space group number 57). Hafnium oxide or zirconium oxide having P42 / nmc (space group number 137), space group Pbca (space group number 61), or Pbcm (space group number 57) is an antiferroelectric. The second polarization domain 20b has antiferroelectric properties.

[0052] The block insulating layer 16 is provided between the tunnel insulating layer 12 and the gate electrode layer 18. The block insulating layer 16 is provided between the charge storage layer 14 and the gate electrode layer 18.

[0053] The blocking insulating layer 16 has the function of blocking the current flowing between the charge storage layer 14 and the gate electrode layer 18.

[0054] The block insulating layer 16 is, for example, an oxide, an oxynitride, or a nitride. The block insulating layer 16 includes, for example, silicon oxide or aluminum oxide.

[0055] The gate electrode layer 18 is a metal or a semiconductor. For example, the gate electrode layer 18 is polycrystalline silicon containing n-type or p-type impurities.

[0056] For example, by connecting the memory cells 100 shown in Figure 1 in series, it becomes possible to form a NAND string of NAND flash memory.

[0057] Next, an example of a method for manufacturing a semiconductor memory device according to the first embodiment will be described. The following description will use the case where the charge storage layer 14 is a hafnium oxide layer as an example.

[0058] First, a silicon oxide film is formed on a silicon substrate by thermal oxidation. The silicon substrate becomes the semiconductor layer 10. The silicon oxide film becomes the tunnel insulating layer 12.

[0059] Next, a hafnium oxide film containing at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn) is formed on the silicon oxide film by atomic layer deposition (ALD). When forming the hafnium oxide film, tensile stress is applied to the hafnium oxide film by deviating the amount of oxygen contained in the hafnium oxide film from the stoichiometric ratio. In addition, when forming the hafnium oxide film, a silicon nitride film, a titanium oxide film, or a cerium oxide film that functions as a stress-applying film is provided in contact with the hafnium oxide film. The hafnium oxide film becomes a charge storage layer 14.

[0060] Furthermore, when forming a hafnium oxide film using the ALD method, it is also possible to include at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca), or at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si), in the hafnium oxide film.

[0061] Next, a silicon oxide film is formed on the charge storage layer 14. For example, chemical vapor deposition (CVD) is used to form the silicon oxide film. The silicon oxide film becomes the block insulating layer 16.

[0062] Next, a polycrystalline silicon film containing conductive impurities is formed. For example, CVD is used to form the polycrystalline silicon film. The polycrystalline silicon film becomes the gate electrode layer 18.

[0063] Next, a polycrystalline silicon film, a silicon oxide film, a hafnium oxide film, and a silicon oxide film are patterned to form a gate electrode structure.

[0064] Next, impurities are ion-implanted into the silicon substrate and activated annealing is performed to form a source region 10a and a drain region 10b.

[0065] Next, the operation and effects of the semiconductor memory device according to the first embodiment will be described.

[0066] Figure 3 is an explanatory diagram of the operation and effects of the semiconductor memory device of the first embodiment. Figure 3 is a schematic cross-sectional view of a part of the charge storage layer of the first embodiment. Figure 3 corresponds to Figure 2. The arrows in Figure 3 indicate the polarization direction of each polarization domain.

[0067] Figure 3 shows the state in which a write voltage is applied between the semiconductor layer 10 and the gate electrode layer 18, and electrons are stored in the charge storage layer 14. When storing electrons in the charge storage layer 14, for example, electrons are injected from the semiconductor layer 10 to the charge storage layer 14 by applying a positive gate voltage to the semiconductor layer 10 from the gate electrode layer 18.

[0068] A gate voltage applied to the gate electrode layer 18 forms a plurality of first polarization domains 20a within the crystal grains 20. The first polarization domains 20a have ferroelectric properties and, upon application of the gate voltage, are polarized such that the semiconductor layer 10 side is positive and the gate electrode layer 18 side is negative.

[0069] As shown in Figure 3, electrons injected into the charge storage layer 14 are trapped in the domain wall 24 on the semiconductor layer 10 side of the first polarization domain 20a, and electrons are stored in the charge storage layer 14.

[0070] If, after electrons have been stored in the charge storage layer 14, the voltage applied to the gate electrode layer 18 becomes zero, the size of the first polarization domain 20a will shrink, the electrons trapped in the first polarization domain 20a will be detrapped, and the density of electrons stored in the charge storage layer 14 will decrease. If the density of electrons stored in the charge storage layer 14 decreases, there is a risk that the data in the memory cell 100 may be lost.

[0071] The charge storage layer 14 of the first embodiment contains at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn). By containing the second element in the charge storage layer 14, a decrease in the density of electrons stored in the charge storage layer 14 is suppressed even when the voltage applied to the gate electrode layer 18 is set to zero.

[0072] It is believed that the presence of a second element in the charge storage layer 14 suppresses the reduction in the size of the first polarization domain 20a even when the voltage applied to the gate electrode layer 18 becomes zero. Specifically, for example, it is thought that the second element contained within the crystal grain 20 pins down the movement of the domain walls, thereby fixing the size of the first polarization domain 20a within the crystal grain 20. In other words, in a typical ferroelectric material, the size of the polarization domain changes as the inversion of the polarization domain propagates with the polarization domain wall as the front line due to an external electric field. That is, the polarization domains facing forward with respect to the external electric field expand, and the polarization domains facing backward with respect to the external electric field contract. This expansion and contraction of the polarization domains is caused by the movement of the polarization domain walls, but the second element has the effect of hindering the movement of the polarization domain walls.

[0073] Therefore, according to the memory cell 100 of the first embodiment, the decrease in the charge density stored in the charge storage layer 14 is suppressed, and the charge storage density of the charge storage layer 14 is improved.

[0074] Furthermore, the presence of a second element in the charge storage layer 14 increases the number of first polarization domains 20a within the crystal grains 20. This is thought to be because the second element contained within the crystal grains 20 promotes the formation of domain nuclei that grow into the first polarization domains 20a within the crystal grains 20 when a gate voltage is applied to the charge storage layer 14.

[0075] Increasing the number of first polarization domains 20a within the crystal grain 20 increases the amount of electrons that can be trapped in a single crystal grain 20, making it possible to further improve the charge storage density of the charge storage layer 14.

[0076] From the viewpoint of increasing the charge storage density of the charge storage layer 14, it is preferable that the charge storage layer 14 contains at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca). It is thought that by containing a third element with a larger ionic radius than hafnium (Hf) or zirconium (Zr) in the crystal grains 20, the strain of the crystal grains 20 increases, and the number of first polarization domains 20a in the crystal grains 20 or the complexity of the structure of the domain walls increases.

[0077] From the viewpoint of increasing the charge storage density of the charge storage layer 14, it is preferable that the charge storage layer 14 contains at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si). It is thought that by containing a fourth element with a smaller ionic radius than hafnium (Hf) or zirconium (Zr) in the crystal grains 20, the strain of the crystal grains 20 increases, and the number of first polarization domains 20a in the crystal grains 20 or the complexity of the domain wall structure increases.

[0078] From the viewpoint of increasing the charge storage density of the charge storage layer 14, it is preferable that the charge storage layer 14 contains both a third element and a fourth element. That is, the atoms of the third element and the atoms of the fourth element mainly substitute for hafnium (Hf) atoms or zirconium (Zr) atoms, but the presence of a third atom with an atomic radius significantly larger than that of hafnium (Hf) atoms or zirconium (Zr) atoms, and a fourth atom with a significantly smaller atomic radius, increases the strain of the oxide crystal lattice containing hafnium (Hf) or zirconium (Zr). In particular, when the third and fourth atoms are not adjacent or far apart, but are simultaneously separated by 1 to 3 hafnium (Hf) atoms or zirconium (Zr) atoms, the strain of the oxide lattice containing hafnium (Hf) or zirconium (Zr) increases further, resulting in a synergistic effect that increases the charge storage density of the charge storage layer 14.

[0079] The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the crystal grains 20 is preferably 1% or more and 9% or less. When the above ratio is 1% or more, the charge storage density of the charge storage layer 14 increases. When the above ratio is 9% or less, the crystal grains 20 of the charge storage layer 14 are stabilized, and the charge storage density stabilizes.

[0080] The median number of first polarization domains 20a contained in each of the multiple crystal grains 20 is preferably 3 to 100, and more preferably 5 to 20. Satisfying the lower limit increases the charge storage density of the charge storage layer 14. Furthermore, satisfying the upper limit facilitates the formation of the first polarization domains 20a. From the viewpoint of increasing the charge storage density, the domain walls 24 separating each domain are preferably of a bent shape or a surface shape with many irregularities rather than a linear or planar shape.

[0081] As described above, according to the first embodiment, a semiconductor memory device that enables an improvement in the charge storage density of the charge storage layer can be realized.

[0082] (Second embodiment) The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the first embodiment in that the first crystal does not include a second region, and the first crystal further includes a third region different from the first region, having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Some descriptions that overlap with the first embodiment may be omitted below.

[0083] The semiconductor memory device of the second embodiment has the same configuration as the memory cell 100 of the first embodiment. The memory cell of the second embodiment includes a charge storage layer 14x instead of the charge storage layer 14 of the memory cell 100 of the first embodiment.

[0084] Figure 4 is a schematic cross-sectional view of a portion of the charge storage layer of the second embodiment. Figure 4 is a cross-section parallel to the direction from the semiconductor layer 10 toward the gate electrode layer 18. In other words, Figure 4 is a cross-section perpendicular to the surface of the semiconductor layer 10.

[0085] The charge storage layer 14x of the second embodiment is polycrystalline. The charge storage layer 14x contains a plurality of crystal grains 21. Grain boundaries 22 exist between adjacent crystal grains 21. Each of the plurality of crystal grains 21 is an example of the first crystal.

[0086] Each crystal grain 21 contains at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O).

[0087] The crystal grains 21 are, for example, hafnium oxide or zirconium oxide. The charge storage layer 14x is, for example, hafnium oxide containing zirconium (Zr). Alternatively, the charge storage layer 14x is, for example, zirconium oxide containing hafnium (Hf).

[0088] The crystal grains 21 are mainly composed of, for example, hafnium oxide or zirconium oxide.

[0089] Crystal grain 21 is mainly composed of, for example, hafnium oxide. Among the elements contained in crystal grain 21, the atomic proportions of hafnium (Hf) and oxygen (O) are, for example, 90% or more. Among the elements contained in crystal grain 21, the atomic proportions of hafnium (Hf), zirconium (Zr), and oxygen (O) are, for example, 90% or more.

[0090] The crystal grain 21 is mainly composed of zirconium oxide, for example. Among the elements contained in the crystal grain 21, the atomic proportions of zirconium (Zr) and oxygen (O) are, for example, 90% or more. Among the elements contained in the crystal grain 21, the atomic proportions of zirconium (Zr), hafnium (Hf), and oxygen (O) are, for example, 90% or more.

[0091] Each crystal grain 21 contains at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn). The ratio of the atomic concentration of the second element to the atomic concentration of the first element in each crystal grain 21 is, for example, between 1% and 9%.

[0092] The crystal grains 21 contain, for example, at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca). The crystal grains 21 also contain, for example, at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si). The charge storage layer 14x contains, for example, the third and fourth elements.

[0093] The median major axis of the crystal grains 21 is, for example, between 1 nm and 5 nm. The median major axis of the crystal grains 21 is, for example, between 1 / 20 and 1 / 2 of the thickness of the charge storage layer 14x in the direction from the semiconductor layer 10 to the gate electrode layer 18.

[0094] A crystal grain 21 contains a first polarization domain 21a and a second polarization domain 21b. A crystal grain 21 contains, for example, multiple first polarization domains 21a and multiple second polarization domains 21b. Domain walls 24 exist between multiple adjacent first polarization domains 21a and second polarization domains 21b.

[0095] The first polarization domain 21a is an example of the first region. The second polarization domain 21b is an example of the third region. The first polarization domain 21a and the second polarization domain 21b are examples of polarization domains.

[0096] The median number of first polarization domains 21a contained within each of the multiple crystal grains 21 is between 3 and 100.

[0097] The first polarization domain 21a has one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Zirconium oxide or zirconium oxide having space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), or Pmn21 (space group number 31) is a ferroelectric. The first polarization domain 21a has ferroelectric properties.

[0098] The second polarization domain 21b has one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31). Zirconium oxide or zirconium oxide having space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), or Pmn21 (space group number 31) is a ferroelectric. The second polarization domain 21b has ferroelectric properties.

[0099] The space group of the second polarization domain 21b and the space group of the first polarization domain 21a are, for example, identical. The second polarization domain 21b and the first polarization domain 21a have different polarization directions.

[0100] The semiconductor memory device of the second embodiment can be manufactured, for example, by adjusting the type and content ratio of each element, the formation conditions of the hafnium oxide film, or the crystallization annealing conditions compared to the manufacturing method of the semiconductor memory device of the first embodiment. Crystallization annealing may be performed by annealing in other manufacturing steps.

[0101] Next, the operation and effects of the semiconductor memory device of the second embodiment will be described.

[0102] Figure 5 is an explanatory diagram of the operation and effects of the semiconductor memory device of the second embodiment. Figure 5 is a schematic cross-sectional view of a part of the charge storage layer of the second embodiment. Figure 5 corresponds to Figure 4. The arrows in Figure 5 indicate the polarization direction of each polarization domain.

[0103] Figure 5 shows the state in which a write voltage is applied between the semiconductor layer 10 and the gate electrode layer 18, and electrons are stored in the charge storage layer 14x. When storing electrons in the charge storage layer 14x, for example, electrons are injected from the semiconductor layer 10 to the charge storage layer 14x by applying a positive gate voltage to the semiconductor layer 10 from the gate electrode layer 18.

[0104] A gate voltage applied to the gate electrode layer 18 forms a plurality of first polarization domains 21a within the crystal grains 21. The first polarization domains 21a have ferroelectric properties and, upon application of the gate voltage, are polarized such that the semiconductor layer 10 side is positive and the gate electrode layer 18 side is negative.

[0105] As shown in Figure 5, electrons injected into the charge storage layer 14x are trapped in the domain wall 24 on the semiconductor layer 10 side of the first polarization domain 21a, and electrons are stored in the charge storage layer 14x.

[0106] If, after electrons have been stored in the charge storage layer 14x, the voltage applied to the gate electrode layer 18 becomes zero, the size of the first polarization domain 21a will shrink, the electrons trapped in the first polarization domain 21a will be detrapped, and the density of electrons stored in the charge storage layer 14x will decrease. A decrease in the density of electrons stored in the charge storage layer 14x may lead to data loss in the memory cell.

[0107] The charge storage layer 14x of the second embodiment, like the charge storage layer 14 of the first embodiment, contains at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn).

[0108] Therefore, according to the memory cell of the second embodiment, the decrease in the charge density stored in the charge storage layer 14x is suppressed by the same action as the charge storage layer 14 of the first embodiment, and the charge storage density of the charge storage layer 14x is improved.

[0109] From the viewpoint of increasing the charge storage density of the charge storage layer 14x, it is preferable that the charge storage layer 14x contains at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca).

[0110] From the viewpoint of increasing the charge storage density of the charge storage layer 14x, it is preferable that the charge storage layer 14x contains at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si).

[0111] From the viewpoint of increasing the charge storage density of the charge storage layer 14x, it is preferable that the charge storage layer 14x contains both the third element and the fourth element.

[0112] The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the crystal grain 21 is preferably 1% or more and 9% or less.

[0113] The median number of first polarization domains 21a contained within each of the multiple crystal grains 21 is preferably 3 to 100, and more preferably 5 to 20. From the viewpoint of increasing the charge storage density, the domain walls 24 separating each domain are preferably bent or have a surface shape with many irregularities rather than being linear or planar.

[0114] As described above, according to the second embodiment, a semiconductor memory device that enables an improvement in the charge storage density of the charge storage layer can be realized.

[0115] (Third embodiment) The semiconductor memory device of the third embodiment differs from the semiconductor memory device of the first embodiment in that the charge storage layer includes a matrix region surrounding at least one first crystal. Some descriptions that overlap with the first embodiment may be omitted below.

[0116] The semiconductor memory device of the third embodiment has the same configuration as the memory cell 100 of the first embodiment. The memory cell of the third embodiment includes a charge storage layer 14y instead of the charge storage layer 14 of the memory cell 100 of the first embodiment.

[0117] Figure 6 is a schematic cross-sectional view of a portion of the charge storage layer of the third embodiment. Figure 6 is a cross-section parallel to the direction from the semiconductor layer 10 toward the gate electrode layer 18. In other words, Figure 6 is a cross-section perpendicular to the surface of the semiconductor layer 10.

[0118] The charge storage layer 14y of the third embodiment includes a plurality of crystal grains 20 and a matrix region 30. The plurality of crystal grains 20 are dispersed within the matrix region 30. The matrix region 30 surrounds the plurality of crystal grains 20.

[0119] The crystal grain 20 of the third embodiment has the same configuration as the crystal grain 20 of the first embodiment.

[0120] The matrix region 30 is amorphous or polycrystalline. If the matrix region 30 is polycrystalline, the median major axis of the crystals contained in the matrix region 30 is smaller than, for example, the median major axis of the crystal grains 20.

[0121] The matrix region 30 includes at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O).

[0122] The matrix region 30 is, for example, hafnium oxide or zirconium oxide. The matrix region 30 is, for example, hafnium oxide containing zirconium (Zr). Alternatively, the matrix region 30 is, for example, zirconium oxide containing hafnium (Hf).

[0123] The matrix region 30 is mainly composed of, for example, hafnium oxide or zirconium oxide.

[0124] The matrix region 30 is mainly composed of, for example, hafnium oxide. Among the elements contained in the matrix region 30, the atomic proportions of hafnium (Hf) and oxygen (O) are, for example, 60% or more. Among the elements contained in the matrix region 30, the atomic proportions of hafnium (Hf), zirconium (Zr), and oxygen (O) are, for example, 60% or more.

[0125] The matrix region 30 is mainly composed of zirconium oxide, for example. Among the elements contained in the matrix region 30, the atomic proportions of zirconium (Zr) and oxygen (O) are, for example, 60% or more. Among the elements contained in the matrix region 30, the atomic proportions of zirconium (Zr), hafnium (Hf), and oxygen (O) are, for example, 60% or more.

[0126] The matrix region 30 contains at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn). The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the crystal grain 20 is, for example, 1% to 40%.

[0127] The matrix region 30 includes, for example, at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca). The matrix region 30 includes, for example, at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si). The matrix region 30 includes, for example, the third and fourth elements.

[0128] The chemical composition of the matrix region 30 differs from, for example, the chemical composition of the crystal grains 20. For example, the atomic concentration of a second element contained in the crystal grains 20 is lower than the atomic concentration of the second element contained in the matrix region 30. Also, for example, the atomic concentration of a third element contained in the crystal grains 20 is lower than the atomic concentration of the third element contained in the matrix region 30. Also, for example, the atomic concentration of a fourth element contained in the crystal grains 20 is lower than the atomic concentration of the fourth element contained in the matrix region 30.

[0129] The semiconductor memory device of the third embodiment can be manufactured, for example, by adjusting the type and content ratio of each element, the formation conditions of the hafnium oxide film, or the crystallization annealing conditions compared to the manufacturing method of the semiconductor memory device of the first embodiment.

[0130] Next, the operation and effects of the semiconductor memory device according to the third embodiment will be described.

[0131] Figure 7 is an explanatory diagram of the operation and effects of the semiconductor memory device of the third embodiment. Figure 7 is a schematic cross-sectional view of a part of the charge storage layer of the third embodiment. Figure 7 corresponds to Figure 6. The arrows in Figure 7 indicate the polarization direction of each polarization domain.

[0132] Figure 7 shows the state in which a write voltage is applied between the semiconductor layer 10 and the gate electrode layer 18, and electrons are stored in the charge storage layer 14y. When storing electrons in the charge storage layer 14y, for example, electrons are injected from the semiconductor layer 10 to the charge storage layer 14y by applying a positive gate voltage to the semiconductor layer 10 from the gate electrode layer 18.

[0133] A gate voltage applied to the gate electrode layer 18 forms a plurality of first polarization domains 20a within the crystal grains 20. The first polarization domains 20a have ferroelectric properties and, upon application of the gate voltage, are polarized such that the semiconductor layer 10 side is positive and the gate electrode layer 18 side is negative.

[0134] As shown in Figure 7, electrons injected into the charge storage layer 14y are trapped in the domain wall 24 on the semiconductor layer 10 side of the first polarization domain 20a, and electrons are stored in the charge storage layer 14y.

[0135] According to the memory cell of the third embodiment, the decrease in the charge density stored in the charge storage layer 14y is suppressed by the same action as the memory cell 100 of the first embodiment, and the charge storage density of the charge storage layer 14y is improved.

[0136] Furthermore, in the charge storage layer 14y of the third embodiment, as shown in Figure 7, electrons are also trapped at the grain boundaries 22 between the crystal grains 20 and the matrix region 30. Therefore, the charge storage density of the charge storage layer 14y is further improved.

[0137] Furthermore, the inclusion of a second element in the charge storage layer 14y allows for a reduction in the grain size of the crystal grains 20. A smaller grain size makes it easier for the first polarization domain 20a to be fixed within the crystal grains 20. Consequently, the charge storage density of the charge storage layer 14y is further improved. Additionally, a smaller grain size of the crystal grains 20 increases the area of ​​the grain boundary 22 between the crystal grains 20 and the matrix region 30. Consequently, the charge storage density of the charge storage layer 14y is further improved.

[0138] From the viewpoint of increasing the charge storage density of the charge storage layer 14y, it is preferable that the charge storage layer 14y contains at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca). From the viewpoint of increasing the charge storage density of the charge storage layer 14y, it is preferable that the charge storage layer 14y contains at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si). From the viewpoint of increasing the charge storage density of the charge storage layer 14y, it is preferable that the charge storage layer 14y contains both the third and fourth elements.

[0139] The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the crystal grain 20 is preferably 1% or more and 9% or less.

[0140] The median number of first polarization domains 20a contained within each of the multiple crystal grains 20 is preferably 3 to 100, and more preferably 5 to 20. From the viewpoint of increasing the charge storage density, the domain walls 24 separating each domain are preferably bent or have a surface shape with many irregularities rather than being linear or planar.

[0141] The crystal included in the matrix region 30 is, for example, a paraelectric material. The crystal included in the matrix region 30 is, for example, hafnium oxide or zirconium oxide of space group P21 / c (space group number 14).

[0142] The crystal included in the matrix region 30 may be, for example, a ferroelectric material. When the crystal included in the matrix region 30 is a ferroelectric material, it is preferable that the polarization direction in the crystal is aligned with the surface of the semiconductor layer 10. By having the polarization direction in the crystal aligned with the surface of the semiconductor layer 10, the apparent influence of the ferroelectric properties of the matrix region 30 on the charge storage density of the charge storage layer 14y is reduced.

[0143] As described above, according to the third embodiment, a semiconductor memory device that enables an improvement in the charge storage density of the charge storage layer can be realized.

[0144] (Fourth embodiment) The semiconductor memory device of the fourth embodiment differs from the semiconductor memory device of the second embodiment in that the charge storage layer includes a matrix region surrounding at least one first crystal. It also differs from the third embodiment in that the configuration of the first crystal is different. In the following, some descriptions that overlap with the second or third embodiment may be omitted.

[0145] The semiconductor memory device of the fourth embodiment has the same configuration as the memory cell 100 of the first embodiment. The memory cell of the fourth embodiment includes a charge storage layer 14z instead of the charge storage layer 14 of the memory cell 100 of the first embodiment.

[0146] Figure 8 is a schematic cross-sectional view of a portion of the charge storage layer of the fourth embodiment. Figure 8 is a cross-section parallel to the direction from the semiconductor layer 10 toward the gate electrode layer 18. In other words, Figure 8 is a cross-section perpendicular to the surface of the semiconductor layer 10.

[0147] The charge storage layer 14z of the fourth embodiment includes a plurality of crystal grains 21 and a matrix region 30. The plurality of crystal grains 21 are dispersed within the matrix region 30. The matrix region 30 surrounds the plurality of crystal grains 21.

[0148] The crystal grains 21 of the fourth embodiment have the same configuration as the crystal grains 21 of the second embodiment. The matrix region 30 of the fourth embodiment has the same configuration as the matrix region 30 of the third embodiment.

[0149] The semiconductor memory device of the fourth embodiment can be manufactured, for example, by adjusting the type and content ratio of each element, the formation conditions of the hafnium oxide film, or the crystallization annealing conditions compared to the manufacturing method of the semiconductor memory device of the first embodiment.

[0150] Next, the operation and effects of the semiconductor memory device according to the fourth embodiment will be described.

[0151] Figure 9 is an explanatory diagram of the operation and effects of the semiconductor memory device of the fourth embodiment. Figure 9 is a schematic cross-sectional view of a part of the charge storage layer of the fourth embodiment. Figure 9 corresponds to Figure 8. The arrows in Figure 9 indicate the polarization direction of each polarization domain.

[0152] Figure 9 shows the state in which a write voltage is applied between the semiconductor layer 10 and the gate electrode layer 18, and electrons are accumulated in the charge storage layer 14z. When accumulating electrons in the charge storage layer 14z, for example, electrons are injected from the semiconductor layer 10 to the charge storage layer 14z by applying a positive gate voltage to the semiconductor layer 10 from the gate electrode layer 18.

[0153] A gate voltage applied to the gate electrode layer 18 forms a plurality of first polarization domains 21a within the crystal grains 21. The first polarization domains 21a have ferroelectric properties and, upon application of the gate voltage, are polarized such that the semiconductor layer 10 side is positive and the gate electrode layer 18 side is negative.

[0154] As shown in Figure 9, electrons injected into the charge storage layer 14z are trapped in the domain wall 24 on the semiconductor layer 10 side of the first polarization domain 21a, and electrons are stored in the charge storage layer 14z.

[0155] According to the memory cell of the fourth embodiment, similar to the memory cell of the second embodiment, the decrease in the charge density stored in the charge storage layer 14z is suppressed, and the charge storage density of the charge storage layer 14z is improved.

[0156] Furthermore, in the charge storage layer 14z of the fourth embodiment, as shown in Figure 9, electrons are also trapped at the grain boundaries 22 between the crystal grains 21 and the matrix region 30. Therefore, the charge storage density of the charge storage layer 14z is further improved.

[0157] Furthermore, the inclusion of a second element in the charge storage layer 14z allows for a reduction in the grain size of the crystal grains 21. A smaller grain size makes it easier for the first polarization domain 21a to be fixed within the crystal grains 21. Consequently, the charge storage density of the charge storage layer 14z is further improved. Additionally, a smaller grain size of the crystal grains 21 increases the area of ​​the grain boundary 22 between the crystal grains 21 and the matrix region 30. Consequently, the charge storage density of the charge storage layer 14z is further improved.

[0158] From the viewpoint of increasing the charge storage density of the charge storage layer 14z, it is preferable that the charge storage layer 14z contains at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca). From the viewpoint of increasing the charge storage density of the charge storage layer 14z, it is preferable that the charge storage layer 14z contains at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si). From the viewpoint of increasing the charge storage density of the charge storage layer 14z, it is preferable that the charge storage layer 14z contains both the third and fourth elements.

[0159] The ratio of the atomic concentration of the second element to the atomic concentration of the first element in the crystal grain 21 is preferably 1% or more and 9% or less.

[0160] The median number of first polarization domains 21a contained within each of the multiple crystal grains 21 is preferably 3 to 100, and more preferably 5 to 20. From the viewpoint of increasing the charge storage density, the domain walls 24 separating each domain are preferably bent or have a surface shape with many irregularities rather than being linear or planar.

[0161] The crystal included in the matrix region 30 is, for example, a paraelectric material. The crystal included in the matrix region 30 is, for example, hafnium oxide or zirconium oxide of space group P21 / c (space group number 14).

[0162] The crystal included in the matrix region 30 may be, for example, a ferroelectric material. When the crystal included in the matrix region 30 is a ferroelectric material, it is preferable that the polarization direction in the crystal is aligned with the surface of the semiconductor layer 10.

[0163] As described above, according to the fourth embodiment, a semiconductor memory device that enables an improvement in the charge storage density of the charge storage layer can be realized.

[0164] (Fifth embodiment) The semiconductor memory device of the fifth embodiment comprises a plurality of gate electrode layers arranged in a first direction at a distance from each other, a semiconductor layer extending in the first direction, a first insulating layer provided between the semiconductor layer and at least one gate electrode layer among the plurality of gate electrode layers, a second insulating layer provided between the first insulating layer and the gate electrode layer, and space groups Pca21 (space group number 29), R3 (space group number 146), R3m (space group number 160), and Pmn21 (space group The semiconductor memory device of the fifth embodiment differs from the first to fourth embodiments in that it applies a structure similar to that of the memory cells of the first to fourth embodiments to a three-dimensional NAND flash memory. The fifth embodiment includes a charge storage layer comprising at least one first crystal having a first region having a space group selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one first element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O).

[0165] The semiconductor memory device of the fifth embodiment is a three-dimensional NAND flash memory. The memory cell of the semiconductor memory device of the fifth embodiment is a so-called charge-trap type memory cell.

[0166] Figure 10 is a circuit diagram of a memory cell array of a semiconductor memory device according to the fifth embodiment.

[0167] The memory cell array 300 of the third-dimensional NAND flash memory according to the fifth embodiment comprises a plurality of word lines WL, a common source line CSL, a source selection gate line SGS, a plurality of drain selection gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS, as shown in Figure 10. The word lines WL are an example of a gate electrode layer.

[0168] Multiple word lines WL are arranged in the z direction, spaced apart from each other. Multiple word lines WL are arranged stacked in the z direction. Multiple memory strings MS extend in the z direction. Multiple bit lines BL extend, for example, in the x direction.

[0169] Hereafter, we define the x-direction as the second direction, the y-direction as the third direction, and the z-direction as the first direction. The x-direction, y-direction, and z-direction are, for example, perpendicular to each other.

[0170] As shown in Figure 10, a memory string MS comprises a source selection transistor SST connected in series between a common source line CSL and a bit line BL, multiple memory cells, and a drain selection transistor SDT. By selecting one bit line BL and one drain selection gate line SGD, one memory string MS is selected, and by selecting one word line WL, one memory cell becomes selectable. The word line WL is the gate electrode of the memory cell transistor MT that constitutes the memory cell.

[0171] Figures 11(a) and 11(b) are schematic cross-sectional views of a memory cell array of a semiconductor memory device according to the fifth embodiment. Figures 11(a) and 11(b) show cross-sections of multiple memory cells in a single memory string MS enclosed by a dotted line, for example, within the memory cell array 300 of Figure 10.

[0172] Figure 11(a) is a yz cross-sectional view of the memory cell array 300. Figure 11(a) is the BB' cross-section of Figure 11(b). Figure 11(b) is an xy cross-sectional view of the memory cell array 300. Figure 11(b) is the AA' cross-section of Figure 11(a). In Figure 11(a), the area enclosed by the dashed line represents a single memory cell.

[0173] As shown in Figures 11(a) and 11(b), the memory cell array 300 comprises multiple word lines WL, semiconductor layers 50, multiple interlayer insulating layers 52, tunnel insulating layers 54, charge storage layers 56, block insulating layers 58, and core insulating regions 60. The structure does not necessarily have to be as shown in Figures 11(a) and 11(b), but it is preferable that the charge storage layer 56 of one memory cell enclosed by the dashed line in Figure 11(a) is a separate region rather than a continuous region with the charge storage layers 56 of adjacent memory cells in the z direction.

[0174] Multiple word lines WL and multiple interlayer insulating layers 52 constitute the laminate 70.

[0175] The word wire WL is an example of a gate electrode layer. The tunnel insulating layer 54 is an example of a first insulating layer. The block insulating layer 58 is an example of a second insulating layer.

[0176] The memory cell array 300 is provided, for example, on a semiconductor substrate (not shown). The semiconductor substrate has surfaces parallel to the x and y directions.

[0177] Word lines WL and interlayer insulating layers 52 are alternately stacked on a semiconductor substrate in the z direction. The word lines WL are spaced apart in the z direction. The word lines WL are repeatedly spaced apart from each other in the z direction. Multiple word lines WL and multiple interlayer insulating layers 52 constitute a laminate 70. The word lines WL function as control electrodes for memory cell transistors MT.

[0178] The word line WL is a plate-shaped conductor. The word line WL is, for example, a metal, metal nitride, metal carbide, or semiconductor. For example, the word line WL is tungsten (W). The thickness of the word line WL in the z direction is, for example, 5 nm to 20 nm.

[0179] The interlayer insulating layer 52 separates the word wires WL from each other. The interlayer insulating layer 52 electrically separates the word wires WL from each other.

[0180] The interlayer insulating layer 52 is, for example, an oxide, an oxynitride, or a nitride. The interlayer insulating layer 52 is, for example, silicon oxide. The thickness of the interlayer insulating layer 52 in the z direction is, for example, 5 nm or more and 20 nm or less.

[0181] The semiconductor layer 50 is provided within the laminate 70. The semiconductor layer 50 extends in the z direction. The semiconductor layer 50 extends in a direction perpendicular to the surface of the semiconductor substrate.

[0182] The semiconductor layer 50 is provided penetrating the laminate 70. The semiconductor layer 50 is surrounded by multiple word lines WL. The semiconductor layer 50 is, for example, cylindrical. The semiconductor layer 50 functions as a channel for the memory cell transistor MT.

[0183] The semiconductor layer 50 is, for example, a polycrystalline semiconductor. The semiconductor layer 50 is, for example, polycrystalline silicon.

[0184] The tunnel insulating layer 54 is provided between the semiconductor layer 50 and the word line WL. The tunnel insulating layer 54 is provided between the semiconductor layer 50 and at least one of the multiple word lines WL. The tunnel insulating layer 54 is provided between the semiconductor layer 50 and the charge storage layer 56.

[0185] The tunnel insulating layer 54 has the function of allowing charge to pass through in accordance with the voltage applied between the word line WL and the semiconductor layer 10.

[0186] The tunnel insulating layer 54 is, for example, an oxide, oxynitride, or nitride. The tunnel insulating layer 12 includes, for example, silicon oxide, silicon oxynitride, or silicon nitride. The thickness of the tunnel insulating layer 12 is, for example, 3 nm to 8 nm.

[0187] The charge storage layer 56 is provided between the tunnel insulating layer 54 and the block insulating layer 58. Adjacent charge storage layers 56 in the z direction are, for example, separated from each other. Adjacent charge storage layers 56 in the z direction are, for example, physically separated from each other. However, adjacent charge storage layers 56 in the z direction may be, for example, continuous.

[0188] The charge storage layer 56 has the function of trapping and storing electric charge. This charge is, for example, electrons. The threshold voltage of the memory cell transistor MT changes according to the amount of charge stored in the charge storage layer 56. By utilizing this change in threshold voltage, a single memory cell can store data.

[0189] For example, a change in the threshold voltage of a memory cell transistor (MT) changes the voltage at which the MT turns on. If we define a high threshold voltage state as data "0" and a low threshold voltage state as data "1", then the memory cell can store 1-bit data, either "0" or "1".

[0190] The charge storage layer 56 has the same configuration as the charge storage layer 14 of the first embodiment, the charge storage layer 14x of the second embodiment, the charge storage layer 14y of the third embodiment, or the charge storage layer 14z of the fourth embodiment.

[0191] The thickness of the charge storage layer 56 in the direction from the semiconductor layer 50 toward the word line WL is, for example, 2 nm to 10 nm.

[0192] The block insulating layer 58 is provided between the tunnel insulating layer 54 and the word wire WL. The block insulating layer 58 is provided between the charge storage layer 56 and the word wire WL. The block insulating layer 58 has the function of blocking the current flowing between the charge storage layer 56 and the word wire WL.

[0193] The block insulating layer 58 is, for example, an oxide, an oxynitride, or a nitride. The block insulating layer 58 includes, for example, silicon oxide or aluminum oxide.

[0194] The core insulating region 60 is provided within the laminate 70. The core insulating region 60 extends in the z direction. The core insulating region 60 penetrates the laminate 70. The core insulating region 60 is surrounded by the semiconductor layer 50. The core insulating region 60 is surrounded by multiple word lines WL. The core insulating region 60 is columnar. The core insulating region 60 is, for example, cylindrical.

[0195] The core insulating region 60 is, for example, an oxide, an oxynitride, or a nitride. The core insulating region 60 is, for example, silicon oxide.

[0196] The charge storage layer 56 of the 3D NAND flash memory in the fifth embodiment has a high charge storage density. Therefore, it is possible to thin the charge storage layer 56 and reduce the diameter of the memory holes. Thus, it is possible to miniaturize the memory cells and further increase the memory capacity.

[0197] As described above, according to the fifth embodiment, a semiconductor memory device that enables an improvement in the charge storage density of the charge storage layer can be realized, similar to the first to fourth embodiments. Furthermore, miniaturization of the memory cell becomes possible, and the memory capacity can be further increased.

[0198] In the first to fifth embodiments, the case in which the charge stored in the charge storage layer is electrons was described as an example, but the charge stored in the charge storage layer may also be holes.

[0199] In the fifth embodiment, the case in which the word line WL is a plate-shaped conductor was described as an example, but the shape of the word line WL is not necessarily limited to a plate shape. For example, the word line may be in the shape of a stripe extending in the y direction.

[0200] In the fifth embodiment, the case where the semiconductor layer 50 is cylindrical was described as an example, but the semiconductor layer 50 is not necessarily limited to a cylindrical shape. The semiconductor layer 50 may be cylindrical or rectangular prism-shaped, for example.

[0201] Furthermore, although the fifth embodiment described an example in which the semiconductor layer 50 extends in a direction perpendicular to the surface of the semiconductor substrate, the semiconductor layer 50 may also be configured to extend in a direction parallel to the surface of the semiconductor substrate, for example.

[0202] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0203] 10 Semiconductor Layers 12. Tunnel insulating layer (first insulating layer) 14 Charge storage layer 14x charge storage layer 14y charge storage layer 14z charge storage layer 16. Block insulating layer (second insulating layer) 18 Grid Unit Layer 20 crystal grains (first crystal) 20a First polarization domain (first region, polarization domain) 20b Second polarization domain (second region, polarization domain) 21 crystal grains (first crystal) 21a First polarization domain (first region, polarization domain) 21b Second polarization domain (third region, polarization domain) 50 Semiconductor Layers 54 Tunnel Insulation Layer (First Insulation Layer) 56 Charge storage layer 58 Block insulating layer (second insulating layer) WL Word line (gate electrode layer) 100 memory cells (semiconductor memory devices) 300 memory cell array (semiconductor memory device)

Claims

1. Semiconductor layer, The gate electrode layer, A first insulating layer is provided between the semiconductor layer and the gate electrode layer, A second insulating layer is provided between the first insulating layer and the gate electrode layer, A charge storage layer is provided between the first insulating layer and the second insulating layer, and includes at least one first crystal containing a first region having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31), and includes at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O), A semiconductor memory device equipped with the following features.

2. The semiconductor memory device according to claim 1, wherein the at least one first crystal further includes a second region containing one space group selected from the group consisting of P42 / nmc (space group number 137), space group Pbca (space group number 61), and Pbcm (space group number 57).

3. The semiconductor memory device according to claim 1, wherein the at least one first crystal further includes a third region different from the first region, having a space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31).

4. The semiconductor memory device according to claim 1, wherein the charge storage layer further comprises at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca).

5. The semiconductor memory device according to claim 1, wherein the charge storage layer further comprises at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si).

6. The semiconductor memory device according to claim 1, wherein the median major axis of at least one first crystal is 1 nm or more and 5 nm or less.

7. The semiconductor memory device according to claim 1, wherein the median of the major axis of at least one first crystal is less than or equal to half the thickness of the charge storage layer.

8. The semiconductor memory device according to claim 1, wherein the charge storage layer includes a matrix region surrounding the at least one first crystal.

9. The semiconductor memory device according to claim 8, wherein the matrix region is amorphous.

10. The semiconductor memory device according to claim 8, wherein the matrix region contains the second element, and the atomic concentration of the second element in the first crystal is lower than the atomic concentration of the second element in the matrix region.

11. The semiconductor memory device according to claim 1, wherein each of the at least one first crystals includes a plurality of polarization domains, and the median number of the plurality of polarization domains included in each of the at least one first crystals is 3 or more and 100 or less.

12. Multiple gate electrode layers arranged in a first direction, spaced apart from each other, A semiconductor layer extending in the first direction, A first insulating layer is provided between the semiconductor layer and at least one gate electrode layer among the plurality of gate electrode layers, A second insulating layer is provided between the first insulating layer and the at least one gate electrode layer, A charge storage layer is provided between the first insulating layer and the second insulating layer, and includes at least one first crystal containing a first region having one space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31), and includes at least one first element selected from the group consisting of hafnium (Hf) and zirconium (Zr), at least one second element selected from the group consisting of titanium (Ti), cerium (Ce), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), manganese (Mn), ruthenium (Ru), and tin (Sn), and oxygen (O), A semiconductor memory device equipped with the following features.

13. The semiconductor memory device according to claim 12, wherein the at least one first crystal further includes a second region containing one space group selected from the group consisting of P42 / nmc (space group number 137), space group Pbca (space group number 61), and Pbcm (space group number 57).

14. The semiconductor memory device according to claim 12, wherein the at least one first crystal comprises a space group selected from the group consisting of space group Pca21 (space group number 29), space group R3 (space group number 146), space group R3m (space group number 160), and Pmn21 (space group number 31), and further comprises a third region different from the first region.

15. The semiconductor memory device according to claim 12, wherein the charge storage layer further comprises at least one third element selected from the group consisting of barium (Ba), strontium (Sr), and calcium (Ca).

16. The semiconductor memory device according to claim 12, wherein the charge storage layer further comprises at least one fourth element selected from the group consisting of aluminum (Al) and silicon (Si).

17. The semiconductor memory device according to claim 12, wherein the median major axis of at least one first crystal is 1 nm or more and 5 nm or less.

18. The semiconductor memory device according to claim 12, wherein the median of the major axis of at least one first crystal is less than or equal to half the thickness of the charge storage layer.

19. The semiconductor memory device according to claim 12, wherein the charge storage layer includes a matrix region surrounding the at least one first crystal.

20. The semiconductor memory device according to claim 19, wherein the matrix region is amorphous.

21. The semiconductor memory device according to claim 19, wherein the matrix region contains the second element, and the atomic concentration of the second element in the first crystal is lower than the atomic concentration of the second element in the matrix region.

22. The semiconductor memory device according to claim 12, wherein each of the at least one first crystals includes a plurality of polarization domains, and the median number of the plurality of polarization domains included in each of the at least one first crystals is 3 or more and 100 or less.

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