Semiconductor devices and transmitting devices

Abstract

This circuit suppresses the increase in circuit size and power consumption of the circuit used to test the output signal without degrading the characteristics of the output signal. [Solution] The semiconductor device includes a first circuit that outputs a second signal, which is a serial signal, based on a first signal, which is a parallel or serial signal. The first circuit includes a second circuit that converts the first signal into a third signal, which is a serial signal; a third circuit that outputs the second signal corresponding to the third signal; a fourth circuit that outputs a fourth signal corresponding to the third signal in a predetermined operating mode; and a fifth circuit that outputs a fifth signal, which is a buffered version of the fourth signal.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a transmission device.

Background Art

[0002] M-PHY has attracted attention as a circuit for high-speed serial transmission inside electronic devices such as smartphones. M-PHY is a standard formulated by the MIPI (Mobile Industry Processor Interface) Alliance. In the M-PHY standard, the amplitude level of the output signal is limited for low-power operation.

[0003] A transmission device compliant with the M-PHY standard needs to provide an ILB (Internal Loop Back) test circuit for monitoring the data transmitted to the receiving device.

[0004] However, when the high-speed serial signal path of the transmission device is branched to connect the ILB test circuit, the characteristics of the serial signal output from the transmission device may deteriorate due to the influence of connecting the ILB test circuit. In addition, providing the ILB test circuit increases the circuit scale and power consumption of the transmission device. That is, in a transmission device provided with a circuit for testing an output signal, it is expected to perform the test of the output signal without deteriorating the characteristics of the output signal. Also, it is desired to be able to suppress an increase in the circuit scale and power consumption of the circuit for testing the output signal.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0006] Therefore, in one embodiment of the present invention, a semiconductor device and a transmitting device are provided that can suppress the increase in circuit size and power consumption of a circuit that tests an output signal without degrading the characteristics of the output signal. [Means for solving the problem]

[0007] To solve the above problems, according to one embodiment of the present invention, a first circuit is provided that outputs a second signal which is a serial signal based on a first signal which is a parallel signal or a serial signal, The first circuit is, A second circuit that converts the aforementioned first signal into a third signal which is a serial signal, A third circuit that outputs the second signal corresponding to the third signal, A fourth circuit that outputs a fourth signal corresponding to the third signal when in a predetermined operating mode, The system includes a fifth circuit that outputs a fifth signal obtained by buffering the fourth signal, Semiconductor equipment is provided. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing the schematic configuration of a communication system according to one embodiment. [Figure 2] A block diagram showing the schematic configuration of a transmitting device according to one embodiment. [Figure 3] A block diagram showing an example of the internal configuration of a PISO circuit. [Figure 4] A block diagram showing the internal configuration of the SST circuit. [Figure 5] A circuit diagram showing an example of the internal configuration of one SST unit. [Figure 6A] Figure 5 is a circuit diagram showing an example of the internal configuration of an SST driver. [Figure 6B] Figure 5 shows a circuit diagram illustrating an example of the internal configuration of a dummy driver. [Figure 7] A circuit diagram showing an example of the internal configuration of an SST unit in a comparative example. [Modes for carrying out the invention]

[0009] Embodiments of the semiconductor device and transmitting device will be described below with reference to the drawings. The following description will focus on the main components of the semiconductor device and transmitting device, but there may be components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0010] Figure 1 is a block diagram illustrating the schematic configuration of a communication system 1 according to one embodiment. The communication system 1 in Figure 1 comprises a transmitter 2, a receiver 3, and a differential transmission line 4. The transmitter 2 and receiver 3 perform high-speed serial transmission via the differential transmission line 4. More specifically, the transmitter 2 outputs a differential serial signal to the differential transmission line 4. The transmitter 2 has the function of converting a parallel signal into a differential serial signal. The differential serial signal output by the transmitter 2 is, for example, a signal encoded in a predetermined format. The encoding format is not limited, but in this specification, an example of encoding a binary signal with PAM (Pulse Amplitude Modulation) is described.

[0011] The receiver 3 receives the differential serial signal from the transmitter 2 and decodes it back into the original binary signal. The length of the differential transmission path 4 is not specified. The transmitter 2 and receiver 3 may be mounted on separate semiconductor chips or within the same semiconductor package.

[0012] FIG. 2 is a block diagram showing a schematic configuration of a transmission device 2 according to an embodiment. The transmission device 2 in FIG. 2 includes a PISO (Parallel In Serial Out) circuit 11, an SST (Source Serial Termination) circuit 12, a clock generation circuit 13, and a power supply circuit 14. These circuits may be implemented on a semiconductor chip. The SST circuit 12 constitutes a part of a semiconductor device according to an embodiment. The PISO circuit 11, the SST circuit 12, the clock generation circuit 13, and the power supply circuit 14 may be implemented on one semiconductor chip, or may be implemented on separate semiconductor chips respectively. The PISO circuit 11, the SST circuit 12, the clock generation circuit 13, and the power supply circuit 14 may be implemented as one semiconductor device, or may be implemented as separate semiconductor devices respectively.

[0013] The PISO circuit 11 outputs a first signal that is a parallel signal or a serial signal. For example, the PISO circuit 11 outputs a first signal obtained by converting a parallel signal into a serial signal. Also, for example, the PISO circuit 11 converts a sixth signal that is a parallel signal of a first bit string into a first signal that is a parallel signal of a second bit string having fewer bits than the first bit string and outputs it. In this specification, the PISO circuit 11 may be referred to as a conversion circuit.

[0014] The SST circuit 12 outputs a second signal that is a serial signal based on the first signal output from the PISO circuit 11. The second signal is, for example, a differential serial signal. In this specification, the SST circuit 12 may be referred to as a first circuit.

[0015] The clock generation circuit 13 generates a first clock signal CLK1 for synchronizing the first signal output from the PISO circuit 11 and a second clock signal CLK2 for synchronizing the second signal output from the SST circuit 12. The second clock signal CLK2 is, for example, a divided signal of the first clock signal CLK1.

[0016] As will be described later, the power supply circuit 14 controls the power supply voltage supplied to a part of the circuit of the SST circuit 12 according to the operation mode.

[0017] The power supply circuit 14 may be, for example, an LDO (Low Drop Out) regulator. The LDO regulator can operate even when the voltage difference between the input voltage and the output voltage is small, can suppress heat generation, and has excellent power efficiency.

[0018] FIG. 3 is a block diagram showing an example of the internal configuration of the PISO circuit 11. The PISO circuit 11 in FIG. 3 includes a FFE (Feed Forward Equalizer) processing unit 21 and two multiplexers 22a and 22b.

[0019] When converting the sixth signal, which is a parallel signal, into the first signal, the FFE processing unit 21 performs FFE processing to boost the gain of the Nyquist frequency regarding the data transmission band. The FFE processing is a process for compensating for waveform distortion and ISI (Inter-Symbol Interference) of the differential serial signal output from the transmission device 2.

[0020] The PISO circuit 11 outputs the first signal that has undergone FFE processing by the FFE processing unit 21. The first signal is, for example, a differential parallel signal or a serial signal. In this specification, an example in which the PISO circuit 11 outputs the first signal that is a differential parallel signal will be mainly described. For example, the PISO circuit 11 outputs M sets of differential first signals DP_n<1:0> and DN_n<1:0>. Here, M is an arbitrary integer of 2 or more. The PISO circuit 11 outputs M sets of first signals DP_n<0> and DN_n<0> at the same timing in synchronization with the first clock signal CLK1, and then outputs M sets of first signals DP_n<1> and DN_n<1> at a timing where the first clock signal CLK1 is shifted by a half cycle.

[0021] Figure 4 is a block diagram showing the internal configuration of the SST circuit 12. The SST circuit 12 has M SST units 23 connected in parallel and multiple impedance adjustment circuits (Imp.adj) 16. Each of the M SST units 23 is associated with M pairs of differential first signals DP_n<1:0> and DN_n<1:0> output from the PISO circuit 11. That is, the input signals MUXIN_P and MUXIN_N of each SST unit 23 are the corresponding pairs of first signals DP_n<1:0> and DN_n<1:0> output from the PISO circuit 11.

[0022] Each SST unit 23 outputs differential signals OUT_P and OUT_N, which are obtained by converting the corresponding pair of first signals DP_n<1:0> and DN_n<1:0> into serial signals.

[0023] The output nodes nd of the M SST units 23 are connected to each other. In this specification, the node to which the output nodes nd of the M SST units 23 are connected is called a common connection node n1. More precisely, of the differential signals OUT_P and OUT_N output from each SST unit 23, the output nodes nd_p that output one of the signals OUT_P are connected to each other, and the output nodes nd_n that output the other signal OUT_N are connected to each other. In this specification and drawings, output nodes nd_p and nd_n may be referred to as output node nd.

[0024] When the PISO circuit 11 outputs the PAM4 signal, any four first signals DP_n<1:0> and DN_n<1:0> are output in parallel. These four first signals DP_n<1:0> and DN_n<1:0> are input to a corresponding SST unit 23. Each SST unit 23 generates differential serial signals OUT_P and OUT_N. The voltage levels of the signals OUT_P and OUT_N generated in parallel by each SST unit 23 may differ. However, no problems arise even if the output node nd of each SST unit 23 is connected to the common connection node n1.

[0025] Thus, the SST circuit 12 outputs a second differential signal SSTOUT_P, SSTOUT_N, which is obtained by combining the M differential signals OUT_P, OUT_N generated in parallel by the M SST units 23 at the common connection node n1.

[0026] An impedance adjustment circuit 16 is connected to the common connection node n1. Although there is only one in Figure 5, multiple impedance adjustment circuits 16 may be connected to the common connection node n1. The number of impedance adjustment circuits 16 is arbitrary. Each of the multiple impedance adjustment circuits 16 has the same circuit configuration and the same output resistance. The impedance adjustment circuit 16 has a configuration that allows it to adjust the output impedance of the SST circuit 12.

[0027] Each of the M SST units 23 has a common circuit configuration. Figure 5 is a circuit diagram showing an example of the internal configuration of one SST unit 23. The SST unit 23 according to this embodiment has an ILB test circuit 31 connected on the high-speed serial transmission path. The ILB test circuit 31 is a circuit that monitors the serial signal that the transmitter 2 should transmit to the receiver 3 during ILB test mode. ILB test mode is an operating mode in which an ILB test is performed. The fifth signals ILBOP and ILBON output from the ILB test circuit 31 are received by the receiver 33 in the transmitter 2.

[0028] Each SST unit 23 receives a first enable signal ILB_EN to selectively select either ILB test mode or normal operation mode.

[0029] As shown in Figure 5, each of the M SST units 23 has a serial signal generation circuit 24 and a driver circuit 25. As shown in Figure 4, the output node nd of each SST unit 23 is connected to the common connection node n1 of the SST circuit 12. In Figure 5, the impedance adjustment circuit 16 connected to the output node n1 as shown in Figure 4 is omitted.

[0030] The serial signal generation circuit 24 converts the first signals DP_n<1:0> and DN_n<1:0> output from the PISO circuit 11 into differential serial signals, the third signals MUXOUT_P and MUXOUT_N, respectively, and outputs them. In this specification, the serial signal generation circuit 24 may be referred to as the second circuit.

[0031] The serial signal generation circuit 24 includes a first serial signal generator 24p for the first signal DP_n<1:0> and a second serial signal generator 24n for the first signal DN_n<1:0>.

[0032] The first serial signal generator 24p has a multiplexer 26p and a buffer circuit 27p. The multiplexer 26p serializes the first signal DP_n<1:0> in synchronization with the second clock signal CLK2. The buffer circuit 27p has multiple inverters IV1~IV3 connected in cascade and inverts the logic of the serial signal output from the multiplexer 26p multiple times. Power supply voltage VDD1 is supplied to the multiple inverters IV1~IV3. The number of inverter stages in the buffer circuit 27p is arbitrary. The output node of the buffer circuit 27p outputs a third signal MUXOUT_P, which is the serialized first signal DP_n<1:0>.

[0033] The second serial signal generator 24n has a multiplexer 26n and a buffer circuit 27n. The multiplexer 26n serializes the first signal DN_n<1:0> in synchronization with the second clock signal CLK2. The buffer circuit 27n has multiple inverters IV4~IV6 connected in cascade and inverts the logic of the serial signal output from the multiplexer 26n multiple times. Power supply voltage VDD1 is supplied to the multiple inverters IV4~IV6. The number of inverter stages in the buffer circuit 27n is arbitrary. The output node of the buffer circuit 27n outputs a third signal MUXOUT_N, which is the serialized first signal DN_n<1:0>.

[0034] The driver circuit 25 has multiple SST drivers 28 and dummy drivers 29. Figure 5 shows an example in which the driver circuit 25 has two SST drivers 28 and two dummy drivers 29, but this is just one example. The number of SST drivers 28 and dummy drivers 29 in the driver circuit 25 is arbitrary. For example, the driver circuit 25 may have multiple (e.g., four) SST drivers 28 without any dummy drivers 29. Alternatively, the driver circuit 25 may have three SST drivers 28 and one dummy driver 29.

[0035] The driver circuit 25 outputs signals OUT_P and OUT_N corresponding to the third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24. Signals OUT_P and OUT_N are output from the SST driver 28 within the driver circuit 25. If the driver circuit 25 has multiple SST drivers 28, the output nodes of each SST driver 28 are connected to output nodes nd_p and nd_n, and signals OUT_P and OUT_N are output from these output nodes nd_p and nd_n.

[0036] The SST driver 28 outputs differential serial signals OUT_p and OUT_n, which correspond to the differential third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24. In this specification, the SST driver 28 may be referred to as the third circuit.

[0037] An ILB buffer 30 is connected to the output node of a dummy driver 29 included in the driver circuit 25. The dummy driver 29 and the ILB buffer 30 constitute an ILB test circuit 31. The dummy driver 29 and the ILB buffer 30 that constitute the ILB test circuit 31 output fifth signals ILBOP and ILBON, which correspond to the second signal to be transmitted to the receiving device 3, when in ILB test mode. The fifth signals ILBOP and ILBON are generated based on the third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24.

[0038] The dummy driver 29 outputs a fourth differential serial signal corresponding to the differential third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24 when in a predetermined operating mode (e.g., ILB test mode). In this specification, the dummy driver 29 may be referred to as the fourth circuit.

[0039] An ILB buffer 30 is connected to the output node of the dummy driver 29. The ILB buffer 30 outputs differential fifth signals ILBOP and ILBON, which are obtained by buffering the differential fourth signal. In this specification, the ILB buffer 30 may be referred to as the fifth circuit.

[0040] The dummy driver 29 has a circuit configuration similar to that of the SST driver 28. More specifically, the conductivity type and size of at least some of the transistors constituting the dummy driver 29 are the same as those of the transistors in the SST driver 28.

[0041] Not all SST units 23 need to have an ILB test circuit 31. Some SST units 23 may not have a dummy driver 29 in their driver circuit 25. SST units 23 without a dummy driver 29 do not have an ILB test circuit 31. Also, not all output nodes of the dummy drivers 29 need to be connected to an ILB buffer 30. In other words, at least some of the multiple SSD units 23 provided in the SST circuit 12 have an ILB test circuit 31.

[0042] Figure 6A is a circuit diagram showing an example of the internal configuration of the SST driver 28 shown in Figure 5. The SST driver 28 shown in Figure 6A has PMOS transistors Q1, Q2 and NMOS transistors Q3, Q4 cascode-connected between a power supply voltage node to which the power supply voltage VDD2 is supplied and a ground voltage node, PMOS transistors Q5, Q6 and NMOS transistors Q7, Q8 cascode-connected between the power supply voltage node and the ground voltage node, and resistors R1, R2. The power supply voltage node is a node for supplying the power supply potential to the SST driver 28 and the dummy driver 29. The ground voltage node is a node for supplying the reference potential when the SST driver 28 and the dummy driver 29 are operating. The power supply voltage VDD2 can be set to a potential independent of the power supply voltage VDD1 supplied to the multiple inverters IV1 to IV6 of the serial signal generation circuit 24.

[0043] The second enable signal HZ_EN is input to both gates of transistors Q1 and Q5. The third signal MUXOUT_P, output from the serial signal generation circuit 24, is input to both gates of transistors Q2 and Q3. The drain of transistor Q1 and the source of transistor Q2 are connected to internal node n3. The drains of both transistors Q2 and Q3 are connected to one end of resistor R1. The other end of resistor R1 is connected to output node nd_p of SST unit 23.

[0044] The inverted signal HZ_ENB of the second enable signal is input to both gates of transistors Q4 and Q8. The third signal MUXOUT_N, output from the serial signal generation circuit 24, is input to both gates of transistors Q6 and Q7. The drain of transistor Q5 and the source of transistor Q6 are connected to internal node n4. The drains of both transistors Q6 and Q7 are connected to one end of resistor R2. The other end of resistor R2 is connected to output node nd_n of SST unit 23.

[0045] When the second enable signal HZ_EN is at a low level (HZ_ENB is at a high level), transistors Q1, Q4, Q5, and Q8 turn on, transistors Q2 and Q3 function as inverters, and transistors Q6 and Q7 also function as inverters. At this time, signals OUT_P and OUT_N corresponding to the third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24 are output from the output nodes nd_p and nd_n of the SST unit 23.

[0046] When the second enable signal HZ_EN is at a high level (HZ_ENB is at a low level), the output nodes nd_p and nd_n of the SST unit 23 become high impedance.

[0047] The resistor R1 connected to the drains of transistors Q2 and Q3, and the resistor R2 connected to the drains of transistors Q6 and Q7, have the same resistance value. By adjusting the resistance values ​​of resistors R1 and R2, the output impedance of the SST unit 23 can be adjusted.

[0048] Figure 6B is a circuit diagram showing an example of the internal configuration of the dummy driver 29 shown in Figure 5. The dummy driver 29 shown in Figure 6B has a circuit configuration similar to the SST driver 28 shown in Figure 6A. Specifically, the dummy driver 29 shown in Figure 6B includes PMOS transistors Q11 and Q12, NMOS transistors Q13 and Q14, PMOS transistors Q15, Q16, and Q17, NMOS transistors Q18 and Q19, and PMOS transistor Q20.

[0049] The sources of transistors Q11 and Q16 are connected to the power supply voltage node, and both drains are connected to the internal node n2. Transistors Q12 to Q14 are cascode-connected between the power supply voltage node and the ground voltage node. The gates of transistors Q12 and Q13 are input to the third signal MUXOUT_P output from the serial signal generation circuit 24.

[0050] The source of transistor Q15 is connected to the power supply voltage node, and its drain is connected to the drains of both transistors Q12 and Q13. The gates of transistors Q14 and Q15 are input to the first enable signal ILB_EN. The gates of transistors Q11 and Q16 are input to the second enable signal HZ_EN.

[0051] Transistors Q17 to Q19 are cascode-connected between the power supply voltage node and the ground voltage node. The third signal MUXOUT_N, output from the serial signal generation circuit 24, is input to both gates of transistors Q17 and Q18.

[0052] The source of transistor Q20 is connected to the power supply voltage node, and its drain is connected to the drains of both transistors Q17 and Q18. The gates of transistors Q19 and Q20 are input to the first enable signal ILB_EN.

[0053] The internal node n2, to which both drains of transistors Q11 and Q16 are connected, becomes the power supply voltage VDD2 when the second enable signal HZ_EN is low level, and becomes high impedance when the second enable signal HZ_EN is high level. Thus, the internal node n2 of the dummy driver 29 is at the same potential as the internal nodes (first internal nodes) n3 and n4 of the SST driver 28 shown in Figure 6A, to which the drains of transistors Q1 and Q5 are connected. The internal nodes n3 and n4 of the SST driver 28 and the internal node (second internal node) n2 of the dummy driver 29 are electrically connected via wiring patterns, etc. By providing the dummy driver 29, the output impedance of the SST unit 23 can be adjusted. The SST circuit 12 has M SST units 23, and by providing the dummy driver 29 on at least some of the M SST units 23, the output impedance of the M SST units 23 can be made equal.

[0054] When the second enable signal HZ_EN is at a low level (HZ_ENB is at a high level), the first enable signal ILB_EN is controlled to be at a low level. In this case, it is the normal operating mode, and transistors Q14 and Q19 are turned off and transistors Q15 and Q20 are turned on, so the output node of the dummy driver 29 is at a level corresponding to the power supply voltage VDD2.

[0055] In normal operation mode, the second enable signal HZ_EN is at a low level (HZ_ENB is at a high level), and the SST driver 28 shown in Figure 6A outputs signals OUT_P and OUT_N corresponding to the third signals MUXOUT_P and MUXOUT_N. Since the internal nodes n2 to n4 of the SST driver 28 and the dummy driver 29 are electrically connected to each other, the supply of output levels corresponding to the power supply voltage VDD2 for signals OUT_P and OUT_N can be enhanced. In the dummy driver 29, the node between transistors Q13 and Q14 and the node between transistors Q18 and Q19 may be connected separately as node n2. The nodes connected to the drains of the transistors Q14 and Q19 are connected to the nodes between transistors Q3 and Q4 and the node between transistors Q7 and Q8 in the SST driver 28. With this configuration, the supply of output levels corresponding to the ground potential for signals OUT_P and OUT_N can be enhanced.

[0056] When the second enable signal HZ_EN is high, the first enable signal ILB_EN is controlled to be high. In this case, it is ILB test mode, and in the dummy driver 29, transistors Q14 and Q19 are turned on, and transistors Q15 and Q20 are turned off. Therefore, Q12 and Q13 function as inverters, and Q17 and Q18 also function as inverters. As a result, the dummy driver 29 outputs a fourth signal corresponding to the third signals MUXOUT_P and MUXOUT_N output from the serial signal generation circuit 24.

[0057] The power supply circuit 14 switches the voltage level of the power supply voltage VDD2 supplied to the driver circuit 25 between normal operation mode and ILB test mode. In normal operation mode, the voltage level of the power supply voltage VDD2 is lower than in ILB test mode. This reduces power consumption during high-speed serial transmission. In ILB test mode, increasing the voltage level of the power supply voltage VDD2 makes the fifth signals ILBOP and IOBON received by the receiver 33 of the transmitter 2 less susceptible to noise, thereby improving the reliability of the ILB test.

[0058] More specifically, in ILB test mode, the power supply circuit 14 sets the power supply voltage VDD1 of the serial signal generation circuit 24 and the power supply voltage VDD2 of the driver circuit 25 to the same voltage level. On the other hand, in normal operation mode, the power supply circuit 14 lowers the power supply voltage VDD2 of the driver circuit 25 compared to the power supply voltage VDD1 of the serial signal generation circuit 24.

[0059] Figure 7 is a circuit diagram showing an example of the internal configuration of an SST unit 230 according to one comparative example. In Figure 7, circuit elements common to Figure 5 are given the same reference numerals, and the differences will be explained below. In the SST unit 230 according to one comparative example, the ILB test circuit 310 is not located inside the driver circuit 25, but is provided on a path branched from the serial signal generation circuit 24.

[0060] More specifically, the ILB test circuit 310 in one comparative example includes a logic circuit 32 and an ILB buffer 30. The logic circuit 32 is connected to the output node of inverter IV2 in buffer circuit 27p and the output node of inverter IV5 in buffer circuit 27n in the serial signal generation circuit 24.

[0061] The logic circuit 32 includes a first AND circuit 32p that generates a logical AND signal between the output signal of inverter IV2 and the first enable signal ILB_EN, and a second AND circuit 32n that generates a logical AND signal between the output signal of inverter IV5 and the first enable signal ILB_EN. The ILB buffer 30 buffers the output signals of the first AND circuit 32p and the second AND circuit 32n.

[0062] In one comparative example, an ILB test circuit 310 having a logic circuit 32 is provided separately from the driver circuit 25. As a result, the circuit size of the SST unit 230 in this comparative example is larger than that of the SST unit 23 in this embodiment, and the current consumption also increases.

[0063] Furthermore, in one comparative example, branch paths are provided to the buffer circuits 27p and 27n of the serial signal generation circuit 24 and connected to the ILB test circuit 310. This increases the load on the buffer circuits 27p and 27n, which may degrade the characteristics of the serial signal transmitted from the buffer circuits 27p and 27n to the driver circuit 25.

[0064] Furthermore, in one comparative example, since a branch path for the ILB test circuit 310 is provided in the serial signal generation circuit 24, it is not possible to monitor the high-speed serial transmission path on the driver circuit 25 side from the connection node of the branch path in the serial signal generation circuit 24. Therefore, the monitorable range is narrower compared to this embodiment.

[0065] Thus, in this embodiment, the ILB buffer 30 is connected to the output node of the dummy driver 29 provided in the driver circuit 25 within the SST circuit 12, and the dummy driver 29 and the ILB buffer 30 constitute the ILB test circuit 31. This reduces the circuit size of the ILB test circuit 31 and reduces power consumption.

[0066] Furthermore, since the ILB test circuit 31 according to this embodiment is located on a path different from the high-speed serial transmission path, there is no degradation of the second signals SSTOUT_P and SSTOUT_N, which are serial signals transmitted from the SST circuit 12 to the receiving device 3.

[0067] Furthermore, since the ILB test circuit 31 according to this embodiment is located on the output node side of the transmitter 2, it is possible to monitor almost the entire high-speed serial transmission path within the transmitter 2, thereby improving the accuracy of the monitoring.

[0068] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0069] [Note] [Item 1] It comprises a first circuit that outputs a second signal, which is a serial signal, based on a first signal, which is a parallel signal or a serial signal. The first circuit is, A second circuit that converts the aforementioned first signal into a third signal which is a serial signal, A third circuit that outputs the second signal corresponding to the third signal, A fourth circuit that outputs a fourth signal corresponding to the third signal when in a predetermined operating mode, The system includes a fifth circuit that outputs a fifth signal obtained by buffering the fourth signal, Semiconductor equipment. [Item 2] The fourth circuit has the same circuit configuration as a part of the third circuit. Semiconductor device as described in item 1. [Item 3] The system includes a receiving unit that receives the aforementioned fifth signal, Semiconductor device as described in item 1 or 2. [Item 4] The fourth circuit performs an ILB (Internal Loop Back) test in the predetermined operating mode. A semiconductor device as described in any one of items 1 through 3. [Item 5] The fourth circuit switches whether or not it is in the predetermined operating mode based on the logic of the first enable signal. A semiconductor device as described in any one of items 1 through 4. [Item 6] The fourth circuit outputs a fixed voltage level when the first enable signal is of first logic, and outputs the fourth signal corresponding to the third signal when the first enable signal is of second logic. Semiconductor device as described in item 5. [Item 7] The first circuit has a plurality of the third circuits, The fourth circuit is provided in a second number equal to or less than the first number of the plurality of third circuits, and is configured to match the output impedance of the plurality of third circuits when the first enable signal is first logic. Semiconductor device as described in item 6. [Item 8] The plurality of resistors are connected to the output nodes of the plurality of third circuits, Semiconductor device as described in item 7. [Item 9] The system includes a power supply circuit that, when the first enable signal is the second logic, supplies a power supply voltage at a higher voltage level than when the first logic is enabled to the third and fourth circuits. A semiconductor device as described in any one of items 6 through 8. [Item 10] The power supply circuit supplies the second circuit, the third circuit, and the fourth circuit with a power supply voltage of the same voltage level. Semiconductor device as described in item 9. [Item 11] The power supply circuit, when the first enable signal is the second logic, supplies power supply voltages of the same voltage level to the second circuit, the third circuit, and the fourth circuit, and when the first enable signal is the first logic, sets the power supply voltage supplied to the third circuit and the fourth circuit to be higher than the power supply voltage supplied to the second circuit. Semiconductor device as described in item 9 or 10. [Item 12] The third circuit has a first internal node that becomes high impedance when the first enable signal is the second logic and the second enable signal is a predetermined logic, The fourth circuit has a second internal node that becomes high impedance when the second enable signal is of a predetermined logic, The first internal node and the second internal node are electrically connected. A semiconductor device as described in any one of items 6 through 11. [Item 13] The output node of the third circuit becomes high impedance when the first enable signal is the second logic and the second enable signal is the predetermined logic. The output node of the fourth circuit outputs a fourth signal corresponding to the third signal when the first enable signal is the second logic and the third enable signal is a predetermined logic. Semiconductor device as described in item 12. [Item 14] If the first circuit includes two or more of the fourth circuits, the fifth circuit is connected to at least one of the fourth circuits. A semiconductor device as described in any one of items 1 through 13. [Item 15] The circuit comprises multiple of the above-mentioned first circuits, The plurality of first circuits include two or more first circuits, each having a different number of third circuits and a different number of fourth circuits. A semiconductor device as described in any one of items 1 through 14. [Item 16] The first signal, the second signal, the third signal, and the fourth signal are differential signals. A semiconductor device as described in any one of items 1 through 15. [Item 17] A conversion circuit that outputs a first signal which is a parallel or serial signal, A semiconductor device described in any one of items 1 to 16 that performs processing based on the first signal, Transmitter. [Item 18] The conversion circuit converts the sixth signal, which is a parallel signal of the first bit sequence, into the first signal, which is a parallel signal of the second bit sequence with fewer bits than the first bit sequence, and outputs it. The transmitting device described in item 17. [Item 19] The conversion circuit outputs the first signal which has undergone FFE (Feed Forward Equalizer) processing on the parallel signal of the first bit sequence. The transmitting device described in item 18. [Explanation of Symbols]

[0070] 1 Communication system, 2 Transmitter, 3 Receiver, 4 Differential transmission line, 11 PISO circuit, 12 SST circuit, 13 Clock generation circuit, 14 Power supply circuit, 15 Semiconductor device, 16 Impedance adjustment circuit, 21 FFE processing unit, 22a Multiplexer, 22b Multiplexer, 23 SST unit, 24 Serial signal generation circuit, 24n Second serial signal generator, 24p First serial signal generator, 25 Driver circuit, 26n Multiplexer, 26p Multiplexer, 27n Buffer circuit, 27p Buffer circuit, 28 SST driver, 29 Dummy driver, 30 ILB buffer, 31 ILB test circuit, 32 Logic circuit, 32n Second AND circuit, 32p First AND circuit, 33 Receiver, 230 SST unit, 310 ILB test circuit

Claims

1. The system includes a first circuit that outputs a second signal, which is a serial signal, based on a first signal, which is a parallel or serial signal. The first circuit is, A second circuit that converts the aforementioned first signal into a third signal which is a serial signal, A third circuit that outputs the second signal corresponding to the third signal, A fourth circuit that outputs a fourth signal corresponding to the third signal when in a predetermined operating mode, The system includes a fifth circuit that outputs a fifth signal obtained by buffering the fourth signal, Semiconductor equipment.

2. The fourth circuit has the same circuit configuration as a part of the third circuit. The semiconductor device according to claim 1.

3. The fourth circuit switches whether or not it is in the predetermined operating mode based on the logic of the first enable signal. The semiconductor device according to claim 1.

4. The fourth circuit outputs a fixed voltage level when the first enable signal is of first logic, and outputs the fourth signal corresponding to the third signal when the first enable signal is of second logic. The semiconductor device according to claim 3.

5. The system includes a power supply circuit that, when the first enable signal is the second logic, supplies a power supply voltage at a higher voltage level than when the first logic is present to the third and fourth circuits. The semiconductor device according to claim 4.

6. The third circuit has a first internal node that becomes high impedance when the first enable signal is the second logic and the second enable signal is a predetermined logic, The fourth circuit has a second internal node that becomes high impedance when the second enable signal is of a predetermined logic, The first internal node and the second internal node are electrically connected. The semiconductor device according to claim 4.

7. A conversion circuit that outputs a first signal which is a parallel or serial signal, A semiconductor device according to any one of claims 1 to 6 that performs processing based on the first signal, Transmitter.

8. The conversion circuit converts the sixth signal, which is a parallel signal of the first bit sequence, into the first signal, which is a parallel signal of the second bit sequence with fewer bits than the first bit sequence, and outputs it. The transmitting device according to claim 7.

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