Semiconductor device and method for manufacturing the same

Abstract

We provide a semiconductor device with a trench structure that incorporates various semiconductor layers. [Solution] A method for manufacturing a semiconductor device includes the steps of: preparing a structure including a semiconductor portion in which a trench extending along a first direction is formed; forming a BSG film on the upper surface of the structure and the surface of the trench; forming a resist pattern on the structure and performing lithography; removing the BSG film in areas other than where the resist pattern remains; and performing an annealing process on the structure including the remaining BSG film.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method of manufacturing the same.

Background Art

[0002] Techniques related to semiconductor devices having a trench structure such as MOS (metal-oxide-semiconductor) have been developed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of embodiments of the present invention is to provide a semiconductor device having a trench structure including various semiconductor layers and a method of manufacturing the same.

Means for Solving the Problems

[0005] A method of manufacturing a semiconductor device according to an embodiment includes a step of preparing a structure including a semiconductor part in which a trench extending along a first direction is formed, a step of forming a BSG film on an upper surface of the structure and a surface of the trench, a step of forming a resist pattern on the structure and performing lithography, a step of removing the BSG film except at a location where the resist pattern remains, and a step of performing an annealing process on the structure including the remaining BSG film.

[0006] A semiconductor device according to an embodiment can realize a trench structure including various semiconductor layers.

Brief Description of the Drawings

[0007] [Figure 1]This is a plan view of a semiconductor device according to an embodiment. [Figure 2] This is a flowchart showing the process for manufacturing a semiconductor device according to the first embodiment. [Figure 3] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Modification 1. [Figure 9] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the modified example 1. [Figure 10] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the modified example 1. [Figure 11] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to modified example 2. [Figure 12] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to modified example 2. [Figure 13] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to modified example 2. [Figure 14] This is a flowchart showing the process for manufacturing a semiconductor device according to the second embodiment. [Figure 15] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 16] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 17] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments do not limit the present invention. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, the same elements as those described above with respect to the previous drawings are denoted by the same reference numerals, and detailed descriptions thereof are omitted as appropriate.

[0009] In the description of the embodiments, an XYZ orthogonal coordinate system is used. That is, the direction from the drain electrode 41 to the source electrode 42 is defined as the Z direction. Two directions that are perpendicular to the Z direction and orthogonal to each other are defined as the X direction and the Y direction.

[0010] In addition, with regard to terms used in this specification for specifying shapes, geometric conditions, and their degrees, such as "parallel", "same", etc., they are not bound by a strict meaning and are interpreted to include a range where similar functions can be expected.

[0011] In the following description, n + 、n - and p + 、The notations of p represent the relative levels of impurity concentrations in each conduction type. That is, the notation with a "+" indicates that the impurity concentration is relatively higher than the notation without either "+" or "-", and the notation with a "-" indicates that the impurity concentration is relatively lower than the notation without either. When both p-type impurities and n-type impurities are included in each region, these notations represent the relative levels of the net impurity concentration after compensation of these impurities. For each of the embodiments described below, the p-type and n-type of each semiconductor region may be inverted to implement each embodiment.

[0012] <1. First Embodiment> (1.1. Structure of Semiconductor Device 100) Referring to FIG. 1, the semiconductor device 100 according to the present embodiment will be described. Figure 1 is a plan view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 is, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). As shown in Figure 1, the semiconductor device 100 includes a semiconductor portion 10, a drain electrode 41 as a first electrode, and a source electrode 42 as a second electrode. The semiconductor device 100 includes a cell portion, which is a region where current mainly flows when the power is turned on and functions as a MOSFET, for example, and a termination portion provided around the cell portion.

[0013] The semiconductor portion 10 includes, for example, silicon and is provided between the drain electrode 41 and the source electrode 42. The semiconductor portion 10 includes a first semiconductor layer 10a of a first conductivity type, a second semiconductor layer 10b of a second conductivity type, a third semiconductor layer 10c of a first conductivity type, a fourth semiconductor layer 10d of a second conductivity type, a fifth semiconductor layer 10e of a second conductivity type, and a sixth semiconductor layer 10f of a second conductivity type. Hereinafter, as an example, the first conductivity type will be described as n-type and the second conductivity type as p-type, but it is not limited to this.

[0014] Multiple trenches TR extending along the X direction are formed in the semiconductor portion 10. The trenches TR are formed in the shape of elongated grooves with a rectangular cross-section, for example, but are not limited to this example. A gate electrode 12 and an insulating portion 30 are arranged within the trenches TR.

[0015] The first semiconductor layer 10a is, for example, an n placed on the upper surface of the drain electrode 41. + Shape drift layer and n + n placed on the upper surface of the shape drift layer - It includes a shape drift layer. The first semiconductor layer 10a extends between the drain electrode 41 and the source electrode 42.

[0016] The second semiconductor layer 10b is, for example, a p-type base layer. The second semiconductor layer 10b is provided on the first semiconductor layer 10a.

[0017] The third semiconductor layer 10c is, for example, n +This is a source layer. The third semiconductor layer 10c is partially provided on the second semiconductor layer 10b. The third semiconductor layer 10c is electrically connected to the source electrode 42.

[0018] The fourth semiconductor layer 10d is, for example, p + This is a contact layer. The fourth semiconductor layer 10d is partially provided on the second semiconductor layer 10b. The fourth semiconductor layer 10d contains a second conductivity type impurity at a higher concentration than the second conductivity type impurity in the second semiconductor layer 10b. The source electrode 42 is electrically connected to the second semiconductor layer 10b, the third semiconductor layer 10c, and the fourth semiconductor layer 10d via the source contact 51.

[0019] The fifth semiconductor layer 10e is, for example, a p-type guard ring layer. The fifth semiconductor layer 10e is provided around the trench TR provided at the terminal end. The fifth semiconductor layer 10e is provided extending from around the upper end to around the lower end of the trench TR.

[0020] The sixth semiconductor layer 10f is, for example, a p-type deep layer. The sixth semiconductor layer 10f is provided around the lower end of the trench TR provided in the cell portion. The height of the p-type deep layer (i.e., the length in the Z direction, and so on hereafter) can be set as appropriate.

[0021] The gate electrode 12 is provided so as to extend in the X direction within the trench TR in the cell portion. The gate electrode 12 may, for example, include polysilicon, which is silicon mixed with impurities.

[0022] The insulating portion 30 contains silicon oxide (SiO2) and is provided inside the trench TR and on top of the semiconductor portion 10.

[0023] (1.2. Method for manufacturing semiconductor device 100) A method for manufacturing the semiconductor device 100 will be described with reference to Figures 2 to 7. Figure 2 is a flowchart showing the process for manufacturing a semiconductor device according to the first embodiment. Figures 3 to 7 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiment. As shown in Figure 2, steps S110 to S160 are performed in the manufacturing method of the semiconductor device 100.

[0024] In step S110, as shown in Figure 3, a structure 20 with trenches TR formed in the semiconductor portion 21 is prepared as a preparation step. An SiO2 film 22 and a SiN film 23 are placed on top of the structure 20. The SiO2 film 22 and the SiN film 23 function as mask materials when forming trenches TR in the semiconductor portion 21.

[0025] In step S120, a BSG film formation process is performed as shown in Figure 4. In the BSG film formation process, a BSG (Borosilicate Glass) film 24 is formed on the upper surface of the structure 20 and the surface of the trench TR, for example, by the CVD (Chemical Vapor Deposition) method. Note that the formation of the BSG film 24 may be carried out using known techniques other than CVD.

[0026] In step S130, as shown in Figure 5, a lithography process is performed in which a negative resist 25a is applied to the structure 20 to form a resist pattern, and then exposed to light L using a mask M to form the desired pattern, followed by development. As a result, the negative resist 25a that has been cured by exposure remains in the trench TR.

[0027] In step S140, as shown in Figure 6, the negative resist 25a remaining in the trench TR is removed by CDE (Chemical Dry Etching) as an etching process. Furthermore, wet etching is performed on the BSG film 24 on the upper surface of the structure 20 and the surface of the trench TR. This removes the BSG film 24 in areas other than where negative resist 25a remains in the trench TR. Subsequently, the negative resist 25a remaining in the trench TR is removed.

[0028] In step S150, an annealing process is performed as shown in Figure 7. In the annealing process, first, a TEOS (Tetra Ethoxy Silane) film 26 is formed on the structure 20 as a protective film, for example by the CVD method. Next, the structure 20 is subjected to heat treatment. The heat treatment conditions may include, for example, maintaining a temperature of 900°C to 1200°C for 10 to 20 minutes. As a result, boron is solid-phase diffused from the remaining BSG film, and a P layer 27 is formed around the trench TR provided at the end. As mentioned above, forming the TEOS film 26 as a protective film prevents boron from solid-phase diffused into the exposed silicon layer, but the formation of the TEOS film 26 is not required.

[0029] In step S160, as a post-processing step, the BSG film 24 and TEOS film 26 are removed by wet etching, and an oxide film as an insulating portion 30 is formed on the upper surface of the structure 20 and the surface of the trench TR. A polysilicon layer is also placed in the trench TR to form the gate electrode 12. Furthermore, a second semiconductor layer 10b, a third semiconductor layer 10c, and a fourth semiconductor layer 10d are provided by impurity implantation. In addition, a drain electrode 41 is provided on the lower surface of the semiconductor portion 10, and a source electrode 42 and a source contact 51 are provided on the upper surface of the semiconductor portion 10. Thus, the semiconductor device 100 is manufactured.

[0030] (1.3.Summary) Thus, in the semiconductor device 100 of this embodiment, after forming trenches TR in the structure 20, P-layer regions can be formed by solid-phase diffusion. This makes it possible to simultaneously form P-layer regions of different heights. Furthermore, by forming the P-layer by solid-phase diffusion, epitaxial growth and ion implantation can be omitted, and crystal defects caused by ion implantation damage can be suppressed. In addition, with ion implantation, when the ion beam passes through the opening of the resist pattern, if the width of the opening (i.e., the length in the X or Y direction) is narrow, the ion beam is more likely to collide with the edge of the resist pattern, causing the beam to scatter and lose energy before the ions reach the silicon wafer, resulting in the problem of shallow implantation depth. Therefore, with ion implantation, it is necessary to ensure the width of the resist pattern, but in this embodiment, by using solid-phase diffusion, the width of the trench TR formed by trench RIE can be narrowed, and as a result, the width of the P-layer pattern diffused from the trench can be narrowed. Furthermore, the P-layer formed around the bottom of the trench TR mitigates the concentration of the electric field on the oxide film at the bottom of the trench TR. Furthermore, the formation of a P layer around the bottom of the trench TR provides a rate-increasing effect, suppressing the breakdown of the oxide film.

[0031] (1.4. Variation 1) Referring to Figures 8 to 10, the semiconductor device 100 according to this embodiment will be described. Figures 8 to 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to Modification 1. In Modification 1, the lithography process in step S130 differs from the embodiment described above. The differences will be explained below.

[0032] In the lithography step S130, as shown in Figure 8, a positive resist 25b is applied to the structure 20 to form a resist pattern, and it is exposed to light L using a mask M to form the desired pattern, and then developed. As a result, the positive resist 25b, excluding the parts dissolved by exposure, remains in the trench TR.

[0033] In the etching process of step S140, as shown in Figure 9, the positive resist 25b remaining in the trench TR is recessed by CDE (Chemical Dry Etching). This allows the positive resist 25b remaining in multiple trench TRs to be at different heights depending on the trench TR. Subsequently, wet etching is performed on the BSG film 24 on the upper surface of the structure 20 and the surface of the trench TR. This removes the BSG film 24 in areas other than where positive resist 25b remains in the trench TR. After that, the positive resist 25b remaining in the trench TR is removed.

[0034] In the annealing process of step S150, as shown in Figure 10, a TEOS film 26 is formed as a protective film, similar to the embodiment described above, and the structure 20 is subjected to heat treatment. As a result, boron is diffused in solid phase from the remaining BSG film, and a P layer 27 is formed around the trenches TR provided in the terminal and cell portions. Thus, in this modified example 1, by using positive resist 25b in the lithography process, the height of the P layer 27 formed around the trench TR1 in the terminal portion and the trench TR2 in the cell portion can be made different.

[0035] (1.5. Variation 2) A semiconductor device 100 according to this embodiment will be described with reference to Figures 11 to 13. Figures 11 to 13 are cross-sectional views showing a method for manufacturing a semiconductor device according to modified example 2. In Modification 2, the lithography process in step S130 differs from the above embodiment and Modification 1. The differences will be explained below.

[0036] In the lithography process of step S130, as shown in Figure 11(a), a positive resist 25b is applied to the structure 20, and it is exposed to light L using a first mask M1 to form a desired pattern, and then developed. Furthermore, as shown in Figure 11(b), it is exposed to light L using a second mask M2 to form a desired pattern, and then developed. This makes it possible to have different heights of remaining positive resist 25b in multiple trenches TR of the cell portion.

[0037] In the etching process of step S140, as shown in Figure 12, the positive resist 25b remaining in the trench TR is receded by CDE (Chemical Dry Etching). This makes it possible to have the positive resist 25b remaining in multiple trench TRs in the cell portion at different heights depending on the trench TR. Subsequently, wet etching is performed on the BSG film 24 on the upper surface of the structure 20 and the surface of the trench TR. This removes the BSG film 24 in areas other than where positive resist 25b remains in the trench TR. After that, the positive resist 25b remaining in the trench TR is removed.

[0038] In the annealing process of step S150, as shown in Figure 13, a TEOS film 26 is formed as a protective film, similar to the embodiment described above, and the structure 20 is subjected to heat treatment. As a result, boron is solid-phase diffused from the remaining BSG film 24, and a P layer 27 is formed around the trench TR1 at the end and the first trench TR2-1 provided in the cell section. On the other hand, a P layer 27 is not formed around the second trench TR2-2 provided in the cell section. Thus, in this modified example 2, by using a positive resist 25b in the lithography process and repeating exposure and development multiple times, the exposure amount is made different for the end and cell sections, so that the height of the P layer formed around the trench TR1 at the end, the first trench TR2-1 in the cell section, and the second trench TR2-2 in the cell section are different. With this configuration, the P layer provided from around the upper end to around the lower end of the trench TR at the end functions as a guard ring, suppressing electric field concentration near the surface of the boundary between the cell section and the end section.

[0039] <2. Second Embodiment> Referring to Figures 14 to 17, the semiconductor device 100 according to this embodiment will be described. Figure 14 is a flowchart showing the process for manufacturing a semiconductor device according to the second embodiment. Figures 15 to 17 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. As shown in Figure 14, the second embodiment differs from the first embodiment in that the order of the post-processing step (S250) and the annealing step (S260) is reversed. The differences will be explained below. Note that the preparation step (S210), lithography step (S230), and etching step (S240) in the second embodiment are the same as in the first embodiment, so their explanation will not be repeated.

[0040] In step S220, an oxide film 28 is formed on the upper surface of the structure 20 before the BSG film 24 is formed, and the BSG film 24 is formed on the surface of the oxide film 28. Subsequently, a lithography process (S230) and an etching process (S240) are performed. In step S250, as shown in Figure 15, as a post-process, an oxide film 28 is formed again on the upper surface of the structure 20 and on the parts of the trench TR where the BSG film 24 has not been formed. Next, as shown in Figure 16, a polysilicon layer 29 for forming a gate electrode is formed on the structure 20, for example by the CVD method. Subsequently, as shown in Figure 17, the polysilicon layer 29 is etched away.

[0041] In step S260, an annealing process is performed as shown in Figure 17. In the annealing process, the structure 20 is subjected to heat treatment. As a result, boron is diffused in solid phase from the remaining BSG film, and a P layer 27 is formed around the trench TR. Thus, in the second embodiment, since solid phase diffusion by annealing is performed after the formation of the polysilicon layer 29 which will become the gate electrode 12, boron is also diffused into the polysilicon layer 29.

[0042] Subsequently, impurities are injected to form a second semiconductor layer 10b, a third semiconductor layer 10c, and a fourth semiconductor layer 10d. Furthermore, a drain electrode 41 is provided on the lower surface of the semiconductor portion 10, and a source electrode 42 as a second electrode and a source contact 51 are provided on the upper surface of the semiconductor portion 10. This completes the manufacturing of the semiconductor device 100 according to the second embodiment.

[0043] In this way, in the semiconductor device 100 according to the second embodiment, since it is manufactured by the process described above, a BSG film 24 is formed between the gate electrode 12 formed in the trench TR and the trench TR.

[0044] <3. Other Embodiments> While embodiments of the present disclosure have been described above, the application of the technical ideas in this disclosure is not limited to the examples described above. For example, in the above embodiments, the BSG film 24 is formed in step S120, but the application is not limited to this example. That is, any material that enables solid-phase diffusion in the subsequent annealing step (S150) is acceptable, and for example, other (insulating) films containing boron may be used.

[0045] Furthermore, in the above embodiment, the TEOS film 26 is formed on the structure 20 as a protective film before the annealing process, but the invention is not limited to this example.

[0046] Furthermore, although the semiconductor device 100 is a MOSFET in the above embodiment, it may be other semiconductor devices. For example, it may be an IGBT (Insulated Gate Bipola Transistor), or a diode such as an FRD (Fast Recovery Diode). Also, for example, an IGBT and an FRD may be mounted together. In this way, the technical concept of this disclosure can be applied to a wide variety of semiconductor devices.

[0047] Although several embodiments of the present invention have been described above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0048] The present invention includes the following embodiments. (Note 1) A step of forming a trench extending along a first direction and preparing a structure including a semiconductor part, The process of forming a BSG film on the upper surface of the structure and the surface of the trench, The process involves forming a resist pattern on the aforementioned structure and performing lithography. A step of removing the BSG film in areas other than those where the resist pattern remains, A method for manufacturing a semiconductor device, comprising the step of subjecting the structure, which includes the remaining BSG film, to an annealing process. (Note 2) The method for manufacturing a semiconductor device according to Appendix 1, wherein in the step of performing the annealing process, a protective film is formed on at least the portion of the structure from which the BSG film has been removed, and then the structure is subjected to heat treatment. (Note 3) The method for manufacturing a semiconductor device according to Appendix 1, wherein in the step of performing the annealing treatment, an oxide film and a polysilicon layer are formed on the upper surface of the structure and the surface of the trench, and then the structure is subjected to heat treatment. (Note 4) The method for manufacturing a semiconductor device as described in Appendix 1, wherein the exposure amount is different between the cell portion and the terminal portion adjacent to the cell portion in the lithography step. (Note 5) First electrode and, A semiconductor portion comprising: a first semiconductor layer having a first conductivity type, provided on the first electrode and having a plurality of trenches formed along a first direction and connected to the first electrode; a second semiconductor layer having a second conductivity type provided on the first semiconductor layer; a third semiconductor layer having the first conductivity type provided on the second semiconductor layer; a semiconductor layer having the second conductivity type provided extending from around the upper end to around the lower end of a portion of the plurality of trenches; and a semiconductor layer having the second conductivity type provided around the lower end of another portion of the plurality of trenches; A gate electrode disposed within the trench, An insulating portion is provided on the semiconductor portion and inside the trench. A semiconductor device comprising a second electrode provided on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer. (Note 6) In the terminal portion adjacent to the cell portion, the second conductive semiconductor layer is provided extending from around the upper end to around the lower end of the trench, The semiconductor device according to Appendix 5, wherein the cell portion comprises the second conductive semiconductor layer provided around the lower end of the trench. (Note 7) The semiconductor device according to Appendix 5, wherein a BSG film is formed between a gate electrode formed in the trench and the surface of the trench. [Explanation of Symbols]

[0049] 10: Semiconductor part, 10a: First semiconductor layer, 10b: Second semiconductor layer, 10c: Third semiconductor layer, 10d: Fourth semiconductor layer, 10e: Fifth semiconductor layer, 10f: Sixth semiconductor layer, 12: Gate electrode, 20: Structure, 21: Semiconductor part, 22: SiO2 film, 23: SiN film, 24: BSG film, 25a: Negative resist, 25b: Positive resist, 26: TEOS film, 27: P layer, 28: Oxide film, 29: Polysilicon layer, 30: Insulating part, 41: Drain electrode, 42: Source electrode, 51: Source contact, 100: Semiconductor device

Claims

1. A trench extending along a first direction is formed, and a structure including a semiconductor part is prepared. The process of forming a BSG film on the upper surface of the structure and the surface of the trench, The process involves forming a resist pattern on the aforementioned structure and performing lithography. A step of removing the BSG film in areas other than those where the resist pattern remains, A method for manufacturing a semiconductor device, comprising the step of subjecting the structure, which includes the remaining BSG film, to an annealing process.

2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of performing the annealing process, a protective film is formed on at least the portion of the structure from which the BSG film has been removed, and then the structure is subjected to heat treatment.

3. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of performing the annealing treatment, an oxide film and a polysilicon layer are formed on the upper surface of the structure and the surface of the trench, and then the structure is subjected to heat treatment.

4. The method for manufacturing a semiconductor device according to claim 1, wherein in the lithography step, the exposure amount is different between the cell portion and the terminal portion adjacent to the cell portion.

5. First electrode and, A semiconductor portion comprising: a first semiconductor layer having a first conductivity type, provided on the first electrode and having a plurality of trenches formed along a first direction and connected to the first electrode; a second semiconductor layer having a second conductivity type provided on the first semiconductor layer; a third semiconductor layer having the first conductivity type provided on the second semiconductor layer; a semiconductor layer having the second conductivity type provided extending from around the upper end to around the lower end of a portion of the plurality of trenches; and a semiconductor layer having the second conductivity type provided around the lower end of another portion of the plurality of trenches; A gate electrode disposed within the trench, An insulating portion is provided on the semiconductor portion and inside the trench. A semiconductor device comprising a second electrode provided on the semiconductor portion and connected to the second semiconductor layer and the third semiconductor layer.

6. In the terminal portion adjacent to the cell portion, the second conductivity type semiconductor layer is provided extending from around the upper end to around the lower end of the trench, The semiconductor device according to claim 5, wherein the cell portion comprises a second conductive semiconductor layer provided around the lower end of the trench.

7. The semiconductor device according to claim 5, wherein a BSG film is formed between a gate electrode formed in the trench and the surface of the trench.

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