Semiconductor devices and semiconductor memory devices

Abstract

To provide a semiconductor device with excellent transistor characteristics. [Solution] The semiconductor device of the embodiment, the semiconductor device of the first embodiment, comprises a first electrode, a second electrode, a first oxide semiconductor layer between the first electrode and the second electrode, a second oxide semiconductor layer separated from the first oxide semiconductor layer in a second direction perpendicular to the first direction connecting the first electrode and the second electrode, a gate electrode surrounding the first oxide semiconductor layer and the second oxide semiconductor layer and extending in a second direction, and a gate insulating layer. The gate electrode includes a first portion and a second portion. The first portion faces the first oxide semiconductor layer in the second direction and is in contact with the gate insulating layer and has a first length in the first direction, and the second portion is separated from the first oxide semiconductor layer by a distance of half the distance between the first oxide semiconductor layer and the second oxide semiconductor layer in the second direction and has a second length in the first direction. The first length is longer than the second length.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device.

Background Art

[0002] An oxide semiconductor transistor that forms a channel in an oxide semiconductor layer has excellent characteristics such that the channel leakage current during the off operation is extremely small. For this reason, for example, it is possible to apply the oxide semiconductor transistor to a switching transistor of a memory cell of a Dynamic Random Access Memory (DRAM).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device having excellent transistor characteristics.

Means for Solving the Problems

[0005] The semiconductor device of the embodiment includes a first electrode, a second electrode, a first oxide semiconductor layer provided between the first electrode and the second electrode, a third electrode, a fourth electrode, a second oxide semiconductor layer provided between the third electrode and the fourth electrode and spaced apart from the first oxide semiconductor layer in a second direction perpendicular to a first direction connecting the first electrode and the second electrode, a gate electrode surrounding the first oxide semiconductor layer and the second oxide semiconductor layer and extending in the second direction, and the gate electrode and the first A gate electrode comprises a gate insulating layer provided between it and an oxide semiconductor layer, wherein the gate electrode includes a first portion and a second portion, the first portion facing the first oxide semiconductor layer in the second direction and in contact with the gate insulating layer and having a first length in the first direction, and the second portion moving away from the first oxide semiconductor layer in the second direction by a distance of half the distance between the first oxide semiconductor layer and the second oxide semiconductor layer and having a second length in the first direction, the first length being longer than the second length. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 18] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 20] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 21] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 22] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 23] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 24] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 25] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 26] A schematic cross-sectional view of a semiconductor device of a first modified example of the first embodiment. [Figure 27] A schematic cross-sectional view of a semiconductor device of a second modified example of the first embodiment. [Figure 28] Schematic cross-sectional view of the semiconductor device of the second embodiment. [Figure 29] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the second embodiment. [Figure 30] Schematic cross-sectional view of the semiconductor device of the first modification of the second embodiment. [Figure 31] Schematic cross-sectional view of the semiconductor device of the second modification of the second embodiment. [Figure 32] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the second modification of the second embodiment. [Figure 33] Schematic cross-sectional view of the semiconductor device of the third embodiment. [Figure 34] Schematic cross-sectional view of the semiconductor device of the fourth embodiment. [Figure 35] Schematic cross-sectional view of the semiconductor device of the fourth embodiment. [Figure 36] Schematic cross-sectional view of the semiconductor device of the fifth embodiment. [Figure 37] Schematic cross-sectional view of the semiconductor device of the fifth embodiment. [Figure 38] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 39] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 40] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 41] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 42] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 43] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 44] Schematic cross-sectional view showing an example of a method of manufacturing the semiconductor device of the fifth embodiment. [Figure 45] Equivalent circuit diagram of the semiconductor memory device of the sixth embodiment. [Figure 46] Schematic cross-sectional view of the semiconductor memory device of the sixth embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described may be omitted from the description as appropriate.

[0008] Furthermore, for convenience, the terms "upper," "lower," "upper part," or "lower part" may be used in this specification. "Upper," "lower," "upper part," or "lower part" are terms that indicate relative positions within the drawings and do not define positions relative to gravity.

[0009] Qualitative and quantitative analysis of the chemical composition of components constituting semiconductor devices and semiconductor memory devices described herein can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), or Rutherford back-scattering spectroscopy (RBS). Furthermore, a transmission electron microscope (TEM) can be used to measure the thickness, distance between components, and grain size of components constituting semiconductor devices and semiconductor memory devices. Additionally, X-ray photoelectron spectroscopy (XPS), hard X-ray photoelectron spectroscopy (HAXPES), or electron energy loss spectroscopy (EELS) can be used to identify the constituent materials of semiconductor devices and semiconductor memory devices and to measure the relative abundance of those materials.

[0010] In this specification, "metal" refers to a general term for substances that exhibit metallic properties, and for example, metal compounds such as metal nitrides and metal carbides that exhibit metallic properties are included in the scope of "metal".

[0011] (First Embodiment) The semiconductor device of the first embodiment includes a first electrode, a second electrode, a first oxide semiconductor layer provided between the first electrode and the second electrode, a third electrode, a fourth electrode, a second oxide semiconductor layer provided between the third electrode and the fourth electrode and spaced apart from the first oxide semiconductor layer in a second direction perpendicular to a first direction connecting the first electrode and the second electrode, a gate electrode surrounding the first oxide semiconductor layer and the second oxide semiconductor layer and extending in a second direction, and a gate insulating layer provided between the gate electrode and the first oxide semiconductor layer. The gate electrode includes a first portion and a second portion. The first portion faces the first oxide semiconductor layer in the second direction and is in contact with the gate insulating layer and has a first length in the first direction, while the second portion is spaced apart from the first oxide semiconductor layer in the second direction by a distance of half the distance between the first oxide semiconductor layer and the second oxide semiconductor layer and has a second length in the first direction. The first length is longer than the second length.

[0012] Figures 1, 2, and 3 are schematic cross-sectional views of a semiconductor device according to the first embodiment. Figure 1 is a cross-sectional view of AA' in Figure 2. Figure 2 is a cross-sectional view of BB' in Figure 1. Figure 3 is a cross-sectional view of CC' in Figure 2.

[0013] In Figure 1, the vertical direction is referred to as the first direction. In Figure 1, the horizontal direction is referred to as the third direction. The third direction is perpendicular to the first direction. In Figure 3, the horizontal direction is referred to as the second direction. The second direction is perpendicular to the first and third directions. The first direction is the direction connecting the lower electrode 12 and the upper electrode 14.

[0014] The semiconductor device of the first embodiment includes a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The gate electrode of the transistor 100 is provided surrounding the oxide semiconductor layer in which the channel is formed. The transistor 100 is a so-called Surrounding Gate Transistor (SGT). The transistor 100 is a so-called vertical transistor.

[0015] The transistor 100 comprises a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, and an interlayer insulating layer 22.

[0016] The lower electrode 12 is an example of a first electrode. The upper electrode 14 is an example of a second electrode. The oxide semiconductor layer 16 is an example of a first oxide semiconductor layer.

[0017] The semiconductor device of the first embodiment includes, in addition to transistor 100, transistor 100x, a first wiring layer 24, and a second wiring layer 26.

[0018] The transistor 100x comprises a lower electrode 13, an upper electrode 15, an oxide semiconductor layer 17, a gate electrode 18, a gate insulating layer 20, and an interlayer insulating layer 22.

[0019] The lower electrode 13 is an example of a third electrode. The upper electrode 15 is an example of a fourth electrode. The oxide semiconductor layer 17 is an example of a second oxide semiconductor layer.

[0020] The transistor 100x is provided in the second direction of transistor 100. The oxide semiconductor layer 17 is provided spaced apart from the oxide semiconductor layer 16 in the second direction.

[0021] Transistor 100x has the same configuration as transistor 100. A detailed description of transistor 100x is omitted below.

[0022] The lower electrode 12 is provided beneath the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. The lower electrode 12 is in contact with the oxide semiconductor layer 16, for example. The lower electrode 12 functions as either the source electrode or the drain electrode of the transistor 100.

[0023] The lower electrode 12 is a conductor. The lower electrode 12 includes, for example, an oxide conductor. The lower electrode 12 is, for example, an oxide conductor layer.

[0024] The lower electrode 12 includes, for example, indium (In), tin (Sn), and oxygen (O). The lower electrode 12 includes, for example, indium tin oxide. The lower electrode 12 is, for example, an indium tin oxide layer.

[0025] The lower electrode 12 contains, for example, tin (Sn) and oxygen (O). The lower electrode 12 contains, for example, tin oxide. The lower electrode 12 is, for example, a tin oxide layer.

[0026] The lower electrode 12 contains, for example, a metal. The lower electrode 12 is, for example, a metal layer.

[0027] The lower electrode 12 includes, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The lower electrode 12 is, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0028] The lower electrode 12 may, for example, have a laminated structure of multiple conductors. The lower electrode 12 may, for example, have a laminated structure of an oxide conductor layer and a metal layer. For example, the surface of the lower electrode 12 on the side of the oxide semiconductor layer 16 is the oxide conductor layer.

[0029] The upper electrode 14 is provided on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. The upper electrode 14 is in contact with the oxide semiconductor layer 16, for example. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 100.

[0030] The upper electrode 14 is a conductor. The upper electrode 14 includes, for example, an oxide conductor. The upper electrode 14 is, for example, an oxide conductor layer.

[0031] The upper electrode 14 includes, for example, indium (In), tin (Sn), and oxygen (O). The upper electrode 14 includes, for example, indium tin oxide. The upper electrode 14 is, for example, an indium tin oxide layer.

[0032] The upper electrode 14 contains, for example, tin (Sn) and oxygen (O). The upper electrode 14 contains, for example, tin oxide. The upper electrode 14 is, for example, a tin oxide layer.

[0033] The upper electrode 14 contains, for example, a metal. The upper electrode 14 is, for example, a metal layer.

[0034] The upper electrode 14 includes, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The upper electrode 14 is, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0035] The upper electrode 14 may, for example, have a laminated structure of multiple conductors. The upper electrode 14 may, for example, have a laminated structure of an oxide conductor layer and a metal layer. For example, the surface of the upper electrode 14 on the side of the oxide semiconductor layer 16 is the oxide conductor layer.

[0036] The lower electrode 12 and the upper electrode 14 are formed from, for example, the same material. The lower electrode 12 and the upper electrode 14 are, for example, oxide conductors containing indium (In), tin (Sn), and oxygen (O). The lower electrode 12 and the upper electrode 14 contain, for example, indium tin oxide. The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide layers.

[0037] The oxide semiconductor layer 16 is provided between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is in contact with, for example, the lower electrode 12. The oxide semiconductor layer 16 is in contact with, for example, the upper electrode 14.

[0038] The oxide semiconductor layer 16 is columnar. The oxide semiconductor layer 16 is, for example, cylindrical. The oxide semiconductor layer 16 may also be, for example, a rectangular prism.

[0039] A channel is formed in the oxide semiconductor layer 16 that serves as a current path when the transistor 100 is turned on.

[0040] The oxide semiconductor layer 16 is an oxide semiconductor. For example, the oxide semiconductor layer 16 is amorphous.

[0041] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), as well as zinc (Zn) and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16 includes, for example, indium gallium zinc oxide. The oxide semiconductor layer 16 is, for example, an indium gallium zinc oxide layer.

[0042] The oxide semiconductor layer 16 includes, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W), and oxygen (O). The oxide semiconductor layer 16 includes, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 is, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0043] The oxide semiconductor layer 16 has a chemical composition different from, for example, the chemical composition of the lower electrode 12 and the chemical composition of the upper electrode 14.

[0044] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.

[0045] The length of the oxide semiconductor layer 16 in the first direction is, for example, 80 nm to 200 nm. The length of the oxide semiconductor layer 16 in the second direction is, for example, 20 nm to 100 nm.

[0046] The gate electrode 18 surrounds the oxide semiconductor layer 16 and the oxide semiconductor layer 17. The gate electrode 18 is positioned such that its position coordinate in the first direction is between the position coordinates of the lower electrode 12 and the upper electrode 14 in the first direction.

[0047] As shown in Figure 2, the gate electrode 18 extends in a second direction perpendicular to the first direction.

[0048] The length of the gate electrode 18 in the first direction in the portion of the oxide semiconductor layer 16 that is in contact with the gate insulating layer 20 is longer than the length of the gate electrode 18 in the first direction in other portions that are away from the oxide semiconductor layer 16 in a second direction.

[0049] As shown in Figure 3, the gate electrode 18 includes a first portion 18a and a second portion 18b. The first portion 18a is the portion that faces the oxide semiconductor layer 16 in a second direction and is in contact with the gate insulating layer 20. The first portion 18a has a first length (L1 in Figure 3) in the first direction. The second portion 18b is the portion that is separated from the oxide semiconductor layer 16 by a distance of half the distance between the oxide semiconductor layer 16 and the oxide semiconductor layer 17 (d in Figure 3) (d / 2 in Figure 3). The second portion 18b has a second length (L2 in Figure 3) in the first direction. The first length L1 is longer than the second length L2.

[0050] Furthermore, as shown in Figure 1, the gate electrode 18 includes a third portion 18c. The third portion 18c is the portion that faces the oxide semiconductor layer 16 in a third direction and is in contact with the gate insulating layer 20. The third portion 18c has a third length (L3 in Figure 1) in the first direction. The third length L3 is longer than the second length L2.

[0051] The first length L1 is, for example, 1.2 times or more and 2 times or less of the second length L2. The third length L3 is, for example, 1.2 times or more and 2 times or less of the second length L2.

[0052] The gate electrode 18 is a conductor. The gate electrode 18 is, for example, a metal, a metallic compound, or a semiconductor. The gate electrode 18 includes, for example, tungsten (W).

[0053] The length of the gate electrode 18 in the first direction is, for example, between 20 nm and 100 nm.

[0054] The gate insulating layer 20 is provided between the oxide semiconductor layer 16 and the gate electrode 18. The gate insulating layer 20 is provided surrounding the oxide semiconductor layer 16. The gate insulating layer 20 is provided between the lower electrode 12 and the upper electrode 14.

[0055] The gate insulating layer 20 does not come into contact with, for example, the lower electrode 12. The gate insulating layer 20 comes into contact with, for example, the upper electrode 14.

[0056] The gate insulating layer 20 is provided, for example, between the gate electrode 18 and the lower electrode 12 in the first direction. It does not contact the gate electrode 18. The gate insulating layer 20 is provided, for example, between the gate electrode 18 and the interlayer insulating layer 22 in the first direction. The gate insulating layer 20 contacts the gate electrode 18 and the interlayer insulating layer 22 in the first direction.

[0057] The gate insulating layer 20 is, for example, an oxide, a nitride, or an oxynitride. The gate insulating layer 20 includes, for example, silicon oxide, aluminum oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The gate insulating layer 20 is, for example, a silicon oxide layer, an aluminum oxide layer, a silicon nitride layer, an aluminum nitride layer, or a silicon oxynitride layer.

[0058] The gate insulating layer 20 may have, for example, a multilayer structure. The gate insulating layer 20 may have, for example, a multilayer structure of a nitride film and an oxide film. The gate insulating layer 20 may have, for example, a multilayer structure of a silicon nitride film and a silicon oxide film. For example, a silicon oxide film is provided between the oxide semiconductor layer 16 and the silicon nitride film. The thickness of the gate insulating layer 20 is, for example, 0.5 nm or more and 5 nm or less.

[0059] The lower electrode 12 is separated from the gate insulating layer 20 in a first direction, for example. In the first direction, an interlayer insulating layer 22 is provided between the lower electrode 12 and the gate insulating layer 20, for example.

[0060] The first wiring layer 24 extends in a second direction. The first wiring layer 24 is provided adjacent to the gate electrode 18 in a third direction. For example, the gate electrode 18 is sandwiched between two first wiring layers 24 in the third direction.

[0061] The first wiring layer 24 contains the same material as the gate electrode 18. The first wiring layer 24 is formed from the same material as the gate electrode 18. The first wiring layer 24 is formed, for example, at the same time as the gate electrode 18.

[0062] In the cross-section including the oxide semiconductor layer 16, which is parallel to the first and third directions shown in Figure 1, the fourth length of the first wiring layer 24 in the first direction (L4 in Figure 1) is shorter than the first length of the gate electrode 18 (L1 in Figure 3). Furthermore, the fourth length L4 of the first wiring layer 24 is shorter than the third length of the gate electrode 18 (L3 in Figure 1). Also, the fourth length L4 of the first wiring layer 24 is approximately the same as the second length of the gate electrode 18 (L2 in Figure 3).

[0063] A gate insulating layer 20 is provided on the lower surface of the first wiring layer 24. The gate insulating layer 20 is provided between the first wiring layer 24 and the interlayer insulating layer 22. The gate insulating layer 20 is in contact with the first wiring layer 24 and the interlayer insulating layer 22.

[0064] The second wiring layer 26 extends, for example, in a third direction. The second wiring layer 26 is repeatedly provided, for example, on the gate electrode 18 and the first wiring layer 24 in a second direction. An interlayer insulating layer 22 is provided between the second wiring layer 26 and the gate electrode 18 and the first wiring layer 24. The second wiring layer 26 intersects, for example, the gate electrode 18 and the first wiring layer 24. A portion of the second wiring layer 26 is electrically connected, for example, to the upper electrode 14.

[0065] The interlayer insulating layer 22 surrounds, for example, the lower electrode 12, the upper electrode 14, the oxide semiconductor layer 16, and the gate insulating layer 20. The interlayer insulating layer 22 is provided, for example, between the lower electrode 12 and the gate electrode 18. The interlayer insulating layer 22 is provided, for example, between the upper electrode 14 and the gate electrode 18. The interlayer insulating layer 22 is provided, for example, between the gate electrode 18 and the first wiring layer 24.

[0066] The interlayer insulating layer 22 is an insulator. The interlayer insulating layer 22 is, for example, an oxide, nitride, or oxynitride. The interlayer insulating layer 22 contains, for example, silicon (Si) and oxygen (O). The interlayer insulating layer 22 contains, for example, silicon oxide. The interlayer insulating layer 22 is, for example, silicon oxide. The interlayer insulating layer 22 contains, for example, silicon (Si) and nitrogen (N). The interlayer insulating layer 22 contains, for example, silicon nitride. The interlayer insulating layer 22 is, for example, silicon nitride.

[0067] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0068] Figures 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, and 21 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 4 to 21 each show a cross-section corresponding to Figure 1. Figures 4 to 21 are diagrams showing an example of a method for manufacturing transistor 100.

[0069] The following explanation will use the example of a transistor 100 where the lower electrode 12 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a silicon oxide layer, and the interlayer insulating layer 22 is a silicon oxide layer.

[0070] First, a first silicon oxide film 32 and a first silicon nitride film 34 are formed on the indium tin oxide layer 31 formed within the silicon oxide layer 30 (Figure 4). The first silicon oxide film 32 and the first silicon nitride film 34 are formed, for example, by the Chemical Vapor Deposition (CVD) method.

[0071] The silicon oxide layer 30 eventually becomes the interlayer insulating layer 22. The indium tin oxide layer 31 eventually becomes the lower electrode 12. A portion of the first silicon oxide film 32 eventually becomes the interlayer insulating layer 22.

[0072] Next, the first silicon nitride film 34 and the first silicon oxide film 32 are etched to form the first opening 35 (Figure 5). The first opening 35 is formed, for example, using lithography and reactive ion etching (RIE).

[0073] Next, the first opening 35 is filled with an amorphous silicon film 36 (Figure 6). The amorphous silicon film 36 is formed, for example, by deposition using the CVD method and planarization treatment using the chemical mechanical polishing (CMP) method.

[0074] Next, the first silicon nitride film 34 is etched to expose the amorphous silicon film 36 (Figure 7). The exposed amorphous silicon film 36 forms columnar bodies 37.

[0075] Next, the columnar body 37 is covered with a second silicon oxide film 38 (Figure 8). The second silicon oxide film 38 is formed, for example, by a CVD method. A portion of the second silicon oxide film 38 ultimately becomes the gate insulating layer 20.

[0076] Next, the columnar body 37 is embedded with a tungsten film 39 (Figure 9). The tungsten film 39 is formed, for example, using the CVD method. A portion of the tungsten film 39 will ultimately become the gate electrode 18 and the first wiring layer 24.

[0077] Next, the upper surface of the tungsten film 39 is flattened (Figure 10). The tungsten film 39 is flattened by the CVD method. The upper surface of the columnar body 37 is exposed.

[0078] Next, a portion of the tungsten film 39 is etched to expose a portion of the second silicon oxide film 38 on the side surface of the columnar body 37 (Figure 11). At this time, the tungsten film 39 is etched in such a way that the tungsten film 39 around the columnar body 37 remains thicker than the other parts.

[0079] For example, by performing isotropic dry etching, the tungsten film 39 around the columnar body 37 can be made thicker than other parts.

[0080] Next, the columnar body 37 is covered with a second silicon nitride film 40 (Figure 12). The second silicon nitride film 40 is formed, for example, by the CVD method.

[0081] Next, the second silicon nitride film 40 is etched to form side walls 41 on the sides of the columnar body 37 (Figure 13). The side walls 41 are formed, for example, using the RIE method.

[0082] Next, the columnar body 37 and the side wall 41 are embedded with a third silicon oxide film 42 (Figure 14). The third silicon oxide film 42 is formed, for example, by the CVD method.

[0083] Next, the third silicon oxide film 42 is etched to form a second opening 43 in which the side wall 41 and the tungsten film 39 are exposed (Figure 15). The second opening 43 is formed using lithography and RIE.

[0084] Next, the tungsten film 39 is etched using the third silicon oxide film 42 and the side wall 41 as a mask (Figure 16). The tungsten film 39 is etched using, for example, the RIE method.

[0085] Next, the side wall 41 is removed (Figure 17). The side wall 41 is removed, for example, using a wet etching method.

[0086] Next, the second opening 43 is filled with a fourth silicon oxide film 44 (Figure 18). The fourth silicon oxide film 44 is formed, for example, by CVD.

[0087] Next, the fourth silicon oxide film 44 and the third silicon oxide film 42 on the columnar body 37 are removed, exposing the upper surface of the columnar body 37 (Figure 19). The fourth silicon oxide film 44 and the third silicon oxide film 42 are removed, for example, using the CMP method.

[0088] Next, the columnar bodies 37 are etched and removed to form a third opening 45 on the side surface, exposing the second silicon oxide film 38 (Figure 20). The amorphous silicon film 36 forming the columnar bodies 37 is etched, for example, using a wet etching method.

[0089] Next, the third opening 45 is filled with an indium gallium zinc oxide film 46 (Figure 21). The indium gallium zinc oxide film 46 is formed, for example, using a CVD method and then planarized using a CMP method. The indium gallium zinc oxide film 46 ultimately becomes an oxide semiconductor layer 16.

[0090] Subsequently, the upper electrode 14 of the indium tin oxide layer and the second wiring layer 26 are formed using known process techniques.

[0091] By the above manufacturing method, a semiconductor device including the transistor 100 shown in Figures 1, 2, and 3 is manufactured.

[0092] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0093] Figures 22, 23, 24, and 25 are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 22, 23, 24, and 25 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device of a comparative example.

[0094] The comparative example's method for manufacturing a semiconductor device differs from the first embodiment's method for manufacturing a semiconductor device in that, after forming an opening 45x corresponding to the third opening 45 of the first embodiment's method for manufacturing a semiconductor device, a second silicon oxide film 38 which serves as a gate insulating layer is formed.

[0095] For example, as shown in Figure 22, an opening 45x is formed in which a tungsten film 39 is exposed on the side and an indium tin oxide layer 31 is exposed on the bottom. Next, as shown in Figure 23, a second silicon oxide film 38, which will serve as a gate insulating layer, is formed inside the opening 45x. Then, as shown in Figure 24, the second silicon oxide film 38 at the bottom of the opening 45x is removed using the RIE method. After that, as shown in Figure 25, the opening 45x is filled with an indium gallium zinc oxide film 46.

[0096] RIE is an anisotropic etching method that utilizes ionic shock. In the manufacturing method of the comparative example described above, as shown in Figure 24, when the second silicon oxide film 38 at the bottom of the opening 45x is removed using the RIE method, the surface of the second silicon oxide film 38 formed on the side of the opening 45x is directly exposed to ionic shock. As a result, processing damage remains on the second silicon oxide film 38.

[0097] The second silicon oxide film 38 ultimately becomes the gate insulating layer. Because processing damage remains on the gate insulating layer, the reliability of the gate insulating layer decreases. Specifically, for example, the time-dependent dielectric breakdown characteristics (TDDB characteristics) of the gate insulating layer deteriorate.

[0098] In the semiconductor device manufacturing method of the first embodiment, a columnar body 37 is formed, and a second silicon oxide film 38, which will ultimately become the gate insulating layer 20, is formed on the surface of the columnar body 37. As shown in Figures 19 and 20, when forming the third opening 45 in which the indium tin oxide layer 31 is exposed on the bottom surface, wet etching is used instead of the RIE method. Therefore, the second silicon oxide film 38, which will become the gate insulating layer 20, is not exposed to the ionic shock of RIE.

[0099] Therefore, the reliability of the gate insulating layer 20 is improved compared to the semiconductor device manufacturing method of the comparative example. Thus, a transistor 100 with improved reliability can be realized.

[0100] Furthermore, in the transistor 100 of the first embodiment, the length of the gate electrode 18 in the first direction of the portion of the oxide semiconductor layer 16 that is in contact with the gate insulating layer 20 is long. In other words, the gate length of the transistor 100 is long. By having a long gate length, for example, the short-channel effect of the transistor 100 is suppressed, and a transistor 100 with stable characteristics can be realized. Also, by having a long gate length, for example, a high threshold voltage can be realized, and therefore, for example, a transistor 100 with low off-leak current can be realized.

[0101] On the other hand, in the first embodiment, the transistor 100 has a shorter length in the first direction of other parts that are separated from the gate insulating layer 20 in a second direction perpendicular to the first direction, i.e., the parts used as wiring layers. Therefore, compared to, for example, the case where the length in the first direction of the parts used as wiring layers is about the same as the gate length of the transistor 100, the capacitance between wirings is reduced, and the power consumption of the semiconductor circuit using the transistor 100 can be reduced.

[0102] Specifically, for example, the distance between the second wiring layer 26, which is provided on the gate electrode 18 and intersects with the gate electrode 18, and the gate electrode 18 becomes longer. Therefore, the inter-wiring capacitance between the gate electrode 18 and the second wiring layer 26 can be reduced. Also, the area of ​​the surface that extends in the same direction as the gate electrode 18 and faces the adjacent first wiring layer 24 becomes smaller. Therefore, the inter-wiring capacitance between the gate electrode 18 and the first wiring layer 24 can be reduced.

[0103] Furthermore, by reducing the interwiring capacitance between the gate electrode 18 and the first wiring layer 24, it is possible to suppress the malfunction of the transistor 100 caused by changes in the potential of the gate electrode 18 due to coupling with the potential of adjacent first wiring layers 24.

[0104] Furthermore, as can be seen from Figure 2, the effective width of the gate electrode 18 in the third direction narrows near the transistor 100. In other words, the effective width of the gate electrode 18 in the third direction narrows around the oxide semiconductor layer 16. As a result, the wiring resistance of the gate electrode 18 in the second direction increases due to the narrowing of the effective width of the gate electrode 18 around the oxide semiconductor layer 16. In the transistor 100 of the first embodiment, the length of the gate electrode 18 in the first direction is long in the portion of the gate electrode 18 that is in contact with the gate insulating layer 20 around the oxide semiconductor layer 16. Therefore, even if the effective width of the gate electrode 18 around the oxide semiconductor layer 16 narrows, the increase in the electrical resistance of the gate electrode 18 around the oxide semiconductor layer 16 can be suppressed. Consequently, the increase in the wiring resistance of the gate electrode 18 in the second direction can be suppressed.

[0105] As described above, the semiconductor device of the first embodiment can be realized with excellent transistor characteristics.

[0106] (First variation) Figure 26 is a schematic cross-sectional view of a semiconductor device of a first modified example of the first embodiment. Figure 26 corresponds to Figure 1 of the first embodiment.

[0107] The transistor 110, a first modification of the first embodiment, differs from the transistor 100 of the first embodiment in that the width of the oxide semiconductor layer 16 in the third direction decreases from the upper electrode 14 towards the lower electrode 12. It also differs from the transistor 100 of the first embodiment in that the oxide semiconductor layer 16 has a so-called forward taper shape.

[0108] (Second variation) Figure 27 is a schematic cross-sectional view of a semiconductor device of a second modified example of the first embodiment. Figure 27 corresponds to Figure 1 of the first embodiment.

[0109] The transistor 120, a second modification of the first embodiment, differs from the transistor 100 of the first embodiment in that the width of the oxide semiconductor layer 16 in the third direction increases from the upper electrode 14 towards the lower electrode 12. It also differs from the transistor 100 of the first embodiment in that the oxide semiconductor layer 16 has a so-called inverse tapered shape.

[0110] As described above, semiconductor devices with excellent transistor characteristics can be realized according to the first embodiment and its modified counterparts.

[0111] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the oxide semiconductor layer includes a first region and a second region provided between the first region and the second electrode, the first region is in contact with the gate insulating layer in a first direction, the second region is surrounded by the gate insulating layer, and in a cross section parallel to the first direction, the first width of the first region in a third direction perpendicular to the second direction is wider than the second width of the second region in the third direction. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0112] Figure 28 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. Figure 28 corresponds to Figure 1 of the first embodiment.

[0113] The oxide semiconductor layer 16 of the transistor 200 in the second embodiment includes a first region 16a and a second region 16b. The second region 16b is provided between the first region 16a and the upper electrode 14.

[0114] The first region 16a is in contact with the gate insulating layer 20 in a first direction. The second region 16b is surrounded by the gate insulating layer 20. The first region 16a is, for example, physically continuous with the second region 16b.

[0115] In a cross-section parallel to the first direction, the first width (w1 in Figure 28) of the first region 16a in the third direction perpendicular to the second direction is wider than the second width (w2 in Figure 28) of the second region 16b in the third direction. The difference between the first width w1 of the first region 16a and the second width w2 of the second region 16b is, for example, between 1 nm and 20 nm.

[0116] In the second embodiment, the oxide semiconductor layer 16 of the transistor 200 has a smaller cross-sectional area perpendicular to the first direction of the oxide semiconductor layer 16 surrounded by the gate electrode 18 compared to, for example, the transistor 100 of the first embodiment. Also, in the second embodiment, the oxide semiconductor layer 16 of the transistor 200 includes a first region 16a and a second region 16b, so that the end of the gate insulating layer 20 on the lower electrode 12 side extends inward into the oxide semiconductor layer 16.

[0117] Figure 29 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0118] For example, in the semiconductor device manufacturing method of the first embodiment, after forming columnar bodies 37 of amorphous silicon film 36, a step of etching the columnar bodies 37 to make them thinner, as shown in Figure 29, can be added to manufacture the transistor 200 of the second embodiment.

[0119] According to the transistor 200 of the second embodiment, the cross-sectional area of ​​the oxide semiconductor layer 16 surrounded by the gate electrode 18 perpendicular to the first direction becomes smaller, which increases the strength of the electric field applied to the oxide semiconductor layer 16 by the gate electrode 18. Therefore, for example, the threshold voltage of the transistor 200 can be increased.

[0120] Furthermore, in the second embodiment of the transistor 200, the oxide semiconductor layer 16 has an end of the gate insulating layer 20 on the lower electrode 12 side embedded in the oxide semiconductor layer 16. Therefore, the controllability of the electric field in the oxide semiconductor layer 16 near the end of the gate insulating layer 20 on the lower electrode 12 side by the gate electrode 18 is improved. Thus, for example, an increase in on-current and a reduction in leakage current can be achieved.

[0121] As described above, the semiconductor device of the second embodiment can realize a semiconductor device with excellent transistor characteristics.

[0122] (First variation) The semiconductor device of the first modification of the second embodiment differs from the semiconductor device of the second embodiment in that, in the first direction, a gate insulating layer is provided between the first region and the gate electrode.

[0123] Figure 30 is a schematic cross-sectional view of a semiconductor device of the first modified example of the second embodiment. Figure 30 corresponds to Figure 28 of the second embodiment.

[0124] In the first modified example of the second embodiment, the transistor 210 has a gate insulating layer 20 provided between the first region 16a and the gate electrode 18 in the first direction.

[0125] The length w2 of the second region 16b in the third direction is even shorter than that of the transistor 200 in the second embodiment. Therefore, the oxide semiconductor layer 16 of the transistor 210 of the second modification has an even smaller cross-sectional area of ​​the oxide semiconductor layer 16 surrounded by the gate electrode 18, perpendicular to the first direction, compared to, for example, the transistor 200 in the second embodiment.

[0126] According to the transistor 210 of the first modification of the second embodiment, the cross-sectional area of ​​the oxide semiconductor layer 16 surrounded by the gate electrode 18 perpendicular to the first direction is further reduced, which allows the threshold voltage of the transistor 210 to be further increased.

[0127] Furthermore, in the first modified example of the second embodiment, the oxide semiconductor layer 16 of the transistor 210 has the lower electrode 12 side of the gate insulating layer 20 further embedded in the oxide semiconductor layer 16. Therefore, for example, an increase in on-current and a reduction in leakage current can be achieved.

[0128] (Second variation) The semiconductor device of the second modified example of the second embodiment differs from the semiconductor device of the second embodiment in that, in the first direction, a gate insulating layer is not provided between the first electrode and the gate electrode.

[0129] Figure 31 is a schematic cross-sectional view of a semiconductor device of a second modified example of the second embodiment. Figure 31 corresponds to Figure 28 of the second embodiment.

[0130] In the second modified example of the second embodiment, the transistor 220 does not have a gate insulating layer 20 between the lower electrode 12 and the gate electrode 18 in the first direction.

[0131] Figure 32 is a schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device of a second modification of the second embodiment.

[0132] For example, in the semiconductor device manufacturing method of the first embodiment, after forming columnar bodies 37 of amorphous silicon film 36, instead of forming a second silicon oxide film 38 which will ultimately become the gate insulating layer 20 by CVD, an oxide film 38x is formed by oxidizing the amorphous silicon film 36. The oxide film 38x is formed, for example, by thermal oxidation or plasma oxidation of the amorphous silicon film 36. The oxide film 38x obtained by oxidizing the amorphous silicon film 36 ultimately becomes the gate insulating layer 20.

[0133] As described above, semiconductor devices with excellent transistor characteristics can be realized according to the second embodiment and its modified examples.

[0134] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the gate insulating layer includes a first film and a second film which has a different chemical composition from the first film and sandwiches the first film between itself and an oxide semiconductor layer. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0135] Figure 33 is a schematic cross-sectional view of a semiconductor device according to the third embodiment. Figure 33 corresponds to Figure 1 of the first embodiment.

[0136] The gate insulating layer 20 of the transistor 300 in the third embodiment includes a first film 20a and a second film 20b. The second film 20b sandwiches the first film 20a between itself and the oxide semiconductor layer 16. The first film 20a is provided between the oxide semiconductor layer 16 and the second film 20b. The gate insulating layer 20 has a laminated structure of the first film 20a and the second film 20b.

[0137] The chemical composition of the second film 20b is different from that of the first film 20a. The first film 20a contains, for example, silicon oxide. The second film 20b contains, for example, a substance with a dielectric constant higher than that of silicon oxide.

[0138] Substances with a dielectric constant higher than that of silicon oxide contained in the second film 20b include, for example, silicon nitride, aluminum nitride, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, or tantalum oxide.

[0139] According to the transistor 300 of the third embodiment, the gate insulating layer 20 has a laminated structure of a first film 20a and a second film 20b, which allows for, for example, a higher threshold voltage of the transistor 300. Furthermore, the gate insulating layer 20 has a laminated structure of a first film 20a and a second film 20b, which allows for, for example, an improvement in the reliability of the gate insulating layer 20.

[0140] As described above, the semiconductor device of the third embodiment makes it possible to realize a semiconductor device with excellent transistor characteristics.

[0141] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that the gate electrode includes a first layer and a second layer, which has a different chemical composition from the first layer and sandwiches the first layer between itself and the gate insulating layer. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0142] Figures 34 and 35 are schematic cross-sectional views of the semiconductor device according to the fourth embodiment. Figure 34 corresponds to Figure 1 of the first embodiment. Figure 35 corresponds to Figure 3 of the first embodiment.

[0143] The gate electrode 18 of the transistor 400 in the fourth embodiment includes a first layer 18x and a second layer 18y. The second layer 18y sandwiches the first layer 18x between itself and the gate insulating layer 20. The first layer 18x is provided between the gate insulating layer 20 and the second layer 18y. The gate electrode 18 has a laminated structure of the first layer 18x and the second layer 18y.

[0144] The chemical composition of the second layer 18y is different from that of the first layer 18x. The second layer 18y contains different materials than the first layer 18x. The electrical resistivity of the materials in the second layer 18y is, for example, lower than that of the materials in the first layer 18x.

[0145] The material contained in the first layer 18x is, for example, titanium nitride, tungsten nitride, or tantalum nitride. The material contained in the second layer 18y is, for example, tungsten or molybdenum.

[0146] According to the transistor 400 of the fourth embodiment, the gate electrode 18 has a stacked structure of a first layer 18x and a second layer 18y, which makes it possible to achieve both control of the threshold voltage of the transistor 400 and low resistance of the gate electrode 18. Specifically, for example, the first layer 18x is made of a material having a work function suitable for optimizing the threshold voltage of the transistor 400. Then, for example, the second layer 18y is made of a material with low electrical resistivity.

[0147] As described above, the semiconductor device of the fourth embodiment can be realized with excellent transistor characteristics.

[0148] (Fifth embodiment) The semiconductor device of the fifth embodiment differs from the semiconductor device of the fourth embodiment in that the gate electrode further includes a third portion, the third portion facing the oxide semiconductor layer and in contact with the gate insulating layer in a third direction perpendicular to the first and second directions, and having a third length in the first direction, the third length being shorter than the first length. Hereafter, some descriptions that overlap with the fourth embodiment may be omitted.

[0149] Figures 36 and 37 are schematic cross-sectional views of a semiconductor device according to the fifth embodiment. Figure 36 corresponds to Figure 1 of the first embodiment. Figure 37 corresponds to Figure 3 of the first embodiment.

[0150] The gate electrode 18 of the transistor 500 in the fifth embodiment includes a first layer 18x and a second layer 18y, similar to the transistor 400 in the fourth embodiment. The second layer 18y sandwiches the first layer 18x between itself and the gate insulating layer 20. The first layer 18x is provided between the gate insulating layer 20 and the second layer 18y. The gate electrode 18 has a laminated structure of the first layer 18x and the second layer 18y.

[0151] As shown in Figure 36, the gate electrode 18 includes a third portion 18c. The third portion 18c is the portion that faces the oxide semiconductor layer 16 in a third direction and is in contact with the gate insulating layer 20. The third portion 18c has a third length in the first direction (L3 in Figure 36).

[0152] Furthermore, as shown in Figure 37, the gate electrode 18 includes a first portion 18a. The first portion 18a is the portion that faces the oxide semiconductor layer 16 in the second direction and is in contact with the gate insulating layer 20. The first portion 18a has a first length (L1 in Figure 37) in the first direction. The third length L3 is shorter than the first length L1.

[0153] The third length L3 is, for example, 0.5 times or more and 0.8 times or less of the first length L1.

[0154] The gate electrode 18 provided in the third direction of the oxide semiconductor layer 16 does not include the second layer 18y. The gate electrode 18 provided in the third direction of the oxide semiconductor layer 16 is formed only from the first layer 18x.

[0155] Figures 38, 39, 40, 41, 42, 43, and 44 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the fifth embodiment. Figures 38 to 43 correspond to Figure 36. Figure 44 corresponds to Figure 37.

[0156] For example, in the method for manufacturing a semiconductor device according to the first embodiment, a titanium nitride film 50 is formed before embedding the columnar body 37 with a tungsten film 39. The tungsten film 39 is then formed on top of the titanium nitride film 50 (Figure 38).

[0157] The titanium nitride film 50 is formed, for example, by the CVD method. The tungsten film 39 is formed, for example, by the CVD method. A portion of the titanium nitride film 50 and a portion of the tungsten film 39 ultimately become the gate electrode 18 and the first wiring layer 24. A portion of the titanium nitride film 50 becomes the first layer 18x. A portion of the tungsten film 39 becomes the second layer 18y.

[0158] Next, a portion of the tungsten film 39 is etched to expose the titanium nitride film 50 on the top and side surfaces of the columnar body 37 (Figure 39). The tungsten film 39 is etched, for example, by the RIE method.

[0159] Next, the titanium nitride film 50 on the upper surface of the columnar body 37 is etched to expose a portion of the second silicon oxide film 38 on the side surface of the columnar body 37 (Figure 40). At this time, the titanium nitride film 50 is etched in such a way that the titanium nitride film 50 along the side surface of the columnar body 37 remains thicker than the other parts.

[0160] For example, by using a wet etching method, a thick titanium nitride film 50 can be left along the columnar body 37.

[0161] Next, the columnar body 37 and the side wall 41 are embedded with a third silicon oxide film 42 (Figure 41). The third silicon oxide film 42 is formed, for example, by the CVD method.

[0162] Next, the third silicon oxide film 42 is etched to form a second opening 43 in which the titanium nitride film 50 and the tungsten film 39 are exposed (Figure 42). The second opening 43 is formed using lithography and RIE.

[0163] Next, the tungsten film 39 and the titanium nitride film 50 are etched using the third silicon oxide film 42 as a mask (Figure 43). The tungsten film 39 and the titanium nitride film 50 are etched, for example, using the RIE method.

[0164] The etching process involves two steps: etching the tungsten film 39 and etching the titanium nitride film 50. For etching the tungsten film 39, conditions are selected that allow for a selectivity ratio with the titanium nitride film 50. This ensures that the titanium nitride film 50 along the sides of the columnar body 37 remains intact.

[0165] Figure 44 is a cross-sectional view perpendicular to Figure 43. In this direction, the tungsten film 39 and the titanium nitride film 50 are completely masked by the third silicon oxide film 42; therefore, the tungsten film 39 and the titanium nitride film 50 remain unetched.

[0166] Subsequently, the transistor 500 of the fifth embodiment can be manufactured using the same method as the manufacturing method of the first embodiment.

[0167] According to the fifth embodiment of the transistor 500, similar to the fourth embodiment, the gate electrode 18 has a stacked structure of a first layer 18x and a second layer 18y, which allows for both control of the threshold voltage of the transistor 500 and low resistance of the gate electrode 18. Specifically, the first layer 18x is made of a material having a work function suitable for optimizing the threshold voltage of the transistor 500. The second layer 18y is made of a material with low electrical resistivity.

[0168] When the gate electrode 18, provided in the third direction of the oxide semiconductor layer 16, is formed only from the first layer 18x, as in transistor 500, the increase in the electrical resistance of the gate electrode 18 around the oxide semiconductor layer 16 can be suppressed compared to when it is a stacked structure of the first layer 18x and the second layer 18y, as in transistor 400 of the fourth embodiment. As described in the first embodiment, the effective width of the gate electrode 18 in the third direction is narrowed around the oxide semiconductor layer 16. For example, an oxide film is formed at the interface between the first layer 18x and the second layer 18y. When the effective width is narrow and both the first layer 18x and the second layer 18y are thin, the nanowire effect caused by electron scattering of the oxide film at the interface becomes apparent, and the electrical resistance of the gate electrode 18 in the third direction of the oxide semiconductor layer 16 increases. In the fifth embodiment of the transistor 500, the gate electrode 18 provided in the third direction of the oxide semiconductor layer 16 is formed only of the first layer 18x, so there is no interface. Therefore, the nanowire effect caused by electron scattering of the oxide film at the interface does not occur, and the increase in the electrical resistance of the gate electrode 18 in the third direction of the oxide semiconductor layer 16 is suppressed. Thus, for example, the increase in the wiring resistance of the gate electrode 18 in the second direction can be suppressed.

[0169] Furthermore, in the fifth embodiment of the transistor 500, the length of the gate electrode 18 in the third direction of the oxide semiconductor layer 16 along the oxide semiconductor layer 16 is shortened. This portion functions as an oxygen supply path after the transistor 500 is formed. Therefore, it becomes easier to adjust the oxygen vacancy concentration in the oxide semiconductor layer 16, and the characteristics of the transistor 500 are stabilized.

[0170] Furthermore, the transistor 500 of the fifth embodiment can be manufactured without forming the side wall 41 used in the manufacturing method of the first embodiment when forming the pattern of the gate electrode 18. Therefore, it can be manufactured using a simpler method.

[0171] As described above, the semiconductor device of the fifth embodiment can be realized with excellent transistor characteristics.

[0172] (Sixth embodiment) The semiconductor memory device of the sixth embodiment comprises the semiconductor device of the first embodiment and a capacitor electrically connected to the first electrode or the second electrode.

[0173] The semiconductor memory device of the sixth embodiment is a semiconductor memory 600. The semiconductor memory device of the sixth embodiment is a DRAM. The semiconductor memory 600 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.

[0174] In the following, some descriptions that overlap with the first embodiment will be omitted.

[0175] Figure 45 is an equivalent circuit diagram of a semiconductor memory device according to the sixth embodiment. Although Figure 45 illustrates the case where there is one memory cell MC, multiple memory cell MCs may be provided, for example, in an array.

[0176] The semiconductor memory 600 comprises a memory cell MC, a word line WL, a bit line BL, and a plate line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. In Figure 45, the area enclosed by the dashed line is the memory cell MC.

[0177] The word wire WL is electrically connected to the gate electrode of the switching transistor TR. The bit wire BL is electrically connected to one of the source and drain electrodes of the switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of the switching transistor TR. The other electrode of capacitor CA is connected to the plate wire PL.

[0178] Memory cells (MC) store data by accumulating electric charge in capacitors (CA). Data is written to and read by turning on a switching transistor (TR).

[0179] For example, a switching transistor TR is turned on while a desired voltage is applied to the bit line BL, and data is written to the memory cell MC.

[0180] Furthermore, for example, by turning on a switching transistor TR, the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor is detected, and data from the memory cell MC is read out.

[0181] Figure 46 is a schematic cross-sectional view of a semiconductor memory device according to the sixth embodiment. Figure 46 shows a cross-section of the memory cell MC of the semiconductor memory 600.

[0182] The semiconductor memory 600 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, and an interlayer insulating layer 22.

[0183] The switching transistor TR comprises a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, and a gate insulating layer 20.

[0184] The switching transistor TR has the same structure as the transistor 100 in the first embodiment.

[0185] Capacitor CA is provided between the silicon substrate 10 and the switching transistor TR. Capacitor CA is provided between the silicon substrate 10 and the lower electrode 12. Capacitor CA is electrically connected to the lower electrode 12.

[0186] The capacitor CA comprises a cell electrode 71, a plate electrode 72, and a capacitor insulating film 73. The cell electrode 71 is electrically connected to the lower electrode 12. The cell electrode 71 is, for example, in contact with the lower electrode 12.

[0187] The cell electrode 71 and plate electrode 72 are made of, for example, titanium nitride. The capacitor insulating film 73 has a layered structure of, for example, zirconium oxide, aluminum oxide, and zirconium oxide.

[0188] The gate electrode 18 is electrically connected to, for example, a word line WL (not shown). The upper electrode 14 is electrically connected to, for example, a bit line BL (not shown). The plate electrode 72 is connected to, for example, a plate line PL (not shown).

[0189] The semiconductor memory 600 applies an oxide semiconductor transistor, which exhibits extremely low channel leakage current during off-operation, to the switching transistor TR. Therefore, a DRAM with excellent charge retention characteristics is realized.

[0190] Furthermore, the switching transistor TR of the semiconductor memory 600 has a highly reliable gate insulating layer 20. Therefore, the reliability of the semiconductor memory 600 is improved.

[0191] In the sixth embodiment, a semiconductor memory to which the transistor of the first embodiment is applied was described as an example, but the semiconductor memory of the embodiment of the present invention may also be a semiconductor memory to which the transistor of the second to fourth embodiments is applied.

[0192] In the sixth embodiment, the case in which the capacitor CA is electrically connected to the lower electrode 12 was described as an example, but the capacitor CA may also be electrically connected to the upper electrode 14.

[0193] According to the semiconductor memory device of the sixth embodiment, a semiconductor memory device with excellent transistor characteristics can be realized.

[0194] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0195] 12 Lower electrode (first electrode) 13. Lower electrode (third electrode) 14. Upper electrode (second electrode) 15 Upper electrode (fourth electrode) 16. Oxide semiconductor layer (first oxide semiconductor layer) 16a First area 16b Second area 17. Oxide semiconductor layer (second oxide semiconductor layer) 18 Guard gate 18a Part 1 18b Part 2 18c Third part 18x First layer 18y Second layer 20 Gate insulating layer 20a First membrane 20b Second membrane 100 Transistors (Semiconductor Devices) 200 Transistors (Semiconductor Equipment) 300 Transistors (Semiconductor Devices) 400 Transistors (Semiconductor Devices) 500 Transistors (Semiconductor Devices) 600 Semiconductor memory (semiconductor storage device) w1 First width w2 Second width CA Capacitor L1 First length L2 Second length L3 Third length L4, the fourth length

Claims

1. The first electrode and The second electrode and A first oxide semiconductor layer is provided between the first electrode and the second electrode, The third electrode and The fourth electrode and A second oxide semiconductor layer is provided between the third electrode and the fourth electrode, and is provided in a second direction perpendicular to the first direction connecting the first electrode and the second electrode, and is separated from the first oxide semiconductor layer. A gate electrode enclosing the first oxide semiconductor layer and the second oxide semiconductor layer and extending in the second direction, The gate insulating layer is provided between the gate electrode and the first oxide semiconductor layer, The aforementioned gate electrode includes a first part and a second part, The first portion faces the first oxide semiconductor layer in the second direction and is in contact with the gate insulating layer, and has a first length in the first direction. The second portion is separated from the first oxide semiconductor layer by a distance of half the distance between the first oxide semiconductor layer and the second oxide semiconductor layer in the second direction, and has a second length in the first direction. A semiconductor device in which the first length is longer than the second length.

2. The semiconductor device according to claim 1, wherein the gate insulating layer is provided between the gate electrode and the first electrode in the first direction.

3. The aforementioned gate electrode further includes a third portion, The third portion faces the first oxide semiconductor layer and is in contact with the gate insulating layer in a third direction perpendicular to the first and second directions, and has a third length in the first direction. The semiconductor device according to claim 1, wherein the third length is longer than the second length.

4. The first oxide semiconductor layer includes a first region and a second region provided between the first region and the second electrode, wherein the first region is in contact with the gate insulating layer in the first direction, and the second region is surrounded by the gate insulating layer. The semiconductor device according to claim 1, wherein in a cross section parallel to the first direction, the first width of the first region in a third direction perpendicular to the second direction is wider than the second width of the second region in the third direction.

5. The semiconductor device according to claim 4, wherein the gate insulating layer is provided between the first region and the gate electrode in the first direction.

6. The semiconductor device according to claim 4, wherein the difference between the first width and the second width is 1 nm or more and 20 nm or less.

7. The semiconductor device according to claim 1, wherein the gate insulating layer includes a first film and a second film having a different chemical composition from the first film and sandwiching the first film between itself and the first oxide semiconductor layer.

8. The semiconductor device according to claim 7, wherein the first film contains silicon oxide, and the second film contains a material with a dielectric constant higher than that of silicon oxide.

9. The semiconductor device according to claim 1, wherein the gate electrode includes a first layer and a second layer having a different chemical composition from the first layer and sandwiching the first layer between itself and the gate insulating layer.

10. The semiconductor device according to claim 9, wherein the electrical resistivity of the material contained in the second layer is lower than the electrical resistivity of the material contained in the first layer.

11. The aforementioned gate electrode further includes a third portion, The third portion faces the first oxide semiconductor layer and is in contact with the gate insulating layer in a third direction perpendicular to the first and second directions, and has a third length in the first direction. The semiconductor device according to claim 9, wherein the third length is shorter than the first length.

12. The device further comprises a first wiring layer provided in a third direction perpendicular to the first and second directions of the gate electrode, extending in the first direction and containing the same material as the gate electrode, The semiconductor device according to claim 1, wherein the fourth length in the first direction of the first wiring layer in a cross-section including the first oxide semiconductor layer, parallel to the first and third directions, is shorter than the first length.

13. The semiconductor device according to claim 12, wherein the gate insulating layer is in contact with the first wiring layer.

14. The semiconductor device according to claim 1, wherein the first electrode is separated from the gate insulating layer in the first direction.

15. The semiconductor device according to claim 1, A capacitor electrically connected to the first electrode or the second electrode, A semiconductor memory device equipped with the following features.

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