Liquid ejection device and print head drive circuit

Abstract

To provide a liquid dispensing device capable of driving a large number of drive elements at a high frequency. [Solution] A liquid dispensing device in which a first transistor included in an amplification circuit of a print head drive circuit that outputs a drive signal includes a first conductor as an emitter electrode, a second conductor as a base electrode, a third conductor as a collector electrode, a first layer including a first semiconductor region of a first conductivity type having a trench and a second semiconductor region of a second conductivity type provided in the trench, a second layer including a third semiconductor region of a second conductivity type, and a third layer including a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a second conductivity type located spaced apart from the fifth semiconductor region, wherein the first layer is positioned above the third conductor, the second layer is positioned above the first layer, the third layer is positioned above the second layer, the first conductor is positioned above the fifth semiconductor region, and the second conductor is positioned above the sixth semiconductor region.

Description

Technical Field

[0001] The present invention relates to a liquid ejection device and a print head drive circuit.

Background Art

[0002] A liquid ejection device such as an inkjet printer has a print head that ejects a liquid and a print head drive circuit that controls the print head. The print head drive circuit outputs a drive signal for driving a drive element such as a piezoelectric element provided in the print head, and the print head ejects ink by driving the drive element. In such a liquid ejection device, an image is formed on a medium by landing the ink ejected from the print head at a desired position on the medium.

[0003] For example, Patent Document 1 discloses a liquid ejection device having a head drive circuit that outputs a drive signal and a print head unit that ejects ink in response to the drive signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, in response to the market demand for improving productivity in liquid ejection devices, an improvement in the image formation speed with respect to a medium has been demanded for liquid ejection devices. Therefore, a print head drive circuit that ejects a liquid is required to output a drive signal capable of driving more drive elements at a higher frequency. However, the technique described in Patent Document 1 is not sufficient from the viewpoint of outputting a drive signal capable of driving many drive elements at a higher frequency, and there is room for improvement.

Means for Solving the Problems

[0006] One embodiment of the liquid dispensing device according to the present invention is: A print head that ejects liquid in response to a drive signal, A print head drive circuit that outputs the aforementioned drive signal, Equipped with, The print head drive circuit has an amplification circuit that outputs the drive signal amplified by the first transistor and the second transistor, The first transistor is, A first conductor that functions as an emitter electrode, A second conductor that functions as a base electrode, A third conductor that functions as a collector electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer including the third semiconductor region of the second conductivity type, A third layer including a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type located spaced apart from the fifth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The third layer is positioned above the second layer. The first conductor is positioned above the fifth semiconductor region. The second conductor is positioned above the sixth semiconductor region.

[0007] One embodiment of the print head drive circuit according to the present invention is: A print head drive circuit that outputs the drive signal to a print head that ejects liquid in response to the drive signal, The device includes an amplification circuit that outputs the drive signal amplified by the first and second transistors, The first transistor is, A first conductor that functions as an emitter electrode, A second conductor functioning as a base electrode, A third conductor functioning as a collector electrode, A first layer including a first semiconductor region of a first conductivity type having a trench and a second semiconductor region of a second conductivity type provided in the trench, A second layer including the second semiconductor region of the second conductivity type, A third layer including the fourth semiconductor region of the first conductivity type, the fifth semiconductor region of the first conductivity type, and the sixth semiconductor region of the second conductivity type located apart from the fifth semiconductor region, including The first layer is disposed above the third conductor, The second layer is disposed above the first layer, The third layer is disposed above the second layer, The first conductor is disposed above the fifth semiconductor region, The second conductor is disposed above the sixth semiconductor region.

Brief Description of the Drawings

[0008] [Figure 1] It is a diagram showing an example of the schematic configuration of a liquid ejection device. [Figure 2] It is a diagram showing an example of the functional configuration of a liquid ejection device. [Figure 3] It is a diagram showing the schematic structure of a discharge part. [Figure 4] It is a diagram showing an example of the signal waveforms of drive signals COMA, COMB, and COMC. [Figure 5] It is a diagram showing an example of the configuration of a selection control circuit and a selection circuit. [Figure 6] It is a diagram showing an example of the decoding content in a decoder. [Figure 7] It is a diagram showing an example of the configuration of a selection circuit. [Figure 8] It is a diagram for explaining the operations of a selection control circuit and a selection circuit. [Figure 9] It is a diagram showing an example of the configuration of a drive circuit. [Figure 10] It is a diagram showing an example of the operation of an amplification control circuit. [Figure 11] It is a diagram showing an example of the structure of the transistor 511. [Figure 12] It is a diagram showing a comparison result between an example of the current amplification factor of a conventional npn bipolar transistor and an example of the current amplification factor of the transistor 511 of the present embodiment.

Mode for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. Note that the embodiments described below do not unduly limit the content of the present invention described in the claims. Also, not all of the configurations described below are essential constituent elements of the present invention.

[0010] 1. Outline of the liquid ejection device FIG. 1 is a diagram showing an example of the schematic configuration of the liquid ejection device 1. The liquid ejection device 1 is a serial printing type inkjet printer that forms a desired image on the medium P by discharging ink as an example of a liquid, and the carriage 21 on which the print head 20 for discharging ink is mounted reciprocates along the scanning axis and discharges ink onto the medium P conveyed along the conveyance direction. As the medium P used in such a liquid ejection device 1, any printing target such as printing paper, resin film, cloth, etc. can be used. Note that the liquid ejection device 1 is not limited to a serial printing type inkjet printer, and may be a line printing type inkjet printer. Also, the liquid ejection device 1 is not limited to an inkjet printer, and may be a color material ejection device used for manufacturing color filters such as liquid crystal displays, an electrode material ejection device used for forming electrodes such as organic EL displays and FEDs (surface emission displays), a biological organic matter ejection device used for manufacturing biochips, a three-dimensional modeling device, and a printing device.

[0011] As shown in Figure 1, the liquid dispensing device 1 comprises an ink container 2, a control unit 10, a print head 20, a moving unit 30, and a transport unit 40.

[0012] The ink container 2 stores multiple types of ink that are dispensed onto the medium P. The colors of the ink stored in the ink container 2 include black, cyan, magenta, yellow, red, and gray. The ink container 2 can be an ink cartridge, a bag-shaped ink pack made of flexible film, or an ink tank that allows for ink replenishment.

[0013] The control unit 10 includes, for example, processing circuits such as a CPU (Central Processing Unit) and an FPGA (Field Programmable Gate Array), storage circuits such as semiconductor memory, and various other circuits, and controls each element of the liquid ejection device 1, including the print head 20.

[0014] The print head 20 is mounted on the carriage 21. The carriage 21 is fixed to an endless belt 32 included in the moving unit 30. In addition to the print head 20, the carriage 21 may also be equipped with an ink container 2.

[0015] The print head 20 mounted on the carriage 21 receives a control signal Ctrl-H and a drive signal COM, both output by the control unit 10, to control the print head 20. Ink stored in the ink container 2 is supplied to the print head 20 via a tube (not shown). The print head 20 then ejects the ink supplied from the ink container 2 based on the input control signal Ctrl-H and drive signal COM.

[0016] The moving unit 30 includes a carriage motor 31 and an endless belt 32. The carriage motor 31 is driven based on a control signal Ctrl-C input from the control unit 10. The endless belt 32 rotates in accordance with the drive of the carriage motor 31. As a result, the carriage 21 fixed to the endless belt 32 reciprocates along the scanning axis. That is, the print head 20 mounted on the carriage 21 reciprocates along the scanning axis that intersects the transport direction in which the medium P is transported.

[0017] The transport unit 40 includes a transport motor 41 and transport rollers 42. The transport motor 41 is driven based on a control signal Ctrl-T input from the control unit 10. The transport rollers 42 rotate in accordance with the drive of the transport motor 41. As the transport rollers 42 rotate, the medium P is transported in the transport direction.

[0018] In the liquid dispensing device 1 configured as described above, the transport unit 40 transports the medium P, and the moving unit 30 reciprocates the carriage 21, causing the print head 20 mounted on the carriage 21 to dispense ink onto the medium P. As a result, the ink dispensed from the print head 20 lands at any desired position on the surface of the medium P. Consequently, a desired image is formed on the medium P.

[0019] A specific example of the functional configuration of the liquid dispensing device 1, which is configured as described above, will now be explained. Figure 2 is a diagram showing an example of the functional configuration of the liquid dispensing device 1. As shown in Figure 2, the liquid dispensing device 1 has a control unit 10, a print head 20, a moving unit 30, and a transport unit 40.

[0020] The control unit 10 includes a control circuit 100, drive circuits 50a, 50b, 50c, and a reference voltage output circuit 52.

[0021] The control circuit 100 receives an image signal from an external device such as a host computer, generates various control signals corresponding to the image signal, and outputs them to the corresponding configuration.

[0022] Specifically, the control circuit 100 generates control signals Ctrl-T and Ctrl-C when an image signal is input and printing is performed on the medium P. The control signal Ctrl-T output by the control circuit 100 is input to the transport motor 41 included in the transport unit 40. The transport motor 41 is driven according to the control signal Ctrl-T. The medium P is transported along the transport direction by the driving force of this transport motor 41. The control signal Ctrl-C output by the control circuit 100 is input to the carriage motor 31 included in the moving unit 30. The carriage motor 31 is driven according to the control signal Ctrl-C. The carriage 21 on which the print head 20 is mounted moves back and forth along the scanning axis by the driving force of this carriage motor 31. The transport unit 40 may include one or more transport rotors in addition to the transport motor 41. The transport unit 40 may also include a transport motor driver circuit for converting the control signal Ctrl-T into a predetermined signal to drive the transport motor 41. Furthermore, the mobile unit 30 may include a carriage motor driver circuit for converting the control signal Ctrl-C into a predetermined signal for driving the carriage motor 31.

[0023] Furthermore, the control circuit 100 generates digital base drive signals dA, dB, and dC and outputs them to the corresponding drive circuits 50a, 50b, and 50c.

[0024] The base drive signal dA is input to the drive circuit 50a. The drive circuit 50a converts the input base drive signal dA from digital to analog, and generates a drive signal COMA as a drive signal COM by amplifying the converted analog signal in class AB, which is then output to the print head 20. The base drive signal dB is input to the drive circuit 50b. The drive circuit 50b converts the input base drive signal dB from digital to analog, and generates a drive signal COMB as a drive signal COM by amplifying the converted analog signal in class AB, which is then output to the print head 20. The base drive signal dC is input to the drive circuit 50c. The drive circuit 50c converts the input base drive signal dC from digital to analog, and generates a drive signal COMC as a drive signal COM by amplifying the converted analog signal in class AB, which is then output to the print head 20.

[0025] In other words, the control circuit 100 outputs base drive signals dA, dB, dC, which are the basis for the drive signals COMA, COMB, COMC, and the drive circuits 50a, 50b, 50c generate the drive signals COMA, COMB, COMC by performing Class AB amplification of the signal waveform defined by the input base drive signals dA, dB, dC, and output them to the print head 20.

[0026] Furthermore, the drive circuits 50a, 50b, and 50c may generate the corresponding drive signals COMA, COMB, and COMC by using Class B amplification instead of Class AB amplification, but it is preferable to use Class AB amplification from the viewpoint of improving the waveform accuracy of the output drive signals COMA, COMB, and COMC. Also, the base drive signals dA, dB, and dC are generated by the corresponding drive circuit 50 It is sufficient to define the signal waveforms of the drive signals COMA, COMB, and COMC output by a, 50b, and 50c, and these signals may be analog signals.

[0027] The reference voltage output circuit 52 generates a reference voltage signal VBS, which is a constant DC voltage with a voltage value of 5.5V, 6V, etc., and outputs it to the print head 20. The reference voltage signal VBS functions as the reference potential for driving the piezoelectric element 60, which will be described later, located in the print head 20. Note that the potential of the reference voltage signal VBS is not limited to 5.5V or 6V, but may also be the ground potential.

[0028] Furthermore, the control circuit 100 generates a control signal Ctrl-H, consisting of a clock signal SCK, a print data signal SI, and a latch signal LAT, based on the image signal input from an external device, and outputs them to the print head 20.

[0029] The print head 20 includes a selection control circuit 210, a plurality of selection circuits 230, and a plurality of ejection units 600. The plurality of ejection units 600 are provided corresponding to each of the plurality of selection circuits 230.

[0030] The selection control circuit 210 receives the clock signal SCK, print data signal SI, and latch signal LAT as control signals Ctrl-H. Based on the input clock signal SCK, print data signal SI, and latch signal LAT, the selection control circuit 210 generates a selection signal S corresponding to each of the multiple selection circuits 230 and outputs it to the corresponding selection circuit 230.

[0031] Each selection circuit 230 receives drive signals COMA, COMB, and COMC as drive signals COM, and a corresponding selection signal S output by the selection control circuit 210. Based on the input selection signal S, the selection circuit 230 generates a drive signal VOUT by selecting or deselecting each of the drive signals COMA, COMB, and COMC, and supplies the generated drive signal VOUT to the corresponding discharge unit 600.

[0032] Each of the multiple ejection units 600 includes a piezoelectric element 60. A drive signal VOUT, output by the corresponding selection circuit 230, is supplied to one end of the piezoelectric element 60 in each of the multiple ejection units 600. A reference voltage signal VBS, output by the reference voltage output circuit 52, is supplied to the other end of the piezoelectric element 60 in each of the multiple ejection units 600. The piezoelectric element 60 is driven according to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the drive of the piezoelectric element 60 is ejected from the ejection unit 600.

[0033] As described above, the liquid ejection device 1 of this embodiment comprises a print head 20 that ejects ink in accordance with drive signals COMA, COMB, and COMC, and a control unit 10 that includes drive circuits 50a, 50b, and 50c that output a drive signal COM. In other words, the drive circuits 50a, 50b, and 50c of the control unit 10 output drive signals COMA, COMB, and COMC to the print head 20 that ejects ink in accordance with the drive signals COMA, COMB, and COMC.

[0034] Here, an example of the structure of the ejection unit 600 of the print head 20 will be described. Figure 3 is a schematic diagram of one of the multiple ejection units 600 of the print head 20. As shown in Figure 3, the ejection unit 600 includes a piezoelectric element 60, a diaphragm 621, a cavity 631, and a nozzle 651.

[0035] Cavity 631 is filled with ink supplied from reservoir 641. In addition, ink is introduced into the reservoir 641 from the ink container 2 via an ink tube (not shown) and a supply port 661. That is, the cavity 631 is filled with the ink stored in the corresponding ink container 2.

[0036] The diaphragm 621 is displaced by the drive of the piezoelectric element 60 located on its upper surface in Figure 3. As the diaphragm 621 is displaced, the internal volume of the cavity 631, where the ink is filled, expands and contracts. In other words, the diaphragm 621 functions as a diaphragm that changes the internal volume of the cavity 631.

[0037] The nozzle 651 is provided on the nozzle plate 632 and is an opening that communicates with the cavity 631. As the internal volume of the cavity 631 changes, an amount of ink corresponding to the change in internal volume is ejected from the nozzle 651.

[0038] The piezoelectric element 60 has a structure in which a piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612. In a piezoelectric body 601 with this structure, the central portion of the electrodes 611 and 612 flexes vertically together with the diaphragm 621 in accordance with the potential difference of the signal supplied to the electrodes 611 and 612.

[0039] For example, a drive signal VOUT is supplied to one end of the piezoelectric element 60, to either electrode 611 or electrode 612, and a reference voltage signal VBS is supplied to the other end of the piezoelectric element 60, to the other electrode 611 or electrode 612. When the voltage value of the drive signal VOUT increases, the piezoelectric element 60 bends upward. As the piezoelectric element 60 bends upward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 expands. As a result, ink is drawn in from the reservoir 641. On the other hand, when the voltage value of the drive signal VOUT decreases, the piezoelectric element 60 bends downward. As the piezoelectric element 60 bends downward, the diaphragm 621 is displaced, and the internal volume of the cavity 631 shrinks. As a result, an amount of ink corresponding to the degree of shrinkage is ejected from the nozzle 651.

[0040] In other words, the ejection unit 600 includes a piezoelectric element 60 that is driven by a drive signal VOUT based on a drive signal COM, and the piezoelectric element 60 is driven to eject ink. In other words, the print head 20 ejects ink according to the drive signals COMA, COMB, and COMC.

[0041] In this embodiment, the liquid ejection device 1 is assumed to have a print head 20 with 3,000 or more ejection units 600, and drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the 3,000 or more ejection units 600, with the aim of improving the speed of image formation on the medium P and increasing productivity in the liquid ejection device 1. That is, the print head 20 is assumed to have 3,000 or more piezoelectric elements 60, and drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC to the 3,000 or more piezoelectric elements 60. This increases the amount of ink that can be ejected at once, which increases the number of dots that can be formed on the medium P at once, thereby improving the speed of image formation on the medium P and increasing productivity in the liquid ejection device 1. In other words, in the liquid ejection device 1 of this embodiment, the print head 20 includes 3,000 or more piezoelectric elements 60, and the 3,000 or more piezoelectric elements 60 are driven by drive signals COMA, COMB, COMC output by drive circuits 50a, 50b, 50c of the control unit 10.

[0042] Furthermore, the structure of the piezoelectric element 60 is not limited to the example shown in Figure 3, and any structure that allows ink to be ejected from the ejection unit 600 is acceptable. Therefore, the structure of the piezoelectric element 60 is not limited to the bending vibration structure described above, and for example, a structure using longitudinal vibration may also be used. Also, when the voltage value of the drive signal VOUT increases, the piezoelectric element 60 bends downward, and when the voltage value of the drive signal VOUT decreases... It may also be configured to bend upwards.

[0043] 2. Signal waveform of the drive signal Next, we will describe an example of the signal waveforms of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c. Figure 4 shows an example of the signal waveforms of the drive signals COMA, COMB, and COMC. As shown in Figure 4, each of the drive signals COMA, COMB, and COMC includes drive waveforms Adp, Bdp, and Cdp, which are arranged in the period tp from when the latch signal LAT rises until when the latch signal LAT rises again. Then, the selection control circuit 210 and the selection circuit 230 select one of the drive signals COMA, COMB, or COMC and one of the drive waveforms Adp, Bdp, or Cdp based on the clock signal SCK and the print data signal SI for each period tp, and output it as the drive signal VOUT.

[0044] As shown in Figure 4, the drive waveform Adp drives the corresponding piezoelectric element 60 by changing the voltage value between voltages va1 and va5 during the period tp. This driving of the piezoelectric element 60 causes a predetermined amount of ink to be ejected from the corresponding nozzle 651. In other words, the drive waveform Adp included in the drive signal COMA is a signal waveform for driving the corresponding piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejection unit 600. Hereinafter, in the explanation, we will assume that voltage va1 is 36V, voltage va2 is 15V, voltage va3 is 12V, voltage va4 is 8V, and voltage va5 is 5V, but the values ​​of voltages va1 to va5 are not limited to these.

[0045] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Adp is constant at voltage va3. Subsequently, the voltage value of the drive waveform Adp begins to rise at time ta1 and becomes constant at voltage va1 at time ta2. Then, the voltage value of the drive waveform Adp begins to fall at time ta3, becomes constant at voltage va2 at time ta4, begins to fall again at time ta5, and becomes constant at voltage va5 at time ta6. Subsequently, the voltage value of the drive waveform Adp begins to rise at time ta7, becomes constant at voltage va4 at time ta8, begins to rise again at time ta9, and becomes constant at voltage va3 at time ta10. After that, the period tp ends as the latch signal LAT rises.

[0046] In the ejection unit 600 to which the drive waveform Adp described above is supplied, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time ta1, when the voltage value of the drive waveform Adp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3.

[0047] Subsequently, at time ta2, the voltage value of the drive waveform Adp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the ejection unit 600. Then, at time ta3, when the voltage value of the drive waveform Adp decreases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied bends downward as shown in Figure 3, and the internal volume of the cavity 631 decreases. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, and a downward-extending liquid column is formed as shown in Figure 3. It will be accomplished.

[0048] At time ta4, when the voltage value of the drive waveform Adp becomes constant, the liquid column formed in the center of the meniscus tends to extend downward due to inertia, as shown in Figure 3. Then, at time ta5, the voltage value of the drive waveform Adp decreases, and the internal volume of the cavity 631 decreases, pressurizing the ink stored in the cavity 631. As a result, the ink separates from the liquid column and is ejected as droplets.

[0049] Subsequently, at time ta6, the voltage value of the drive waveform Adp becomes constant, and from time ta7 to ta10, the voltage value of the drive waveform Adp increases and becomes constant at voltage va3. As a result, the displacement of the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Adp is supplied, and the internal volume of the cavity 631, are in the state corresponding to the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 by capillary action. As a result, the position of the meniscus in the nozzle 651 of the ejection unit 600 at the timing of the rising edge of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0050] Furthermore, as shown in Figure 4, the drive waveform Bdp drives the corresponding piezoelectric element 60 by changing the voltage value between voltage vb1 and voltage vb5 during the period tp. This driving of the piezoelectric element 60 causes a smaller amount of ink than the predetermined amount described above to be ejected from the corresponding nozzle 651. In other words, the drive waveform Bdp included in the drive signal COMB is a signal waveform for driving the corresponding piezoelectric element 60 so that a smaller amount of ink than the predetermined amount is ejected from the ejection unit 600. Hereinafter, in the following explanation, we will assume that voltage vb1 is 36V, voltage vb2 is 20V, voltage vb3 is 12V, voltage vb4 is 10V, and voltage vb5 is 7V, but the values ​​of voltages vb1 to vb5 are not limited to these.

[0051] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Bdp is constant at voltage vb3. Subsequently, the voltage value of the drive waveform Bdp begins to rise at time tb1 and becomes constant at voltage vb1 at time tb2. Then, the voltage value of the drive waveform Bdp begins to fall at time tb3, becomes constant at voltage vb4 at time tb4, then begins to rise at time tb5, becomes constant at voltage vb2 at time tb6, then begins to fall at time tb7, and becomes constant at voltage vb5 at time tb8. Finally, the voltage value of the drive waveform Bdp begins to rise at time tb9 and becomes constant at voltage vb3 at time tb10. After that, the period tp ends as the latch signal LAT rises.

[0052] In the ejection unit 600 to which the drive waveform Bdp is supplied as described above, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the meniscus in the nozzle 651, which is the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, is approximately the same as the position of the tip of the nozzle 651. Then, at time tb1, when the voltage value of the drive waveform Bdp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied bends upward as shown in Figure 3, and the internal volume of the cavity 631 increases. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3.

[0053] Subsequently, at time tb2, the voltage value of the drive waveform Bdp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the discharge unit 600. Then, at time tb3, when the voltage value of the drive waveform Bdp decreases, the discharge unit 60 to which the drive waveform Bdp is supplied... At value 0, the piezoelectric element 60 bends downward as shown in Figure 3, reducing the internal volume of the cavity 631. This pressurizes the ink stored in the cavity 631, causing it to move toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming the downward-extending liquid column shown in Figure 3.

[0054] At time tb4, when the voltage value of the drive waveform Bdp becomes constant, the liquid column formed in the center of the meniscus tries to extend downward due to inertia, as shown in Figure 3. Then, at time tb5, as the voltage value of the drive waveform Bdp increases and the internal volume of the cavity 631 increases, the liquid column that was trying to extend downward due to inertia is pulled in. Subsequently, at time tb6, after the voltage value of the drive waveform Bdp becomes constant, at time tb7, as the voltage value of the drive waveform Bdp decreases, the internal volume of the cavity 631 decreases, the ink stored in the cavity 631 is pressurized, the ink separates from the liquid column and is ejected as droplets. At this time, at time tb5, the liquid column that was trying to extend downward as shown in Figure 3 is pulled in by inertial force, and then at time tb7, the pressurized ink droplets separated from the liquid column are ejected. As a result, the amount of ink ejected from the ejection unit 600 supplied with the drive waveform Bdp is less than the amount of ink ejected from the ejection unit 600 supplied with the drive waveform Adp.

[0055] Subsequently, at time tb8, the voltage value of the drive waveform Bdp becomes constant, and at times ta9 to tb10, the voltage value of the drive waveform Bdp increases and becomes constant at voltage vb3. As a result, the displacement of the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Bdp is supplied, and the internal volume of the cavity 631, are in the state corresponding to the rising edge of the latch signal LAT. At this time, an amount of ink corresponding to the amount of ink ejected is supplied from the ink container 2 to the cavity 631 via the supply port 661 by capillary action. As a result, the position of the meniscus in the nozzle 651 of the ejection unit 600 at the timing of the rising edge of the latch signal LAT is approximately the same as the position of the tip of the nozzle 651.

[0056] Furthermore, as shown in Figure 4, the drive waveform Cdp drives the corresponding piezoelectric element 60 by changing the voltage value between voltage vc1 and voltage vc2 during the period tp. This driving of the piezoelectric element 60 prevents ink from being ejected from the corresponding nozzle 651, and causes the ink near the opening of the nozzle 651 to vibrate. This reduces the risk of an increase in the viscosity of the ink near the opening of the nozzle 651. In other words, the drive waveform Cdp included in the drive signal COMC is a signal waveform for driving the piezoelectric element 60 so that ink is not ejected from the ejection unit 600, and the ink near the opening of the nozzle 651 of the ejection unit 600 vibrates. Hereinafter, in the following explanation, we will assume that voltage vc1 is 15V and voltage vc2 is 12V, but the values ​​of voltage vc1 and voltage vc2 are not limited to these.

[0057] Specifically, at the timing when the latch signal LAT rises, which marks the start of period tp, the voltage value of the drive waveform Cdp is constant at voltage vc2. Subsequently, the voltage value of the drive waveform Cdp begins to rise at time tc1 and becomes constant at voltage vc1 at time tc2. Then, the voltage value of the drive waveform Cdp begins to fall at time tc3 and becomes constant at voltage vc1 at time tc4. After that, the period tp ends when the latch signal LAT rises.

[0058] In the ejection unit 600 to which the drive waveform Cdp described above is supplied, at the timing when the latch signal LAT rises, the ink stored in the ink container 2 is supplied to the cavity 631 via the supply port 661. At this time, the position of the tip of the ink stored inside the nozzle 651 of the ejection unit 600, and the position of the meniscus in the nozzle 651, is approximately the same as the position of the tip of the nozzle 651. Then, at time tc1 When the voltage value of the drive waveform Cdp increases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Cdp is supplied bends upward as shown in Figure 3, increasing the internal volume of the cavity 631. As a result, the ink stored inside the nozzle 651 of the ejection unit 600 is drawn into the cavity 631, and the position of the meniscus in the nozzle 651 moves upward as shown in Figure 3. Subsequently, at time tc2, the voltage value of the drive waveform Bdp becomes constant, maintaining the position of the meniscus in the nozzle 651 of the ejection unit 600. Then, at time tc3, when the voltage value of the drive waveform Cdp decreases, the piezoelectric element 60 in the ejection unit 600 to which the drive waveform Cdp is supplied bends downward as shown in Figure 3, decreasing the internal volume of the cavity 631. As a result, the ink stored in the cavity 631 is pressurized and moves toward the corresponding nozzle 651. At this time, the central part of the meniscus formed by the ink stored inside the nozzle 651 is pushed out, forming a downward-extending liquid column as shown in Figure 3. Subsequently, at time tc4, the voltage value of the drive waveform Cdp becomes constant. At this time, the change in the voltage value of the drive waveform Cdp is smaller than the change in the voltage value of the drive waveform Adp and the change in the voltage value of the drive waveform Bdp, and therefore the ink does not separate from the liquid column. Consequently, the ink only vibrates from the nozzle 651 and is not ejected.

[0059] Furthermore, at time tc4, as the voltage value of the drive waveform Cdp becomes constant at voltage vc2, the displacement of the piezoelectric element 60 in the discharge section 600 to which the drive waveform Cdp is supplied, and the internal volume of the cavity 631, are in the rising edge state of the latch signal LAT.

[0060] As described above, the drive circuit 50a outputs a drive signal COMA including a drive waveform Adp that drives the piezoelectric element 60 so that a predetermined amount of ink is ejected from the ejection unit 600, the drive circuit 50b outputs a drive signal COMB including a drive waveform Bdp that drives the piezoelectric element 60 so that a smaller amount than a predetermined amount of ink is ejected from the ejection unit 600, and the drive circuit 50c outputs a drive signal COMC including a drive waveform Cdp that drives the piezoelectric element 60 so that no ink is ejected from the ejection unit 600, but the ink near the opening of the corresponding nozzle 651 vibrates. In the following description, when the drive waveform Adp is supplied to one end of the piezoelectric element 60, the amount of ink ejected from the corresponding ejection unit 600 may be referred to as a large amount, and when the drive waveform Bdp is supplied to one end of the piezoelectric element 60, the amount of ink ejected from the corresponding ejection unit 600 may be referred to as a small amount. Furthermore, when the drive waveform Cdp is supplied to one end of the piezoelectric element 60, the operation that vibrates the ink near the nozzle opening of the ejection unit 600 corresponding to the piezoelectric element 60 is sometimes referred to as micro-vibration.

[0061] Here, in the liquid ejection device 1 of this embodiment, in order to improve the speed of image formation on the medium P and to improve productivity in the liquid ejection device 1, it is assumed that the period tp in which ink is ejected from the ejection unit 600 by the drive signals COMA, COMB, COMC is 10 μs or less. That is, it is assumed that the frequency of the period tp of the drive signals COMA, COMB, COMC output by the drive circuits 50a, 50b, 50c is 100 kHz or higher. As a result, the liquid ejection device 1 of this embodiment can improve the speed of image formation on the medium P and improve productivity in the liquid ejection device 1. That is, the frequency of the drive signals COMA, COMB, COMC is 100 kHz or higher.

[0062] 3. Configuration and Operation of Selection Control Circuit and Selection Circuit Next, the configuration and operation of the selection control circuit 210 and selection circuit 230, which generate the drive signal VOUT by selecting or deselecting the signal waveforms included in the drive signals COMA, COMB, and COMC and outputting it to the corresponding ejection unit 600, will be described. Figure 5 shows an example of the configuration of the selection control circuit 210 and selection circuit 230. In the following description, the 3000 piezoelectric elements 60 in the print head 20 will be generalized and described as n piezoelectric elements 60.

[0063] The selection control circuit 210 receives a clock signal SCK, a print data signal SI, and a latch signal LAT. Furthermore, the selection control circuit 210 is equipped with a set of shift registers (S / R) 212, latch circuits 214, and decoders 216, each corresponding to one of the n piezoelectric elements 60. In other words, the selection control circuit 210 includes n shift registers 212, n latch circuits 214, and n decoders 216.

[0064] The print data signal SI is input to the selection control circuit 210 in synchronization with the clock signal SCK. The print data signal SI also serially includes 2 bits of print data [SIH,SIL] corresponding to each of the n piezoelectric elements 60 for selecting one of the following: "large dot LD", "small dot SD", "non-recorded ND", and "micro-vibration BSD". The print data [SIH,SIL] included in the print data signal SI is held in n shift registers 212 corresponding to the n piezoelectric elements 60. Specifically, the n shift registers 212 corresponding to the piezoelectric elements 60 are connected in cascading order, and the serially input print data signal SI is sequentially transferred to the subsequent shift registers 212 according to the clock signal SCK. When the print data [SIH,SIL] is held in the corresponding shift register 212, the clock signal SCK stops. As a result, the print data [SIH,SIL] included in the print data signal SI is held in the corresponding shift register 212. In Figure 5, the n shift registers 212 are labeled as 1st stage, 2nd stage, ..., nth stage in order from the upstream side where the print data signal SI is input, in order to distinguish them.

[0065] Each of the n latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the corresponding shift register 212 on the rising edge of the latch signal LAT. The print data [SIH,SIL] latched by the latch circuits 214 is then input to the corresponding decoder 216. Figure 6 shows an example of the decoding content in the decoder 216. At period tp, the decoder 216 outputs selection signals S1, S2, and S3 as selection signals S of a logic level defined by the input print data [SIH,SIL]. For example, if print data [SIH,SIL]=[1,0] is input to the decoder 216, the decoder 216 outputs an L-level selection signal S1, an H-level selection signal S2, and an L-level selection signal S3 at period tp.

[0066] The selection signals S1, S2, and S3 output by the decoder 216 are input to the selection circuit 230. The selection circuit 230 is provided corresponding to each of the n output units 600. Figure 7 shows an example of the configuration of the selection circuit 230. As shown in Figure 7, the selection circuit 230 includes inverters 232a, 232b, and 232c, which are NOT gates, and transfer gates 234a, 234b, and 234c.

[0067] The selection signal S1 is input to the positive control terminal of the transfer gate 234a that is not marked with a circle, and after its logic level is inverted by the inverter 232a, it is also input to the negative control terminal of the transfer gate 234a that is marked with a circle. In addition, the drive signal COMA is supplied to the input terminal of the transfer gate 234a. The transfer gate 234a conducts between its input terminal and output terminal when a high-level selection signal S1 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S1 is input. That is, the transfer gate 234a outputs the drive waveform Adp included in the drive signal COMA from its output terminal when the logic level of the selection signal S1 is high, and does not output the drive waveform Adp included in the drive signal COMA from its output terminal when the logic level of the selection signal S1 is low.

[0068] The selection signal S2 is input to the positive control terminal of the transfer gate 234b that is not marked with a circle, and after its logic level is inverted by the inverter 232b, The negative control terminal, marked with a circle, is also input to the transfer gate 234b. Additionally, the drive signal COMB is supplied to the input terminal of the transfer gate 234b. The transfer gate 234b conducts between its input and output terminals when a high-level selection signal S2 is input, and deconducts between its input and output terminals when a low-level selection signal S2 is input. That is, the transfer gate 234b outputs the drive waveform Bdp included in the drive signal COMB from its output terminal when the logic level of the selection signal S2 is high, and does not output the drive waveform Bdp included in the drive signal COMB from its output terminal when the logic level of the selection signal S2 is low.

[0069] The selection signal S3 is input to the positive control terminal of the transfer gate 234c that is not marked with a circle, and after its logic level is inverted by the inverter 232c, it is also input to the negative control terminal of the transfer gate 234c that is marked with a circle. In addition, the drive signal COMC is supplied to the input terminal of the transfer gate 234c. The transfer gate 234c conducts between its input terminal and output terminal when a high-level selection signal S3 is input, and does not conduct between its input terminal and output terminal when a low-level selection signal S3 is input. That is, the transfer gate 234c outputs the drive waveform Cdp included in the drive signal COMC from its output terminal when the logic level of the selection signal S3 is high, and does not output the drive waveform Cdp included in the drive signal COMC from its output terminal when the logic level of the selection signal S3 is low.

[0070] Then, in the selection circuit 230, the output terminals of transfer gate 234a, transfer gate 234b, and transfer gate 234c are connected in common. The signal at this connection point where the output terminals of transfer gate 234a, transfer gate 234b, and transfer gate 234c are connected in common is output as the drive signal VOUT.

[0071] Here, the operation of the selection control circuit 210 and the selection circuit 230 will be explained using Figure 8. Figure 8 is a diagram illustrating the operation of the selection control circuit 210 and the selection circuit 230. The print data signal SI is input to the selection control circuit 210 as a serial signal synchronized with the clock signal SCK, and in synchronization with the clock signal SCK, it is sequentially transferred to the n shift registers 212 corresponding to the n piezoelectric elements 60. After that, when the input of the clock signal SCK stops, the shift registers 212 hold the print data [SIH, SIL] corresponding to each of the n piezoelectric elements 60. The print data signal SI is input in the order corresponding to the nth, ..., 2nd, and 1st stages of the piezoelectric elements 60 in the shift registers 212.

[0072] Then, when the latch signal LAT rises, each of the latch circuits 214 simultaneously latches the print data [SIH,SIL] held in the shift register 212. Note that LT1, LT2, ..., LTn shown in Figure 8 represent the print data [SIH,SIL] latched by the latch circuits 214 corresponding to the 1st, 2nd, ..., nth stage shift register 212.

[0073] The decoder 216 outputs selection signals S1, S2, and S3, whose logic levels are defined by the latched print data [SIH, SIL], at each period tp. The selection circuit 230 then generates the drive signal VOUT by selecting or deselecting the drive signals COMA, COMB, and COMC according to the logic levels of the selection signals S1, S2, and S3 output by the decoder 216.

[0074] Specifically, when the printed data [SIH,SIL]=[1,1] is input to the decoder 216, the decoder 216 sets the logic levels of the selection signals S1, S2, S3 at period tp to H, L, L levels. As a result, the selection circuit 230 is driven at period tp. A drive signal VOUT, including the waveform Adp, is supplied to the piezoelectric element 60 of the corresponding ejection unit 600. As a result, a large amount of ink is ejected from the corresponding ejection unit 600. This large amount of ink ejected from the ejection unit 600 lands on the medium P, forming a large dot LD on the medium P.

[0075] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[1,0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to L, H, and L levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Bdp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, a small amount of ink is ejected from the corresponding ejection unit 600. This small amount of ink ejected from the ejection unit 600 lands on the medium P, forming small dots SD on the medium P.

[0076] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[0,1], the decoder 216 sets the logic levels of the selection signals S1, S2, S3 at period tp to L, L, L. As a result, the selection circuit 230 does not select any of the drive waveforms Adp, Bdp, or Cdp at period tp. At this time, the piezoelectric element 60 of the corresponding ejection unit 600 is supplied with a signal of a constant voltage value held by the capacitive component of the piezoelectric element 60. That is, at period tp, the selection circuit 230 supplies a drive signal VOUT of a constant voltage value to the piezoelectric element 60 of the corresponding ejection unit 600. As a result, the piezoelectric element 60 of the corresponding ejection unit 600 is not driven, and no ink is ejected from this ejection unit 600. Therefore, no ink lands on the medium P, and non-recording ND is performed, which does not form dots on the medium P.

[0077] Furthermore, when the decoder 216 receives print data [SIH,SIL]=[0,0], the decoder 216 sets the logic levels of the selection signals S1, S2, and S3 at period tp to L, L, and H levels. As a result, the selection circuit 230 supplies a drive signal VOUT, including the drive waveform Cdp, to the piezoelectric element 60 of the corresponding ejection unit 600 at period tp. Consequently, no ink is ejected from the corresponding ejection unit 600, and a micro-vibration BSD is performed, which vibrates the ink near the opening of the nozzle 651 of the ejection unit 600.

[0078] As described above, the selection control circuit 210 and the selection circuit 230 generate the drive signal VOUT by selecting or deselecting the signal waveforms of the drive signals COMA, COMB, and COMC output by the drive circuits 50a, 50b, and 50c, and output it to the piezoelectric element 60 of the corresponding discharge unit 600.

[0079] 4. Configuration and Operation of the Drive Circuit As described above, in the liquid dispensing device 1 of this embodiment, in response to market demands for improved productivity, the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC of a high frequency of 100 kHz or higher to a large number of piezoelectric elements 60, which number 3,000 or more.

[0080] If a conventional Class AB amplifier circuit were to be used as a drive circuit to supply such high-frequency drive signals to a large number of drive elements, the liquid dispensing device would have a large number of drive elements such as piezoelectric elements. As a result, it would not be possible to supply sufficient current to these drive elements, which could lead to a decrease in the driving accuracy of the drive elements and thus a decrease in the liquid dispensing accuracy.

[0081] Furthermore, when a conventional Class D amplifier circuit configuration is applied as a drive circuit that supplies high-frequency drive signals to a large number of drive elements, the drive elements such as piezoelectric elements in the liquid discharge device Due to their large number, the amount of current flowing through the switching elements constituting a Class D amplifier circuit increases. As a result, the amount of heat generated in these switching elements increases, leading to a problem of reduced reliability of the drive circuit. In particular, in a Class D amplifier circuit, because the switching operation of the switching elements amplifies the signal that is modulated from the base drive signal that forms the basis of the drive signal, if the frequency of the output drive signal is 100 kHz or higher, the drive frequency of the switching elements may exceed 10 MHz. As a result, the amount of heat generated in these switching elements increases significantly, potentially further reducing the reliability of the drive circuit.

[0082] In addressing this problem, when applying a circuit configuration using a conventional Class D amplifier circuit, it is possible to reduce the switching loss in the switching element and thus reduce the amount of heat generated by the switching element by lowering the drive frequency of the switching element in the Class D amplifier circuit. However, in a configuration where a piezoelectric element 60 is used as the drive element, as in the liquid ejection device 1 shown in this embodiment, it is necessary to finely control the displacement of the piezoelectric element 60 during the ejection cycle in order to precisely control the amount of ink ejected. Therefore, the voltage value of the drive signal changes significantly in a short time, as shown in Figure 4. As a result, when the frequency of the drive signal is high, such as 100 kHz or higher, the change in the voltage value of the drive signal may exceed 20 V per 1 μs, and the period during which the voltage value of the drive signal remains constant may be less than 0.3 μs. Therefore, if the drive frequency of the switching element constituting the Class D amplifier circuit that outputs the drive signal is lowered, it becomes impossible to secure a sufficient number of samples, resulting in a decrease in the waveform accuracy of the output drive signal and a decrease in the liquid ejection accuracy.

[0083] In other words, if a conventional Class D amplifier circuit configuration were applied as a drive circuit that supplies high-frequency drive signals to a large number of drive elements, a problem arose in that it became difficult to achieve both a reduction in the heat generated by the switching elements constituting the Class D amplifier circuit and an improvement in the waveform accuracy of the output drive signal.

[0084] In response to the aforementioned problems, the liquid discharge device 1 and drive circuits 50a, 50b, and 50c of this embodiment utilize Class AB amplifier circuits as the circuit configuration for the drive circuits 50a, 50b, and 50c to meet market demands for increased productivity. Furthermore, the transistors constituting these Class AB amplifier circuits have a distinctive structure that enables high current amplification. As a result, even when the drive circuits 50a, 50b, and 50c supply drive signals COMA, COMB, and COMC with a high frequency of 100 kHz or higher to a large number of piezoelectric elements 60, including 3,000 or more piezoelectric elements 60, the amount of heat generated by the drive circuits 50a, 50b, and 50c can be reduced. Moreover, sufficient current can be supplied to the large number of piezoelectric elements 60, and the risk of a decrease in the waveform accuracy of the drive signals COMA, COMB, and COMC can be reduced. This makes it possible to realize drive circuits 50a, 50b, and 50c that can supply high-frequency drive signals COMA, COMB, and COMC to a large number of piezoelectric elements 60, and as a result, the productivity of the liquid dispensing device 1 having these drive circuits 50a, 50b, and 50c can be improved.

[0085] The configuration and operation of the drive circuits 50a, 50b, and 50c of the liquid dispensing device 1 of this embodiment will now be described. Here, the drive circuits 50a, 50b, and 50c have the same configuration, differing only in the input signals and output signals. Therefore, in the following description, the drive circuits 50a, 50b, and 50c will not be distinguished and will simply be referred to as drive circuit 50. In this description, the drive circuit 50 will be described as receiving a base drive signal dO as base drive signals dA, dB, and dC, and outputting a drive signal COM as drive signals COMA, COMB, and COMC.

[0086] Figure 9 shows an example of the configuration of the drive circuit 50. As shown in Figure 9, the drive circuit 50 has an amplification control circuit 500 and an amplification circuit 510.

[0087] The amplification control circuit 500 includes a memory 501, a latch circuit 502, an adder 503, a latch circuit 504, a D / A converter 505, and a drive circuit 506. The amplification control circuit 500 also receives the voltage change amount data dDATA, a latch signal dLAT, and a clock signal dCK as the base drive signal dO output from the control circuit 100.

[0088] The voltage change data dDATA is input to memory 501. Memory 501 holds the voltage change information Dv contained in the input voltage change data dDATA. The latch signal dLAT is input to latch circuit 502. At the rising edge of the input latch signal dLAT, latch circuit 502 latches the voltage change information Dv held in memory 501. Then, latch circuit 502 outputs the latched voltage change information Dv to adder 503.

[0089] The adder 503 receives not only the voltage change amount information Dv output by the latch circuit 502, but also the signal output by the latch circuit 504, which will be described later. The adder 503 calculates and stores the summed voltage change amount information by adding the voltage change amount information Dv to the signal output by the latch circuit 504.

[0090] The clock signal dCK is input to the latch circuit 504. The latch circuit 504 latches the summation voltage change information held by the adder 503 at the rising edge of the clock signal dCK. The latch circuit 504 then outputs the latched summation voltage change information to the adder 503 and the D / A converter 505. In other words, the adder 503 calculates and holds new summation voltage change information by adding the voltage change information Dv latched by the latch circuit 502 to the summation voltage change information latched by the latch circuit 504.

[0091] The D / A converter 505 converts the summation voltage change information output by the latch circuit 504 into an analog signal and outputs it to the drive circuit 506 as a drive waveform signal WS. The signal waveform obtained by amplifying this drive waveform signal WS corresponds to the signal waveform of the drive signal COM.

[0092] The drive circuit 506 receives a drive waveform signal WS output by the D / A converter 505, as well as a voltage signal Vamp with a predetermined voltage value that is input to the amplifier circuit 510. Based on the drive waveform signal WS and the voltage signal Vamp, the drive circuit 506 generates amplification control signals Hdr and Ldr and outputs them to the amplifier circuit 510. Here, the voltage value of the voltage signal Vamp is greater than or equal to the maximum voltage value of the drive waveforms Adp, Bdp, and Cdp included in the drive signals COMA, COMB, and COMC.

[0093] The operation of the amplification control circuit 500 configured as described above will now be explained. Figure 10 shows an example of the operation of the amplification control circuit 500. As shown in Figure 10, at time t0, the control circuit 100 generates voltage change amount data dDATA, which includes voltage change amount information Dv1 for changing the voltage value by voltage ΔV1, as the base drive signal dO, and outputs it to the memory 501. As a result, the voltage change amount information Dv1 is stored in the memory 501.

[0094] Then, at time t1, the control circuit 100 sets the logic level of the latch signal dLAT, which is the base drive signal dO, to high. As a result, the voltage change amount information Dv1 held in memory 501 is latched by the latch circuit 502. Subsequently, at time t3, the control circuit 100 outputs voltage change amount data dDATA, which includes voltage change amount information Dv0 for maintaining a constant voltage value, to memory 501 as the base drive signal dO. In other words, memory 501 now holds voltage change amount information Dv0 instead of voltage change amount information Dv1.

[0095] At time t1, the voltage change information Dv1 latched by the latch circuit 502 is input to the adder 503. The adder 503 then processes the summation voltage change information output by the latch circuit 504. The voltage change amount information Dv1 latched by the latch circuit 502 is added and stored as new added voltage change amount information.

[0096] Furthermore, the control circuit 100 generates a clock signal dCK, which is at a high level every period ΔT, as the base drive signal dO, and outputs it to the latch circuit 504. Then, at times t2, t4, and t5, when a high-level clock signal dCK is input to the latch circuit 504, the latch circuit 504 latches information on the summation voltage change amount, in which the voltage value increases by voltage ΔV1 each time a high-level clock signal dCK is input, and outputs it to the D / A converter 505. As a result, the D / A converter 505 generates and outputs a drive waveform signal WS, in which the voltage value increases by voltage ΔV1 at times t2, t4, and t5.

[0097] At the time t6, the control circuit 100 sets the logic level of the latch signal dLAT, which is the base drive signal dO, to high. As a result, the voltage change amount information Dv0, which is necessary to keep the voltage value held in memory 501 constant, is latched by the latch circuit 502. Then, at the time t8, the control circuit 100 generates voltage change amount data dDATA, which includes voltage change amount information Dv2 for changing the voltage value by voltage -ΔV2, as the base drive signal dO, and outputs it to memory 501. In other words, memory 501 now holds voltage change amount information Dv2 instead of voltage change amount information Dv0.

[0098] The voltage change amount information Dv0 latched by the latch circuit 502 is input to the adder 503. The adder 503 adds the voltage change amount information Dv0 latched by the latch circuit 502 to the added voltage change amount information output by the latch circuit 504 and stores it as new added voltage change amount information.

[0099] Furthermore, at times t7 and t9, a high-level clock signal dCK is input to the latch circuit 504. At this time, the voltage change amount information Dv0 latched by the latch circuit 502 is information for maintaining a constant voltage value. Therefore, even when a high-level clock signal dCK is input, the latch circuit 504 latches the summation voltage change amount information, which does not change the voltage value, and outputs it to the D / A converter 505. As a result, the D / A converter 505 generates and outputs a drive waveform signal WS with a constant voltage value at times t7 and t9.

[0100] Then, at time t10, the control circuit 100 sets the logic level of the latch signal dLAT to high as the base drive signal dO. As a result, the voltage change amount information Dv2, which is used to change the voltage value held in memory 501 by voltage -ΔV2, is latched by the latch circuit 502.

[0101] The voltage change information Dv2 latched by the latch circuit 502 is input to the adder 503. The adder 503 then adds the voltage change information Dv2 latched by the latch circuit 502 to the added voltage change information output by the latch circuit 504 and stores it as new added voltage change information.

[0102] Furthermore, the control circuit 100 generates a clock signal dCK, which is at a high level every period ΔT, as the base drive signal dO, and outputs it to the latch circuit 504. Then, at times t11 and t12, when a high-level clock signal dCK is input to the latch circuit 504, the latch circuit 504 latches summation voltage change information, in which the voltage value decreases by voltage ΔV2 each time a high-level clock signal dCK is input, and outputs it to the D / A converter 505. As a result, the D / A converter 505 generates and outputs a drive waveform signal WS, in which the voltage value decreases by voltage ΔV2 at times t11 and t12.

[0103] As described above, the drive circuit 506 increases the voltage value based on the base drive signal dO. A drive waveform signal WS with a constant voltage, a drive waveform signal WS with a decreasing voltage, and a drive waveform signal WS with a constant voltage are input. This allows the waveform shape of the drive waveform signal WS input to the drive circuit 506 to be arbitrarily set according to the base drive signal dO output by the control circuit 100.

[0104] The drive circuit 506 generates an amplified drive waveform signal by voltage amplified based on the voltage signal Vamp of the input drive waveform signal WS. At this time, the waveform shape of the amplified drive waveform signal generated by the drive circuit 506 is the same as the waveform shapes of the drive waveforms Adp, Bdp, and Cdp included in the drive signals COMA, COMB, and COMC shown in Figure 4.

[0105] The drive circuit 506 then generates an amplification control signal Hdr, which is obtained by adding a predetermined voltage bias voltage to the amplified drive waveform signal, and an amplification control signal Ldr, which is obtained by subtracting a predetermined voltage bias voltage from the amplified drive waveform signal, and outputs these to the amplifier circuit 510. Here, it is preferable that the voltage value of the bias voltage added to the amplified drive waveform signal is determined according to the voltage value of the base-emitter saturation voltage of transistor 511 in the amplifier circuit 510 (described later), and the voltage value of the bias voltage subtracted from the amplified drive waveform signal is determined according to the voltage value of the base-emitter saturation voltage of transistor 512 in the amplifier circuit 510 (described later). This reduces the risk of distortion occurring in the signal waveform of the output drive signal COM.

[0106] In this embodiment, the voltage change data dDATA included in the base drive signal dO input to the amplification control circuit 500 in the liquid dispensing device 1 was described as data indicating the change in the voltage value of the drive waveform signal WS for each period of the clock signal dCK. However, the voltage change data dDATA included in the base drive signal dO may also be data indicating the absolute value of the voltage value of the drive waveform signal WS for each period of the clock signal dCK.

[0107] By making the voltage change data dDATA included in the base drive signal dO data that shows the change in the voltage value of the drive waveform signal WS for each period of the clock signal dCK, it is possible to reduce the amount of data in the voltage change data dDATA included in the base drive signal dO, and as a result, the transmission speed of the voltage change data dDATA included in the base drive signal dO can be increased. On the other hand, if the voltage change data dDATA included in the base drive signal dO is data that shows the absolute value of the voltage value of the drive waveform signal WS for each period of the clock signal dCK, the amplification control circuit 500 does not need to have an adder 503 or a latch circuit 504, and as a result, the amplification control circuit 500 can be made smaller.

[0108] Returning to Figure 9, the amplification circuit 510 includes transistors 511 and 512. In this embodiment, transistor 511 is an NPN bipolar transistor, and transistor 512 is a PNP bipolar transistor. In this case, it is preferable that transistors 511 and 512 form a complementary pair.

[0109] The collector terminal of transistor 511 is input to a voltage signal Vamp. The base terminal of transistor 511 is input to an amplification control signal Hdr. The emitter terminal of transistor 511 is electrically connected to the emitter terminal of transistor 512. The base terminal of transistor 512 is input to an amplification control signal Ldr. The collector terminal of transistor 512 is input to ground potential Gnd. The amplification circuit 510 outputs the signal at the connection point where the emitter terminals of transistor 511 and transistor 512 are connected as the drive signal COM.

[0110] In such an amplification circuit 510, when the voltage value of the drive waveform signal WS increases, When the voltage value of the amplified drive waveform signal, obtained by voltage amplified from the drive waveform signal WS, rises, the collector terminal and emitter terminal of transistor 511 are controlled to conduct, and the emitter terminal and collector terminal of transistor 512 are controlled to not conduct. At this time, a current based on the voltage signal Vamp is supplied to the plurality of piezoelectric elements 60 connected to the connection point where the emitter terminals of transistor 511 and transistor 512 are electrically connected, via transistor 511. As a result, due to the capacitive component of the piezoelectric elements 60, the voltage value at the connection point where the emitter terminals of transistor 511 and transistor 512 are electrically connected, which is the voltage value of the drive signal COM output by the amplification circuit 510, rises in accordance with the voltage value of the amplified drive waveform signal.

[0111] Furthermore, if the voltage value of the drive waveform signal WS decreases, and the voltage value of the amplified drive waveform signal obtained by voltage amplified from the drive waveform signal WS decreases, the collector terminal and emitter terminal of transistor 511 are controlled to be non-conductive, and the emitter terminal and collector terminal of transistor 512 are controlled to be conductive. At this time, the charge stored in the plurality of piezoelectric elements 60 connected to the connection point where the emitter terminals of transistor 511 and transistor 512 are electrically connected is released to ground potential Gnd via transistor 512. As a result, the voltage value at the connection point where the emitter terminals of transistor 511 and transistor 512 are electrically connected, which is the voltage value of the drive signal COM output by the amplification circuit 510, decreases in accordance with the voltage value of the amplified drive waveform signal.

[0112] Furthermore, when the voltage value of the drive waveform signal WS is constant, and the voltage value of the amplified drive waveform signal obtained by voltage amplified from the drive waveform signal WS is constant, the collector terminal and emitter terminal of transistor 511 are controlled to be non-conductive, and the emitter terminal and collector terminal of transistor 512 are controlled to be non-conductive. At this time, the voltage value of the drive signal COM output by the amplification circuit 510, which is the voltage value at the connection point where the emitter terminal of transistor 511 and the emitter terminal of transistor 512 are connected, is maintained by the capacitive component of the piezoelectric element 60 connected to the connection point. That is, the voltage value of the drive signal COM output by the amplification circuit 510, which is the voltage value at the connection point where the emitter terminal of transistor 511 and the emitter terminal of transistor 512 are electrically connected, is maintained at the same voltage value as the amplified drive waveform signal.

[0113] As described above, in the liquid dispensing device 1 of this embodiment, the drive circuit 50 has an amplification control circuit 500 and an amplification circuit 510. The amplification control circuit 500 defines the signal waveform of the drive signal COM based on the base drive signal dO, and the amplification circuit 510 outputs a drive signal COM that can drive the plurality of piezoelectric elements 60 of the print head 20 by current amplification of the signal waveform of the drive signal COM defined by the amplification control circuit 500.

[0114] As described above, the drive circuit 50 of the control unit 10 includes push-pull connected transistors 511 and 512, and has an amplification circuit 510 that current-amplifies an amplified drive waveform signal, which is a signal waveform defined by the base drive signal dO that forms the basis of the drive signal COM, and the voltage value of the drive waveform signal WS, based on the voltage signal Vamp, and outputs it as the drive signal COM.

[0115] In such a drive circuit 50, if sufficient current cannot be supplied to the multiple piezoelectric elements 60 of the print head 20, or if sufficient charge cannot be discharged from the multiple piezoelectric elements 60 of the print head 20, distortion may occur in the signal waveform of the output drive signal COM, potentially reducing the drive accuracy of the piezoelectric elements 60 and the ink ejection accuracy from the ejection unit 600. The amount of current supplied from the drive circuit 50 to the multiple piezoelectric elements 60 is limited by the current amplification factor of the transistor 511, and the amount of current supplied from the multiple piezoelectric elements 60 to the drive circuit 50 is The amount of charge discharged from the multiple piezoelectric elements 60 is limited by the current amplification factor of the transistor 512. Therefore, in the drive circuit 50 of this embodiment, which has a large number of piezoelectric elements 60 and outputs a drive signal COM to 3000 or more piezoelectric elements 60, the transistors 511 and 512 have a characteristic structure that enables a large current amplification factor, with respect to the waveform accuracy of the output drive signal COM, which improves the drive accuracy of the piezoelectric elements 60 and the ink ejection accuracy from the ejection unit 600.

[0116] An example of the structure of transistors 511 and 512 will be described. Figure 11 shows an example of the structure of transistor 511. In describing the structure of transistor 511, mutually orthogonal X and Y axes will be used. In the following description, the starting point of the X-axis arrow shown in the diagram will be referred to as the -X side and the tip as the +X side, and the starting point of the Y-axis arrow shown in the diagram will be referred to as the -Y side and the tip as the +Y side.

[0117] As shown in Figure 11, the transistor 511 has layers 701 to 704 stacked along the Y-axis from the +Y side to the -Y side, an emitter electrode 721, a base electrode 722, and a collector electrode 723. In this case, layers 701 to 704 are stacked along the Y-axis from the +Y side to the -Y side in the order of layer 701, layer 702, layer 703, and layer 704. Layer 701 includes an n-type semiconductor layer 715, a p-type well 716, and an n-type well 717; layer 702 includes a p-type channel layer 714; layer 703 includes an n-type column layer 712 and a p-type column layer 713; and layer 704 includes an n-type semiconductor layer 711. In the following explanation, the n-type semiconductor layer 711 included in layer 704, the n-type column layer 712 and p-type column layer 713 included in layer 703, and the p-type channel layer 714 included in layer 702 may be collectively referred to as the semiconductor substrate 710.

[0118] The n-type semiconductor layer 711 contained in layer 704 is an n-type semiconductor layer located on the -Y side of the semiconductor substrate 710. The n-type column layer 712 contained in layer 703 is an n-type semiconductor layer, and the p-type column layer 713 is a p-type semiconductor layer. The n-type column layer 712 is located on the +Y side of layer 704 and has a plurality of trenches 733 formed from the +Y side surface toward the -Y side. The p-type column layer 713 is provided in each of the plurality of trenches 733 of the n-type column layer 712. Specifically, the n-type column layer 712 is an n-type semiconductor layer formed on the +Y side of the n-type semiconductor layer 711 of the semiconductor substrate 710 and has a plurality of trenches 733 aligned along the X axis. The p-type column layer 713 is a p-type semiconductor layer formed by epitaxially growing p-type crystals in the trenches 733. In other words, the n-type column layer 712 and the p-type column layer 713 are located on the +Y side of the n-type semiconductor layer 711 and are adjacent to each other, alternating in the direction along the X-axis. In other words, the semiconductor substrate 710 includes a plurality of n-type column layers 712 and a plurality of p-type column layers 713, and the plurality of n-type column layers 712 and a plurality of p-type column layers 713 are arranged alternately in the direction along the X-axis. This forms a column region on the semiconductor substrate 710. The p-type channel layer 714 included in layer 702 is a p-type semiconductor layer, located on the +Y side of layer 703 which includes the column region, and is in contact with the n-type column layer 712 and the p-type column layer 713 included in the column region.

[0119] The n-type semiconductor layer 715 contained in layer 701 is an n-type semiconductor layer located on the +Y side of layer 702. This n-type semiconductor layer 715 is an n-type semiconductor layer formed by, for example, epitaxial growth. The p-type well 716 and n-type well 717 are n-type diffusion layers formed by doping the n-type semiconductor layer 715 with impurities. Specifically, the p-type well 716 is a p-type diffusion layer formed so as to reach the p-type channel layer 714 from the +Y side surface of the n-type semiconductor layer 715, and the n-type well 717 is a p-type diffusion layer formed on the +Y side surface of the n-type semiconductor layer 715. In this case, the p-type well 716 is provided so as to be in contact with the p-type channel layer 714, and the n-type well 717 is formed by the n-type semiconductor layer 715. It is provided spaced apart from the p-type channel layer 714 and the p-type well 716.

[0120] Here, the impurity concentration of the n-type semiconductor layer 715 is lower than that of the n-type column layer 712, the impurity concentration of the n-type semiconductor layer 711 and the impurity concentration of the n-type well 717 are higher than that of the n-type column layer 712, and the impurity concentration of the p-type channel layer 714 and the impurity concentration of the p-type well 716 are higher than that of the p-type column layer 713.

[0121] The base electrode 722 is located on the +Y side of the p-type well 716 contained in layer 701 and is connected to the p-type well 716 via a contact (not shown). The emitter electrode 721 is located on the +Y side of the n-type well 717 contained in layer 701 and is positioned to cover the entire transistor 511 and is connected to the n-type well 717 via a contact (not shown). An insulating layer 731 is located between the base electrode 722 and the emitter electrode 721. The insulating layer 731 is composed of a silicon oxide film, a silicon nitride film, etc. This insulating layer 731 insulates the base electrode 722 and the emitter electrode 721. The collector electrode 723 is located on the -Y side of the semiconductor substrate 710 contained in layer 704 and on the -Y side of the n-type semiconductor layer 711 and is positioned to cover the entire transistor 511 and is connected to the n-type semiconductor layer 711 via a contact (not shown).

[0122] In other words, transistor 511 includes a layer 703 containing an n-type n-type column layer 712 having a trench 733, and a p-type p-type column layer 713 provided in the trench 733, an emitter electrode 721 and a base electrode 722 located on the +Y side, which is one side of layer 703 in the direction along the Y axis, a collector electrode 723 located on the -Y side, which is the other side of layer 703 in the direction along the Y axis, and a p-type p-type column layer located at least a portion of which is between layer 703 and the base electrode 722 in the direction along the Y axis. The layer includes a layer 702 containing a channel layer 714, an n-type n-type semiconductor layer 715, an n-type n-type well 717 provided in the n-type semiconductor layer 715, and a p-type p-type well 716 provided in the n-type semiconductor layer 715 and spaced apart from the n-type well 717, and a layer 701 in which at least a portion is located between the layer 702 and the base electrode 722 in the direction along the Y axis, and a layer 704 in which at least a portion is located between the layer 703 and the collector electrode 723 in the direction along the Y axis and contains an n-type n-type semiconductor layer 711.

[0123] In other words, transistor 511 includes an emitter electrode 721 that functions as an emitter terminal, a base electrode 722 that functions as a base terminal, a collector electrode 723 that functions as a collector terminal, an n-type n-type column layer 712 having a trench 733, a layer 703 including a p-type p-type column layer 713 provided in the trench 733, a layer 702 including a p-type p-type channel layer 714, an n-type n-type semiconductor layer 715, an n-type n-type well 717, and an n-type well 717 spaced apart from it. The transistor 511 includes a layer 701 containing a p-type well 716, with a layer 703 positioned above the collector electrode 723, a layer 702 positioned above the layer 703, a layer 701 positioned above the layer 702, an emitter electrode 721 positioned above the n-type well 717, and a base electrode 722 positioned above the p-type well 716. The transistor 511 further includes a layer 704 containing an n-type semiconductor layer 711, with the layer 704 positioned between the collector electrode 723 and the layer 703. Here, "configuration B is positioned above configuration A" means that configuration B is positioned at least on the +Y side than configuration A. That is, "configuration B is positioned above configuration A" means that configuration B may be positioned adjacent to configuration A along the Y axis, or different configurations may be provided between configuration A and configuration B along the Y axis.

[0124] The operation of transistor 511, configured as described above, will now be explained.

[0125] Transistor 511 is turned ON when a positive voltage is supplied to the collector electrode 723 and a positive voltage is supplied to the base electrode 722, such that the collector side potential is positive relative to the source side potential.

[0126] Specifically, when a positive voltage is supplied to the collector electrode 723 such that the collector potential is positive relative to the source potential, and a positive voltage is also supplied to the base electrode 722, holes are injected from the p-type well 716 into the n-type well 717, and also from the p-type well 716 into the p-type channel layer 714. The holes injected into the p-type channel layer 714 flow through the p-type channel layer 714 into the p-type column layer 713 and the n-type column layer 712. As a result, at least the superstructure of the column region composed of the p-type column layer 713 and the n-type column layer 712 becomes less resistive due to conductivity modulation. At this time, electrons are injected from the n-type well 717 into the p-type channel layer 714. The electrons injected into the p-type channel layer 714 then flow through the p-type channel layer 714 into the less resistive p-type column layer 713 and the n-type column layer 712, and reach the collector electrode 723. As a result, current flows between the emitter electrode 721 and the collector electrode 723, and transistor 511 turns on.

[0127] On the other hand, transistor 511 is in an off state when no positive voltage is supplied to the base electrode 722. When a positive voltage is supplied to the collector electrode 723 when no positive voltage is supplied to the base electrode 722, a depletion layer spreads from each of the multiple pn junctions formed between the p-type column layer 713 and the n-type column layer 712 toward both sides of the p-type column layer 713 and the n-type column layer 712. As a result, the column region composed of the p-type column layer 713 and the n-type column layer 712 is depleted at a low electric field strength, allowing transistor 511 to have a high breakdown voltage. At this time, the current between the emitter electrode 721 and the collector electrode 723 is interrupted, and transistor 511 is in an off state.

[0128] In the transistor 511 configured as described above, in the off state, a reverse bias is maintained in the column region composed of the p-type column layer 713 and the n-type column layer 712. As a result, the depletion layer spread to the p-type channel layer 714 is reduced, and the p-type channel layer 714 can be made thinner. Therefore, in the on state, the electron injection efficiency from the emitter side to the collector side can be increased. Furthermore, in the on state, holes are efficiently injected from the base electrode 722 into the n-type column layer 712 via the p-type column layer 713. This causes a conductivity modulation phenomenon, which reduces the on-resistance of the transistor 511 and increases the current amplification factor.

[0129] Figure 12 shows a comparison of an example of the current amplification factor of a conventional NPN bipolar transistor and an example of the current amplification factor of transistor 511 of this embodiment. In Figure 12, the comparison results are shown when a voltage of 2V is supplied between the collector and emitter. In the comparison results shown in Figure 12, the current density of the collector current is plotted on the horizontal axis, and the current amplification factor is plotted on the vertical axis.

[0130] As shown in Figure 12, the transistor 511 of this embodiment can achieve a current amplification factor of 10 times or more compared to a conventional NPN bipolar transistor.

[0131] Here, the only difference between transistor 511 and transistor 512 is whether it is an NPN bipolar transistor or a PNP bipolar transistor; they have the same configuration.

[0132] In other words, although not shown in the diagram, transistor 512 is a semiconductor substrate corresponding to semiconductor substrate 710, a p-type semiconductor layer replacing n-type semiconductor layer 715, and an n-type well replacing p-type well 716. The semiconductor substrate has a well, a p-type well replacing the n-type well 717, an emitter electrode corresponding to the emitter electrode 721, a base electrode corresponding to the base electrode 722, and a collector electrode corresponding to the collector electrode 723. The semiconductor substrate includes a p-type semiconductor layer replacing the n-type semiconductor layer 711, a p-type column layer replacing the n-type column layer 712, an n-type column layer replacing the p-type column layer 713, and an n-type channel layer replacing the p-type channel layer 714.

[0133] The transistor 512 includes a layer containing a p-type column layer that replaces the n-type column layer 712 having a trench, and an n-type column layer that replaces the p-type column layer 713 provided in the trench; an emitter electrode and a base electrode located on the +Y side, which is one side of the layer containing the p-type column layer and the n-type column layer in the direction along the Y axis; a collector electrode located on the -Y side, which is the other side of the layer containing the p-type column layer and the n-type column layer in the direction along the Y axis; and a layer containing an n-type channel layer that replaces the p-type channel layer 714, at least a portion of which is located between the layer containing the p-type column layer and the n-type column layer and the base electrode in the direction along the Y axis; and an n-type semiconductor The transistor 512 also includes a p-type semiconductor layer that replaces the body layer 715, a p-type well that replaces the n-type well 717 provided in the p-type semiconductor layer, and a p-type well that replaces the n-type well 717 provided in the p-type semiconductor layer and is spaced apart from the p-type well, and in the direction along the Y axis, at least a portion of which is located between the base electrode and a layer that includes an n-type channel layer that replaces the p-type channel layer 714, and in the direction along the Y axis, at least a portion of which is located between the collector electrode and a layer that includes a p-type semiconductor layer that replaces the n-type semiconductor layer 711, thereby enabling a large current amplification factor to be obtained in the transistor 512 as well.

[0134] Here, drive signal COM is an example of a drive signal, at least one of the control unit 10 and the drive circuit 50 of the control unit 10 is an example of a print head drive circuit, the amplification circuit 510 of the drive circuit 50 is an example of an amplification circuit, transistor 511 is an example of a first transistor, and transistor 512 is an example of a second transistor. Also, layer 703 is an example of a first layer, layer 702 is an example of a second layer, layer 701 is an example of a third layer, and layer 704 is an example of a fourth layer. Furthermore, n-type is an example of the first conductivity type, p-type is an example of the second conductivity type, trench 733 is an example of a trench, n-type column layer 712 is an example of the first semiconductor region, p-type column layer 713 is an example of the second semiconductor region, p-type channel layer 714 is an example of the third semiconductor region, n-type semiconductor layer 715 is an example of the fourth semiconductor region, n-type well 717 is an example of the fifth semiconductor region, p-type well 716 is an example of the sixth semiconductor region, and n-type semiconductor layer 711 is an example of the seventh semiconductor region. Emitter electrode 721 is an example of the first conductor, base electrode 722 is an example of the second conductor, and collector electrode 723 is an example of the third conductor.

[0135] 5. Effects In the liquid dispensing device 1 of this embodiment, configured as described above, the drive circuit 50 that outputs the drive signal COM is composed of a Class AB amplifier circuit including push-pull connected transistors 511 and 512. Compared to the case where the drive circuit 50 is composed of a Class D amplifier circuit, the switching losses in transistors 511 and 512 can be reduced. As a result, from the viewpoint of improving the productivity of the liquid dispensing device 1, even when the drive circuit 50 outputs a high-frequency drive signal COM, the risk of an increase in the amount of heat generated in the drive circuit 50, specifically the amount of heat generated by transistors 511 and 512, is reduced.

[0136] Furthermore, in the liquid dispensing device 1 of this embodiment configured as described above, the transistor 511 has an emitter electrode 721 that functions as an emitter terminal, a base electrode 722 that functions as a base terminal, a collector electrode 723 that functions as a collector terminal, and a trace The transistor 511 includes a layer 703 containing an n-type n-type column layer 712 having a trench 733 and a p-type p-type column layer 713 provided in the trench 733, a layer 702 containing a p-type p-type channel layer 714, and a layer 701 containing an n-type n-type semiconductor layer 715, an n-type n-type well 717, and a p-type p-type well 716 located spaced apart from the n-type well 717. The current amplification factor of the transistor 511 can be increased by arranging the layer 703 above the collector electrode 723, the layer 702 above the layer 703, the layer 701 above the layer 702, the emitter electrode 721 above the n-type well 717, and the base electrode 722 above the p-type well 716. Therefore, from the viewpoint of improving the productivity of the liquid ejection device 1, even if the print head 20 has a large number of piezoelectric elements 60 and these numerous piezoelectric elements 60 are driven by a drive signal COM output by the drive circuit 50, a sufficient current can be supplied to the piezoelectric elements 60. Consequently, the risk of a decrease in the driving accuracy of the piezoelectric elements 60 is reduced.

[0137] In other words, in the liquid ejection device 1 of this embodiment, the drive circuit 50 can stably supply a high-frequency drive signal COM to the numerous piezoelectric elements 60 of the print head 20, thereby increasing the productivity of the liquid ejection device 1.

[0138] Furthermore, in the liquid dispensing device 1 of this embodiment configured as described above, the transistor 512 has the same configuration as transistor 511, so that even when the print head 20 has a large number of piezoelectric elements 60 and these numerous piezoelectric elements 60 are driven by the drive signal COM output by the drive circuit 50, a sufficient current can be supplied to the piezoelectric elements 60 more stably. Therefore, the risk of a decrease in the driving accuracy of the piezoelectric elements 60 is further reduced.

[0139] Furthermore, in the liquid ejection device 1 of this embodiment, the drive circuit 50 can stably supply a high-frequency drive signal COM to the numerous piezoelectric elements 60 of the print head 20. Therefore, even when the print head 20 includes 3,000 or more piezoelectric elements 60 and the drive circuit 50 supplies the drive signal COM to these 3,000 or more piezoelectric elements 60, or when the drive circuit 50 outputs a drive signal COM with a frequency of 100 kHz or higher, and the period includes a time when the voltage value of the drive signal COM output by the drive circuit 50 changes by 20V or more per 1 μs, or when the period includes a time when the voltage value of the drive signal COM is constant for less than 0.3 μs, the drive circuit 50 can stably supply a high-frequency drive signal COM of 100 kHz or higher to the 3,000 or more piezoelectric elements 60 of the print head 20. This increases the productivity of the liquid ejection device 1.

[0140] Although embodiments and modified examples have been described above, the present invention is not limited to these embodiments and can be implemented in various forms without departing from its spirit. For example, the above embodiments can be combined as appropriate.

[0141] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0142] The following conclusions can be drawn from the embodiments described above.

[0143] One embodiment of a liquid dispensing device is: A print head that ejects liquid in response to a drive signal, A print head drive circuit that outputs the aforementioned drive signal, Equipped with, The print head drive circuit has an amplification circuit that outputs the drive signal amplified by the first transistor and the second transistor, The first transistor is, A first conductor that functions as an emitter electrode, A second conductor that functions as a base electrode, A third conductor that functions as a collector electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer including the third semiconductor region of the second conductivity type, A third layer including a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type located spaced apart from the fifth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The third layer is positioned above the second layer. The first conductor is positioned above the fifth semiconductor region. The second conductor is positioned above the sixth semiconductor region.

[0144] In this liquid ejection device, the print head drive circuit includes a push-pull connected first and second transistors, and has an amplification circuit that amplifies the base drive signal that forms the basis of the drive signal and outputs it as a drive signal. As a result, even when outputting a high-frequency drive signal, the risk of a significant increase in the drive frequency of the first and second transistors is reduced. This reduces the heat generated in the print head drive circuit, including the first and second transistors.

[0145] Furthermore, in this liquid dispensing device, the first transistor in the amplification circuit includes a first conductor that functions as an emitter electrode, a second conductor that functions as a base electrode, a third conductor that functions as a collector electrode, a first layer including a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, a second layer including a third semiconductor region of a second conductivity type, and a third layer including a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a second conductivity type located spaced apart from the fifth semiconductor region. The first layer is positioned above the third conductor, the second layer above the first layer, the third layer above the second layer, the first conductor above the fifth semiconductor region, and the second conductor above the sixth semiconductor region, thereby increasing the current amplification factor of the first transistor. As a result, even when many driving elements are driven by the driving signal COM, sufficient current can be supplied to drive the driving elements.

[0146] As described above, this liquid dispensing device can stably supply high-frequency drive signals to a large number of drive elements, thereby increasing the productivity of the liquid dispensing device.

[0147] In one embodiment of the liquid dispensing device, The impurity concentration in the fourth semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than the impurity concentration in the first semiconductor region. The impurity concentration in the third semiconductor region and the impurity concentration in the sixth semiconductor region may be higher than the impurity concentration in the second semiconductor region.

[0148] In one embodiment of the liquid dispensing device, The first transistor further includes a fourth layer containing a seventh semiconductor region of the first conductivity type. fruit, The fourth layer is disposed between the third conductor and the first layer, The impurity concentration in the seventh semiconductor region may be higher than the impurity concentration in the first semiconductor region.

[0149] In one embodiment of the liquid dispensing device, The print head includes more than 3,000 piezoelectric elements, More than 3,000 of the piezoelectric elements may be driven by the drive signal.

[0150] This liquid ejection device can stably supply high-frequency drive signals to a large number of drive elements, and therefore, even when drive signals are supplied to more than 3,000 piezoelectric elements, it can achieve stable operation of both the liquid ejection device and the print head drive circuit.

[0151] In one embodiment of the liquid dispensing device, The frequency of the drive signal may be 100 kHz or higher.

[0152] This liquid ejection device can stably supply high-frequency drive signals to a large number of drive elements, and therefore, even when the drive signal frequency is 100 kHz or higher, it can achieve stable operation of both the liquid ejection device and the print head drive circuit.

[0153] In one embodiment of the liquid dispensing device, The aforementioned drive signal may include a period during which the voltage value changes by 20V or more per 1μs.

[0154] This liquid ejection device can stably supply high-frequency drive signals to a large number of drive elements, thus enabling stable operation of the liquid ejection device and print head drive circuit even when the drive signal includes periods where the voltage value changes by more than 20V per 1μs.

[0155] In one embodiment of the liquid dispensing device, The aforementioned drive signal may include a period of less than 0.3 μs during which the voltage value remains constant.

[0156] This liquid ejection device can stably supply high-frequency drive signals to a large number of drive elements, thus enabling stable operation of the liquid ejection device and print head drive circuit even when the drive signal includes a period of less than 0.3 μs during which the voltage value remains constant.

[0157] In one embodiment of the liquid dispensing device, The amplification circuit may be a Class AB amplification circuit.

[0158] This liquid dispensing device can reduce the amount of heat generated by the amplification circuit, and even when outputting a large current due to supplying drive signals to numerous drive elements, it can supply sufficient current to those drive elements, thereby reducing the risk of a decrease in the waveform accuracy of the drive signals.

[0159] One embodiment of a print head drive circuit is: A print head drive circuit that outputs the drive signal to a print head that ejects liquid in response to the drive signal, The device includes an amplification circuit that outputs the drive signal amplified by the first and second transistors, The first transistor is, A first conductor that functions as an emitter electrode, A second conductor that functions as a base electrode, A third conductor that functions as a collector electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, A second layer including the third semiconductor region of the second conductivity type, A third layer including a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type located spaced apart from the fifth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The third layer is positioned above the second layer. The first conductor is positioned above the fifth semiconductor region. The second conductor is positioned above the sixth semiconductor region.

[0160] This printhead drive circuit includes a push-pull connected first and second transistors, and has an amplification circuit that amplifies the base drive signal that forms the basis of the drive signal and outputs it as a drive signal. As a result, even when outputting a high-frequency drive signal, the risk of a significant increase in the drive frequency of the first and second transistors is reduced. This reduces the heat generated in the printhead drive circuit including the first and second transistors.

[0161] Furthermore, in this printhead drive circuit, the first transistor in the amplification circuit includes a first conductor that functions as an emitter electrode, a second conductor that functions as a base electrode, a third conductor that functions as a collector electrode, a first layer including a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, a second layer including a third semiconductor region of a second conductivity type, and a third layer including a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of a first conductivity type, and a sixth semiconductor region of a second conductivity type located spaced apart from the fifth semiconductor region. The first layer is positioned above the third conductor, the second layer above the first layer, the third layer above the second layer, the first conductor above the fifth semiconductor region, and the second conductor above the sixth semiconductor region, thereby increasing the current amplification factor of the first transistor. As a result, even when many drive elements are driven by the drive signal COM, sufficient current can be supplied to drive the drive elements.

[0162] As described above, this print head drive circuit can stably supply high-frequency drive signals to a large number of drive elements, thereby increasing the productivity of the liquid ejection device on which it is implemented.

[0163] In one embodiment of the print head drive circuit, The impurity concentration in the fourth semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than the impurity concentration in the first semiconductor region. The impurity concentration in the third semiconductor region and the impurity concentration in the sixth semiconductor region may be higher than the impurity concentration in the second semiconductor region.

[0164] In one embodiment of the print head drive circuit, The first transistor further includes a fourth layer containing a seventh semiconductor region of the first conductivity type, The fourth layer is disposed between the third conductor and the first layer, The impurity concentration in the seventh semiconductor region may be higher than the impurity concentration in the first semiconductor region.

[0165] In one embodiment of the print head drive circuit, The print head includes more than 3,000 piezoelectric elements, The aforementioned drive signal may be used to drive 3,000 or more of the piezoelectric elements.

[0166] This printhead drive circuit can stably supply high-frequency drive signals to a large number of drive elements, thus enabling stable operation of the liquid ejection device and printhead drive circuit even when drive signals are supplied to more than 3,000 piezoelectric elements.

[0167] In one embodiment of the print head drive circuit, The frequency of the drive signal may be 100 kHz or higher.

[0168] This printhead drive circuit can stably supply high-frequency drive signals to a large number of drive elements, and therefore, even when the drive signal frequency is 100kHz or higher, stable operation of the liquid ejection device and the printhead drive circuit can be achieved.

[0169] In one embodiment of the print head drive circuit, The aforementioned drive signal may include a period during which the voltage value changes by 20V or more per 1μs.

[0170] This printhead drive circuit can stably supply high-frequency drive signals to a large number of drive elements, thus enabling stable operation of the liquid ejection device and printhead drive circuit even when the drive signal includes periods where the voltage value changes by more than 20V per 1μs.

[0171] In one embodiment of the print head drive circuit, The aforementioned drive signal may include a period of less than 0.3 μs during which the voltage value remains constant.

[0172] This printhead drive circuit can stably supply high-frequency drive signals to a large number of drive elements. Therefore, even when the drive signal includes a period of less than 0.3 μs during which the voltage value remains constant, stable operation of the liquid ejection device and the printhead drive circuit can be achieved.

[0173] In one embodiment of the print head drive circuit, The amplification circuit may be a Class AB amplification circuit.

[0174] This printhead drive circuit reduces the amount of heat generated by the amplification circuit, and even when a large amount of current is output due to supplying drive signals to numerous drive elements, it is possible to supply sufficient current to those drive elements, thereby reducing the risk of a decrease in the waveform accuracy of the drive signals. [Explanation of symbols]

[0175] 1…Liquid ejection device, 2…Ink container, 10…Control unit, 20…Print head, 21…Carriage, 30…Movement unit, 31…Carriage motor, 32…Endless belt, 40…Transport unit, 41…Transport motor, 42…Transport roller, 50, 50a, 50b, 50c…Drive circuit, 52…Reference voltage output circuit, 60…Piezoelectric element, 100…Control circuit, 210…Selection control circuit, 212…Shift register, 214…Latch circuit, 216…Decoder, 230…Selection circuit, 232a, 232b, 232c…Inverter, 234a, 234b, 234c…Transfer gate, 500…Amplification control circuit, 501…Memory, 502…Latch circuit, 503…Adder, 504…Latch circuit, 505…D / A converter, 5 06…Drive circuit, 510…Amplifier circuit, 511,512…Transistor, 600…Discharge section, 601…Piezoelectric element, 611,612…Electrodes, 621…Diaphragm, 631…Cavity, 632…Nozzle plate, 641…Reservoir, 651…Nozzle, 661…Feed port, 701~704…Layers, 710…Semiconductor substrate, 711…n-type semiconductor layer, 712…n-type column layer, 713…p-type column layer, 714…p-type channel layer, 715…n-type semiconductor layer, 716…p-type well, 717…n-type well, 721…Emitter electrode, 722…Base electrode, 723…Collector electrode, 731…Insulating layer, 733…Trench, P…Medium

Claims

1. A print head that ejects liquid in response to a drive signal, A print head drive circuit that outputs the aforementioned drive signal, Equipped with, The print head drive circuit has an amplification circuit that outputs the drive signal amplified by the first transistor and the second transistor, The aforementioned first transistor is A first conductor that functions as an emitter electrode, A second conductor that functions as a base electrode, A third conductor that functions as a collector electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, The second layer includes the third semiconductor region of the second conductivity type, A third layer including a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type located spaced apart from the fifth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The third layer is positioned above the second layer. The first conductor is positioned above the fifth semiconductor region. The second conductor is positioned above the sixth semiconductor region. A liquid dispensing device characterized by the following features.

2. The impurity concentration in the fourth semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than that in the first semiconductor region. The impurity concentration in the third semiconductor region and the impurity concentration in the sixth semiconductor region are higher than the impurity concentration in the second semiconductor region. The liquid dispensing device according to feature 1.

3. The first transistor further includes a fourth layer containing a seventh semiconductor region of the first conductivity type, The fourth layer is disposed between the third conductor and the first layer. The impurity concentration in the seventh semiconductor region is higher than the impurity concentration in the first semiconductor region. The liquid dispensing device according to feature 1.

4. The print head includes more than 3,000 piezoelectric elements, The more than 3,000 piezoelectric elements are driven by the drive signal. The liquid dispensing device according to feature 1.

5. The frequency of the aforementioned drive signal is 100 kHz or higher. The liquid dispensing device according to feature 1.

6. The aforementioned drive signal includes a period during which the voltage value changes by 20V or more per 1μs. The liquid dispensing device according to feature 1.

7. The aforementioned drive signal includes a period of less than 0.3 μs during which the voltage value remains constant. The liquid dispensing device according to feature 1.

8. The aforementioned amplification circuit is a Class AB amplification circuit. A liquid dispensing device according to any one of claims 1 to 7.

9. A print head drive circuit that outputs the drive signal to a print head that ejects liquid in response to the drive signal, The device includes an amplification circuit that outputs the drive signal amplified by the first transistor and the second transistor, The aforementioned first transistor is A first conductor that functions as an emitter electrode, A second conductor that functions as a base electrode, A third conductor that functions as a collector electrode, A first layer comprising a first semiconductor region of a first conductivity type having a trench, and a second semiconductor region of a second conductivity type provided in the trench, The second layer includes the third semiconductor region of the second conductivity type, A third layer including a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type located spaced apart from the fifth semiconductor region, Includes, The first layer is positioned above the third conductor. The second layer is positioned above the first layer. The third layer is positioned above the second layer. The first conductor is positioned above the fifth semiconductor region. The second conductor is positioned above the sixth semiconductor region. A print head drive circuit characterized by the following features.

10. The impurity concentration in the fourth semiconductor region is lower than the impurity concentration in the first semiconductor region. The impurity concentration in the fifth semiconductor region is higher than that in the first semiconductor region. The impurity concentration in the third semiconductor region and the impurity concentration in the sixth semiconductor region are higher than the impurity concentration in the second semiconductor region. The print head drive circuit according to feature 9.

11. The first transistor further includes a fourth layer containing a seventh semiconductor region of the first conductivity type, The fourth layer is disposed between the third conductor and the first layer. The impurity concentration in the seventh semiconductor region is higher than the impurity concentration in the first semiconductor region. The print head drive circuit according to feature 9.

12. The print head includes more than 3,000 piezoelectric elements, The aforementioned drive signal drives 3,000 or more of the piezoelectric elements. The print head drive circuit according to feature 9.

13. The frequency of the aforementioned drive signal is 100 kHz or higher. The print head drive circuit according to feature 9.

14. The aforementioned drive signal includes a period during which the voltage value changes by 20V or more per 1μs. The print head drive circuit according to feature 9.

15. The aforementioned drive signal includes a period of less than 0.3 μs during which the voltage value remains constant. The print head drive circuit according to feature 9.

16. The aforementioned amplification circuit is a Class AB amplification circuit. A print head drive circuit according to any one of claims 9 to 15.

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