Method for manufacturing a semiconductor device and a semiconductor device.

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that improve the accuracy of overcurrent detection. [Solution] The semiconductor device manufacturing method includes a semiconductor wafer test step WTS for testing a semiconductor wafer on which a semiconductor chip equipped with an overcurrent detection circuit is arranged. The overcurrent detection circuit includes a comparison circuit that compares a sense voltage generated at a sense resistor with a reference voltage generated at a reference resistor to form an overcurrent detection signal. The semiconductor chip includes a replica resistor arranged adjacent to the sense resistor. The semiconductor wafer test step WTS includes a first test step WTS1 for determining the resistance fluctuation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer, and a third test step WTS3 for determining the fluctuation value of the reference current based on the resistance fluctuation rate obtained in the first test step WTS1 and setting the current value of the current circuit to reduce the fluctuation value.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that includes an overcurrent detection circuit for detecting an overcurrent flowing through a power device, and to a semiconductor device that includes an overcurrent detection circuit. [Background technology]

[0002] An overcurrent detection circuit for detecting overcurrents flowing through a power device is described, for example, in Patent Document 1.

[0003] For example, paragraph number

[0003] and in Patent Document 1

[0004] The diagram shows how to construct an overcurrent detection circuit using a sense resistor and a comparator. In this overcurrent detection circuit, the sense voltage generated by the current flowing through the sense resistor is compared with a reference voltage by the comparator. When an overcurrent flows through the sense resistor, the output of the comparator inverts, and the overcurrent is detected. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2007-201116 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] The inventors believed that improving the accuracy of overcurrent detection would remain important. However, it was found that variations in the resistance value of the sensing resistor due to manufacturing variations make it difficult to improve the accuracy of overcurrent detection. [Means for solving the problem]

[0006] A brief overview of some of the representative embodiments disclosed in this application is as follows.

[0007] In other words, a semiconductor device manufacturing method according to one embodiment includes a semiconductor wafer manufacturing step of manufacturing a semiconductor wafer on which a semiconductor chip equipped with an overcurrent detection circuit is arranged; a semiconductor wafer testing step of testing the manufactured semiconductor wafer; and a semiconductor device assembly step of cutting out a semiconductor chip from the semiconductor wafer and assembling a semiconductor device. The overcurrent detection circuit includes a sense device through which a sense current proportional to the current flowing through a power device flows; a sense resistor connected between the sense device and a predetermined node; a reference resistor connected between the predetermined node and a current circuit; and a comparison circuit that compares a sense voltage generated at the sense resistor by the sense current with a reference voltage generated at the reference resistor by the reference current from the current circuit to form an overcurrent detection signal. The semiconductor chip includes a replica resistor arranged adjacent to the sense resistor. The semiconductor wafer testing step includes a first test step of determining the resistance fluctuation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer; and a setting step of determining the fluctuation value of the reference current based on the resistance fluctuation rate obtained in the first test step and setting the current value of the current circuit to reduce the fluctuation value.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Effects of the Invention]

[0009] According to one embodiment, it is possible to provide a method for manufacturing a semiconductor device that can improve the accuracy of overcurrent detection. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a circuit diagram showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] Figure 2 is a flowchart showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 3]FIG. 3(A) to (C) are diagrams for explaining a semiconductor wafer, a semiconductor wafer test process, and a semiconductor chip according to Embodiment 1. [Figure 4] FIG. 4 is a flowchart showing in detail the semiconductor wafer test process according to Embodiment 1. [Figure 5] FIG. 5 is a diagram for explaining the first test process according to Embodiment 1. [Figure 6] FIG. 6 is a diagram for explaining the second test process according to Embodiment 1. [Figure 7] FIG. 7 is a diagram for explaining the second test process according to Embodiment 1. [Figure 8] FIG. 8 is a diagram for explaining the third test process according to Embodiment 1. [Figure 9] FIG. 9 is a circuit diagram showing the configuration of a variable current circuit according to Embodiment 1. [Figure 10] FIGS. 10(A) and (B) are diagrams showing the configuration of a semiconductor device according to Embodiment 2. [Figure 11] FIG. 11 is a circuit diagram showing the configuration of an overcurrent detection circuit studied by the present inventor. [Figure 12] FIG. 12 is a diagram for explaining Embodiment 1.

Mode for Carrying Out the Invention

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention.

[0012] Also, in this specification and each figure, elements that are the same as those described above with respect to the previously shown figures may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0013] <Comparative Example> First, the problem will be explained in more detail using the overcurrent detection circuit considered by the inventors. Figure 11 is a circuit diagram showing the configuration of the overcurrent detection circuit considered by the inventors.

[0014] In Figure 11, PWT represents an N-channel field-effect transistor (hereinafter also referred to as an N-type transistor), which is a power device (power transistor). The source-drain path of the N-type transistor PWT is connected between the power supply voltage VCC and the output terminal OUT. The gate of the N-type transistor PWT is connected to the control driver DRV. When no overcurrent is flowing through the N-type transistor PWT, the control driver DRV supplies a drive signal to the gate of the N-type transistor PWT according to the input signal IN. When the N-type transistor PWT becomes conductive due to the drive signal, current is supplied from the power supply voltage VCC to the output terminal OUT, and the load (not shown) connected to the output terminal OUT is driven.

[0015] In Figure 11, OIDT represents an overcurrent detection circuit. The overcurrent detection circuit OIDT comprises an N-type transistor SNT as a sense device (sense transistor), a sense resistor Rs, a reference resistor Rref, N-type transistors MN1 and MN2, and P-channel field-effect transistors (hereinafter also referred to as P-type transistors) MP1 and MP2.

[0016] The gate of the sense device, an N-type transistor SNT, is connected to the gate of an N-type transistor PWT, its drain is connected to the power supply voltage VCC, and its source is connected to the output terminal OUT via a sense resistor Rs. In this comparative example, the size of the sense device, the N-type transistor SNT, is 1 / K (hereinafter, K is also referred to as the size ratio) relative to the size of the power device, the N-type transistor PWT. As a result, when both the N-type transistor PWT and SNT are made to conduct by the control driver DRV, the value of the current Is (sense current) flowing through the source-drain path of the N-type transistor SNT is 1 / K times the value of the current IL flowing through the source-drain path of the N-type transistor PWT.

[0017] The source-drain paths of the P-type transistor MP1, the source-drain paths of the N-type transistor MN1, and the reference resistor Rref are connected in series between the power supply voltage (e.g., the output voltage of a boost circuit) CP and the output terminal OUT, in this order. Similarly, the source-drain paths of the P-type transistor MP2, the source-drain paths of the N-type transistor MN2, and the sense resistor Rs are also connected in series between the power supply voltage CP and the output terminal OUT, in this order.

[0018] The gates of P-type transistors MP1 and MP2 are connected to each other and connected to a predetermined bias voltage (not shown). Furthermore, the size of P-type transistor MP2 is set to N times that of P-type transistor MP1. As a result, the current Ib' flowing through the source-drain path of P-type transistor MP2 is set to N times (=NIb) the current Ib flowing through the source-drain path of P-type transistor MP1.

[0019] The gate of N-type transistor MN1 is connected to the drain of N-type transistor MN1 and also to the gate of N-type transistor MN2. In addition, an overcurrent detection signal OID is output from the connection node connecting N-type transistor MN2 and P-type transistor MP2.

[0020] In the overcurrent detection circuit OIDT shown in Figure 11, a reference current Iref is supplied from the power supply voltage CP to the reference resistor Rref via the P-type transistor MP1 and the N-type transistor MN1. Furthermore, a reference current Iref' is supplied to the sense resistor Rs from the power supply voltage CP via the P-type transistor MP2 and the N-type transistor MN2, and a sense current Is is supplied from the N-type transistor SNT. As a result, a reference voltage Vr is generated at the reference resistor Rref by the reference current Iref, and a sense voltage Vs is generated at the sense resistor Rs by the reference current Iref' and the sense current Is.

[0021] The N-type transistors MN1 and MN2 effectively form a comparator circuit CMP, generating an overcurrent detection signal OID corresponding to the sense current Is. This overcurrent detection signal OID is supplied to the control driver DRV. When the control driver DRV is notified of overcurrent detection by the overcurrent detection signal OID, it outputs a drive signal that de-conducts the N-type transistors PWT and SNT, for example, independently of the input signal IN. This prevents the N-type transistor PWT, which is a power device, from being destroyed.

[0022] In the comparative example, the sense voltage Vs changes when the sense current Is flows. This change in sense voltage Vs causes the source voltage of the sense device, the N-type transistor SNT, to rise compared to the source voltage of the power device, the N-type transistor PWT. As a result, the ratio between the current IL flowing through the N-type transistor PWT and the sense current Is flowing through the N-type transistor SNT no longer matches the size ratio K. In other words, an error occurs in the size ratio K, which becomes an error in the overcurrent detection circuit OIDT.

[0023] Furthermore, variations in the resistance value of the sense resistor Rs due to manufacturing variations lead to variations in the change in the sense voltage Vs and the size ratio K, resulting in further errors in the overcurrent detection circuit OIDT. The inventors have confirmed that the size ratio K depends on the sense resistor Rs and the sense voltage Vs, and that there is a proportional relationship between the variation in the sense resistor Rs and the variation in the size ratio K. For example, if the value of the sense resistor Rs increases due to manufacturing variations, the sense voltage Vs and the size ratio K also increase. To give one example, if the resistance value of the sense resistor Rs varies by ±30% due to manufacturing variations, the size ratio K will vary by about ±15% when the sense voltage Vs is about 0.1V, making it difficult to improve the accuracy of overcurrent detection.

[0024] One way to obtain semiconductor devices with high overcurrent detection accuracy is to select those with high overcurrent detection accuracy during the manufacturing process. For example, one could select devices with high overcurrent detection accuracy during the final testing stage of the manufacturing process and ship them out. However, in this case, the yield would decrease, and since it would not be possible to select and discard devices with low accuracy before reaching the final testing stage, the materials and manpower invested up to the final testing stage would be wasted, further reducing the overall yield.

[0025] (Embodiment 1) <Configuration of semiconductor device> Figure 1 is a circuit diagram showing the configuration of a semiconductor device according to Embodiment 1. In Figure 1, the CHP shown by the dashed line represents a semiconductor device. The semiconductor device CHP according to Embodiment 1, as will be explained later, comprises a semiconductor chip cut from a semiconductor wafer, a package that encapsulates the semiconductor chip, and external terminals protruding from the package.

[0026] The semiconductor device CHP has numerous external terminals, but only the external terminals necessary for explanation are shown on the dashed lines in Figure 1. In Figure 1, VCC represents the external terminal for power supply, VSS represents the external terminal for ground voltage, DIN represents the external terminal for inputting data, and OUT represents the external terminal for output. These external terminals are electrically connected to circuit elements, circuit blocks, etc., formed on the semiconductor chip within the package.

[0027] The semiconductor device CHP includes a drive circuit HLD that drives a load LOD connected between an output external terminal OUT and a ground voltage external terminal VSS, a control driver DRV that controls the drive circuit HLD according to an input signal IN from a control circuit CNT, and a memory circuit MEM. The drive circuit HLD comprises a high-side drive circuit HDD and a low-side drive circuit LDD. Since the low-side drive circuit LDD is similar to the high-side drive circuit HDD, the high-side drive circuit HDD will be described here as a representative example.

[0028] The high-side drive circuit HDD includes an N-type transistor PWT, which is a power device (power transistor) with a source-drain path connected between the external power supply terminal VCC and the external output terminal OUT; a high-side overcurrent detection circuit OIDT_H; and a replica resistor Rrep.

[0029] The high-side overcurrent detection circuit OIDT_H comprises an N-type transistor SNT, which is a high-side sense device (sense transistor), a high-side variable current circuit IRF_H, a high-side reference resistor Rref, a high-side sense resistor Rs, and a high-side comparator circuit CMP. The gate of the N-type transistor SNT is connected to the gate of an N-type transistor PWT, its drain is connected to the external power supply terminal VCC, and its source is connected to the external output terminal OUT via the sense resistor Rs. The reference resistor Rref is connected between the variable current circuit IRF_H and the external output terminal OUT. The negative input terminal (sign - in Figure 1) of the comparator circuit CMP is connected to the connection node connecting the reference resistor Rref and the variable current circuit IRF_H, and the positive input terminal (sign +) is connected to the connection node connecting the sense resistor Rs and the source of the N-type transistor SNT.

[0030] The variable current circuit IRF_H is supplied with high-side current data (hereinafter also referred to as H current data) IRD_H from the memory circuit MEM, and generates and outputs a reference current Iref with a current value specified by this H current data IRD_H. The memory circuit MEM receives data from the external input terminal DIN and generates H current data IRD_H according to the supplied data. In Embodiment 1, the memory circuit MEM and the variable current circuit IRF_H are collectively referred to as the current circuit. The output external terminal OUT is also referred to as a predetermined node.

[0031] The comparison circuit CMP compares the reference voltage generated at the reference resistor Rref by the reference current Iref with the sense voltage generated at the sense resistor Rs by the sense current Is. For example, if the sense voltage generated at the sense resistor Rs exceeds the reference voltage generated at the reference resistor Rref, it outputs a high-level overcurrent detection signal OID_H to the control driver DRV. In Embodiment 1, although not particularly limited, when the overcurrent detection signal OID_H is at a low level, the high-side overcurrent detection circuit OIDT_H indicates that no overcurrent has been detected (no overcurrent is flowing through the N-type transistor PWT), and when the overcurrent detection signal OID_H is at a high level, the high-side overcurrent detection circuit OIDT_H indicates that an overcurrent has been detected (an overcurrent is flowing through the N-type transistor PWT).

[0032] When the overcurrent detection signal OID_H is at a low level, i.e., when no overcurrent is detected by the high-side overcurrent detection circuit OIDT_H, the control driver DRV supplies a drive signal DRV_H to the gates of the N-type transistors PWT and SNT, in accordance with the input signal IN from the control circuit CNT, causing them to conduct. As a result, the N-type transistor PWT supplies a current IL according to the drive signal DRV_H to the output terminal OUT, and the N-type transistor SNT outputs a sense current Is proportional to the current IL to the sense resistor Rs. Conversely, when the overcurrent detection signal OID_H is at a high level, i.e., when an overcurrent is detected by the high-side overcurrent detection circuit OIDT_H, the control driver DRV supplies a drive signal DRV_H to the gates of the N-type transistors PWT and SNT, in accordance with the input signal IN from the control circuit CNT, causing them to deconduct. This prevents the N-type transistor PWT from being destroyed.

[0033] The sense resistor Rs and reference resistor Rref according to Embodiment 1 are constructed by connecting multiple unit resistors in series, parallel, or series-parallel. In other words, the sense resistor Rs and reference resistor Rref are constructed by combining multiple resistors (unit resistors) with the same resistance value.

[0034] In Figure 1, the symbols TPW1_1, TPW1_2, TPW2_1, TPW2_2, TPW3_1, and TPW_C, represented by squares filled with ×s, indicate pads within the semiconductor device CHP. In Embodiment 1, these pads are not connected to the external terminals of the semiconductor device CHP (indicated by squares in Figure 1). That is, the pads do not protrude outside the semiconductor device CHP. As will be explained later, pads TPW1_1, TPW1_2, TPW2_1, TPW2_2, TPW3_1, and TPW_C are connected to a tester device during the semiconductor wafer testing process.

[0035] In Embodiment 1, the replica resistor Rrep is composed of the same unit resistance as the unit resistance that constitutes the sense resistor Rs. Furthermore, the unit resistance that constitutes the replica resistor Rrep is arranged adjacent to multiple unit resistances that constitute the sense resistor Rs on the semiconductor chip. As a result, the same resistance value variations that occur in the sense resistor Rs due to manufacturing variations will also occur in the replica resistor Rrep.

[0036] In Figure 1, DRV_L represents the drive signal (corresponding to DRV_H) supplied from the control driver DRV to the low-side drive circuit LDD, OID_L represents the low-side overcurrent detection signal (corresponding to OID_H), and IRD_L represents the L current data (corresponding to IRD_H) supplied from the memory circuit MEM to the variable current circuit (corresponding to IRF_H) within the low-side drive circuit LDD.

[0037] Figure 1 shows an example where the high-side drive circuit HDD and the low-side drive circuit LDD are connected to a common output external terminal OUT, but this is not the only option. For example, the output external terminal OUT may be divided into two, one for the high-side drive circuit HDD and one for the low-side drive circuit LDD, and the load LOD may be connected in series between the two output external terminals. Also, the overcurrent detection circuit may be provided in only one of the high-side drive circuit HDD and the low-side drive circuit LDD, rather than both.

[0038] <Manufacturing methods for semiconductor devices, semiconductor wafers, and test equipment> Next, the method for manufacturing the semiconductor device CHP according to Embodiment 1 shown in Figure 1 will be explained with reference to the drawings. Figure 2 is a flowchart showing the method for manufacturing the semiconductor device according to Embodiment 1.

[0039] As shown in Figure 1, the semiconductor device CHP is equipped with semiconductor chips. In the manufacturing method of the semiconductor device, first, a semiconductor wafer on which multiple semiconductor chips are arranged is prepared. In Figure 2, WPS shows the semiconductor wafer manufacturing process for producing a semiconductor wafer on which multiple semiconductor chips are arranged, and WTS shows the semiconductor wafer testing process for testing the semiconductor wafer.

[0040] Examples of semiconductor wafers manufactured in the WPS semiconductor wafer manufacturing process, examples of tests performed in the WTS semiconductor wafer testing process, and examples of semiconductor chips will be explained using drawings. Figure 3 is a diagram illustrating a semiconductor wafer, a semiconductor wafer testing process, and a semiconductor chip according to Embodiment 1. Here, Figure 3(A) is a plan view of the semiconductor wafer seen from above, Figure 3(B) is a conceptual diagram showing the connection between a semiconductor chip placed on the semiconductor wafer and a tester device, and Figure 3(C) is a plan view showing examples of sense resistors and replica resistors placed on the semiconductor chip.

[0041] In Figure 3(A), WP represents a semiconductor wafer, and CH arranged on the semiconductor wafer WP represents semiconductor chips. In the semiconductor wafer manufacturing process WPS, active elements, passive elements, pads, etc., are formed within the region of each semiconductor chip CH placed on the semiconductor wafer WP by known semiconductor manufacturing techniques, and these are electrically connected by wiring layers. As a result, various circuit blocks (for example, the drive circuit HLD, memory circuit MEM, control driver DRV, and control circuit CNT shown in Figure 1) are realized on each semiconductor chip CH.

[0042] The semiconductor wafer WP manufactured in the semiconductor wafer manufacturing process is then tested by a tester device in the semiconductor wafer testing process WTS. In the semiconductor device manufacturing method according to Embodiment 1, data is set (written) to the semiconductor chip CH by the tester device according to the test results in the semiconductor wafer testing process WTS.

[0043] An example of a tester device used in the semiconductor wafer testing process (WTS) is shown in Figure 3(B) by the symbol TST. The tester device TST is not particularly limited, but it comprises a control unit TST_C, a test unit TST_T controlled by the control unit TST_C, and a setting unit TST_S, also controlled by the control unit TST_C.

[0044] The test unit TST_T includes a test power supply circuit, a test current circuit, and a test measurement circuit for measuring voltage, current, etc. The control unit TST_C controls the entire system, including the test unit TST_T, the setting unit TST_S, and the tester device TST, and also performs calculations and other processing. The setting unit TST_S, for example, supplies data to the semiconductor chip CH and performs writing operations.

[0045] Furthermore, in Figure 3(B), the PBT represents a probe that electrically connects the tester device TST to a pad located on the semiconductor chip CH. Although Figure 3(B) shows an example where one semiconductor chip CH is connected to the tester device TST by the probe PBT, in reality, multiple semiconductor chips CH located on a semiconductor wafer WP are connected to a common tester device TST by the probe PBT substantially simultaneously, and tested at the same time.

[0046] In Figure 3(B), the pads indicated by the symbols TPW1 to TPW3 represent the pads shown in Figure 1 (e.g., TPW1_1, TPW2_1, TPW3_1), and the pads indicated by the symbols EXP1 to EXP5 represent the pads connected to the external terminals shown in Figure 1 (e.g., the output external terminal OUT) in the semiconductor device assembly process ASS (Figure 2).

[0047] Furthermore, in Figure 3(B), the region indicated by the symbol RAR shows an example of a resistance region where the sense resistor Rs and replica resistor Rrep shown in Figure 1 are arranged. The resistance region RAR is not particularly limited, but five identical unit resistors are arranged adjacent to each other. Here, the sense resistor Rs is composed of four of the five unit resistors UR_S, and the replica resistor Rrep is composed of one unit resistor UR_P, which is positioned between the four unit resistors UR_S.

[0048] The semiconductor wafer testing process (WTS) will be explained in more detail later using diagrams, so we will omit further explanation here. Returning to Figure 2, we will continue the explanation of the semiconductor device manufacturing method.

[0049] The semiconductor wafer WP, tested in the semiconductor wafer testing (WTS) process, moves on to the semiconductor device assembly (ASS) process. In the ASS process, multiple semiconductor chips CH are cut out from the semiconductor wafer WP by dicing. In the ASS process, among the pads placed on the cut semiconductor chips, the pads that are connected to external terminals (indicated as EXP1 to EXP5 in Figure 3(B)) are electrically connected to external terminals (indicated as OUT in Figure 1, etc.), and the semiconductor chips are then sealed with resin or the like. This completes the semiconductor device CHP.

[0050] Subsequently, the completed semiconductor device (CHP) is tested in the final testing (FTS) stage, and only the CHP deemed to be in good condition is shipped.

[0051] <Correction in the semiconductor wafer testing process> In the semiconductor device manufacturing method according to Embodiment 1, resistance fluctuations caused by manufacturing variations are determined in the semiconductor wafer testing process, and the reference current supplied to the reference resistor Rref is corrected to a value that reduces the resistance fluctuations. More specifically, the semiconductor wafer testing process WTS comprises a first test process WTS1, a second test process WTS2, and a third test process (hereinafter also referred to as the setting process) WTS3, as described below. In the first test process WTS1, resistance fluctuations are determined, and in the third test process WTS3, data that reduces resistance fluctuations is set in the current circuit.

[0052] <<Current flowing through power devices, sense resistance, reference resistance, and reference current>> Before detailing the first test process WTS1 to the third test process WTS3, let's describe the relationship between the current IL_oc, sense resistor Rs, reference resistor Rref, and reference current Iref detected by the overcurrent detection circuit OIDT_H (Figure 1) shown in Figure 1. Figure 12 is a diagram illustrating Embodiment 1.

[0053] The overcurrent detection circuit OIDT_H detects a current proportional to the current IL flowing through the source-drain path of the N-type transistor PWT. The current IL_oc detected by this overcurrent detection circuit OIDT_H can be equivalently expressed by equation (1) shown in Figure 12.

[0054] In equation (1), K(Rs) represents the size ratio K mentioned earlier. The size ratio depends on the resistance value of the sense resistor Rs and is proportional to the sense resistor Rs. Therefore, in equation (1), the size ratio is expressed with the sense resistor Rs as the variable (Rs). As can be understood from equation (1), if the resistance value of the sense resistor Rs varies, the size ratio K will vary, and the value of the detected current IL_oc will also vary, resulting in detection errors and a decrease in accuracy. Since the variation in the size ratio K is proportional to the variation in the sense resistor Rs, it is possible to reduce the change in current IL_oc due to manufacturing variations by changing (correcting) the reference current Iref in a direction that cancels out the variation in the sense resistor Rs (in the opposite direction to the variation). In other words, by appropriately correcting the reference current Iref, it is possible to reduce the decrease in accuracy due to resistance fluctuations caused by manufacturing variations.

[0055] If we move the sense resistor Rs listed on the right side of equation (1) to the left side and rewrite it, we can see that the comparison circuit CMP shown in Figure 1 compares the voltage (IL_oc × Rs) on the left side of equation (1) with the voltage ((K(Rs) × Rref × Iref) on the right side. In this case, the value of the current IL_oc in equation (1) represents the threshold value of the overcurrent detection circuit OIDT_H when the overcurrent detection signal OID_H changes from a low level to a high level.

[0056] <<First Test Process, Second Test Process, and Third Test Process (Setup Process)>> Next, the first test process WTS1, the second test process WTS2, and the third test process WTS3 according to Embodiment 1 will be described with reference to the drawings. Figure 4 is a flowchart showing the semiconductor wafer test process according to Embodiment 1 in detail. Figure 4 is similar to Figure 2. The main difference is that Figure 4 shows the first test process, the second test process, and the third test process performed in the semiconductor wafer test process WTS in detail.

[0057] <<<First Test Process WTS1>>> In the first test process WTS1, the resistance value of the replica resistor Rrep is measured by the tester device TST. From the measured resistance value of the replica resistor Rrep, the tester device TST calculates (estimates) the variation in resistance values ​​due to manufacturing variations of resistors, including the sense resistor Rs.

[0058] The state of the semiconductor device CHP and the tester device TST during the first test process WTS1 will be explained using drawings. Figure 5 is a diagram illustrating the first test process according to Embodiment 1. Figure 5 is a combined diagram of Figure 1 and Figure 3(B). Specifically, Figure 5 shows the high-side drive circuit HDD, the memory circuit MEM, and the control driver DRV as the semiconductor device CHP, as shown in Figure 1. To avoid complexity, the control driver DRV is depicted more simply in Figure 5 compared to Figure 1. Furthermore, only the pads and external terminals necessary for the explanation are shown in Figure 5. Also, only the tester device TST (control unit TST_C, test unit TST_T, and setting unit TST_S) shown in Figure 3(B) is shown in Figure 5.

[0059] In the first test process WTS1, the control unit TST_C supplies the power supply voltage from the test power supply circuit TST_V1 in the test unit TST_T to the power terminal VCC of the semiconductor device CHP. Also in the first test process WTS1, the control unit TST_C supplies the test current IF from the test current circuit TST_I1 in the test unit TST_T to the pad TPW1_1 in the semiconductor device CHP, and measures the voltage between the pad TPW1_2 in the semiconductor device CHP and the output terminal OUT with the test measurement circuit TST_D1. Furthermore, during the first test process WTS1, the control unit TST_C supplies a control signal to the control driver DRV via the pad TPW_C to control the control driver DRV so that the N-type transistors PWT and SNT are in a non-conducting state.

[0060] As shown in Figure 5, one end of the replica resistor Rrep is connected to pads TPW1_1 and TPW1_2, and the other end of the replica resistor Rrep is connected to the output terminal OUT.

[0061] If the voltage measured by the test measurement circuit TST_D1, i.e., the voltage drop across the replica resistor Rrep generated by the test current IF, is Vsns, then the control unit TST_C performs the calculation shown in Figure 12, equation (2), based on the test current IF from the test current circuit TST_I1 and the voltage Vsns measured by the test measurement circuit TST_D1, and determines the resistance value R of the replica resistor Rrep in the semiconductor device CHP. meas Calculate.

[0062] Next, the control unit TST_C calculates the resistance value R of the replica resistor Rrep. meas And the ideal value R of the replica resistor Rrep ideal The difference ΔR is calculated. This difference ΔR represents the variation in resistance, including the sense resistance Rs, that occurs due to manufacturing variations. In Embodiment 1, the ideal value R ideal The difference ΔR is normalized based on this. That is, the control unit TST_C executes equation (3) shown in Figure 12, thereby normalizing the difference ΔR / Rideal Calculate this difference ΔR / R ideal In this specification, this is also referred to as the resistance fluctuation rate. Furthermore, the ideal value R of the replica resistance Rrep is also specified. ideal This is, for example, the resistance value during the design phase.

[0063] <<<WTS2 (Whole Testing Process)>>> After calculating the resistance variation rate due to manufacturing variations, the second test process is performed. In the second test process, the variation of other parts (e.g., the comparator circuit CMP) is determined, excluding the variation of the sense resistor Rs caused by manufacturing variations.

[0064] The state of the semiconductor device CHP and the tester device TST during the second test process WTS2 will be explained using drawings. Figures 6 and 7 are diagrams illustrating the second test process according to Embodiment 1. Figure 6 is similar to Figure 5. The difference is that in Figure 6, pads TPW2_1 and TPW2_2 are explicitly shown in the semiconductor device CHP, and the state of the tester device TST is that of the second test process WTS2.

[0065] Pad TPW2_1 is connected to the connection node that connects the source of the N-type transistor SNT to the sense resistor Rs. Pad TPW2_2 is connected to the output terminal of the comparator circuit CMP.

[0066] In the tester device TST, during the second test process WTS2, the control unit TST_C connects the test current circuit TST_I2 within the test unit TST_T between the power terminal VCC of the semiconductor device CHP and the pad TPW2_1, and supplies the test sense current Isns from the test current circuit TST_I2 to the connected node. Also, similar to the first test process WTS1, the control unit TST_C controls the control driver DRV during the second test process WTS2 to make the N-type transistors PWT and SNT non-conductive.

[0067] Also, in the second test step WTS2, the control unit TST_C monitors the overcurrent detection signal OID_H, which is the output of the comparison circuit CMP supplied to the pad TPW2_2, and detects the timing (inversion timing) at which the logical value (level) of the overcurrent detection signal OID_H is inverted. The control unit TST_C measures the current value of the test sense current Isns at the inversion timing.

[0068] FIG. 7 shows the relationship between the test sense current Isns output from the test current circuit TST_I2 and the overcurrent detection signal OID_H. The test current circuit TST_I2 according to Embodiment 1 forms and outputs a test sense current Isns whose value increases as time t elapses in the second test step WTS2 as shown in FIG. 7. The control unit TST_C measures the test sense current Isns at the inversion timing (the timing at which the overcurrent detection signal OID_H changes from a low level to a high level) of the overcurrent detection signal OID_H.

[0069] In FIG. 7, the time toc2 indicates the timing at which the level of the overcurrent detection signal OID_H is inverted when the test sense current Isns is applied to the connection node between the source of the N-type transistor SNT and the sense resistor Rs in the second test step WTS2. The value of the test sense current Isns measured by the control unit TST_C at this time is indicated by the symbol Ioc0 meas is shown. On the other hand, the time toc1 and the symbol Ioc0 shown in FIG. 7 ideal represent the ideal inversion timing and the value of the ideal test sense current Isns.

[0070] The control unit TST_C obtains the difference ΔIoc0 between the measured test current value Ioc0 meas and the ideal test current value Ioc0 ideal This difference ΔIoc0 represents the variation other than the sense resistor Rs due to manufacturing variations. Regarding the variation amount which is the difference ΔIoc0, similar to the variation amount which is the difference ΔR, in Embodiment 1, the ideal value Ioc0 idealThe difference is normalized based on this. That is, the control unit TST_C executes equation (4) shown in Figure 12, thereby normalizing the difference ΔIoc0 / Ioc0 ideal Calculate this difference ΔIoc0 / Ioc0 ideal In this specification, this is also referred to as the current regulation rate. Furthermore, the ideal reversal timing toc1 and the ideal test current value Ioc0 are also specified. ideal These include, for example, the inversion timing and the test current value during the design phase.

[0071] <<<Third Test Process WTS3>>> In the third test process WTS3, the final reference current is calculated from the results obtained in the first test process WTS1 and the second test process WTS2, and the current circuit is set up so that the current value supplied to the reference resistor Rref is equal to the calculated reference current.

[0072] The control unit TST_C uses the resistance fluctuation rate ΔR / R calculated by equation (3) shown in Figure 12. ideal The resistance fluctuation rate for the sense resistor Rs is calculated by multiplying by the constant α and then adding the constant β. Here, the constants α and β are constants obtained from the resistance variation and the size ratio variation K that were previously calculated by simulation. The control unit TST_C calculates the resistance fluctuation rate (α × ΔR / R) for this sense resistor Rs as shown in equation (5) in Figure 12. ideal +β) + the current regulation rate (ΔIoc0 / Ioc0) calculated in the second test process WTS2 ideal Add the value of the ideal reference current Iref. ideal By multiplying by a factor, the variation value caused by manufacturing variations is calculated. In order to reduce or offset the calculated variation value through correction, the calculated variation value is multiplied by -1 to calculate the variation value ΔIref that should be corrected. This variation value ΔIref is added to the reference current Iref that should be generated by the variable current circuit IRF_H, and set in the variable current circuit IRF_H.

[0073] In the configuration for setting the variable current circuit IRF_H, the control unit TST_C may execute equation (5) to obtain the fluctuation value ΔIref, calculate the reference current Iref by adding this fluctuation value ΔIref, and set it in the memory circuit MEM. In this case, the H current data IRD_H (Figure 1) according to the value set in the memory circuit MEM will be output from the memory circuit MEM to the variable current circuit IRF_H.

[0074] However, in the first embodiment, the following processing is performed in the third test step WTS3 so that a more accurate reference current is output from the variable current circuit IRF_H.

[0075] Figure 8 is a diagram illustrating the third test step according to Embodiment 1. Figure 8 is similar to Figure 5. The difference is that in the semiconductor device CHP in Figure 8, pad TPW3_1 is explicitly shown, and the state of the tester device TST is the state of the third test step WTS3.

[0076] Pad TPW3_1 is connected to a connection node that connects the reference resistor Rref and the variable current circuit IRF_H.

[0077] In the tester device TST, as in the second test process WTS2, the control unit TST_C controls the control driver DRV to make the N-type transistors PWT and SNT non-conductive. In addition, the setting unit TST_S within the tester device TST is connected to the memory circuit MEM via the input terminal DIN.

[0078] In the third test process WTS3, the control unit TST_C instructs the setting unit TST_S to sequentially change (sweep the code) the H current data IRD_H (Figure 1) supplied to the variable current circuit IRF_H via the memory circuit MEM. As a result, the variable current circuit IRF_H sequentially outputs a reference current with a value according to the supplied H current data IRD_H. The control unit TST_C measures (understands) the value of the currently outputting reference current from the value supplied via the pad TPW3_1. The control unit TST_C instructs the memory circuit MEM via the setting unit TST_S to write the H current data IRD_H to the memory circuit MEM when the measured reference current Iref reaches a value obtained by adding the fluctuation value ΔIref calculated based on equation (5). This makes it possible to set the reference current while knowing the actual value of the reference current Iref, and makes it possible to set a more accurate reference current.

[0079] The memory circuit MEM, for example, is equipped with a fuse, and the high current data IRD_H is written to the fuse upon instruction from the setting unit TST_S. In the semiconductor device CHP after shipment, the reference current according to the high current data IRD_H written to the fuse is output from the variable current circuit IRF_H, thereby improving accuracy.

[0080] Thus, the third test step WTS3 can be considered to include a current measurement step that measures the reference current output from the variable current circuit IRF_H while sequentially changing the H current data, and a writing step that writes the H current data to the memory circuit MEM when the current value of the reference current measured in the current measurement step reaches a correction value that reduces or cancels out the fluctuation value.

[0081] <<<Configuration of the variable current circuit>>> Figure 9 is a circuit diagram showing the configuration of a variable current circuit according to Embodiment 1. The variable current circuit IRF_H shown in Figure 1, etc., comprises P-type transistors MP3 to MPn, a current source Irrf, and switches SW1 to SWm that are switched-controlled by H current data IRD_H from the memory circuit MEM, as shown in Figure 9. The P-type transistor MP3 and the current source Irrf are connected in series between the power supply voltage VCC and the ground voltage VSS, and the gates of the P-type transistors MP3 to MPn are commonly connected to the connection node between the P-type transistor MP3 and the current source Irrf. In addition, the P-type transistors MP4 to MPn and switches SW1 to SWm are connected in series between the power supply voltage VCC and the common node nC, as shown in Figure 9. This common node nC is connected to the negative input terminal (-) of the comparator circuit CMP shown in Figure 1, for example, and outputs a reference current Iref.

[0082] Of the switches SW1 to SWm, a number of switches corresponding to the H current data IRD_H from the memory circuit MEM will become conductive, and a reference current Iref with a value corresponding to the H current data IRD_H will be supplied to the reference resistor Rref.

[0083] Figure 4 shows an example in which both the first test process WTS1 and the second test process WTS2 are performed, but the process is not limited to this. For example, the second test process WTS2 may be omitted, and only the first test process WTS1 and the third test process WTS3 may be performed. In this case, in the third test process WTS3, the fluctuation value ΔIref of the reference current can be calculated by performing equation (6) instead of equation (5) shown in Figure 12.

[0084] In Embodiment 1, the resistance fluctuation rate and current fluctuation rate caused by manufacturing variations are calculated in the semiconductor wafer test process (WTS) rather than the final test process (FTS), thereby improving the accuracy of the overcurrent detection circuit. In other words, since the accuracy of the overcurrent detection circuit is improved before the final test process (FTS), it is possible to reduce the waste of materials and manpower spent on semiconductor devices, thereby improving the overall yield. Furthermore, in Embodiment 1, processing to improve the accuracy of the overcurrent detection circuit is performed in the semiconductor wafer test process (WTS), but since this processing does not require supplying a large current to the pads or external terminals of the semiconductor chip, it is possible to process multiple semiconductor chips arranged on the semiconductor wafer simultaneously, thereby shortening the processing time.

[0085] (Embodiment 2) Embodiment 1 describes an example of improving the accuracy of an overcurrent detection circuit during the semiconductor device manufacturing process. Embodiment 2 describes an example of a semiconductor device in which the accuracy of an overcurrent detection circuit can be improved.

[0086] Figure 10 shows the configuration of a semiconductor device according to Embodiment 2. Here, Figure 10(A) is a block diagram showing the main parts of the semiconductor device, and Figure 10(B) is a circuit diagram showing the configuration of the test current circuit.

[0087] To avoid making the diagram too complex, Figure 10(A) only shows the high-side drive circuit HDD (Figure 1) of the semiconductor device CHP.

[0088] In Figure 10(A), PWT represents a power device, which is a power transistor (N-type transistor), and SNT represents a sense device, which is a sense transistor (N-type transistor). The source-drain path of the power transistor PWT is connected between the power supply terminal VCC and the output terminal OUT, and the source-drain path of the sense transistor SNT is connected between the power supply terminal VCC and the connection node nT2, with a sense resistor Rs connected between the connection node nT2 and the output terminal OUT. The gates of the sense transistor SNT and the power transistor PWT are connected to a control driver DRV, and when no overcurrent is detected, the sense transistor SNT and the power transistor PWT are driven by a drive signal from the control driver DRV.

[0089] In Figure 10(A), Rrep represents a replica resistor, and is positioned adjacent to the sense resistor Rs, similar to Embodiment 1. Also in Figure 10(A), TST_ICK represents a test current circuit. The test current circuit TST_ICK, as will be illustrated later using Figure 10(B), comprises a fixed current circuit Itst1 and a variable current circuit Itst2. The fixed current circuit Itst1, switch SW_T1, and replica resistor Rrep are connected in series between the power supply terminal VCC and the output terminal OUT, while the variable current circuit Itst2 and switch SW_T2 are connected in series between the power supply terminal VCC and connection node nT2. Switch SW_T1 conducts when the first test signal Tst1_en is at a high level (selection level), and switch SW_T2 conducts when the second test signal Tst2_en is at a high level (selection level).

[0090] Similar to Embodiment 1, the comparator circuit CMP, which outputs an overcurrent detection signal OID_H, has its negative input terminal (-) connected to the output terminal OUT via a reference resistor Rref, and the positive input terminal (+) of the comparator circuit CMP is connected to the connection node nT2. In addition, a reference current Iref is supplied to the negative input terminal (-) from the variable current circuit IRF_H.

[0091] In the semiconductor device CHP according to Embodiment 2, a compensation circuit for reducing fluctuations caused by manufacturing variations is configured using the following components: a multiplexer MUX, an analog-to-digital conversion circuit (hereinafter also referred to as an AD circuit) ADC, an arithmetic circuit OPC, a lookup table LUT, an AND circuit AND, and a memory circuit MEM.

[0092] <Compensation circuit> The multiplexer MUX is connected to connection nodes nT1 and nT2, which connect switch SW_T1 and replica resistor Rrep, and selects either connection node nT1 or nT2 according to the first test signal Tst1_en and the second test signal Tst2_en. For example, when the first test signal Tst1_en is high, the multiplexer MUX selects connection node nT1, and when the second test signal Tst2_en is high, it selects connection node nT2. The analog signal at the connection node selected by the multiplexer MUX is converted to a digital signal by the ADC and supplied to the OPC.

[0093] The AND circuit supplies the output of the comparator circuit CMP to the memory circuit MEM when the second test signal Tst2_en is high. The memory circuit MEM transmits and receives data with the arithmetic circuit OPC.

[0094] The lookup table LUT pre-stores multiple reference current fluctuation values ​​ΔIref and multiple reference current values ​​(corresponding to the H current data IRD_H in Figure 1). Here, there is a one-to-one correspondence between the reference current value and the fluctuation value ΔIref. The lookup table LUT selects a reference current value corresponding to the data (reference current fluctuation value) supplied from the arithmetic circuit OPC and supplies it to the variable current circuit IRF_H. As a result, the variable current circuit IRF_H generates a reference current Iref corresponding to the supplied reference current value and supplies it to the reference resistor Rref.

[0095] In Figure 10(A), L_CNT represents the control circuit. Before using the semiconductor device CHP, the control circuit L_CNT controls the control driver DRV with the control signal OFF so that the power transistor PWT and sense transistor SNT are in a non-conducting state. Next, with the power transistor PWT and sense transistor SNT in a non-conducting state, the control circuit L_CNT sets the first test signal Tst1_en to a high level, then sets the first test signal Tst1_en to a low level, and then sets the second test signal Tst2_en to a high level. This allows the compensation circuit to perform an operation to reduce the fluctuation values ​​caused by manufacturing variations.

[0096] Next, an example of the test current circuit TST_ICK will be described using Figure 10(B). The test current circuit TST_ICK comprises current limiting resistors Rtst1 and Rtst2, P-type transistors MPo and MPp, operational amplifier OP1, and a variable voltage circuit VBG that supplies a voltage value according to the code (data) T_CD to the operational amplifier OP1.

[0097] The current-limiting resistor Rtst1 and the source-drain path of the P-type transistor MPo are connected in series between the power supply voltage VCC and the switch SW_T1, and the gate of the P-type transistor MPo is connected to the output terminal of the operational amplifier OP1. The output of the operational amplifier OP1 is supplied to the P-type transistor MPo and the current-limiting resistor Rtst1, forming a fixed current circuit Itst1, which outputs a test current IF.

[0098] The current-limiting resistor Rtst2 and the source-drain path of the P-type transistor MPp are connected in series between the power supply voltage VCC and the switch SW_T2, and the gate of the P-type transistor MPp is connected to the output terminal of the operational amplifier OP1. One input of the operational amplifier OP1 is connected to the connection node between the P-type transistor MPp and the current-limiting resistor Rtst2. The output voltage of the variable voltage circuit VBG is supplied to the other input of the operational amplifier OP1. Since the output voltage of the variable voltage circuit VBG changes according to the code T_CD, the value of the test sense current Isns supplied to the switch SW_T2 changes according to the code T_CD due to the feedback operation of the operational amplifier OP1. In other words, the current-limiting resistor Rtst2, the P-type transistor MPp, and the operational amplifier OP1 constitute the variable current circuit Itst2. Although not particularly limited, the code T_CD is output from the control circuit L_CNT and changes (increases or decreases) over time.

[0099] <Example of operation> When the first test signal Tst1_en becomes high level, the test current IF is supplied from the fixed current circuit Itst1 to the replica resistor Rrep. The multiplexer MUX selects the connection node nT1, and the voltage at connection node nT1 is converted by the AD circuit ADC and supplied to the arithmetic circuit OPC. Since the value of the test current IF is known in advance, the arithmetic circuit OPC uses the value of the test current IF and the voltage value from the AD circuit ADC to perform the calculation shown in equation (2) in Figure 12. Furthermore, the arithmetic circuit OPC uses the ideal value of the replica resistor Rrep and the result of the calculation in equation (2) to perform the calculation in equation (3) in Figure 12, and the resistance regulation ΔR / R ideal Calculate.

[0100] Next, the second test signal Tst2_en becomes high level. At this time, the control circuit L_CNT supplies the code T_CD, which changes over time, to the test current circuit TST_ICK. As a result, the test current circuit TST_ICK outputs a test sense current Isns that changes over time, as shown in Figure 7. This test sense current Isns is supplied to the connected node nT2 and then to the sense resistor Rs.

[0101] The AND circuit supplies the output of the comparator circuit CMP to the memory circuit MEM when the second test signal Tst2_en is at a high level. Therefore, the result of comparing the sense voltage generated at the sense resistor Rs by the test sense current Isns with the reference voltage generated at the reference resistor Rref is supplied to the memory circuit MEM. Furthermore, the sense voltage generated at the sense resistor Rs by the test sense current Isns is converted by the AD circuit ADC via the multiplexer MUX and supplied to the arithmetic circuit OPC.

[0102] The arithmetic circuit OPC selects the voltage supplied from the AD circuit ADC at the moment the comparison result of the comparator circuit CMP stored in the memory circuit MEM shows an inversion. The arithmetic circuit OPC divides this selected voltage by the sense resistor Rs to obtain the current Ioc0 shown in equation (4) of Figure 12. meas Calculate the value and compare it to the ideal value Ioc0 ideal The calculation in equation (4) is performed to obtain the current regulation rate ΔIoc0 / Ioc0 ideal Calculate.

[0103] Subsequently, the OPC calculation circuit calculates the resistance fluctuation rate ΔR / R ideal And the current regulation rate ΔIoc0 / Ioc0 idealUsing this, the fluctuation value ΔIref of the reference current is calculated by executing equation (5) in Figure 12 and supplied to the lookup table LUT. Based on this fluctuation value ΔIref, the lookup table LUT selects the corresponding reference current value from the multiple reference current values ​​stored and supplies the selected reference current value to the variable current circuit IRF_H. An example of the variable current circuit IRF_H is explained in Figure 9 and is therefore omitted here.

[0104] Furthermore, in Embodiment 2, the replica resistor Rrep is composed of unit resistors, similar to Embodiment 1, and the sense resistor Rs is composed of multiple identical unit resistors. Of course, when viewed in plan view, the unit resistors constituting the replica resistor are arranged adjacent to the unit resistors constituting the sense resistor Rs.

[0105] Furthermore, in Figure 10, the resistance fluctuation rate ΔR / R is used as the fluctuation rate. ideal and current regulation ΔIoc0 / Ioc0 ideal An example of calculating the fluctuation value ΔIref using the above has been explained, but as in Embodiment 1, the fluctuation rate is the resistance fluctuation rate ΔR / R ideal Alternatively, the variation ΔIref may be calculated using only (equation (6) in Figure 12).

[0106] In embodiments 1 and 2, the code DRV was referred to as a control driver to distinguish it from the drive circuit HLD (for example, Figure 1). However, since the code DRV outputs drive signals DRV_H and DRV_L, the code DRV can also be considered as a drive circuit.

[0107] <Note> This specification discloses several inventions, some of which are described in the claims, but also discloses other inventions, some of which are representative and listed below. (A) Power transistor and A sense transistor comprising a gate connected to the gate of the power transistor and a source connected to a predetermined node via a sense resistor, A reference resistor connected between the current circuit and the predetermined node, A comparison circuit that forms an overcurrent detection signal by comparing the sense voltage generated in the sense resistor by the sense current supplied from the sense transistor to the sense resistor with the reference voltage generated in the reference resistor by the reference current supplied from the current circuit to the reference resistor, When no overcurrent is detected by the overcurrent detection signal, a drive circuit supplies a drive signal to the gate of the power transistor, A replica resistor is positioned adjacent to the aforementioned sense resistor, A test current circuit that supplies a first test current to the replica resistor, A compensation circuit that, based on the replica voltage generated in the replica resistor by the first test current, determines the resistance fluctuation rate of the replica resistor due to manufacturing variations, determines the fluctuation value of the reference current based on the resistance fluctuation rate, and sets the current value of the current circuit to reduce the fluctuation value, Equipped with, Semiconductor equipment. (B) In the semiconductor device described in Appendix (A), The test current circuit supplies a second test current, which changes over time, to the sense resistor. The compensation circuit determines the current regulation rate, which is the difference between the value of the second test current when the output of the comparison circuit is inverted and the ideal value of the second test current that inverts the output of the comparison circuit; determines the fluctuation value of the reference current based on the resistance regulation rate; and generates the reference current with the current circuit to a value that reduces the fluctuation value. Semiconductor equipment. (C) In the semiconductor device described in Appendix (B), The sense resistor is formed by a combination of multiple unit resistors, and the replica resistor is formed by the unit resistors. Semiconductor equipment.

[0108] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0109] ASS Semiconductor Assembly Process CH semiconductor chip CHP Semiconductor CMP comparison circuit FTS Final Testing Process IRF_H Variable Current Circuit PWT Power Devices Rref Reference Resistor Rrep Replica Resistor Rs Sense Resistance SNT Sense Device TST Tester Device WP semiconductor wafer WPS semiconductor wafer manufacturing process WTS Semiconductor Wafer Testing Process WTS1 First Test Process WTS2 Test Process 2 WTS3 Third Test Process (Configuration Process)

Claims

1. A semiconductor wafer manufacturing process for manufacturing a semiconductor wafer on which a plurality of semiconductor chips are arranged, each comprising a power device and an overcurrent detection circuit for detecting the current flowing through the power device, A semiconductor wafer testing process for testing the semiconductor wafer manufactured in the semiconductor wafer manufacturing process, A semiconductor device assembly process, which involves cutting out the plurality of semiconductor chips from the semiconductor wafer tested in the semiconductor wafer test process and assembling a semiconductor device equipped with the cut-out semiconductor chips, Equipped with, The overcurrent detection circuit comprises a sense device through which a sense current proportional to the current flowing through the power device flows, a sense resistor connected between the sense device and a predetermined node, a reference resistor connected between the predetermined node and a current circuit, and a comparison circuit that compares the sense voltage generated at the sense resistor by the sense current with the reference voltage generated at the reference resistor by the reference current from the current circuit to form an overcurrent detection signal. The semiconductor chip includes a replica resistor positioned adjacent to the sense resistor, The aforementioned semiconductor wafer testing process is: A first test step for determining the resistance fluctuation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer, A setting step involves determining the fluctuation value of the reference current based on the resistance fluctuation rate obtained in the first test step, and setting the current value of the current circuit to reduce the fluctuation value, Equipped with, A method for manufacturing a semiconductor device.

2. In the method for manufacturing a semiconductor device according to claim 1, The current circuit comprises a variable current circuit that outputs a current value according to the supplied data as the reference current, and a storage circuit that stores the data. The aforementioned setting process is: A current measurement step in which the reference current output from the variable current circuit is measured while changing the data supplied to the variable current circuit, A writing step in which the current value measured in the current measurement step reaches a correction value that cancels out the fluctuation value, and writes the data to the memory circuit when the current value measured in the current measurement step reaches a correction value that cancels out the fluctuation value, It is equipped with A method for manufacturing a semiconductor device.

3. In the method for manufacturing a semiconductor device according to claim 1, The semiconductor wafer testing process further includes a second testing step of applying a test current to the sense resistor, determining the test current value when the overcurrent detection signal inverts, and determining the current fluctuation rate between the determined test current value and the ideal test current value. In the setting step, the fluctuation value of the reference current is determined based on the resistance fluctuation rate and the current fluctuation rate, and the current value of the current circuit is set to reduce the fluctuation value. A method for manufacturing a semiconductor device.

4. In the method for manufacturing a semiconductor device according to claim 3, The current circuit comprises a variable current circuit that outputs a current value according to the supplied data as the reference current, and a storage circuit that stores the data. The aforementioned setting process is: A current measurement step in which the reference current output from the variable current circuit is measured while changing the data supplied to the variable current circuit, A writing step in which the current value measured in the current measurement step reaches a correction value that cancels out the fluctuation value, and writes the data to the memory circuit when the current value measured in the current measurement step reaches a correction value that cancels out the fluctuation value, It is equipped with A method for manufacturing a semiconductor device.

5. In the method for manufacturing a semiconductor device according to claim 4, The sense device comprises a sense transistor whose source is connected to the predetermined node via the sense resistor. The power device comprises a power transistor having a gate connected to the gate of the sense transistor, and having a power transistor that is larger in size than the sense transistor. The power transistor and the sense transistor are made non-conductive during the first test step, the second test step, and the setting step. A method for manufacturing a semiconductor device.

6. In the method for manufacturing a semiconductor device according to claim 5, The resistance fluctuation rate is the difference between the ideal resistance value of the replica resistor and the resistance value of the replica resistor measured in the first test step, normalized with the ideal resistance value as the unit. The current fluctuation rate is the difference between the test current value obtained in the second test step and the ideal test current value, normalized using the ideal test current value as the unit. A method for manufacturing a semiconductor device.

7. In the method for manufacturing a semiconductor device according to claim 6, The sense resistor is formed by a combination of multiple unit resistors, and the replica resistor is formed by the unit resistors. A method for manufacturing a semiconductor device.

8. Power transistors and A sense transistor comprising a gate connected to the gate of the power transistor and a source connected to a predetermined node via a sense resistor, A reference resistor connected between the current circuit and the predetermined node, A comparison circuit that compares the sense voltage generated in the sense resistor by the sense current supplied from the sense transistor to the sense resistor with the reference voltage generated in the reference resistor by the reference current supplied from the current circuit to the reference resistor to form an overcurrent detection signal. When no overcurrent is detected by the overcurrent detection signal, a drive circuit supplies a drive signal to the gate of the power transistor, A replica resistor is positioned adjacent to the aforementioned sense resistor, Equipped with, The reference current supplied from the current circuit to the reference resistor is set to reduce the fluctuation value of the reference current based on the resistance fluctuation rate of the replica resistor that occurs due to manufacturing variations. Semiconductor equipment.

9. In the semiconductor device described in claim 8, The sense resistor is formed by a combination of multiple unit resistors, and the replica resistor is formed by the unit resistors. Semiconductor equipment.

10. In the semiconductor device described in claim 9, The current circuit comprises a variable current circuit that outputs a current value according to the supplied data as the reference current, and a storage circuit that stores the data. Semiconductor equipment.

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