Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same that reduce drain leakage current. [Solution] A semiconductor device is provided, comprising: a first semiconductor 11 made of 4H-SiC or 6H-SiC; a second semiconductor 12 made of 3C-SiC provided on the main surface of the first semiconductor and forming a heterointerface; and an electrode group including a gate electrode 14 provided on the surface of the second semiconductor facing the heterointerface and positioned between a source electrode 13 and a drain electrode 15, wherein the second semiconductor has a two-dimensional gas region 16 of electrons or holes extending along the heterointerface, and the first semiconductor has a first region 18 in at least a portion of the region below the gate electrode and the region between the gate electrode and the drain electrode, having a conductivity type opposite to that of the two-dimensional gas region.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device having a single-crystal semiconductor layer grown epitaxially on a semiconductor substrate, and a method for manufacturing the same. [Background technology]

[0002] SiC single crystals exist in various polytypes (crystal polymorphs), such as 3C (cubic)-SiC, 4H (hexagonal)-SiC, and 6H (hexagonal)-SiC. Transistors are known in which a 3C-SiC single crystal layer is grown on a 4H-SiC substrate or a 6H-SiC substrate to form a heterojunction, and gate electrodes, source electrodes, and drain electrodes are formed on the surface of the 3C-SiC single crystal layer (see, for example, Patent Document 1 and Non-Patent Document 1). In this transistor, a two-dimensional carrier gas is induced at the interface of the heterojunction. By controlling the potential of the gate electrode using this as a channel, the current flowing between the source electrode and the drain electrode is modulated, and the gate signal is amplified.

[0003] SiC heterojunction transistors have extremely small lattice mismatches and differences in thermal expansion coefficients because the heterojunction is formed by crystals of different SiC crystal systems. This is an advantage over GaN-based HEMTs (high electron mobility transistors) in power semiconductors that require high power density (see, for example, Non-Patent Document 2). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2024-035252 [Non-patent literature]

[0005] [Non-Patent Document 1] H. Sazawa et al., Appl. Phys. Lett. 120 212102 (2022) [Non-Patent Document 2] H. Sazawa et al., Appl. Phys. Lett. 124 120601 (2024) Summary of the Invention Problems to be Solved by the Invention

[0006] In the case of a transistor in the OFF state, it is preferable that the current (drain current) flowing between the source electrode and the drain electrode is zero. However, as disclosed in Non-Patent Document 2, in a SiC heterojunction transistor, when the gate voltage that should be OFF is -4V, the drain current does not become zero, that is, a drain leakage current occurs.

[0007] The present disclosure provides a semiconductor device for reducing drain leakage current and a method for manufacturing the same. Means for Solving the Problems

[0008] According to one aspect of the present disclosure, there is provided a semiconductor device including a first semiconductor of 4H-SiC or 6H-SiC, a second semiconductor of 3C-SiC provided on a main surface of the first semiconductor to form a heterointerface, and an electrode group including a gate electrode provided on a surface of the second semiconductor facing the heterointerface and disposed between a source electrode and a drain electrode. The second semiconductor has a two-dimensional gas region of electrons or holes extending along the heterointerface, and the first semiconductor has a first region having a conductivity type opposite to that of the two-dimensional gas region in at least a part of a region below the gate electrode and a region between the gate electrode and the drain electrode.

[0009] According to the above embodiment, the semiconductor device includes a first semiconductor made of 4H-SiC or 6H-SiC, a second semiconductor made of 3C-SiC laminated on its main surface, and a group of electrodes formed on the surface of the second semiconductor, including a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode. The second semiconductor has a two-dimensional gas region of electrons or holes along the heterointerface. A first region having a conductivity type opposite to that of the two-dimensional gas region is provided in at least a portion of the first semiconductor below the gate electrode and the region between the gate electrode and the drain electrode. Due to the potential-raising effect of the first region, electrons or holes flowing through the channel become concentrated and distributed near the heterointerface. This effect makes it possible to provide a semiconductor device with reduced drain leakage current.

[0010] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising the steps of (a) preparing a first semiconductor of 4H-SiC or 6H-SiC, (b) forming a first region in a part of the first semiconductor by implanting impurity ions from the main surface of the first semiconductor, (c) forming a second semiconductor of 3C-SiC on the first semiconductor, and (d) forming an electrode group on the surface of the second semiconductor including a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode, wherein the second semiconductor has a two-dimensional gas region of electrons or holes extending along the interface between the first semiconductor and the second semiconductor, and in step (b), the first region is formed with impurities that generate a charge having a conductivity type opposite to that of the two-dimensional gas region in at least a portion of the region of the first semiconductor below the gate electrode and the region between the gate electrode and the drain electrode, with respect to the position where the gate electrode and the drain electrode will be formed.

[0011] According to the other embodiments described above, the process of forming the second semiconductor of 3C-SiC is performed after the process of forming the first region by implanting impurity ions. Therefore, a manufacturing method is provided that avoids degradation of the crystallinity of the second semiconductor of 3C-SiC due to the impurity ion implantation process, and avoids the occurrence of electron or hole scattering in the two-dimensional gas region caused by such degradation or impurity ions. [Brief explanation of the drawing]

[0012] [Figure 1A] This is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment. [Figure 1B] This is a top view showing the configuration of a semiconductor device according to the first embodiment. [Figure 2A] This is a schematic band diagram (shown by the solid line) of the area below the gate electrode when an ion implantation region is not provided. [Figure 2B] This is a schematic band diagram (shown by the solid line) below the gate electrode when an ion implantation region is provided. [Figure 3] This is a process diagram (part 1) of the semiconductor device according to the first embodiment. [Figure 4] This is a process diagram (part 2) of the semiconductor device according to the first embodiment. [Figure 5A] This is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment. [Figure 5B] This is a top view showing the configuration of a semiconductor device according to the second embodiment. [Figure 6A] This is a cross-sectional view showing the configuration of a semiconductor device according to the third embodiment. [Figure 6B] This is a top view showing the configuration of a semiconductor device according to the third embodiment. [Figure 7] This figure shows the parameters for the position and distribution width of the ion implantation region. [Figure 8] This figure shows the location and distribution width of the ion implantation region for calculation examples 1 to 7. [Figure 9] This figure shows the relationship between gate voltage and drain current (calculation results) for calculation examples 1 to 4. [Figure 10]This figure shows the relationship between gate voltage and drain current (calculation results) for calculation examples 5 to 7. [Modes for carrying out the invention]

[0013] Embodiments of this disclosure will be described below with reference to the drawings. Elements common to multiple drawings are denoted by the same reference numerals, and detailed descriptions of those elements will not be repeated.

[0014] [Semiconductor device according to the first embodiment] Figure 1A is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment, and Figure 1B is a top view showing the configuration of a semiconductor device according to the first embodiment.

[0015] Referring to Figures 1A and 1B, the semiconductor device 10 is a HEMT and includes a 4H-SiC substrate or a 6H-SiC substrate (hereinafter referred to as "H-SiC substrate") 11, a 3C-SiC layer 12 laminated on the main surface 11a of the H-SiC substrate 11, and a source electrode 13, a gate electrode 14, and a drain electrode 15 formed on the surface of the 3C-SiC layer 12. In the first embodiment, the main surface 11a of the H-SiC substrate 11 is the (000-1) plane (C plane). The main surface 11a of the H-SiC substrate 11 and the lower surface of the 3C-SiC layer 12 form a heterointerface made of crystals of different crystal systems. A two-dimensional electron gas region 16 is formed in the 3C-SiC layer 12, in which a two-dimensional electron gas is distributed along the heterointerface. The two-dimensional electron gas region 16 functions as an n-type channel of the semiconductor device 10.

[0016] The H-SiC substrate 11 may have a conductivity type opposite to that of the two-dimensional electron gas region 16, i.e., p-type, or it may be so-called semi-insulating, i.e., with a resistivity of 1 × 10⁻⁶. 5 It may have an insulating property of Ωcm or more.

[0017] The H-SiC substrate 11 may have an off-plane inclined from the (000-1) plane of its main surface 11a at a predetermined off-angle in a predetermined direction, for example. The predetermined orientation is, for example, within ±15 degrees from the <01-10> direction, and the predetermined off-angle is, for example, in the range of 0 degrees or more and 1.0 degrees or less from the (000-1) plane. Instead of the H-SiC substrate 11, a 4H-SiC crystal layer or 6H-SiC crystal layer (also referred to as "H-SiC layer") formed on a silicon substrate or the like may be used, or bulk 4H-SiC crystal or 6H-SiC crystal (also referred to as "H-SiC crystal"). The thickness of the H-SiC substrate 11 is not particularly limited, but is preferably, for example, 100 μm to 1000 μm. One or more layers of SiC may be further included between the H-SiC substrate 11 and the 3C-SiC layer 12.

[0018] The 3C-SiC layer 12 is a crystalline layer epitaxially grown on the main surface ((000-1) plane) of the H-SiC substrate 11 (or H-SiC layer, bulk H-SiC crystal). The thickness of the 3C-SiC layer 12 is preferable as a thicker layer reduces gaterick current and as a thinner layer increases transconductance. The thickness of the 3C-SiC layer 12 is determined by a balance between these two properties, and is preferably 1 nm or more and 200 nm or less, more preferably 2 nm or more and 70 nm or less, particularly preferably 3 nm or more and 40 nm or less, and most preferably 3 nm or more and 10 nm or less.

[0019] A source electrode 13 and a drain electrode 15 are provided on the surface of the 3C-SiC layer 12, and a gate electrode 14 is provided between the source electrode 13 and the drain electrode 15. The source electrode 13 and the drain electrode 15 are, for example, nickel (Ni) films, and the gate electrode 14 is a gold (Au) film or a platinum (Pt) film. The film thickness of the source electrode 13, the gate electrode 14, and the drain electrode 15 is, for example, 50 nm. The space between the source electrode 13 and the gate electrode 14 and the space between the gate electrode 14 and the drain electrode 15 are not particularly limited, but are, for example, 1 μm. The gate length (length of the gate electrode 14 in the longitudinal direction (X direction)) is not particularly limited, but is, for example, 1 μm. The gate width (length of the gate electrode 14 in the depth direction (Y direction)) is not particularly limited, but is, for example, 50 μm.

[0020] The H-SiC substrate 11 has an ion implantation region 18 in at least a portion of the area below the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15. The ion implantation region 18 contains impurities that produce holes with a conductivity type opposite to that of the two-dimensional electron gas region 16. The impurities are group III elements, including, for example, aluminum. The ion implantation region 18 has a p-type conductivity. If the H-SiC substrate 11 has p-type impurities, the ion implantation region 18 contains p-type impurities at a higher concentration than the concentration of those impurities.

[0021] The ion implantation region 18 has the effect of raising the potential on the H-SiC substrate 11 side of the channel (i.e., the region through which the drain current flows) formed in the two-dimensional electron gas region 16. This creates an energy barrier on the H-SiC substrate 11 side for electrons flowing through the channel. In addition, the ion implantation region 18 has the effect of mitigating the electric field applied to the 3C-SiC layer 12 directly beneath it by the gate electrode 14.

[0022] Figure 2A shows a schematic band diagram (shown by a solid line) below the gate electrode when the ion implantation region 18 is not provided. Figure 2B shows a schematic band diagram (shown by a solid line) below the gate electrode when the ion implantation region is provided. Referring to Figure 2A together with Figure 1A, when the ion implantation region is not provided, the electron concentration in the two-dimensional electron gas region peaks near the heterointerface between the H-SiC substrate 11 and the 3C-SiC layer 12, and spreads out in the depth direction of the H-SiC substrate 11. These electrons that have spread out in the depth direction are insensitive to the potential change of the gate electrode 14 and therefore become a leakage current. Referring to Figure 2B in conjunction with Figure 1A, when an ion implantation region 18 is provided, the potential rises in the depth direction of the H-SiC substrate 11 from the heterointerface between the H-SiC substrate 11 and the 3C-SiC layer 12. This acts as a barrier to electrons flowing through the channels formed in the two-dimensional electron gas region 16, causing electrons to concentrate and distribute near the heterointerface. This action of the ion implantation region 18 can reduce the drain leakage current.

[0023] For the ion implantation region 18 to exert its effect of raising the potential on the H-SiC substrate 11 side, the ion implantation region 18 only needs to be located in at least a portion of the H-SiC crystal of the H-SiC substrate 11 directly beneath the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15. However, if the distribution width of the ion implantation region 18 in the length direction (X direction shown in Figure 1A) is too narrow, the carrier leakage suppression effect due to the potential raising effect will not be sufficiently exerted, so there is a lower limit to the preferred range of the ion implantation region 18. On the other hand, if the distribution width of the ion implantation region in the length direction is too wide, it will lead to an increase in channel resistance, so there is an upper limit to the preferred range.

[0024] The ion implantation regions 18 are distributed in the H-SiC substrate 11, but may be formed in the H-SiC crystal of the H-SiC substrate 11 not only directly beneath the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15, but also directly beneath the region between the gate electrode 14 and the source electrode 13. However, if the ion implantation regions 18 are located in this position, the drain current flowing between the source electrode 13 and the drain electrode 15 may decrease, and the transconductance may decrease. For this reason, it is preferable to limit the ion implantation regions 18 to a specific range. Thus, the drain leakage current reduction effect exhibits both positive and negative effects depending on the location of the ion implantation regions 18. Even if the ion implantation regions 18 are distributed both directly beneath the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15, and extending outward in the longitudinal direction, the effect of reducing drain leakage current may be improved.

[0025] The ion implantation region 18 is preferably distributed in the H-SiC crystal of the H-SiC substrate 11 directly below the drain electrode 15 side end 14d of the gate electrode 14 (hereinafter also referred to as the "drain side end"). The electric field from the gate electrode 14 tends to concentrate directly below the drain side end 14d of the gate electrode 14. However, by distributing the ion implantation region 18 directly below the drain side end 14d of the gate electrode 14, the electric field directly below the gate electrode 14 can be mitigated.

[0026] Returning to Figures 1A and 1B, the ion implantation region 18 is formed in the H-SiC crystal of the H-SiC substrate 11, but when viewed from above, it is preferable that it be formed in the region overlapping with the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15. By providing the ion implantation region 18 in this position, the drain leakage current can be effectively suppressed. On the other hand, by providing the ion implantation region 18 so as to overlap with the drain-side end 14d of the gate electrode 14, the electric field applied to the 3C-SiC layer 12 directly beneath the gate electrode 14 is mitigated. If the length of the gate electrode 14 (gate length, length in the X direction) is L, the width of the ion implantation region 18 in the length direction (X direction shown in Figure 1A) is preferably 6.0 L or less, more preferably 4.0 L or less, even more preferably 2.0 L or less, particularly preferably 1.25 L or less, and most preferably 1.0 L or less. The ion implantation region 18 preferably has a width of 0.05 L or more in the longitudinal direction, more preferably 0.10 L or more, even more preferably 0.15 L or more, particularly preferably 0.20 L or more, and most preferably 0.25 L or more. The ion implantation region 18 may be provided within the above range so as to be shifted toward the drain electrode 15 side from directly below the drain side end 14d of the gate electrode 14.

[0027] From the viewpoint of suppressing leakage from the gate edge in the Y direction, it is preferable that the width direction (Y direction shown in Figure 1B) of the ion implantation region 18 is the same as or longer than the gate width of the gate electrode 14.

[0028] Preferably, the ion implantation region 18 is distributed so that its depth direction (Z direction shown in Figure 1A) is away from the two-dimensional electron gas region 16. On the other hand, if the ion implantation region 18 is too far below the two-dimensional electron gas region 16, a layer with insufficient potential elevation on the H-SiC substrate 11 side, as shown in Figure 2B, is formed parallel to the bottom of the channel, making it easier for drain leakage current to occur through this layer. There are no particular restrictions on the width of the ion implantation region 18 in the depth direction, but since implanting high-energy impurity ions is necessary to achieve a deep distribution, which degrades the crystallinity of the main surface 11a of the H-SiC substrate 11, there is a preferred range.

[0029] From the viewpoint of sufficiently raising the potential on the H-SiC substrate 11 side and maintaining good crystallinity of the main surface 11a of the H-SiC substrate 11, the upper surface of the ion implantation region 18 is preferably 0 nm or more and 50 nm or less in depth from the heterointerface, more preferably 1 nm or more and 40 nm or less, particularly preferably 2 nm or more and 25 nm or less, and most preferably 3 nm or more and 10 nm or less. The width in the depth direction of the ion implantation region 18 (width in the Z direction (distance between the top and bottom surfaces)) is preferably 5 nm or more and 200 nm or less, more preferably 10 nm or more and 150 nm or less, particularly preferably 15 nm or more and 100 nm or less, and most preferably 20 nm or more and 40 nm or less.

[0030] Furthermore, the boundaries of the ion implantation region 18 in the length direction (X direction), width direction (Y direction), and depth direction (Z direction) were determined by defining the position where the impurity concentration drops by one order of magnitude from the peak (maximum) concentration.

[0031] The higher the impurity concentration in the ion implantation region 18, the higher the barrier effect due to the potential rise and the more favorable it is in terms of reducing the electric field concentration from the gate electrode 14. On the other hand, when impurity ions are implanted into the H-SiC substrate 11 at a high concentration, the crystallinity of the main surface 11a deteriorates, and the crystallinity of the 3C-SiC layer 12 epitaxially grown on the main surface 11a deteriorates. The deterioration of the crystallinity of the 3C-SiC layer 12 causes scattering of channel electrons. From these viewpoints, the peak (maximum) value of the impurity concentration is preferably 1×10 17 cm -3 or more and 1×10 21 cm -3 or less, more preferably 2×10 18 cm -3 or more and 5×10 19 cm -3 or less, and even more preferably 5×10 18 cm -3 or more and 2×10 19 cm -3 or less. In this range, the impurity concentration may vary in the X direction. For example, it may gradually increase, gradually decrease, or periodically change along the X direction. The impurity concentration at the site with a strong electric field distribution may be increased, and the impurity concentration at the site with a weak electric field distribution may be decreased. Thereby, it is possible to effectively reduce the leakage current while suppressing unnecessary scattering of channel carriers.

[0032] According to this embodiment, the semiconductor device 10 includes a 3C-SiC layer 12 laminated on the main surface 11a ((000-1) surface) of an H-SiC substrate 11, and a source electrode 13, a gate electrode 14, and a drain electrode 15 formed on the surface of the 3C-SiC layer 12. A two-dimensional electron gas region 16 is formed in the 3C-SiC layer 12 along the heterointerface. An ion implantation region 18 containing impurities that create holes with a conductivity type opposite to that of the two-dimensional electron gas region 16 is provided in at least a portion of the H-SiC substrate 11 below the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15. Due to the potential-raising effect of the ion implantation region 18, electrons flowing through the channel become concentrated and distributed near the heterointerface. This effect makes it possible to reduce the drain leakage current.

[0033] [Manufacturing method for a semiconductor device according to the first embodiment] Figures 3 and 4 are process diagrams of a semiconductor device according to the first embodiment, with the left side being a cross-sectional view and the right side being a plan view. The manufacturing method of the semiconductor device according to the first embodiment will be explained with reference to Figures 3(a) to (d) and Figures 4(a) to (c) in conjunction with Figures 1A and 1B.

[0034] In the process shown in Figure 3(a), a 4H or 6H single-crystal SiC substrate, i.e., an H-SiC substrate 11, is prepared. The H-SiC substrate 11 may have a p-type structure, or it may be so-called semi-insulating, i.e., with a resistivity of 1 × 10⁻⁶. 5 It may have insulating properties of Ωcm or more. The main surface 11a of the H-SiC substrate 11 is the (000-1) plane. Specifically, the main surface 11a is an off-plane tilted from the (000-1) plane in a predetermined direction and at a predetermined off-angle. The predetermined direction is, for example, within ±15 degrees from the <01-10> direction, and the predetermined off-angle is, for example, in the range of 0 degrees or more and 1.0 degrees or less from the (000-1) plane. Such a 4H-SiC substrate 11 can be obtained by slicing and polishing an ingot with a wire saw to have the above direction and off-angle.

[0035] In the process shown in Figure 3(b), a through-film 21 is formed on the main surface 11a of the H-SiC substrate 11. The through-film 21 is an SiO2 film formed, for example, by CVD (chemical vapor deposition). The through-film 21 functions as a resistor to adjust the implantation depth of impurity ions in the ion implantation process in the subsequent process shown in Figure 3(c). The thickness of the through-film 21 is determined by a balance between the depth of the ion implantation region to be formed and the acceleration voltage of the impurity ions, and is selected, for example, from the range of 10 nm to 200 nm. Next, a photoresist is applied to the surface of the through-film 21 to form an implantation mask 22 with openings 22a formed by photolithography. The position of the openings 22a is determined considering the positions of the gate electrode 14 and drain electrode 15 to be formed in the subsequent process shown in Figure 4(c).

[0036] In the process shown in Figure 3(c), ion implantation is performed on the H-SiC substrate 11 using impurity ions to form ion implantation regions 18A within the H-SiC substrate 11. The impurity ions are ions of group III elements that produce holes of the opposite conductivity type to the two-dimensional electron gas region 16 induced in the 3C-SiC layer 12 formed in the process shown in Figure 4(a), such as aluminum ions. The ion implantation process can use general ion implantation methods widely used in the fabrication process of transistor elements using H-SiC crystals (see, for example, A. Hallen et al., Surf. Coat. Technol. 306 (2016) 190 - 193). The range of the lateral distribution of the ion implantation regions is controlled by the shape of the opening 22a of the implantation mask 22. The range of the ion implantation region 18A in the depth direction is adjusted by the thickness of the through-film 21, the acceleration voltage of the impurity ions, and the incident angle of the impurity ions on the H-SiC substrate 11. The concentration of impurity ions in the ion implantation region 18A is adjusted by the ion implantation time.

[0037] In the step shown in Figure 3(d), the implantation mask 22 and the through-film 21 are removed. Next, it is preferable to form a cap layer 23 over the entire main surface of the H-SiC substrate 11. The cap layer 23 is a protective film to prevent surface roughness of the main surface of the H-SiC substrate 11 during the activation aneel treatment of impurity ions. The cap layer 23 is, for example, a graphite film. The cap layer 23 may be formed, for example, by coating the main surface of the H-SiC substrate 11 with a resist and heating it at 800°C in a vacuum, or by depositing carbon on the main surface of the H-SiC substrate 11 by sputtering. The formation of the cap layer 23 is not essential and may be omitted. Next, the activation aneel treatment is performed. This forms an ion implantation region 18 containing activated impurity ions. The activation aneel treatment is performed by heating in an argon gas or nitrogen gas atmosphere at a temperature of 1500°C to 1700°C. The heating time is, for example, 5 minutes.

[0038] In the process shown in Figure 4(a), if a cap layer 23 is present, the cap layer 23 is removed, and the main surface of the H-SiC substrate 11 is cleaned by RCA cleaning. For example, the cap layer 23 can be removed by ashing with oxygen plasma. Next, a 3C-SiC layer 12 is formed on the main surface of the H-SiC substrate 11 by epitaxial growth of 3C-SiC crystals using thermal CVD, liquid phase growth, plasma CVD, etc. A two-dimensional electron gas is induced in the 3C-SiC layer 12, forming a two-dimensional electron gas region 16.

[0039] From the viewpoint of controllability, it is preferable to use the thermal CVD method for forming the 3C-SiC layer 12. In the thermal CVD method, hydrogen gas is introduced into the reactor of the thermal CVD apparatus while reducing the pressure inside the reactor, for example, at a pressure in the range of 5kPa to 50kPa, the substrate temperature is set to, for example, 1380°C, and the substrate temperature is maintained for a period of 1 minute to 2 hours, and the main surface of the H-SiC substrate 11 is etched by thermal etching. Next, SiH4 or Si2H6 and C3H8 are introduced into the reactor of the thermal CVD apparatus as raw material gas, and H2 is introduced as a carrier gas, the substrate temperature is set to, for example, 1380°C, and the 3C-SiC layer 12 is epitaxially grown on the main surface of the H-SiC substrate 11. The ratio of C atoms to Si atoms (C / Si ratio) of the raw material gas is set to, for example, 0.85. For the method of forming the 3C-SiC layer 12, for example, the method described in Non-Patent Literature 1 can be used. The film thickness of the 3C-SiC layer 12 is preferably set to the film thickness described above.

[0040] In the process shown in Figure 4(b), a source electrode 13 and a drain electrode 15 are formed on the surface of the 3C-SiC layer 12 by a lift-off method using lithography. Specifically, a nickel (Ni) film with a thickness of, for example, 50 nm is deposited on the surface of the 3C-SiC layer using electron beam deposition, and then the Ni film is patterned using the lift-off method to form the source electrode and drain electrode. Next, the electrodes are heated to, for example, 850°C in an argon gas atmosphere to form ohmic contact between the source electrode 13 and the drain electrode 15 and the 3C-SiC layer 12.

[0041] In the process shown in Figure 4(c), a gate electrode 14 is formed on the surface of the 3C-SiC layer 12 between the source electrode 13 and the drain electrode 15 using a lift-off method with a lithography technique. Specifically, a resist film is applied to the surface of the 3C-SiC layer 12, exposed, and developed to remove the resist film at the location of the gate electrode 14 and form an opening. The gate electrode 14 is formed by depositing a material for the gate electrode 14, such as gold (Au) or platinum (Pt) with a thickness of 50 nm, using an electron beam deposition method, and then removing the resist film. An insulating layer (not shown), such as SiO2 or SiN, may be formed between the gate electrode 14 and the 3C-SiC layer 12. Next, a protective film (not shown), such as SiO2 or SiN, may be formed on the exposed surfaces of the 3C-SiC layer 12, for example, the surface of the 3C-SiC layer 12 between the source electrode 13 and the gate electrode 14, and the surface of the 3C-SiC layer 12 between the gate electrode 14 and the drain electrode 15.

[0042] As described above, the semiconductor device 10 of the first embodiment is formed. According to the manufacturing method of this embodiment, the 3C-SiC layer 12 formation step (step in Figure 4(a)) is performed after the ion implantation treatment and activation aneel treatment performed in steps 3(c) and 3(d). This makes it possible to avoid adverse effects on the 3C-SiC layer caused by the ion implantation treatment. Specifically, these adverse effects include deterioration of the crystallinity of the 3C-SiC layer 12 caused by collisions of impurity ions during the ion implantation treatment, and the occurrence of scattering of channel electrons in the two-dimensional electron gas region 16. These lead to deterioration of transistor characteristics. By performing the formation of the 3C-SiC layer 12 after the ion implantation treatment and activation aneel treatment, these adverse effects can be avoided.

[0043] [Semiconductor device according to the second embodiment] Figure 5A is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment, and Figure 5B is a top view showing the configuration of a semiconductor device according to the second embodiment.

[0044] Referring to Figures 5A and 5B, the semiconductor device 30 includes a 4H-SiC substrate or a 6H-SiC substrate (hereinafter referred to as "H-SiC substrate") 31, a 3C-SiC layer 32 laminated on the main surface of the H-SiC substrate 31, and a source electrode 13, a gate electrode 14, and a drain electrode 15 formed on the main surface of the 3C-SiC layer 32. In the second embodiment, the main surface 31a of the H-SiC substrate 31 is the (0001) plane (Si plane), and this main surface and the 3C-SiC layer 32 form a heterointerface. The 3C-SiC layer 32 has a two-dimensional hole gas region 36 formed therein, where two-dimensional hole gas is distributed along the heterointerface. The two-dimensional hole gas region 36 functions as a p-type channel of the semiconductor device 30. The H-SiC substrate 31 may have a conductivity type opposite to that of the two-dimensional hole gas region 36, i.e., n-type, or it may be so-called semi-insulating, i.e., with a resistivity of 1 × 10⁻⁶. 5 It may have an insulating property of Ωcm or more.

[0045] The H-SiC substrate 31 may have, for example, an off-plane whose main surface is tilted from the (0001) plane in a predetermined direction at a predetermined off-angle. The predetermined orientation is, for example, within ±15 degrees from the <01-10> direction, and the predetermined off-angle is, for example, in the range of 0 degrees or more and 1.0 degrees or less from the (0001) plane. Instead of the H-SiC substrate 31, an H-SiC layer formed on a silicon substrate or the like, or a bulk H-SiC crystal may be used. The thickness of the H-SiC substrate is not particularly limited, but is preferably, for example, 100 μm or more.

[0046] The 3C-SiC layer 32 is a crystalline layer epitaxially grown on the main surface ((0001) surface) of the H-SiC substrate 31 (or H-SiC layer, bulk H-SiC crystal). The film thickness of the 3C-SiC layer 32 is the same as that of the semiconductor device 10 according to the first embodiment.

[0047] An ion implantation region 38 is provided in the H-SiC substrate 31 below the gate electrode 14 and the region between the gate electrode 14 and the drain electrode 15, that is, in at least a portion of the H-SiC crystal. The ion implantation region 38 contains impurities that generate electrons of the opposite conductivity type to the two-dimensional hole gas region. The impurities are Group V elements, including nitrogen, for example. That is, the ion implantation region 38 has an n-type conductivity type. If the H-SiC substrate 31 has n-type impurities, the ion implantation region 38 contains n-type impurities at a higher concentration than the impurity concentration of the H-SiC substrate 31. The position and range of the ion implantation region 38 are the same as in the semiconductor device 10 according to the first embodiment, and its effects are also the same.

[0048] [Manufacturing method for a semiconductor device according to the second embodiment] The method for manufacturing a semiconductor device according to the second embodiment is substantially the same as the method for manufacturing a semiconductor device according to the first embodiment, except that the plane orientation of the main surface of the H-SiC substrate 11 is different. Specifically, the difference is that in the ion implantation process (the process shown in Figure 3(c)), the impurity ions implanted are ions of a group V element that generate electrons, such as nitrogen ions. As a result, the method for manufacturing a semiconductor device according to the second embodiment provides the same effects as the method for manufacturing a semiconductor device according to the first embodiment.

[0049] [Semiconductor device and manufacturing method according to the third embodiment] Figure 6A is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment, and Figure 6B is a top view showing the configuration of the semiconductor device according to the third embodiment.

[0050] Referring to Figures 6A and 6B, the semiconductor device 40 has two ion implantation regions 18 and 48 provided on the H-SiC substrate 11. Other than this, the semiconductor device 40 has the same configuration as the semiconductor device 10 according to the first embodiment. The ion implantation region 18 is located directly below the drain-side end 14d of the gate electrode 14. The ion implantation region 48 is located closer to the source electrode 13 than the ion implantation region 18. The ion implantation region 48 uses the same impurities as the ion implantation region 18.

[0051] The method for manufacturing the semiconductor device 40 is not shown in the figures, but is the same as the method for manufacturing the semiconductor device 10 according to the first embodiment, except that in the step shown in Figure 3(b) of the method for manufacturing the semiconductor device 10 according to the first embodiment, one additional opening is provided in the implantation mask 22 in addition to the opening 22a.

[0052] As a modification of the semiconductor device 40 according to the third embodiment, a semiconductor device with the same configuration as the semiconductor device 40 according to the third embodiment may be constructed, except that the main surface of the H-SiC substrate 31 is the (0001) plane, and a two-dimensional hole gas region 36 is formed along the heterointerface in the 3C-SiC layer 32, similar to the semiconductor device 30 according to the second embodiment. However, the ion implantation regions 18 and 48 use the same impurity ions as the semiconductor device 30 according to the second embodiment.

[0053] [Calculation example] A simulation was performed to determine the position and distribution width of the ion implantation region in the semiconductor device according to the first embodiment. In the simulation, the relationship between the gate voltage and drain current was determined by changing the impurity concentration for various positions and distribution widths of the ion implantation region.

[0054] Figure 7 shows the parameters for the position and distribution width of the ion implantation region. Referring to Figure 7, the definitions of the parameters for the position and distribution width of the ion implantation region in each calculation example are as follows. a is the width distributed from the source electrode side end 14s of the gate electrode 14 towards the source electrode 13. b is the width distributed from the source electrode side end 14s of the gate electrode 14 towards the drain electrode 15. c is the width distributed from the drain electrode side end 14d of the gate electrode 14 towards the source electrode 13. d is the width distributed from the drain electrode side end 14d of the gate electrode 14 towards the drain electrode 15.

[0055] Figure 8 shows the location and distribution width of the ion implantation region for calculation examples 1 to 7. L is the gate length. Referring to Figure 8 in conjunction with Figure 7, the distribution of the ion implantation region is as follows: For example, in calculation example 1, c = 0.25 L, and a, b, and d are 0, so it is shown that the ion implantation region is distributed from the drain electrode side end 14d of the gate electrode 14 to 0.25 L towards the source electrode 13. Calculation examples 1 to 4 are cases where the ion implantation region is distributed at least directly below the drain electrode side end 14d of the gate electrode 14. Of these, calculation example 4 is a case where the ion implantation region is also distributed directly below the source electrode side end 14s of the gate electrode 14. On the other hand, calculation examples 5 to 7 are cases where the ion implantation region is distributed only directly below the source electrode side end 14s of the gate electrode 14. The depth distribution of the ion implantation region was set so that the depth from the heterointerface between the main surface 11a of the H-SiC substrate 11 and the 3C-SiC layer 12 was 0 nm at the top surface, and the distance between the top surface and the bottom surface was 30 nm.

[0056] The impurity concentration in the ion implantation region is zero (i.e., no ion implantation region is provided) (indicated as D0) and 1 × 10⁻⁶ 18 cm -3 In this case (shown by D1), 1 × 10 18 cm -3 In increments of 8 x 10 18 cm -3 In this case (shown in D8), up to 10x10 18 cm -3 The concentration was set for the case shown in D9. This impurity concentration is the maximum (i.e., peak) impurity concentration in the ion implantation region.

[0057] The calculation involved setting the drain-source voltage to 10V and determining the drain current when the gate voltage was varied from +1V to -10V. The calculated device structure had thicknesses of 30nm and 100μm for the 3C-SiC layer 12 and H-SiC substrate 11, respectively. The distances between the source electrode 13 and the gate electrode 14, and between the gate electrode 14 and the drain electrode 15, were 1μm and 2μm, respectively. A commercially available semiconductor device simulator (Synopsys, USA, product name sentaurus) was used for the calculations. The ion implantation region was Al ion implantation, and an impurity concentration profile based on experimental data from SIMS measurements was input. Furthermore, a calculation model simulating avalanche breakdown in collisional ionization was used.

[0058] Figures 9 and 10 show the relationship between gate voltage and drain current (calculation results) for calculation examples 1 to 7. In Figures 9 and 10, the horizontal axis is the gate voltage V. g (V) and the vertical axis represents the drain current I d (A / mm), and the line in the figure represents a certain gate voltage V g In the drain current I d The line with the largest value corresponds to the impurity concentration D0 (when no ion implantation region is provided), and the drain current I is greater than that. d The lines where the value decreases correspond to impurity concentrations D1 to D9 in order. The line for impurity concentration D0 is common in Figures 9(a) to (d) and Figures 10(a) to (c).

[0059] Referring to Figure 9(a), in calculation example 1, the line for impurity concentration D0 is the gate voltage V g As the voltage decreases from 1V, the drain current I d The gate voltage V also decreases. g The voltage showed a minimum value around -2.8V, and the gate voltage V g When the drain current I is reduced d This increases. This is because the gate voltage V shows a minimum value. g In the gate voltage region below this, the drain current I dThis indicates that there is a leak. In contrast, the lines for impurity ion concentrations D1 to D9 show a minimum value for the gate voltage V. g In the gate voltage region below this, the impurity concentration D0 is below the line, and the drain current I d It can be seen that the leakage has been reduced. In particular, the lines for impurity concentrations D8 and D9 show that the gate voltage V g In the region below -4.85V, the drain current I d The value is 0, and the drain current I d This indicates that there is no leak. In other words, in calculation example 1 (where the ion implantation region is distributed from c=0.25L, that is, from the drain electrode side end of the gate electrode to 0.25L on the source electrode side), for impurity concentrations D1 to D9, the drain current I d Leakage is reduced, and in particular, in the range of high impurity ion concentration (D8 and D9), drain current I d This indicates that no leak has occurred.

[0060] Referring to Figures 9(b) to (d), in calculation examples 2 to 4, the lines for impurity concentrations D1 to D9 show the minimum value of the gate voltage V. g In the gate voltage region below this, the impurity concentration D0 is below the line, and the drain current I d It can be seen that the leakage is reduced. This is the same as in Figure 9(a). Furthermore, at higher impurity concentrations (for example, impurity ion concentrations D6-D9 in Figures 9(b) and (d), and impurity ion concentrations D7-D9 in Figure 9(c)), the drain current I d The value is 0, and the drain current I d This indicates that there is no leak. In calculation examples 2-4, the ion implantation region is distributed at least directly below the drain electrode side end 14d of the gate electrode, so the drain current I d The leakage is reduced, and especially in the range of high impurity concentrations, the drain current I d This indicates that no leak has occurred.

[0061] Referring to Figures 10(a) to (c), in calculation examples 5 to 7, the lines for impurity concentrations D1 to D9 show local minimums, and furthermore, the gate voltage V g When this is reduced, it overlaps with the line of impurity concentration D0, which corresponds to the drain current I d This indicates that the leak has not been reduced. In calculation examples 5 to 7, as shown in Figure 8, the ion implantation region is distributed only directly below the source electrode side end 14s of the gate electrode 14, and not at the drain electrode side end 14d. From this, it can be seen that it is preferable for the ion implantation region to be distributed directly below the drain electrode side end 14d of the gate electrode 14.

[0062] While preferred embodiments of this disclosure have been described in detail above, this disclosure is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the disclosure as described in the claims.

[0063] Furthermore, the following additional information is disclosed regarding the above explanation. (Note 1) A first semiconductor of 4H-SiC or 6H-SiC, A second semiconductor made of 3C-SiC is provided on the main surface of the first semiconductor and forms a heterointerface, The second semiconductor comprises an electrode group including a gate electrode provided on the surface facing the heterointerface and positioned between the source electrode and the drain electrode, The second semiconductor has a two-dimensional gas region of electrons or holes extending along the heterointerface, The first semiconductor is a semiconductor device having a first region having a conductivity type opposite to that of the two-dimensional gas region, in at least a portion of the region below the gate electrode and the region between the gate electrode and the drain electrode. (Note 2) The semiconductor device according to Note 1, wherein the first region is formed in a region including the end of the gate electrode on the drain electrode side when viewed from above. (Note 3) The semiconductor device according to Note 1, wherein, when viewed from above, the first region is formed on the drain electrode side of the end of the gate electrode on the drain electrode side. (Note 4) The semiconductor device according to any one of Notes 1 to 3, wherein the first region has a first width in the gate length direction of the gate electrode, and the first width is 0.05 L or more and 6.0 L or less, where L is the gate length of the gate electrode. (Note 5) The first semiconductor has a conductivity type opposite to that of the two-dimensional gas region. The semiconductor device according to any one of the appendices 1 to 4, wherein the first region contains an impurity at a concentration higher than the impurity concentration of the first semiconductor. (Note 6) The first semiconductor is an insulator, and its resistivity is 1 × 10⁻⁶ 5 A semiconductor device having a capacitance of Ωcm or greater, as described in any one of the appendices 1 to 4. (Note 7) The main surface of the first semiconductor is the (000-1) plane, The aforementioned two-dimensional gas region is a two-dimensional electron gas region, The first region is a p-type region, as described in any one of the appendices 1 to 6. (Note 8) The main surface of the first semiconductor is the (0001) plane, The aforementioned two-dimensional gas region is a two-dimensional hole gas region, The first region is an n-type region, according to any one of the appendices 1 to 6, relating to the semiconductor device described in item 1 to 6. (Note 9) (a) Prepare a first semiconductor of 4H-SiC or 6H-SiC, (b) By implanting impurity ions from the main surface of the first semiconductor, a first region is formed in a part of the first semiconductor. (c) A second semiconductor of 3C-SiC is formed on the first semiconductor, (d) A step of forming an electrode group on the surface of the second semiconductor, which includes a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode, The second semiconductor has a two-dimensional gas region of electrons or holes extending along the interface between the first semiconductor and the second semiconductor. A method for manufacturing a semiconductor device, wherein in step (b), the first region is formed with impurities that generate a charge having a conductivity type opposite to that of the two-dimensional gas region, in at least a portion of the region of the first semiconductor below the gate electrode and the region between the gate electrode and the drain electrode, with respect to the position where the gate electrode and the drain electrode will be formed. (Note 10) The manufacturing method according to Note 9, wherein in step (b), the first region is formed in a region that includes the end of the gate electrode on the drain electrode side when viewed from above. (Note 11) The manufacturing method according to Note 9, wherein in step (b), the first region is formed on the drain electrode side of the end of the gate electrode on the drain electrode side when viewed from above. (Note 12) The manufacturing method according to any one of Notes 9 to 11, wherein the first region has a first width in the gate length direction of the gate electrode, and the first width is 0.05 L or more and 6.0 L or less, where L is the gate length of the gate electrode. (Note 13) The first semiconductor has a conductivity type opposite to that of the two-dimensional gas region. The manufacturing method according to any one of the appendices 9 to 12, wherein the first region contains an impurity at a concentration higher than the impurity concentration of the first semiconductor. (Note 14) The first semiconductor is an insulator, and its resistivity is 1 × 10⁻⁶ 5 A manufacturing method described in any one of the appendices 9 to 12, wherein the density is Ωcm or greater. (Note 15) The main surface of the first semiconductor is the (000-1) plane, The aforementioned two-dimensional gas region is a two-dimensional electron gas region, The manufacturing method according to any one of the appendices 9 to 14, wherein the first region is a p-type region. (Note 16) The main surface of the first semiconductor is the (0001) plane, The aforementioned two-dimensional gas region is a two-dimensional hole gas region, The manufacturing method according to any one of the appendices 9 to 14, wherein the first region is an n-type region. [Explanation of Symbols]

[0064] 10,30,40 Semiconductor equipment 11,31 H-SiC substrate 12,32 3C-SiC layer 13 Source electrode 14 Gate electrodes 14d Drain electrode side end 14s Source electrode side end 15 Drain electrode 16. Two-dimensional electron gas region 18,38,48 Ion implantation area 36 Two-dimensional Hol Gas Region

Claims

1. A first semiconductor of 4H-SiC or 6H-SiC, A second semiconductor made of 3C-SiC is provided on the main surface of the first semiconductor and forms a heterointerface, The second semiconductor comprises an electrode group including a gate electrode provided on the surface facing the heterointerface and positioned between the source electrode and the drain electrode, The second semiconductor has a two-dimensional gas region of electrons or holes extending along the heterointerface, The first semiconductor is a semiconductor device having a first region having a conductivity type opposite to that of the two-dimensional gas region, in at least a portion of the region below the gate electrode and the region between the gate electrode and the drain electrode.

2. The semiconductor device according to claim 1, wherein the first region, when viewed from above, is formed in a region including the end of the gate electrode on the drain electrode side.

3. The semiconductor device according to claim 1, wherein, when viewed from above, the first region is formed on the drain electrode side of the gate electrode's end on the drain electrode side.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first region has a first width in the gate length direction of the gate electrode, and the first width is 0.05 L or more and 6.0 L or less, where L is the gate length of the gate electrode.

5. The first semiconductor has a conductivity type opposite to that of the two-dimensional gas region. The semiconductor device according to any one of claims 1 to 3, wherein the first region contains an impurity at a concentration higher than the impurity concentration of the first semiconductor.

6. The first semiconductor is an insulator, and its resistivity is 1 × 10⁻⁶ 5 A semiconductor device according to any one of claims 1 to 3, wherein the density is Ωcm or greater.

7. The main surface of the first semiconductor is the (000-1) plane, The aforementioned two-dimensional gas region is a two-dimensional electron gas region, The semiconductor device according to any one of claims 1 to 3, wherein the first region is a p-type region.

8. The main surface of the first semiconductor is the (0001) plane, The aforementioned two-dimensional gas region is a two-dimensional hole gas region, The semiconductor device according to any one of claims 1 to 3, wherein the first region is an n-type region.

9. (a) Prepare a first semiconductor of 4H-SiC or 6H-SiC, (b) By implanting impurity ions from the main surface of the first semiconductor, a first region is formed in a part of the first semiconductor. (c) A second semiconductor of 3C-SiC is formed on the first semiconductor, (d) The process includes forming an electrode group on the surface of the second semiconductor, which includes a source electrode, a drain electrode, and a gate electrode disposed between the source electrode and the drain electrode, The second semiconductor has a two-dimensional gas region of electrons or holes extending along the interface between the first semiconductor and the second semiconductor. A method for manufacturing a semiconductor device, wherein in step (b), the first region is formed in at least a portion of the region of the first semiconductor below the gate electrode and the region between the gate electrode and the drain electrode, with respect to the position where the gate electrode and the drain electrode will be formed, by impurities that generate a charge having a conductivity type opposite to that of the two-dimensional gas region.

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